From bca2a7bcac43f9403cad5dd44e60ffde031f8c8a Mon Sep 17 00:00:00 2001 From: rezado <1908819406@qq.com> Date: Wed, 12 Aug 2026 16:51:32 +0800 Subject: [PATCH] fix(dts): align XiangShan profiles with NEMU OpenSBI --- dts/README.md | 36 ++++-- dts/xiangshan-fpga-AIA-mem16g.dts.in | 2 +- ...shan-fpga-noAIA-2hart-mem16g-novec.dts.in} | 14 +-- ...gshan-fpga-noAIA-2hart-mem8g-novec.dts.in} | 14 +-- dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in | 115 ++++++++++++++++++ dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem24g.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem64g.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in | 4 +- dts/xiangshan-fpga-noAIA-mem8g.dts.in | 4 +- dts/xiangshan-fpga-noAIA-novec.dts.in | 4 +- dts/xiangshan-fpga-noAIA.dts.in | 4 +- scripts/generate-xiangshan-multihart-dts.py | 53 +++++++- 15 files changed, 222 insertions(+), 48 deletions(-) rename dts/{xiangshan-fpga-noAIA-2hart-mem16g.dts.in => xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in} (93%) rename dts/{xiangshan-fpga-noAIA-2hart-mem8g.dts.in => xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in} (93%) create mode 100644 dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in diff --git a/dts/README.md b/dts/README.md index 0575f8a..648e13e 100644 --- a/dts/README.md +++ b/dts/README.md @@ -75,8 +75,15 @@ standard templates retain these profiles: | Template | DRAM | |----------|------| | `xiangshan-fpga-noAIA-2hart-mem8g` | 8 GiB | +| `xiangshan-fpga-noAIA-2hart-mem16g` | 16 GiB | | `xiangshan-fpga-noAIA-32hart-mem64g` | 64 GiB | +`xiangshan-fpga-noAIA-mem16g-novec` is the single-hart Host profile for +`virt/linux/*`. It disables AIA and vector advertisement, retains the H +extension required by RISC-V KVM, and describes exactly 16 GiB of DRAM. The +virtual build validates all three properties that affect nesting: one CPU, at +least 16 GiB, and structured ISA extension `h`. + Select the complete template basename explicitly when building, for example: ```sh @@ -97,16 +104,29 @@ python3 scripts/generate-xiangshan-multihart-dts.py \ --output dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in ``` -`--harts` must be in the range 2 through 128. The generator copies the CPU node for each hart, -extends the CLINT, PLIC, and debug interrupt contexts, and applies the NEMU -UARTLITE and PLIC settings. Generated multi-hart templates reserve the fixed -131 MiB checkpoint window `[0x80300000, 0x88600000)`. +Use `--memory-gib` to override the copied DRAM capacity. The checked-in 16 GiB +two-hart profile is generated with: + +```shell +python3 scripts/generate-xiangshan-multihart-dts.py \ + --base dts/xiangshan-fpga-noAIA-mem8g.dts.in \ + --harts 2 \ + --memory-gib 16 \ + --output dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in +``` + +`--harts` must be in the range 2 through 128, and `--memory-gib` must be a +positive integer when specified. The generator copies the CPU node for each +hart, extends the CLINT, PLIC, and debug interrupt contexts, and applies the +NEMU UARTLITE and PLIC settings. Generated multi-hart templates reserve the +fixed 131 MiB checkpoint window `[0x80300000, 0x88600000)`. The full capability block describes XiangShan hardware and is not fully -emulated by the current QEMU `nemu` machine. In particular, DT-advertised -`smrnmi` requires an OpenSBI platform `smrnmi_handlers_init` callback, while -the `nemu` timer path cannot execute the DT-advertised `sstc` CSR sequence. -The current multi-core DTB must omit `smrnmi` and `sstc` and run with +emulated by the current generic OpenSBI/QEMU `nemu` path. In particular, +DT-advertised `smrnmi` requires an OpenSBI platform +`smrnmi_handlers_init` callback, so all generic-platform DTS templates omit +it. The `nemu` timer path likewise cannot execute the DT-advertised `sstc` CSR +sequence; multi-core diagnostic runs may need to omit `sstc` and use `sstc=false`. The build does not invoke this generator automatically. Run it and review the diff --git a/dts/xiangshan-fpga-AIA-mem16g.dts.in b/dts/xiangshan-fpga-AIA-mem16g.dts.in index 2e405a9..645c8d4 100644 --- a/dts/xiangshan-fpga-AIA-mem16g.dts.in +++ b/dts/xiangshan-fpga-AIA-mem16g.dts.in @@ -48,7 +48,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", diff --git a/dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in b/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in similarity index 93% rename from dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in rename to dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in index 07ae234..e964dd8 100644 --- a/dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in +++ b/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in @@ -43,10 +43,10 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = - "i", "m", "a", "f", "d", "c", "v", "h", + "i", "m", "a", "f", "d", "c", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", @@ -64,8 +64,7 @@ "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", - "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", - "zvkt", "zvl128b", "zvl32b", "zvl64b"; + "zksh", "zkt"; riscv,cbom-block-size = <0x40>; riscv,cboz-block-size = <0x40>; @@ -104,10 +103,10 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = - "i", "m", "a", "f", "d", "c", "v", "h", + "i", "m", "a", "f", "d", "c", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", @@ -125,8 +124,7 @@ "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", - "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", - "zvkt", "zvl128b", "zvl32b", "zvl64b"; + "zksh", "zkt"; riscv,cbom-block-size = <0x40>; riscv,cboz-block-size = <0x40>; diff --git a/dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in b/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in similarity index 93% rename from dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in rename to dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in index b2b4100..fa5912f 100644 --- a/dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in +++ b/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in @@ -43,10 +43,10 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = - "i", "m", "a", "f", "d", "c", "v", "h", + "i", "m", "a", "f", "d", "c", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", @@ -64,8 +64,7 @@ "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", - "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", - "zvkt", "zvl128b", "zvl32b", "zvl64b"; + "zksh", "zkt"; riscv,cbom-block-size = <0x40>; riscv,cboz-block-size = <0x40>; @@ -104,10 +103,10 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = - "i", "m", "a", "f", "d", "c", "v", "h", + "i", "m", "a", "f", "d", "c", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", @@ -125,8 +124,7 @@ "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", - "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", - "zvkt", "zvl128b", "zvl32b", "zvl64b"; + "zksh", "zkt"; riscv,cbom-block-size = <0x40>; riscv,cboz-block-size = <0x40>; diff --git a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in index f4d7498..59eccfc 100644 --- a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in new file mode 100644 index 0000000..81b1da0 --- /dev/null +++ b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in @@ -0,0 +1,115 @@ +/* + * Single-hart Host DTS for a virtualized workload. + * + * AIA is disabled and the H extension is advertised so Host Linux can use + * KVM. The 16 GiB profile matches the default 8 GiB Guest configuration. + */ + +/dts-v1/; + +/ { + compatible = "freechips,rocketchip-unknown-dev"; + model = "xiangshan,Kunminghu-dev"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + + cpu0: cpu@0 { + compatible = "ICT,xiangshan", "riscv"; + device_type = "cpu"; + reg = <0>; + status = "okay"; + mmu-type = "riscv,sv48"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = + "i", "m", "a", "f", "d", "c", "h", + "smstateen", "sscofpmf", "sstc", "zicntr", "zihpm", + "svpbmt", "sdtrig", "smcsrind", "sscsrind", "svade"; + + intc_cpu0: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-block-size = <64>; + cache-size = <1048576>; + }; + + memory: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x4 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "freechips,rocketchip-unknown-soc", "simple-bus"; + ranges; + + clint: clint@38000000 { + compatible = "riscv,clint0"; + reg = <0x0 0x38000000 0x0 0x10000>; + reg-names = "control"; + interrupts-extended = <&intc_cpu0 3 &intc_cpu0 7>; + }; + + PLIC: interrupt-controller@3c000000 { + compatible = "riscv,plic0"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x0 0x3c000000 0x0 0x4000000>; + reg-names = "control"; + interrupts-extended = <&intc_cpu0 11 &intc_cpu0 9>; + riscv,max-priority = <7>; + riscv,ndev = <66>; + }; + + uart0: serial@310b0000 { + compatible = "ns16550a"; + reg = <0x0 0x310b0000 0x0 0x10000>; + reg-shift = <0x2>; + reg-io-width = <0x4>; + clock-frequency = <50000000>; + current-speed = <115200>; + status = "okay"; + }; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "console=hvc0 earlycon=sbi loglevel=8"; + stdout-path = "serial0:115200n8"; + linux,initrd-start = ; + linux,initrd-end = ; + + opensbi-config { + compatible = "opensbi,config"; + cold-boot-harts = <&cpu0>; + }; + }; +}; diff --git a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in index 0a49655..b688437 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem24g.dts.in b/dts/xiangshan-fpga-noAIA-mem24g.dts.in index 74e3688..ca23fff 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in index 910c148..46a081f 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem64g.dts.in b/dts/xiangshan-fpga-noAIA-mem64g.dts.in index 9d866bc..51b4741 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in index ef92f24..db76ca8 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-mem8g.dts.in b/dts/xiangshan-fpga-noAIA-mem8g.dts.in index 2a79165..6e4a902 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA-novec.dts.in b/dts/xiangshan-fpga-noAIA-novec.dts.in index 02e5682..39888f9 100644 --- a/dts/xiangshan-fpga-noAIA-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-novec.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/dts/xiangshan-fpga-noAIA.dts.in b/dts/xiangshan-fpga-noAIA.dts.in index bb26306..f9699c8 100644 --- a/dts/xiangshan-fpga-noAIA.dts.in +++ b/dts/xiangshan-fpga-noAIA.dts.in @@ -50,7 +50,7 @@ "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smcsrind", "smdbltrp", - "smmpm", "smnpm", "smrnmi", "smstateen", + "smmpm", "smnpm", "smstateen", "ss1p13", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", @@ -58,7 +58,7 @@ "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", + "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", diff --git a/scripts/generate-xiangshan-multihart-dts.py b/scripts/generate-xiangshan-multihart-dts.py index c4eddf7..fd889f2 100755 --- a/scripts/generate-xiangshan-multihart-dts.py +++ b/scripts/generate-xiangshan-multihart-dts.py @@ -5,7 +5,7 @@ MULTIHART_RISCV_ISA = ( - "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_" + "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_" "sdtrig_smcsrind_sscsrind_svade" ) MULTIHART_CPU_ISA_PROPERTIES = f"""\ @@ -16,10 +16,10 @@ \t\t\t\t"sdtrig", "sha", "shcounterenw", "shgatpa", \t\t\t\t"shlcofideleg", "shtvala", "shvsatpa", "shvstvala", \t\t\t\t"shvstvecd", "smcsrind", "smdbltrp", -\t\t\t\t"smmpm", "smnpm", "smrnmi", "smstateen", +\t\t\t\t"smmpm", "smnpm", "smstateen", \t\t\t\t"ss1p13", "ssccptr", "sscofpmf", \t\t\t\t"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", -\t\t\t\t"sspm", "ssstateen", "ssstrict", "sstc", +\t\t\t\t"sspm", "ssstateen", "ssstrict", \t\t\t\t"sstvala", "sstvecd", "ssu64xl", "supm", \t\t\t\t"sv39", "sv48", "svade", "svbare", "svinval", \t\t\t\t"svnapot", "svpbmt", "za64rs", "zacas", "zawrs", @@ -60,6 +60,16 @@ def positive_harts(value): return harts +def positive_memory_gib(value): + try: + memory_gib = int(value, 0) + except ValueError as exc: + raise argparse.ArgumentTypeError("memory-gib must be an integer") from exc + if memory_gib <= 0: + raise argparse.ArgumentTypeError("memory-gib must be greater than zero") + return memory_gib + + def extract_node(text, node_header): start = text.index(node_header) level = 0 @@ -168,7 +178,35 @@ def add_checkpoint_reserved_memory(text): return text[:close] + CHECKPOINT_RESERVED_NODE + text[close:] -def render(base_text, harts): +def override_memory_profile(text, memory_gib): + start, end = extract_node(text, "\tmemory: memory@80000000 {") + memory_node = text[start:end] + memory_bytes = memory_gib << 30 + size_high = memory_bytes >> 32 + size_low = memory_bytes & 0xFFFFFFFF + if size_high > 0xFFFFFFFF: + raise RuntimeError("memory-gib does not fit in a 64-bit DTS size") + + memory_node, comment_replacements = re.subn( + r"\t\t/\*\n(?:\t\t \*.*\n)+\t\t \*/(?=\n\t\treg)", + "\t\t/*\n" + f"\t\t * Static {memory_gib} GiB memory profile for multi-hart workloads.\n" + "\t\t */", + memory_node, + count=1, + ) + memory_node, reg_replacements = re.subn( + r"reg = <0x0 0x80000000 0x[0-9a-fA-F]+ 0x[0-9a-fA-F]+>;", + f"reg = <0x0 0x80000000 0x{size_high:x} 0x{size_low:08x}>;", + memory_node, + count=1, + ) + if comment_replacements != 1 or reg_replacements != 1: + raise RuntimeError("memory node does not contain the expected static profile") + return text[:start] + memory_node + text[end:] + + +def render(base_text, harts, memory_gib=None): start, end = extract_node(base_text, "\t\tcpu0: cpu@0 {") cpu0_node = normalize_cpu_isa(base_text[start:end]) extra_cpus = "".join("\n\n" + cpu_node(cpu0_node, hart) for hart in range(1, harts)) @@ -190,6 +228,8 @@ def render(base_text, harts): text = replace_fpga_uart_with_nemu_uartlite(text) text = sanitize_nemu_uart_comments(text) text = add_checkpoint_reserved_memory(text) + if memory_gib is not None: + text = override_memory_profile(text, memory_gib) return text @@ -197,12 +237,15 @@ def main(): parser = argparse.ArgumentParser() parser.add_argument("--base", required=True, type=Path) parser.add_argument("--harts", required=True, type=positive_harts) + parser.add_argument("--memory-gib", type=positive_memory_gib) parser.add_argument("--output", required=True, type=Path) args = parser.parse_args() base_text = args.base.read_text(encoding="utf-8") args.output.parent.mkdir(parents=True, exist_ok=True) - args.output.write_text(render(base_text, args.harts), encoding="utf-8") + args.output.write_text( + render(base_text, args.harts, memory_gib=args.memory_gib), encoding="utf-8" + ) if __name__ == "__main__":