diff --git a/.github/SUPPORT.md b/.github/SUPPORT.md new file mode 100644 index 000000000..7615c1e82 --- /dev/null +++ b/.github/SUPPORT.md @@ -0,0 +1,3 @@ +# Getting help with QICK + +For ways to get in touch with developers and members of the QICK community, see the [contact page](https://qick-docs.readthedocs.io/latest/contact.html) on our Read the Docs site. diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..c563e9120 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,14 @@ +# To get started with Dependabot version updates, you'll need to specify which +# package ecosystems to update and where the package manifests are located. +# Please see the documentation for all configuration options: +# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file + +version: 2 +updates: + # Enable version updates for GitHub Actions + - package-ecosystem: "github-actions" + # Workflow files stored in the default location of `.github/workflows` + # You don't need to specify `/.github/workflows` for `directory`. You can use `directory: "/"`. + directory: "/" + schedule: + interval: "weekly" diff --git a/.github/workflows/test_zcu111.yml b/.github/workflows/test_zcu111.yml new file mode 100644 index 000000000..2e982bced --- /dev/null +++ b/.github/workflows/test_zcu111.yml @@ -0,0 +1,48 @@ +# Install the QICK library on the runner (a QICK board) and run tests. +# The FPGA can only be accessed as root, so the tests must run with sudo. +# This pollutes the repo with files owned by root, which interfere with the "clean" step in the checkout action. +# We therefore do the clean manually (with sudo) before checkout. + +name: Test ZCU111 + +on: + workflow_dispatch: + pull_request: + paths: + - 'qick_demos/**' + - 'qick_lib/**' + - '**.py' + - '!qick_lib/qick/VERSION' + +permissions: + contents: write + +jobs: + run_test: + runs-on: [zcu111] + steps: + - name: Clean repo + continue-on-error: true + run: | + sudo git clean -ffdx + sudo git reset --hard HEAD + - uses: actions/checkout@v7 + - name: Install package + run: | + sudo -E -H python -m pip install -e . + - name: Test notebooks + run: | + sudo -E python -m pytest --nbmake --overwrite ./qick_demos/00_Send_receive_pulse.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/01_Phase_coherent_readout.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/02_Sweeping_variables.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/03_Conditional_logic.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/04_Reading_Math_Writing.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/05_PhaseCoherence_QickProgram.ipynb + # sudo -E python -m pytest --nbmake ./qick_demos/06_qubit_demos.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/07_Sweep_ND_variables.ipynb + sudo -E python -m pytest --nbmake ./qick_demos/08_Special_buffers.ipynb + - name: Archive test results + uses: actions/upload-artifact@v7 + with: + name: demo_notebooks + path: qick_demos/*.ipynb diff --git a/.github/workflows/update_version.yml b/.github/workflows/update_version.yml new file mode 100644 index 000000000..8fc23a8cf --- /dev/null +++ b/.github/workflows/update_version.yml @@ -0,0 +1,120 @@ +# Automatically update the package version. +# The version has the format major.minor.PR, where PR is the number of the most recent pull request. +# This action runs automatically when a pull request is opened, or a commit is added to an open pull request. +# https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target +# +# It checks the version number against the PR number; if it does not match, the version number is updated in a new commit. +# The commit will be credited to the GitHub Actions user. +# https://github.com/orgs/community/discussions/26560#discussioncomment-3252339 +# +# We need write access, which is only available using the pull_request_target trigger. +# It is dangerous to have write access at the same time that you are checking out untrusted code from a PR. +# However, we are only extracting a version number and (possibly) committing a new version number back to the PR, which is relatively safe. +# In other words, we are doing a bad thing ("pull_request_target with an explicit PR checkout") but our workflow is safe ("Reformat and commit the code"): +# https://securitylab.github.com/research/github-actions-preventing-pwn-requests/ +# +# If you don't want this action to run (e.g. if you want a different version number for a certain PR), include [skip actions] in the commit message. +# https://docs.github.com/en/actions/managing-workflow-runs/skipping-workflow-runs +# +# If we make a new commit in this action, the action doesn't get run on the new commit (not sure why, actually). +# This is a problem if we want to use this as a status check. +# The workaround is to manually apply the status at the end: ugly! +# Using: https://docs.github.com/en/rest/commits/statuses?apiVersion=2022-11-28#create-a-commit-status +# +# Because this action uses the pull_request_target trigger, it's exempt from the workflow approval rules and will run automatically regardless of the submitter: +# https://docs.github.com/en/actions/managing-workflow-runs/approving-workflow-runs-from-public-forks#about-workflow-runs-from-public-forks + +name: Update version + +on: + pull_request_target: + types: [opened, reopened, synchronize] + branches: + - main + +permissions: + contents: write + pull-requests: write + statuses: write + checks: write + +jobs: + update_version: + runs-on: ubuntu-latest + env: + PR_NUMBER: ${{ github.event.pull_request.number }} + GH_TOKEN: ${{ github.token }} + VERSION_PATH: qick_lib/qick/VERSION + CHECK_TOKEN: ${{ secrets.CHECK_TOKEN }} + steps: + - uses: actions/checkout@v7 + - name: Checkout pull request + run: gh pr checkout $PR_NUMBER + - name: Compare version numbers + run: | + file_version=$(cut -d '.' -f 3 "$VERSION_PATH") + echo "PR number: $PR_NUMBER, VERSION number: $file_version" + echo "file_version=$file_version" >> $GITHUB_ENV + - name: Debug + run: gh auth status + - name: Update VERSION if necessary + if: env.file_version != github.event.pull_request.number + run: | + echo "updating VERSION" + echo "$(cut -d '.' -f -2 $VERSION_PATH).$PR_NUMBER" > "$VERSION_PATH" + git config user.email "129547417+qickbot@users.noreply.github.com" + git config user.name "QICK actions [bot]" + git config push.default upstream + git add "$VERSION_PATH" + git commit -am "update version" + git push + repopath=$(git remote get-url origin|cut -d'/' -f4,5) + headpath=$(gh pr view --json headRepositoryOwner,headRepository -t '{{.headRepositoryOwner.login}}/{{.headRepository.name}}') + new_sha="$(git rev-parse HEAD)" + reporef="/repos/${repopath}/statuses/${new_sha}" + headref="/repos/${headpath}/statuses/${new_sha}" + echo "reporef=$reporef" >> $GITHUB_ENV + echo "headref=$headref" >> $GITHUB_ENV + - name: Set status for update commit using CLI and GITHUB_TOKEN, PR head path + continue-on-error: true + if: env.file_version != github.event.pull_request.number + run: | + gh api \ + --method POST \ + -H "Accept: application/vnd.github+json" \ + -H "X-GitHub-Api-Version: 2022-11-28" \ + "$headref" \ + -f state='success' \ + -f context='update_version' + - name: Set status for update commit using CLI and GITHUB_TOKEN, repo path + continue-on-error: true + if: env.file_version != github.event.pull_request.number + run: | + gh api \ + --method POST \ + -H "Accept: application/vnd.github+json" \ + -H "X-GitHub-Api-Version: 2022-11-28" \ + "$reporef" \ + -f state='success' \ + -f context='update_version' + - name: Set status for update commit using curl and PAT, PR head path + continue-on-error: true + if: env.file_version != github.event.pull_request.number + run: | + curl -L -X POST \ + -H "Accept: application/vnd.github+json" \ + -H "X-GitHub-Api-Version: 2022-11-28" \ + -H "Authorization: Bearer $CHECK_TOKEN" \ + "https://api.github.com${headref}" \ + -d '{"state":"success","context":"update_version"}' + - name: Set status for update commit using curl and PAT, repo path + continue-on-error: true + if: env.file_version != github.event.pull_request.number + run: | + repopath=$(git remote get-url origin|cut -d'/' -f4,5) + curl -L -X POST \ + -H "Accept: application/vnd.github+json" \ + -H "X-GitHub-Api-Version: 2022-11-28" \ + -H "Authorization: Bearer $CHECK_TOKEN" \ + "https://api.github.com${reporef}" \ + -d '{"state":"success","context":"update_version"}' diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml new file mode 100644 index 000000000..fbb482ef4 --- /dev/null +++ b/.github/workflows/wheels.yml @@ -0,0 +1,61 @@ +# Build a wheel and publish to PyPI when a pull request merges. +# https://packaging.python.org/en/latest/guides/publishing-package-distribution-releases-using-github-actions-ci-cd-workflows/ +# +# Based on https://github.com/orgs/community/discussions/26724#discussioncomment-3253102 we trigger this workflow on a push to main branch, and protect the main branch. +# +# We previously used the pull_request_target workflow trigger, but it seems that since sometime between January and March 2026 this no longer works with trusted publishing. +# How that used to work: +# +# We need access to the repo secrets, which are only available using the pull_request_target trigger. +# For security this requires us to use the repo HEAD and not the PR merge commit. +# But since this action only executes on merge, those are the same thing. +# https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target + +name: Build wheel + +on: + push: + branches: + - main + +permissions: + contents: read + pull-requests: read + +jobs: + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v7 + - name: Set up Python + uses: actions/setup-python@v6 + with: + python-version: "3.x" + - name: Build wheel + run: | + python -m pip install --user --upgrade pip build wheel + python -m build + - name: Store the distribution packages + uses: actions/upload-artifact@v7 + with: + name: python-package-distributions + path: dist/ + + publish-to-pypi: + needs: + - build + runs-on: ubuntu-latest + environment: + name: release + url: https://pypi.org/p/qick + permissions: + # IMPORTANT: this permission is mandatory for trusted publishing + id-token: write + steps: + - name: Download all the dists + uses: actions/download-artifact@v8 + with: + name: python-package-distributions + path: dist/ + - name: Publish distribution to PyPI + uses: pypa/gh-action-pypi-publish@release/v1 diff --git a/.gitignore b/.gitignore index 684a22351..823a81765 100644 --- a/.gitignore +++ b/.gitignore @@ -15,78 +15,11 @@ ipython_config.py # Remove previous ipynb_checkpoints # git rm -r .ipynb_checkpoints/ -### C template -# Prerequisites -*.d - -# Object files -*.o -*.ko -*.obj -*.elf - -# Linker output -*.ilk -*.map -*.exp - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf - -### C++ template -# Prerequisites - -# Compiled Object files -*.slo - -# Precompiled Headers - -# Compiled Dynamic libraries - -# Fortran module files -*.mod -*.smod - -# Compiled Static libraries -*.lai - -# Executables +# Vivado +.Xil/ +*.log +*.jou +vivado_pid*.str ### Python template # Byte-compiled / optimized / DLL files @@ -94,135 +27,18 @@ __pycache__/ *.py[cod] *$py.class -# C extensions - -# Distribution / packaging -.Python -build/ -develop-eggs/ -dist/ -downloads/ -eggs/ -.eggs/ -lib/ -lib64/ -parts/ -sdist/ -var/ -wheels/ -share/python-wheels/ +# pip *.egg-info/ .installed.cfg *.egg -MANIFEST - -# PyInstaller -# Usually these files are written by a python script from a template -# before PyInstaller builds the exe, so as to inject date/other infos into it. -*.manifest -*.spec - -# Installer logs -pip-log.txt -pip-delete-this-directory.txt - -# Unit test / coverage reports -htmlcov/ -.tox/ -.nox/ -.coverage -.coverage.* -.cache -nosetests.xml -coverage.xml -*.cover -*.py,cover -.hypothesis/ -.pytest_cache/ -cover/ - -# Translations -*.mo -*.pot - -# Django stuff: -*.log -local_settings.py -db.sqlite3 -db.sqlite3-journal - -# Flask stuff: -instance/ -.webassets-cache -# Scrapy stuff: -.scrapy +# Distribution / packaging +build/ +dist/ # Sphinx documentation docs/_build/ - -# PyBuilder -.pybuilder/ -target/ - -# Jupyter Notebook - -# IPython - -# pyenv -# For a library or package, you might want to ignore these files since the code is -# intended to run in multiple environments; otherwise, check them in: -# .python-version - -# pipenv -# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. -# However, in case of collaboration, if having platform-specific dependencies or dependencies -# having no cross-platform support, pipenv may install dependencies that don't work, or not -# install all needed dependencies. -#Pipfile.lock - -# PEP 582; used by e.g. github.com/David-OConnor/pyflow -__pypackages__/ - -# Celery stuff -celerybeat-schedule -celerybeat.pid - -# SageMath parsed files -*.sage.py - -# Environments -.env -.venv -env/ -venv/ -ENV/ -env.bak/ -venv.bak/ - -# Spyder project settings -.spyderproject -.spyproject - -# Rope project settings -.ropeproject - -# mkdocs documentation -/site - -# mypy -.mypy_cache/ -.dmypy.json -dmypy.json - -# Pyre type checker -.pyre/ - -# pytype static type analyzer -.pytype/ - -# Cython debug symbols -cython_debug/ +docs/_autosummary/ ### macOS template # General @@ -230,9 +46,6 @@ cython_debug/ .AppleDouble .LSOverride -# Icon must end with two \r -Icon - # Thumbnails ._* @@ -252,26 +65,9 @@ Network Trash Folder Temporary Items .apdisk -### Dropbox template -# Dropbox settings and caches -.dropbox -.dropbox.attr -.dropbox.cache - ### Linux template *~ +.*.swp -# temporary files which can be created if a process still has a handle open of a deleted file -.fuse_hidden* - -# KDE directory preferences -.directory - -# Linux trash folder which might appear on any partition or disk -.Trash-* - -# .nfs files are created when an open file is removed but is still being accessed -.nfs* -!/.gitignore !/.gitignore !/README.md diff --git a/.readthedocs.yaml b/.readthedocs.yaml new file mode 100644 index 000000000..ede209771 --- /dev/null +++ b/.readthedocs.yaml @@ -0,0 +1,23 @@ +# readthedocs.yml +# Read the Docs configuration file +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +# Required +version: 2 + +build: + os: ubuntu-22.04 + tools: + python: "3.7" + +# Build documentation in the docs/ directory with Sphinx +sphinx: + configuration: docs/conf.py + +# Optionally build your docs in additional formats such as PDF and ePub +formats: [] + +# Optionally set the version of Python and requirements required to build your docs +python: + install: + - requirements: docs/requirements.txt diff --git a/CITATION.cff b/CITATION.cff new file mode 100644 index 000000000..ab8426972 --- /dev/null +++ b/CITATION.cff @@ -0,0 +1,43 @@ +cff-version: 1.2.0 +# CITATION.cff created with https://github.com/monperrus/bibtexbrowser/ +preferred-citation: + title: "The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors" + doi: "10.1063/5.0076249" + year: "2022" + type: article + journal: "Review of Scientific Instruments" + authors: + - family-names: Stefanazzi + given-names: Leandro + - family-names: Treptow + given-names: Kenneth + - family-names: Wilcer + given-names: Neal + - family-names: Stoughton + given-names: Chris + - family-names: Bradford + given-names: Collin + - family-names: Uemura + given-names: Sho + - family-names: Zorzetti + given-names: Silvia + - family-names: Montella + given-names: Salvatore + - family-names: Cancelo + given-names: Gustavo + - family-names: Sussman + given-names: Sara + - family-names: Houck + given-names: Andrew + - family-names: Saxena + given-names: Shefali + - family-names: Arnaldi + given-names: Horacio + - family-names: Agrawal + given-names: Ankur + - family-names: Zhang + given-names: Helin + - family-names: Ding + given-names: Chunyang + - family-names: Schuster + given-names: David I. diff --git a/LICENSE b/LICENSE index 565945e56..b88b00ecc 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ MIT License -Copyright (c) 2021 Open Quantum Hardware +Copyright (c) Open Quantum Hardware Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -18,4 +18,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file +SOFTWARE. diff --git a/README.md b/README.md index 13d207b31..276a61ba8 100644 --- a/README.md +++ b/README.md @@ -5,46 +5,68 @@ # QICK: Quantum Instrumentation Control Kit -The QICK is a kit of firmware and software to use the Xilinx RFSoC as to control quantum systems. +QICK is an open-source qubit controller, consisting of firmware, software, and an optional frontend for use with Xilinx RFSoC development boards. +The goal of the project is to provide a powerful, flexible, cost-effective, and easy-to-learn platform for control and readout of a diverse range of quantum systems. -It consists of: -* Firmware for the ZCU111 RFSoC evaluation board. -* The `qick` Python package -* [A quick start guide](quick_start) for setting up your board and running a Jupyter notebook example -* [Jupyter notebook examples](qick_demos) demonstrating usage - -Note: The firmware and software here is still very much a work in progress. This is an alpha release. We strive to be consistent with the APIs but can not guarantee backwards compatibility. +QICK supports the ZCU111, ZCU216, and RFSoC4x2 development boards. +We generally recommend using the newer generation of RFSoCs (ZCU216 and RFSoC4x2) for better overall performance. +It consists of: +* Firmware for the supported RFSoC boards, both compiled bitstreams and source for the designs and modules +* The `qick` Python package, which includes the interface to the firmware and an API for writing QICK programs +* [Jupyter notebooks](qick_demos) demonstrating usage -Download and Installation -------------------------- +See our [Read the Docs site](https://docs.qick.dev/) for: +* Documentation of the firmware and software +* A [quick-start guide](https://docs.qick.dev/latest/quick_start.html) for setting up your board and running the example Jupyter notebooks +* [Ways to communicate](https://docs.qick.dev/latest/contact.html) with QICK developers and the community +* Extensions to QICK for added functionailty -Follow the quick start guide located [here](quick_start) to set up your board, install `qick` on your board, and run a Jupyter notebook example. +## Updates -Documentation -------------- +The QICK firmware and software is still very much a work in progress. +We strive to be consistent with the APIs but cannot guarantee backwards compatibility. -The documentation for QICK is available at: https://qick-docs.readthedocs.io/ +> [!NOTE] +> QICK does not yet support PYNQ v3.1. The QICK quick-start guide (linked above) lists the currently recommended PYNQ OS images for your SD card. -Related Packages ----------------- +Frequent updates to the QICK firmware and software are made as pull requests. +Each pull request will be documented with a description of the notable changes, including any changes that will require you to change your code. +We hope that this will help you decide whether or not to update your local code to the latest version. +We strive for, but cannot guarantee, bug-free and fully functional pull requests. +We also do not guarantee that the demo notebooks will keep pace with every pull request, though we make an effort to update the demos after major API changes. -There is one related package on Github: +Our version numbering follows the format major.minor.PR, where PR is the number of the most recently merged pull request. +This will result in the PR number often skipping values, and occasionally decreasing. +The tagged release of a new minor version will have the format major.minor.0. -Documentation source code: https://github.com/openquantumhardware/qick-docs +Tagged releases can be expected periodically. +We recommend that everyone should be using at least the most recent release. +We guarantee the following for releases: +* The demo notebooks will be compatible with the QICK library, and will follow our current best recommendations for writing QICK programs. +* The firmware images for all supported boards will be fully compatible with the library and the demo notebooks. +* Release notes will summarize the pull request notes and explain both breaking API changes (what you need to change in your code) and improvements (why you should move to the new release). +We recommend that you "watch" this repository on GitHub to get automatic notifications of pull requests and releases. -Contribute ----------- +## Contribute You are welcome to contribute to QICK development by forking this repository and sending pull requests. All contributions are expected to be consistent with [PEP 8 -- Style Guide for Python Code](https://www.python.org/dev/peps/pep-0008/). -License -------- -The QICK source code is licensed under the MIT license, which you can find in the LICENSE file. +We welcome bug reports and feature requests via GitHub Issues. + +## License + +The QICK source code is licensed under the MIT license, which you can find in the [LICENSE file](LICENSE). +You are free to use QICK, with or without modification, under the terms of this license. + The [QICK logo](graphics/logoQICK.svg) was designed by Dr. Christie Chiu. -You are free to use this software, with or without modification, provided that the conditions listed in the LICENSE file are satisfied. +### Open-Source Commitment +QICK is and will remain a fully open-source project under the MIT license. +Commercial partnerships or integration agreements with third-party companies do not change the licensing, governance, or availability of this project. +All QICK source code, including firmware, software, and documentation, will continue to be freely available in this repository, and the QICK developers will continue to support the community. +If you have questions or concerns, please don't hesitate to [reach out](https://docs.qick.dev/latest/contact.html). diff --git a/aws/README.md b/aws/README.md new file mode 100644 index 000000000..930a9bff8 --- /dev/null +++ b/aws/README.md @@ -0,0 +1,30 @@ +# SideQICK: AWS-based workload management for QICK + +SideQICK is a QICK interface to the [Cloud Queue for Quantum Devices](https://github.com/aws-samples/cloud-queue-for-quantum-devices), and was developed in collaboration with Amazon Web Services. + +The Cloud Queue for Quantum Devices is a cloud-based application for managing queues of workloads to be executed on quantum devices. +The application is composed of standard AWS services and can be deployed to an AWS account using the open-source code and instructions at https://github.com/aws-samples/cloud-queue-for-quantum-devices. +Once an instance of the application is deployed, its administrator can create queues for devices and user accounts for experimenters. + +Users use SideQICK to submit workloads (sets of programs to be executed by the QICK) to a queue, from which the QICK downloads them. +The QICK uploads results back to the queue, from which users can retrieve them at any time. +Workloads and results are stored securely and resiliently in AWS cloud storage. +SideQICK allows a QICK-based system to be shared with users anywhere in the world without allowing full remote access. + +SideQICK provides two components which interface to the Cloud Queue application: +* A "user client," which is a library and CLI tool that you run on your computer to make requests to the cloud application. This is used for admin operations (adding new devices or users to the application) or queue operations (Python access to workloads as an alternative to the web UI). The user client also includes a WorkloadManager class which can be used to encapsulate QickPrograms into a workload and process the results. +* A "device client," which is a systemd service that runs on the QICK board and executes workloads downloaded from a cloud queue. + +See the [demo notebook](aws_demo.ipynb) for an example of the user client in operation. + +## User client setup (as an admin) +As part of the Cloud Queue application setup, you will have obtained a set of URLs and IDs for the application, and created an admin user with an e-mail address. +Copy the [config.template](config.template) file to `~/.config/qick.conf` or `/etc/qick/config`, and fill out the `[service]` and `[user]` blocks with those parameters. + +## User client setup (as a user) +An admin will provide config parameters, to be copied to `~/.config/qick.conf` or `/etc/qick/config` on your computer. + +## Installing the device client +An admin will provide config and credentials parameters for your device, to be copied to `/etc/qick/config` and `/etc/qick/credentials` on the QICK board. + +* Follow instructions in [qick.service](qick.service) to install the systemd service. diff --git a/aws/aws_demo.ipynb b/aws/aws_demo.ipynb new file mode 100644 index 000000000..4021165f8 --- /dev/null +++ b/aws/aws_demo.ipynb @@ -0,0 +1,767 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "2bba5f04", + "metadata": {}, + "source": [ + "# SideQICK demo notebook\n", + "This was used for the demo presentation on 2022-11-30." + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "id": "valid-turning", + "metadata": {}, + "outputs": [ + { + "data": { + "application/javascript": [ + "\n", + "try {\n", + "require(['notebook/js/codecell'], function(codecell) {\n", + " codecell.CodeCell.options_default.highlight_modes[\n", + " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", + " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", + " Jupyter.notebook.get_cells().map(function(cell){\n", + " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", + " });\n", + "});\n", + "} catch (e) {};\n" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "data": { + "application/javascript": [ + "\n", + "try {\n", + "require(['notebook/js/codecell'], function(codecell) {\n", + " codecell.CodeCell.options_default.highlight_modes[\n", + " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", + " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", + " Jupyter.notebook.get_cells().map(function(cell){\n", + " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", + " });\n", + "});\n", + "} catch (e) {};\n" + ] + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Could not import QickSoc: name 'xrfdc' is not defined\n", + "Populating the interactive namespace from numpy and matplotlib\n" + ] + } + ], + "source": [ + "# Import the QICK drivers and auxiliary libraries\n", + "from qick import *\n", + "from user_client import UserClient, WorkloadManager\n", + "from tqdm.auto import tqdm\n", + "%pylab inline" + ] + }, + { + "cell_type": "markdown", + "id": "eaec3057", + "metadata": {}, + "source": [ + "## Set up initial configuration\n", + "You should have a config file in ~/.config/qick.conf.admin with admin credentials, which we will use to create the demo device and user." + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "id": "baking-brazil", + "metadata": {}, + "outputs": [], + "source": [ + "!rm ~/.cache/qick.tokens\n", + "# use admin config for the setup steps\n", + "!cp ~/.config/qick.conf.admin ~/.config/qick.conf\n", + "# start new client\n", + "client = UserClient()" + ] + }, + { + "cell_type": "markdown", + "id": "familiar-custody", + "metadata": {}, + "source": [ + "## add a device (and start the device client)" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "id": "sweet-chuck", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "initial auth for admin@example.com:\n", + "········\n", + "Device successfully added!\n", + "\n", + "Put the following in the config file /etc/qick/config:\n", + "[service]\n", + "api_url = [REDACTED]\n", + "oauth_url = [REDACTED]\n", + "[device]\n", + "name = QICK Demo Device AAA\n", + "id = [REDACTED]\n", + "\n", + "If using UserClient for workload submission, the [device] block is needed in the client config as well.\n", + "\n", + "Put the following in the device credentials file /etc/qick/credentials:\n", + "[credentials]\n", + "id = [REDACTED]\n", + "secret = [REDACTED]\n" + ] + } + ], + "source": [ + "client.add_device(\"QICK Demo Device\")\n", + "\n", + "# this is equivalent:\n", + "# ./user_client.py add_device \"QICK Demo Device\"" + ] + }, + { + "cell_type": "markdown", + "id": "sitting-diamond", + "metadata": {}, + "source": [ + "## add a user (and log in to the web UI)\n", + "You should of course use a real e-mail address, since a temporary password will be sent there." + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "id": "posted-humanity", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "User successfully added! They should check their e-mail for a temporary password.\n", + "\n", + "They should put the following in ~/.config/qick.conf:\n", + "[service]\n", + "api_url = [REDACTED]\n", + "cognito_url = [REDACTED]\n", + "cognito_clientid = [REDACTED]\n", + "cognito_userpool = [REDACTED]\n", + "[user]\n", + "username = name@example.com\n" + ] + } + ], + "source": [ + "client.add_user(\"name@example.com\", \"Demo User\")\n", + "\n", + "# this is equivalent:\n", + "# ./user_client.py add_user name@example.com \"Demo User\"" + ] + }, + { + "cell_type": "markdown", + "id": "anticipated-toolbox", + "metadata": {}, + "source": [ + "## define the QICK program and the workload" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "id": "cloudy-double", + "metadata": {}, + "outputs": [], + "source": [ + "class FSGenLoopbackProgram(AveragerProgram):\n", + " def initialize(self):\n", + " cfg = self.cfg\n", + " style = cfg['style']\n", + " for iCh, ch in enumerate(cfg[\"gen_chs\"]): # configure the pulse lengths and upconversion frequencies\n", + " length_gen = self.us2cycles(cfg['length'], gen_ch=ch)\n", + " self.declare_gen(ch=ch, nqz=cfg['nqz'][iCh], ro_ch=cfg[\"ro_chs\"][0])\n", + " \n", + " self.default_pulse_registers(ch=ch, \n", + " freq=self.freq2reg(cfg['pulse_freq'],gen_ch=ch,ro_ch=cfg[\"ro_chs\"][0]),\n", + " gain=cfg['pulse_gain'],\n", + " phase=0)\n", + "\n", + " if style == \"const\":\n", + " self.set_pulse_registers(ch=ch, style=style, length=length_gen)\n", + " elif style == \"arb\":\n", + " self.add_gauss(ch=ch, name=\"measure\", sigma=length_gen/5, length=length_gen)\n", + " self.set_pulse_registers(ch=ch, style=style, waveform=\"measure\")\n", + "\n", + " for iCh, ch in enumerate(cfg[\"ro_chs\"]): # configure the readout lengths and downconversion frequencies\n", + " length_ro = self.us2cycles(cfg['length']+cfg['readout_padding'], ro_ch=ch)\n", + " \n", + " self.declare_readout(ch=ch, freq=cfg[\"pulse_freq\"],\n", + " length=length_ro,\n", + " gen_ch=cfg[\"gen_chs\"][0])\n", + "\n", + " self.synci(200) # give processor some time to configure pulses\n", + "\n", + " def body(self):\n", + " self.measure(pulse_ch=self.cfg[\"gen_chs\"],\n", + " adcs=self.ro_chs,\n", + " pins=[0], \n", + " adc_trig_offset=self.us2cycles(self.cfg[\"adc_trig_offset\"]-0.5*self.cfg['readout_padding']),\n", + " wait=True,\n", + " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", + "\n", + " \n", + "def noise(raw, length):\n", + " \"\"\"Helper function for analysis\n", + " \"\"\"\n", + " diq = np.dot(raw, np.array([1,1j]))/length\n", + " dmean = np.mean(diq,axis=1)\n", + " dmag = np.abs(dmean)\n", + " drotated = diq*np.exp(-1j*np.angle(dmean))[:,np.newaxis]\n", + " drmsmag = np.std(np.real(drotated),axis=1) # noise in the radial direction\n", + " drmsrot = np.std(np.imag(drotated), axis=1) # noise in the azimuth direction\n", + " return drmsmag, drmsrot\n", + "\n", + "class SweepWorkload(WorkloadManager):\n", + " def __init__(self, soccfg, start, stop, n_pts):\n", + " self.freqs = np.linspace(start=start, stop=stop, num=n_pts)\n", + " self.amps = np.zeros((n_pts,2))\n", + " self.noises_amp = np.zeros((n_pts,2))\n", + " self.noises_pha = np.zeros((n_pts,2))\n", + " \n", + " self.config = {\n", + " 'gen_chs': [0,4],\n", + " 'ro_chs': [0,1],\n", + " 'nqz': [1,2],\n", + " 'style': 'const',\n", + " 'pulse_gain': 32000,\n", + " 'adc_trig_offset': 0.45,\n", + " 'length': 4,\n", + " 'readout_padding': -0.1,\n", + " 'relax_delay': 1,\n", + " 'reps': 1000,\n", + " 'rounds': 1,\n", + " }\n", + " self.dec_config = {\n", + " 'pulse_freq': 4000,\n", + " 'length': 1,\n", + " 'readout_padding': 0.1,\n", + " 'reps': 1,\n", + " 'soft_avgs': 1000\n", + " }\n", + " super().__init__(soccfg)\n", + " \n", + " def do_stuff(self, make_progs=False, write_progs=False, read_results=False):\n", + " if make_progs:\n", + " # create and add a program\n", + " prog = FSGenLoopbackProgram(self.soccfg, {**self.config, **self.dec_config})\n", + " self.add_program(prog)\n", + " else:\n", + " prog = next(self.prog_iterator)\n", + " if write_progs:\n", + " # now call add_acquire\n", + " self.add_decimated(prog)\n", + " if read_results:\n", + " res = next(self.result_iterator)\n", + " # now do something with \"res\"\n", + " self.dec = res[\"dec\"][...]\n", + " self.dec_t = prog.cycles2us(np.arange(self.dec.shape[1]), ro_ch=self.config['ro_chs'][0])\n", + " \n", + " for i, f in tqdm(list(enumerate(self.freqs))):\n", + " self.config['pulse_freq'] = f\n", + " if make_progs:\n", + " # create and add a program\n", + " prog = FSGenLoopbackProgram(self.soccfg, self.config)\n", + " self.add_program(prog)\n", + " else:\n", + " prog = next(self.prog_iterator)\n", + " if write_progs:\n", + " # now call add_acquire\n", + " self.add_acquire(prog, save_raw=True)\n", + " if read_results:\n", + " res = next(self.result_iterator)\n", + " # now do something with \"res\"\n", + " avg = res[\"avg\"][...]\n", + " raw = res[\"raw\"][...]\n", + " self.amps[i] = np.abs(avg[:,0,:].dot(np.array([1,1j])))\n", + " noise_amp, noise_pha = noise(raw, prog.ro_chs[0]['length'])\n", + " self.noises_amp[i] = noise_amp\n", + " self.noises_pha[i] = noise_pha\n", + " \n", + " def display(self):\n", + " fig, axs = plt.subplots(4,1,figsize=(10,20))\n", + " for ii, iq in enumerate(self.dec):\n", + " plot = axs[2*ii]\n", + " plot.plot(self.dec_t, iq[:,0], label=\"I value, ADC %d\"%(self.config['ro_chs'][ii]))\n", + " plot.plot(self.dec_t, iq[:,1], label=\"Q value, ADC %d\"%(self.config['ro_chs'][ii]))\n", + " plot.plot(self.dec_t, np.abs(iq.dot([1, 1j])), label=\"mag, ADC %d\"%(self.config['ro_chs'][ii]))\n", + " plot.set_ylabel(\"a.u.\")\n", + " plot.set_xlabel(\"Time [us]\")\n", + " plot.set_title(\"Averages = \" + str(self.dec_config[\"soft_avgs\"]))\n", + " plot.legend()\n", + "\n", + " plot = axs[2*ii+1]\n", + " plot.semilogy(self.freqs, self.amps[:,ii], label=\"mean\")\n", + " plot.semilogy(self.freqs, self.noises_amp[:,ii], label=\"amplitude noise\")\n", + " plot.semilogy(self.freqs, self.noises_pha[:,ii], label=\"phase noise\")\n", + " plot.set_ylabel(\"avg a.u.\")\n", + " plot.set_xlabel(\"Frequency [MHz]\")\n", + " plot.set_title(\"Averages = \" + str(self.config[\"reps\"]))\n", + " plot.legend()" + ] + }, + { + "cell_type": "markdown", + "id": "optional-evolution", + "metadata": {}, + "source": [ + "## Manual upload and download (using WorkloadManager class, but not UserClient)" + ] + }, + { + "cell_type": "code", + "execution_count": 6, + "id": "purple-isolation", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "\n", + "QICK configuration:\n", + "\n", + "\tBoard: ZCU216\n", + "\n", + "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", + "\n", + "\t7 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\n", + "\t2 readout channels:\n", + "\t0:\taxis_readout_v2 - controlled by PYNQ\n", + "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", + "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", + "\t1:\taxis_readout_v2 - controlled by PYNQ\n", + "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", + "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", + "\n", + "\t7 DACs:\n", + "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", + "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", + "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", + "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", + "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", + "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", + "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", + "\n", + "\t2 ADCs:\n", + "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", + "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", + "\n", + "\t8 digital output pins (tProc output 0):\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: program memory 8192 words, data memory 4096 words\n", + "\t\texternal start pin: PMOD1_0_LS\n" + ] + } + ], + "source": [ + "import json\n", + "with open('/home/meeg/Downloads/664279d8-f236-4e28-83f4-27cce968d643-configuration.json', 'rt') as f:\n", + " soccfg = QickConfig(json.load(f))\n", + "print(soccfg)" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "id": "norman-poverty", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "initializing WorkloadManager:\n" + ] + }, + { + "data": { + "application/vnd.jupyter.widget-view+json": { + "model_id": "b060e9cbeacc40f2a91388105bb3c9af", + "version_major": 2, + "version_minor": 0 + }, + "text/plain": [ + " 0%| | 0/1001 [00:00" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "print(\"reading results:\")\n", + "with open('/home/meeg/Downloads/3707e60f-365b-40e8-b759-8942554ac96c-output', 'rb') as resultsfile:\n", + " expt.read_results(resultsfile)\n", + "\n", + "print(\"plotting results\")\n", + "expt.display()" + ] + }, + { + "cell_type": "markdown", + "id": "intellectual-solid", + "metadata": {}, + "source": [ + "## Using UserClient to upload work and download results" + ] + }, + { + "cell_type": "code", + "execution_count": 9, + "id": "permanent-festival", + "metadata": {}, + "outputs": [], + "source": [ + "# start new client\n", + "client = UserClient()" + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "id": "widespread-winner", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "initial auth for [REDACTED]:\n", + "········\n", + "\n", + "QICK configuration:\n", + "\n", + "\tBoard: ZCU216\n", + "\n", + "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", + "\n", + "\t7 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", + "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", + "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", + "\n", + "\t2 readout channels:\n", + "\t0:\taxis_readout_v2 - controlled by PYNQ\n", + "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", + "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", + "\t1:\taxis_readout_v2 - controlled by PYNQ\n", + "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", + "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", + "\n", + "\t7 DACs:\n", + "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", + "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", + "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", + "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", + "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", + "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", + "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", + "\n", + "\t2 ADCs:\n", + "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", + "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", + "\n", + "\t8 digital output pins (tProc output 0):\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: program memory 8192 words, data memory 4096 words\n", + "\t\texternal start pin: PMOD1_0_LS\n" + ] + } + ], + "source": [ + "# download QICK configuration\n", + "soccfg = QickConfig(client.get_soccfg())\n", + "print(soccfg)" + ] + }, + { + "cell_type": "code", + "execution_count": 11, + "id": "governing-presentation", + "metadata": { + "scrolled": false + }, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "initializing WorkloadManager:\n" + ] + }, + { + "data": { + "application/vnd.jupyter.widget-view+json": { + "model_id": "dcef4b8164844555804656badf2f34af", + "version_major": 2, + "version_minor": 0 + }, + "text/plain": [ + " 0%| | 0/1001 [00:00" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "print(\"initializing WorkloadManager:\")\n", + "expt = SweepWorkload(soccfg, start=1, stop=10000, n_pts=1001)\n", + "\n", + "print(\"writing programs to workload file:\")\n", + "with expt.write_progs() as workloadfile:\n", + " print(\"submitting workload:\")\n", + " work_id = client.create_work(workloadfile, priority=\"LOW\")\n", + "print(\"workload is submitted, work ID \" + work_id)\n", + "\n", + "client.wait_until_done(work_id, progress=True)\n", + "\n", + "print(\"reading results:\")\n", + "with client.get_results(work_id) as resultsfile:\n", + " expt.read_results(resultsfile)\n", + "\n", + "print(\"plotting results\")\n", + "expt.display()" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.9.2" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/aws/config.template b/aws/config.template new file mode 100644 index 000000000..ff9e25540 --- /dev/null +++ b/aws/config.template @@ -0,0 +1,31 @@ +# This is the QICK client config file. +# Because the device and user clients use a lot of the same parameters, the same config file can be used for both. +# Not all parameters are needed in all cases. +# +# The user client will check for this file in the following locations (in order): +# ~/.config/qick.conf +# /etc/qick/config +# +# The device client requires this file to be in /etc/qick/config. + +# needed for device and user clients +[service] +# only for user client +cognito_userpool = +cognito_url = +clientid = +# only for device client and device registration +oauth_endpoint = +# for all clients +api_endpoint = + +# needed for user client +[user] +username = + +# needed for device client +[device] +id = +# not needed, but useful to put here as a reminder of what device the ID corresponds to +name = + diff --git a/aws/qick.service b/aws/qick.service new file mode 100644 index 000000000..4f13bbb7b --- /dev/null +++ b/aws/qick.service @@ -0,0 +1,23 @@ +[Unit] +Description=QICK service +After=multi-user.target + +[Service] +Type=forking +ExecStart=/home/xilinx/jupyter_notebooks/qick/aws/start_qick_client.sh +PIDFile=/tmp/qick.pid +#Restart=always +#RestartSec=5 + +[Install] +WantedBy=multi-user.target + +# Note the ExecStart parameter must point to the actual location of the start script. +# +# The service can then be installed by doing: +# +# sudo cp qick.service /etc/systemd/system/ +# sudo systemctl daemon-reload +# sudo systemctl enable qick +# sudo systemctl start qick +# sudo systemctl status qick diff --git a/aws/qick_client.py b/aws/qick_client.py new file mode 100755 index 000000000..2623c9d93 --- /dev/null +++ b/aws/qick_client.py @@ -0,0 +1,267 @@ +#!/usr/bin/env python3 +import logging +import argparse +import requests +import multiprocessing +import json +import tempfile +import shutil +import sys +import time +import gzip +import h5py +from oauthlib.oauth2 import BackendApplicationClient +from requests_oauthlib import OAuth2Session +from configparser import ConfigParser +try: + from qick import QickSoc, QickProgram + from qick.helpers import json2progs +except: + pass + +class DummySoc: + def __init__(self): + self._cfg = {"cfg_a": "foo"} + + def get_cfg(self): + return self._cfg + + def dump_cfg(self): + return json.dumps(self._cfg, indent=4) + +class RefetchSession(OAuth2Session): + # requests-oauthlib doesn't support automatically requesting a new token in the "client credentials" flow: + # https://stackoverflow.com/questions/58697334/requests-oauthlib-auto-refresh-bearer-token-in-client-credentials-flow + # this workaround is based on this: + # https://github.com/requests/requests-oauthlib/issues/260 + def __init__(self, **kwargs): + super().__init__(**kwargs) + # define a no-op token_updater + self.token_updater = lambda token: None + + def fetch_token(self, token_url, **kwargs): + # cache the client secret (which is normally not stored) + self._client_secret = kwargs['client_secret'] + # copy token_url to auto_refresh_url (which could be passed in the constructor, but this is easier) + self.auto_refresh_url = token_url + return super().fetch_token(token_url, **kwargs) + + def refresh_token(self, token_url, **kwargs): + # use the previously cached client secret to fetch a fresh token + return super().fetch_token(token_url, client_id=self.client_id, client_secret=self._client_secret) + + +class QickClient: + + def __init__(self, api_endpoint, dummy_mode=False): + self.api_endpoint = api_endpoint + self.session = requests + self.cfg_path = "/etc/qick/config" + self.cred_path = "/etc/qick/credentials" + self.status = "ONLINE" + self.timeout = 24 * 60 * 60 # Run a workload for 24 hours max + if dummy_mode: + self.soc = DummySoc() + else: + self.soc = QickSoc() + + self.soccfg = self.soc.get_cfg() + + clientcfg = ConfigParser() + clientcfg.read(self.cfg_path) + + credcfg = ConfigParser() + credcfg.read(self.cred_path) + + if self.api_endpoint is None: + self.api_endpoint = clientcfg['service']['api_endpoint'] + token_url = clientcfg['service']['oauth_endpoint'] + + self.devid = clientcfg['device']['id'] + self.devname = clientcfg['device']['name'] + + # the OAuth ID is also used as the device ID + self.authid = credcfg['credentials']['id'] + client_secret = credcfg['credentials']['secret'] + + oauth_client = BackendApplicationClient(client_id=self.authid) + self.session = RefetchSession(client=oauth_client) + token = self.session.fetch_token(token_url=token_url+"/oauth2/token", client_id=self.authid, + client_secret=client_secret) + logging.info(f"Got OAuth2 token, expires in {token['expires_in']} seconds") + #force a token refetch + #oauth_client._expires_at -= 3700 + + + def _s3put(self, s3url, payload): + """payload can be byte string or open file handle + """ + rsp = requests.put(s3url, data=payload, headers={'Content-Type': 'application/octet-stream'}) + if rsp.status_code == 200: + logging.info(f"s3 upload success") + else: + logging.warning(f"s3 upload fail: {rsp.status_code}") + + def _s3get(self, s3url): + """return an open file handle + """ + with requests.get(s3url, stream=True) as rsp: + if rsp.status_code == 200: + getfile = tempfile.TemporaryFile() + shutil.copyfileobj(rsp.raw, getfile) + logging.info(f"s3 download success") + getfile.seek(0) + return getfile + else: + logging.warning(f"s3 download fail: {rsp.status_code}") + return None + + def update_status(self, update_config=False): + """ + Send the updated device status to the service. This is used as a heartbeat. + """ + data = { + "DeviceStatus": self.status, + "DeviceConfigurationFileExtension": "json" + } + rsp = self.session.put(self.api_endpoint + "/devices/" + self.devid, json=data) + if rsp.status_code == 200: + logging.info(f"UpdateDevice with status {data['DeviceStatus']}") + logging.debug(f"UpdateDevice request: {data}") + rsp = rsp.json() + logging.debug(f"UpdateDevice response: {rsp}") + #logging.info(f"ID check: {rsp['DeviceId']} {self.devid}") + # if you want to update the device config + if update_config: + logging.info(f"UpdateDevice: uploading soccfg") + self._s3put(rsp['UploadUrl'], json.dumps(self.soccfg)) + else: + logging.warning(f"UpdateDevice API error: {rsp.status_code}, {rsp.content}") + + def get_workload(self): + rsp = self.session.get(self.api_endpoint + "/devices/" + self.devid + "/workload") + if rsp.status_code == 200: + rsp = rsp.json() + logging.debug(f"GetDeviceWork response: {rsp}") + if not rsp: # if no workload is available, the response will be an empty list + logging.info(f"GetDeviceWork: no work for device") + return None + workid = rsp['WorkId'] + logging.info(f"GetDeviceWork: got work {workid}") + workurl = rsp['WorkloadUrl'] + try: + workfile = self._s3get(workurl) + return { + "id": workid, + "workload": workfile + } + except Exception as e: + logging.warning(f"GetDeviceWork S3 error: {e}") + return None + else: + logging.warning(f"GetDeviceWork API error: {rsp.status_code}, {rsp.content}") + return None + + def start_workload(self, workload): + self.resultsfile = tempfile.TemporaryFile() + logging.info("Started workload") + proc = multiprocessing.Process(target=self._run_workload, daemon=True, args=(self.soc, workload, self.resultsfile)) + proc.start() + return proc + + def _run_workload(self, soc, workfile, resultsfile): + + logging.info(f"Running workload") + #self.soc.run_workload(workload, resultsfile) + + if isinstance(soc, DummySoc): + workload = workfile.read() + workfile.close() + logging.info("DummySoc running workload: {workload}") + resultsfile.write(b"test") + resultsfile.seek(0) + time.sleep(10) + else: + with gzip.GzipFile(fileobj=workfile, mode='rb') as f: + proglist = json2progs(f) + logging.info(f"unpacked {len(proglist)} programs from workload") + with h5py.File(resultsfile,'w') as outf: + datagrp = outf.create_group("data", track_order=True) + newprog = QickProgram(soc) + for iProg, progdict in enumerate(proglist): + proggrp = datagrp.create_group(str(iProg)) + newprog.load_prog(progdict) + if progdict['acqtype']=='accumulated': + d_buf, d_avg, d_shots = newprog.acquire(soc, progress=False) + proggrp.create_dataset("avg", data=d_avg) + if progdict['save_raw']: + proggrp.create_dataset("raw", data=d_buf, compression="lzf") + if progdict['save_shots']: + proggrp.create_dataset("shots", data=d_shots, compression="lzf") + elif progdict['acqtype']=='decimated': + d_dec = newprog.acquire_decimated(soc, progress=False) + proggrp.create_dataset("dec", data=d_dec) + resultsfile.seek(0) + logging.info(f"Workload complete") + return + + def is_work_canceled(self, work_id): + # not yet implemented on the service + return False + #rsp = requests.get(self.api_endpoint + "/IsWorkCanceled") + #return rsp.json().get("IsCanceled") + + def upload_results(self, work_id): + self.resultsfile.seek(0) + logging.info(f"PutDeviceWork request for work {work_id}") + rsp = self.session.put(self.api_endpoint + "/devices/" + self.devid + "/workloads/" + work_id) + if rsp.status_code == 200: + rsp = rsp.json() + logging.debug(f"PutDeviceWork response: {rsp}") + try: + self._s3put(rsp['UploadUrl'], self.resultsfile) + logging.info("Uploaded results") + self.resultsfile.close() + except Exception as e: + logging.warning(f"PutDeviceWork S3 error: {e}") + else: + logging.warning(f"PutDeviceWork API error: {rsp.status_code}, {rsp.content}") + +if __name__ == "__main__": + #logging.getLogger().setLevel(logging.DEBUG) + logging.getLogger().setLevel(logging.INFO) + parser = argparse.ArgumentParser() + parser.add_argument("--api", type=str, default=None, help="URL of API endpoint") + parser.add_argument("-n", dest='interval', type=float, default=5.0, help="polling interval") + parser.add_argument("-d", action='store_true', help="run in dummy mode (use DummySoc instead of QickSoc)") + args = parser.parse_args() + + qick = QickClient(args.api, args.d) + + work = None + qick.update_status(update_config=True) + while True: + if qick.status == "ONLINE": + work = qick.get_workload() + if work: + qick.status = "BUSY" + work["process"] = qick.start_workload(work["workload"]) + work["timeout"] = time.time() + qick.timeout + time.sleep(args.interval) # sleep 5 seconds between polling + elif qick.status == "BUSY": + if qick.is_work_canceled(work["id"]) or time.time() > work["timeout"]: + logging.info("terminating workload due to cancel or timeout") + work["process"].terminate() + work["process"].join() + work["process"].close() + qick.upload_results(work["id"]) # upload partial results file + qick.status = "ONLINE" + elif not work["process"].is_alive(): + logging.info(f"workload completed, exit code {work['process'].exitcode}") + work["process"].close() + qick.upload_results(work["id"]) + time.sleep(args.interval) # sleep 5 seconds between polling TODO: this is a workaround + qick.status = "ONLINE" + else: + time.sleep(args.interval) # sleep 5 seconds between polling + qick.update_status() diff --git a/aws/start_qick_client.sh b/aws/start_qick_client.sh new file mode 100755 index 000000000..0828095db --- /dev/null +++ b/aws/start_qick_client.sh @@ -0,0 +1,12 @@ +#!/bin/bash +# environment setup copied from /usr/local/bin/start_jupyter.sh +set -a +. /etc/environment +set +a +for f in /etc/profile.d/*.sh; do source $f; done + +dir=`dirname $0` +$dir/qick_client.py & +pid=$! +echo $pid > /tmp/qick.pid + diff --git a/aws/user_client.py b/aws/user_client.py new file mode 100755 index 000000000..0c82a9386 --- /dev/null +++ b/aws/user_client.py @@ -0,0 +1,747 @@ +#!/usr/bin/env python3 +# standard libraries +import logging +import argparse +import json +import gzip +import base64 +import getpass +import time +import datetime +import sys +import os +from configparser import ConfigParser +import tempfile +import shutil +# dependencies +import requests +# CLI dependency - not needed for the rest of the library +try: + from fire import Fire +except: + pass +# WorkloadManager dependencies - not needed for UserClient +try: + import h5py + from qick.helpers import progs2json +except: + pass + +class CognitoAuth(requests.auth.AuthBase): + TOKEN_PATH = os.path.expanduser('~/.cache/qick.tokens') + def __init__(self): + self.auth_url = None + self.client_id = None + self.username = None + self.pool_id = None + self.tokens = None + self.expire_time = None + self.token_email = None + + if os.path.exists(self.TOKEN_PATH): + with open(self.TOKEN_PATH, 'rt') as f: + self.update_tokens(json.load(f), replace_tokens=True, write_tokens=False) + + def __call__(self, r): + """This is called by the Session to set auth headers. + """ + if self.tokens is None or self.token_email != self.username: + self.initial_auth() + + # if we have less than 60 seconds till expiry, refresh tokens + if self.expire_time - time.time() < 60: + try: + self.refresh_auth() + except: + # if anything goes wrong with refresh, re-auth from scratch + # this should cover expired refresh tokens + self.initial_auth() + + r.headers['Authorization'] = self.auth_header + return r + + def update_tokens(self, new_tokens, replace_tokens=False, write_tokens=True): + if replace_tokens or self.tokens is None: + self.tokens = new_tokens + else: + self.tokens.update(new_tokens) + + # unpack the JWT to get the expiry timestamp + # JWT uses unpadded base64, need to add dummy padding: + # https://stackoverflow.com/questions/2941995/python-ignore-incorrect-padding-error-when-base64-decoding + access_token = self.tokens['AccessToken'] + access_payload = json.loads(base64.b64decode(access_token.split('.')[1] + '==')) + # the expiration time will tell us when to refresh + self.expire_time = access_payload['exp'] + + id_payload = json.loads(base64.b64decode(self.tokens['IdToken'].split('.')[1] + '==')) + # the e-mail will be checked against the config username + self.token_email = id_payload['email'] + logging.info(f"updated tokens: for user {self.token_email}, in groups {id_payload['cognito:groups']}") + + self.auth_header = ' '.join([self.tokens['TokenType'], access_token]) + + if write_tokens: + logging.info("writing updated tokens") + with open(self.TOKEN_PATH, 'wt') as f: + json.dump(self.tokens, f) + + def initial_auth(self): + print(f"initial auth for {self.username}:") + auth_response = self._do_auth_password() + """ + try: + auth_response = self._do_auth_srp() + #auth_response = self._do_auth_srp_warrant() + except: + auth_response = self._do_auth_password() + """ + if 'AuthenticationResult' not in auth_response: + raise RuntimeError("Login failed") + self.update_tokens(auth_response['AuthenticationResult'], replace_tokens=True) + + def refresh_auth(self): + logging.info("refreshing tokens") + refresh_response = self._auth_refresh(self.tokens['RefreshToken']) + if 'AuthenticationResult' not in refresh_response: + raise RuntimeError("Refresh failed") + # update tokens + self.update_tokens(refresh_response['AuthenticationResult']) + + def _do_auth_srp(self): + """this uses pysrp (standard SRP implementation) with patches from warrant (Cognito-specific) + https://stackoverflow.com/questions/41526205/implementing-user-srp-auth-with-python-boto3-for-aws-cognito + """ + logging.info("using pysrp-based SRP for initial auth") + import srp + import six, hmac, hashlib + def long_to_bytes(n): + l = list() + x = 0 + off = 0 + while x != n: + b = (n >> off) & 0xFF + l.append( chr(b) ) + x = x | (b << off) + off += 8 + # weird Cognito padding logic + if (b & 0x80) != 0: + l.append(chr(0)) + l.reverse() + return six.b(''.join(l)) + + def compute_hkdf(ikm, salt): + """ + Standard hkdf algorithm + :param {Buffer} ikm Input key material. + :param {Buffer} salt Salt value. + :return {Buffer} Strong key material. + @private + """ + info_bits = bytearray('Caldera Derived Key', 'utf-8') + prk = hmac.new(salt, ikm, hashlib.sha256).digest() + info_bits_update = info_bits + bytearray(chr(1), 'utf-8') + hmac_hash = hmac.new(prk, info_bits_update, hashlib.sha256).digest() + return hmac_hash[:16] + + def process_challenge(self, bytes_s, bytes_B): + + self.s = srp._pysrp.bytes_to_long( bytes_s ) + self.B = srp._pysrp.bytes_to_long( bytes_B ) + + N = self.N + g = self.g + k = self.k + + hash_class = self.hash_class + + # SRP-6a safety check + if (self.B % N) == 0: + return None + + self.u = srp._pysrp.H( hash_class, self.A, self.B, width=len(long_to_bytes(N)) ) + + # SRP-6a safety check + if self.u == 0: + return None + + self.x = srp._pysrp.gen_x( hash_class, self.s, self.I, self.p ) + self.v = pow(g, self.x, N) + self.S = pow((self.B - k*self.v), (self.a + self.u*self.x), N) + + hkdf = compute_hkdf(long_to_bytes(self.S), + long_to_bytes(self.u)) + return hkdf + + # patch pysrp with our hacked-up functions + srp._pysrp.long_to_bytes = long_to_bytes + srp._pysrp.User.process_challenge = process_challenge + + custom_n = 'FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1'\ + '29024E088A67CC74020BBEA63B139B22514A08798E3404DD' \ + 'EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245' \ + 'E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED' \ + 'EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D' \ + 'C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F' \ + '83655D23DCA3AD961C62F356208552BB9ED529077096966D' \ + '670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B' \ + 'E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9' \ + 'DE2BCBF6955817183995497CEA956AE515D2261898FA0510' \ + '15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64' \ + 'ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7' \ + 'ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B' \ + 'F12FFA06D98A0864D87602733EC86A64521F2B18177B200C' \ + 'BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31' \ + '43DB5BFCE0FD108E4B82D120A93AD2CAFFFFFFFFFFFFFFFF' + custom_g = "2" + + usr = srp.User("dummy", getpass.getpass(), hash_alg=srp.SHA256, ng_type=srp.NG_CUSTOM, + n_hex = custom_n, + g_hex = custom_g) + + _, A = usr.start_authentication() + data = {"AuthFlow": "USER_SRP_AUTH", + "ClientId": self.client_id, + "AuthParameters": {"USERNAME": self.username, + "SRP_A": A.hex()} + } + headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", + "Content-Type": "application/x-amz-json-1.1" + } + rsp = requests.post(self.auth_url, headers=headers, json=data) + if rsp.status_code == 200: + rsp = rsp.json() + else: + raise RuntimeError(f"SRP auth error: {rsp.status_code}, {rsp.content}") + + assert rsp['ChallengeName']=="PASSWORD_VERIFIER" + challenge = rsp['ChallengeParameters'] + + user_id_for_srp = challenge['USER_ID_FOR_SRP'] + usr.I = self.pool_id.split('_')[1]+user_id_for_srp + + salt = challenge['SALT'] + srp_b = challenge['SRP_B'] + secret_block = challenge['SECRET_BLOCK'] + timestamp = datetime.datetime.now(tz=datetime.timezone.utc).strftime("%a %b %d %H:%M:%S %Z %Y") + + hkdf = usr.process_challenge(bytes.fromhex(salt.zfill(32)), bytes.fromhex(srp_b.zfill(768))) + + secret_block_bytes = base64.standard_b64decode(secret_block) + msg = bytearray(self.pool_id.split('_')[1], 'utf-8') + bytearray(user_id_for_srp, 'utf-8') + \ + bytearray(secret_block_bytes) + bytearray(timestamp, 'utf-8') + hmac_obj = hmac.new(hkdf, msg, digestmod=hashlib.sha256) + signature_string = base64.standard_b64encode(hmac_obj.digest()).decode() + + data = {"ChallengeName": "PASSWORD_VERIFIER", + "ClientId": self.client_id, + "ChallengeResponses": {"USERNAME": challenge['USERNAME'], + "TIMESTAMP": timestamp, + "PASSWORD_CLAIM_SECRET_BLOCK": secret_block, + "PASSWORD_CLAIM_SIGNATURE": signature_string + } + } + headers["X-Amz-Target"] = "AWSCognitoIdentityProviderService.RespondToAuthChallenge" + + rsp = requests.post(self.auth_url, headers=headers, json=data) + if rsp.status_code == 200: + return rsp.json() + else: + raise RuntimeError(f"SRP challenge error: {rsp.status_code}, {rsp.content}") + + + def _do_auth_srp_warrant(self): + logging.info("using warrant-based SRP for initial auth") + """this uses aws_srp.py from https://github.com/capless/warrant + """ + from aws_srp import AWSSRP + aws = AWSSRP(username=self.username, password=getpass.getpass(), pool_id=self.pool_id, + client_id=self.client_id, pool_region=self.pool_id.split('_')[0]) + return aws.authenticate_user() + + + def _do_auth_password(self): + logging.info("using password for initial auth") + data = {"AuthFlow": "USER_PASSWORD_AUTH", + "ClientId": self.client_id, + "AuthParameters": {"USERNAME":self.username, "PASSWORD":getpass.getpass()} + } + headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", + "Content-Type": "application/x-amz-json-1.1" + } + rsp = requests.post(self.auth_url, headers=headers, json=data) + if rsp.status_code == 200: + return rsp.json() + else: + raise RuntimeError(f"password authentication error: {rsp.status_code}, {rsp.content}") + + def _auth_refresh(self, refresh_token): + data = {"AuthFlow": "REFRESH_TOKEN_AUTH", + "ClientId": self.client_id, + "AuthParameters": {"REFRESH_TOKEN": refresh_token} + } + headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", + "Content-Type": "application/x-amz-json-1.1" + } + rsp = requests.post(self.auth_url, headers=headers, json=data) + if rsp.status_code == 200: + return rsp.json() + else: + raise RuntimeError(f"token refresh error: {rsp.status_code}, {rsp.content}") + +class WorkloadManager(): + """A base class which allows you to encapsulate a list of programs as a workload. + You should overload the do_stuff() method to handle the creation of programs and processing of results. + + Parameters + ---------- + soccfg : QickConfig + Configuration for the device this workload will run on. + """ + def __init__(self, soccfg): + self.soccfg = soccfg + self.proglist = [] + self.progdicts = [] + self.results = None + self._make_progs() + + def add_program(self, prog): + """Add a program to the program list. + This should be called inside do_stuff() when make_progs=True. + + Parameters + ---------- + prog : QickProgram + A program to add to the workload + """ + self.proglist.append(prog) + + def add_acquire(self, prog, save_raw=False, save_shots=False): + """Add accumulated readout of a program. + This should be called inside do_stuff() when write_progs=True. + + Parameters + ---------- + prog : QickProgram + A program to execute + save_raw : bool + Save raw IQ values for each shot. + save_shots : bool + Save thresholded values for each shot. + """ + dump = prog.dump_prog() + dump['acqtype'] = "accumulated" + dump['save_raw'] = save_raw + dump['save_shots'] = save_shots + self.progdicts.append(dump) + + def add_decimated(self, prog): + """Add decimated readout of a program. + This should be called inside do_stuff() when write_progs=True. + """ + dump = prog.dump_prog() + dump['acqtype'] = "decimated" + self.progdicts.append(dump) + + def _make_progs(self): + """Make all the programs. + """ + self.do_stuff(make_progs=True) + + def _get_progs(self): + """Generator function that returns datasets from a results file. + """ + for prog in self.proglist: + yield prog + + def write_progs(self, filepath=None): + """Write all programs to a workload file. + + Parameters + ---------- + filepath : str or None + Path for the workload file. + If provided, write and close the file. + If None, create and return an open tempfile. + + Returns + ------- + file or None + Workload as a temporary file, if filepath was None. + """ + if filepath is None: + outfile = tempfile.TemporaryFile() + else: + outfile = open(filepath, 'wb') + self.prog_iterator = self._get_progs() + self.do_stuff(write_progs=True) + with gzip.GzipFile(fileobj=outfile, mode='wb') as f: + f.write(progs2json(self.progdicts).encode()) + if filepath is None: + return outfile + else: + outfile.close() + + def _get_results(self, outf): + """Generator function that returns datasets from a results file. + + Parameters + ---------- + outf : h5py.File + HDF5 results file. + """ + datagrp = outf["data"] + for name, proggrp in datagrp.items(): + yield proggrp + + def read_results(self, resultsfile): + """Iterate through a results file. + + Parameters + ---------- + resultsfile : str or file + HDF5 results file path or file object. + """ + self.prog_iterator = self._get_progs() + with h5py.File(resultsfile,'r') as outf: + self.result_iterator = self._get_results(outf) + self.do_stuff(read_results=True) + + def do_stuff(self, make_progs=False, write_progs=False, read_results=False): + """Initialize the workload and process results. + You will not call this method directly; it is called internally at initialization and by write_progs() and read_results(). + For each program you run as part of this workload, you must do the following: + + * If make_progs is True, create a QickProgram and call add_program() to add it to the program list. + If False, call next(self.prog_iterator) to pop a program from the program list. + + * If write_progs is True, call add_acquire() or add_decimated() to define how you want this program to be run. + + * If read_results is True, call next(self.result_iterator) to pop a dataset from the results file. + Process the dataset as needed. + + Parameters + ---------- + make_progs : bool + Create program objects and fill the program list. + write_progs : bool + For each program in the program list, define how to run it and what results to save. + read_results : bool + Read and analyze the results file. + """ + +class UserClient(): + """Provides a Python API to make requests to the cloud service. + A configuration file (containing API URLs and a username) is expected at ~/.config/qick.conf or /etc/qick/config. + A default device ID may also be included in the configuration file. + """ + def __init__(self): + configpaths = [os.path.expanduser('~/.config/qick.conf'), + '/etc/qick/config'] + + self.config = ConfigParser() + self.config.read(configpaths) + + + auth = CognitoAuth() + auth.username = self.config['user']['username'] + auth.auth_url = self.config['service']['cognito_url'] + auth.client_id = self.config['service']['clientid'] + auth.pool_id = self.config['service']['cognito_userpool'] # only needed for SRP + + self.api_endpoint = self.config['service']['api_endpoint'] + + self.session = requests.Session() + self.session.auth = auth + + def add_user(self, email, fullname): + """Create a user account on the cloud service. + A suggested config file will be printed. + The user will get an e-mail with a temporary password. + + Parameters + ---------- + email : str + A valid e-mail address for the user, required to be unique + fullname : str + A display name for the user, not required to be unique + """ + data = { + "Email": email, + "FullName": fullname + } + rsp = self.session.post(self.api_endpoint + '/users', json=data) + if rsp.status_code == 200: + print("User successfully added! They should check their e-mail for a temporary password.") + print() + print("They should put the following in ~/.config/qick.conf:") + print("[service]") + print(f"api_endpoint = {self.api_endpoint}") + print(f"cognito_url = {self.session.auth.auth_url}") + print(f"clientid = {self.session.auth.client_id}") + print(f"cognito_userpool = {self.session.auth.pool_id}") + print("[user]") + print(f"username = {email}") + + else: + logging.warning(f"AddUser API error: {rsp.status_code}, {rsp.content}") + + def add_device(self, device_name, refresh_timeout=60): + """Create a workload queue on the cloud service. + Suggested config and credentials files will be printed. + + Parameters + ---------- + device_name : str + A display name for the device, not required to be unique + refresh_timeout : int + A timeout (in seconds), after which the service will decide the device is offline if it hasn't received a status update. + The normal update interval for the device client is 5 seconds. + """ + data = { + "DeviceName": device_name, + "RefreshTimeout": refresh_timeout + } + rsp = self.session.post(self.api_endpoint + '/devices', json=data) + if rsp.status_code == 201: + rsp = rsp.json() + print("Device successfully added!") + print() + print("Put the following in the config file /etc/qick/config:") + print("[service]") + print(f"api_endpoint = {self.api_endpoint}") + print(f"oauth_endpoint = {self.config['service']['oauth_endpoint']}") + print("[device]") + print(f"name = {rsp['DeviceName']}") + print(f"id = {rsp['DeviceId']}") + print() + print("If using UserClient for workload submission, the [device] block is needed in the client config as well.") + print() + print("Put the following in the device credentials file /etc/qick/credentials:") + print("[credentials]") + print(f"id = {rsp['ClientId']}") + print(f"secret = {rsp['ClientSecret']}") + else: + logging.warning(f"AddDevice API error: {rsp.status_code}, {rsp.content}") + + def get_devices(self): + """Query the cloud service for a list of devices. + + Returns + ------- + list of dict + All devices + """ + rsp = self.session.get(self.api_endpoint + '/devices') + if rsp.status_code == 200: + return rsp.json() + else: + logging.warning(f"GetDevices API error: {rsp.status_code}, {rsp.content}") + return None + + def _s3put(self, s3url, payload): + """Upload a payload to a pre-signed S3 PUT URL. + + Parameters + ---------- + s3url : str + Pre-signed S3 URL + payload : file + A file to be uplaoded + """ + rsp = requests.put(s3url, data=payload, headers={'Content-Type': 'application/octet-stream'}) + if rsp.status_code == 200: + logging.info(f"s3 upload success") + else: + logging.warning(f"s3 upload fail: {rsp.status_code}") + + def _s3get(self, s3url): + """Download a pre-signed S3 GET URL. + + Parameters + ---------- + s3url : str + Pre-signed S3 URL + + Returns + ------- + file + The downloaded file, as a temporary file + """ + with requests.get(s3url, stream=True) as rsp: + if rsp.status_code == 200: + getfile = tempfile.TemporaryFile() + shutil.copyfileobj(rsp.raw, getfile) + getfile.seek(0) + return getfile + else: + logging.warning(f"s3 download fail: {rsp.status_code}") + return None + + def get_soccfg(self, device_id=None): + """Query the cloud service for the most recently uploaded configuration of a device. + The config file is parsed as JSON. + + Parameters + ---------- + device_id : str or None + The unique ID of the device. + If None, the device ID will be read from the user client configuration. + + Returns + ------- + dict + Device configuration, to be loaded into a QickCOnfig object + """ + if device_id is None: + device_id = self.config['device']['id'] + rsp = self.session.get(self.api_endpoint + '/devices/' + device_id) + if rsp.status_code == 200: + logging.info(f"GetDevice response: {rsp.json()}") + rsp = rsp.json() + deviceid = rsp['DeviceId'] + devicename = rsp['DeviceName'] + devicestatus = rsp['DeviceStatus'] + lastrefreshed = rsp['LastRefreshed'] + refreshtimeout = rsp['RefreshTimeout'] + configurl = rsp['DeviceConfigurationUrl'] + try: + cfgfile = self._s3get(configurl) + devcfg = json.load(cfgfile) + cfgfile.close() + except Exception as e: + logging.warning(f"GetDevice S3 error: {e}") + return None + logging.info(f"GetDevice device config from S3: {devcfg}") + return devcfg + else: + logging.warning(f"GetDevice API error: {rsp.status_code}, {rsp.content}") + return None + + def create_work(self, workloadfile, device_id=None, priority="LOW"): + """Upload a workload into a device queue on the cloud service. + The config file is parsed as JSON. + + Parameters + ---------- + workloadfile : file + A file-like object to be uploaded to the queue. + device_id : str or None + The unique ID of the device. + If None, the device ID will be read from the user client configuration. + priority : str + The priority to be assigned to this workload. + The valid values are defined by the cloud service. + + Returns + ------- + str + Workload ID, for checking status and downloading results + """ + workloadfile.seek(0) + if device_id is None: + device_id = self.config['device']['id'] + data = { + "DeviceId": device_id, + "Priority": priority + } + rsp = self.session.post(self.api_endpoint + "/workloads", json=data) + if rsp.status_code == 201: + logging.info(f"UpdateDevice request: {data}") + logging.info(f"UpdateDevice response: {rsp.json()}") + rsp = rsp.json() + work_id = rsp['WorkId'] + upload_url = rsp['UploadUrl'] + try: + self._s3put(rsp['UploadUrl'], workloadfile) + logging.info("Uploaded workload") + workloadfile.close() + except Exception as e: + logging.warning(f"CreateWork S3 error: {e}") + return work_id + else: + logging.warning(f"CreateWork API error: {rsp.status_code}, {rsp.content}") + return None + + def get_work(self, work_id): + """Query the cloud service for the status of a workload. + + Parameters + ---------- + work_id : str + The workload ID. + + Returns + ------- + dict + Information about the workload. + """ + rsp = self.session.get(self.api_endpoint + '/workloads/' + work_id) + if rsp.status_code == 200: + return rsp.json() + else: + logging.warning(f"GetWork API error: {rsp.status_code}, {rsp.content}") + return None + + def wait_until_done(self, work_id, interval=1.0, progress=True): + """Poll the cloud service until the workload reaches DONE status. + + Parameters + ---------- + work_id : str + The workload ID. + progress : bool + Print the workload status as it progresses. + interval : float + Polling interval (in seconds). + """ + last_state = None + while True: + state = self.get_work(work_id)['WorkStatus'] + if state != last_state: + if progress: + if last_state is not None: + print() + print("workload is " + state, end='') + if state == 'DONE': + if progress: print() + break + last_state = state + time.sleep(interval) + if progress: print('.', end='') + + def get_results(self, work_id): + """Download workload results from the cloud service. + If the workload is not in DONE status, raise an error. + + Parameters + ---------- + work_id : str + The workload ID. + + Returns + ------- + file + A temporary file with the workload results (typically an HDF5 file). + """ + rsp = self.session.get(self.api_endpoint + '/workloads/' + work_id) + if rsp.status_code == 200: + rsp = rsp.json() + if rsp['WorkStatus'] != 'DONE': + raise RuntimeError("get_results error: workload is not in DONE status") + try: + resultsfile = self._s3get(rsp['WorkloadResultUrl']) + return resultsfile + except Exception as e: + logging.warning(f"GetWork S3 error: {e}") + return None + else: + logging.warning(f"GetWork API error: {rsp.status_code}, {rsp.content}") + return None + + +if __name__ == "__main__": + logging.getLogger().setLevel(logging.WARNING) + + client = UserClient() + Fire(client) diff --git a/docs/Makefile b/docs/Makefile new file mode 100644 index 000000000..e9e02455b --- /dev/null +++ b/docs/Makefile @@ -0,0 +1,192 @@ +# Makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +PAPER = +BUILDDIR = _build + +# User-friendly check for sphinx-build +ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1) +$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/) +endif + +# Internal variables. +PAPEROPT_a4 = -D latex_paper_size=a4 +PAPEROPT_letter = -D latex_paper_size=letter +ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . +# the i18n builder cannot share the environment and doctrees with the others +I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . + +.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest coverage gettext + +help: + @echo "Please use \`make ' where is one of" + @echo " html to make standalone HTML files" + @echo " dirhtml to make HTML files named index.html in directories" + @echo " singlehtml to make a single large HTML file" + @echo " pickle to make pickle files" + @echo " json to make JSON files" + @echo " htmlhelp to make HTML files and a HTML help project" + @echo " qthelp to make HTML files and a qthelp project" + @echo " applehelp to make an Apple Help Book" + @echo " devhelp to make HTML files and a Devhelp project" + @echo " epub to make an epub" + @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter" + @echo " latexpdf to make LaTeX files and run them through pdflatex" + @echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx" + @echo " text to make text files" + @echo " man to make manual pages" + @echo " texinfo to make Texinfo files" + @echo " info to make Texinfo files and run them through makeinfo" + @echo " gettext to make PO message catalogs" + @echo " changes to make an overview of all changed/added/deprecated items" + @echo " xml to make Docutils-native XML files" + @echo " pseudoxml to make pseudoxml-XML files for display purposes" + @echo " linkcheck to check all external links for integrity" + @echo " doctest to run all doctests embedded in the documentation (if enabled)" + @echo " coverage to run coverage check of the documentation (if enabled)" + +clean: + rm -rf $(BUILDDIR) _autosummary + +html: + $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html + @echo + @echo "Build finished. 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The pseudo-XML files are in $(BUILDDIR)/pseudoxml." diff --git a/docs/README.md b/docs/README.md new file mode 100644 index 000000000..bf145fea8 --- /dev/null +++ b/docs/README.md @@ -0,0 +1,25 @@ +QICK: Quantum Instrumentation Controller Kit +=========================================== + + +**This repository contains the source files for the documentation of the Quantum Instrumentation Controller Kit software, generated via Sphinx and available on ReadTheDocs.** + +To build the Sphinx documentation locally: +``` +export READTHEDOCS=True +make html +``` + +If you want to build in nitpicky mode to generate warning for bad references, use `make html SPHINXOPTS='-n'`. + +To check validity of external links, use `make linkcheck`. + +Documentation +------------- + +The documentation for QICK is available at: https://qick-docs.readthedocs.io + + +Documentation generated from this project: http://romanvm.github.io/sphinx_tutorial/ + +License: [Creative Commons Share Alike](http://creativecommons.org/licenses/by-sa/4.0/) diff --git a/docs/_static/custom.css b/docs/_static/custom.css new file mode 100644 index 000000000..bb98d6d34 --- /dev/null +++ b/docs/_static/custom.css @@ -0,0 +1,21 @@ +body { + --themecolor: black; +} + +.wy-side-nav-search { + background-color: var(--themecolor); +} +.wy-nav-top { + background-color: var(--themecolor); +} + +/* override table width restrictions */ +.wy-table-responsive table td, .wy-table-responsive table th { + /* !important prevents the common CSS stylesheets from + overriding this as on RTD they are loaded after this stylesheet */ + white-space: normal !important; +} + +.wy-table-responsive { + overflow: visible !important; +} \ No newline at end of file diff --git a/docs/conf.py b/docs/conf.py new file mode 100644 index 000000000..ce009a86a --- /dev/null +++ b/docs/conf.py @@ -0,0 +1,352 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Sphinx Apidoc Turorial documentation build configuration file, created by +# sphinx-quickstart on Fri Jan 8 20:52:00 2016. +# +# This file is execfile()d with the current directory set to its +# containing dir. +# +# Note that not all possible configuration values are present in this +# autogenerated file. +# +# All configuration values have a default; values that are commented out +# serve to show the default. + +import sys +import os +import pathlib + +## Make your modules available in sys.path +here = pathlib.Path(__file__).parent.resolve() +sys.path.insert(0, (here / '../qick_lib').resolve().as_posix()) +print(sys.path) + +def get_version(rel_path): + """ + qick_lib/qick/VERSION is a text file containing only the version number. + """ + return (here / rel_path).read_text().strip() + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +#sys.path.insert(0, os.path.abspath('.')) + +# -- General configuration ------------------------------------------------ + +# If your documentation needs a minimal Sphinx version, state it here. +#needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = [ + 'sphinx.ext.autodoc', + 'sphinx.ext.viewcode', + 'sphinx.ext.intersphinx', + 'sphinx.ext.mathjax', + ## Include autosymmary + 'sphinx.ext.autosummary', + 'sphinx.ext.napoleon', + 'sphinx.ext.extlinks', +] + +## Include Python objects as they appear in source files +## Default: alphabetically ('alphabetical') +autodoc_member_order = 'bysource' +## Default flags used by autodoc directives +autodoc_default_options = { + 'members': True, + 'show-inheritance': True, +} + +autodoc_mock_imports = ["pynq", "xrfclk", "xrfdc", "cffi", "Pyro4", "psutil"] + +## Generate autodoc stubs with summaries from code +autosummary_generate = True + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +# source_suffix = ['.rst', '.md'] +source_suffix = '.rst' + +# The encoding of source files. +#source_encoding = 'utf-8-sig' + +# The master toctree document. +master_doc = 'index' + +# General information about the project. +project = 'qick' +copyright = 'openquantumhardware' +author = 'openquantumhardware' + +# The version info for the project you're documenting, acts as replacement for +# |version| and |release|, also used in various other places throughout the +# built documents. +# +# The short X.Y version. +version = get_version("../qick_lib/qick/VERSION") +# The full version, including alpha/beta/rc tags. +release = version + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = 'en' + +# There are two options for replacing |today|: either, you set today to some +# non-false value, then it is used: +#today = '' +# Else, today_fmt is used as the format for a strftime call. +#today_fmt = '%B %d, %Y' + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +exclude_patterns = ['_build'] + +# The reST default role (used for this markup: `text`) to use for all +# documents. +#default_role = None + +# If true, '()' will be appended to :func: etc. cross-reference text. +#add_function_parentheses = True + +# If true, the current module name will be prepended to all description +# unit titles (such as .. function::). +#add_module_names = True + +# If true, sectionauthor and moduleauthor directives will be shown in the +# output. They are ignored by default. +#show_authors = False + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' + +# A list of ignored prefixes for module index sorting. +#modindex_common_prefix = [] + +# If true, keep warnings as "system message" paragraphs in the built documents. +#keep_warnings = False + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = False + + +# -- Options for HTML output ---------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +html_theme = 'sphinx_rtd_theme' + +html_theme_options = { + 'logo_only': True, +} +# Theme options are theme-specific and customize the look and feel of a theme +# further. For a list of options available for each theme, see the +# documentation. + +# Add any paths that contain custom themes here, relative to this directory. +#html_theme_path = [] + +# The name for this set of Sphinx documents. If None, it defaults to +# " v documentation". +#html_title = None + +# A shorter title for the navigation bar. Default is the same as html_title. +#html_short_title = None + +# The name of an image file (relative to this directory) to place at the top +# of the sidebar. +html_logo = "../graphics/logoQICK.svg" + +# The name of an image file (within the static path) to use as favicon of the +# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 +# pixels large. +#html_favicon = None + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] + +# html_css_files = ['custom.css'] + +# Add any extra paths that contain custom files (such as robots.txt or +# .htaccess) here, relative to this directory. These files are copied +# directly to the root of the documentation. +#html_extra_path = [] + +# If not '', a 'Last updated on:' timestamp is inserted at every page bottom, +# using the given strftime format. +#html_last_updated_fmt = '%b %d, %Y' + +# If true, SmartyPants will be used to convert quotes and dashes to +# typographically correct entities. +#html_use_smartypants = True + +# Custom sidebar templates, maps document names to template names. +## Sidebars configuration for alabaster theme + +html_sidebars = { + '**': [ + 'about.html', + 'navigation.html', + 'searchbox.html', + ] +} + +# Additional templates that should be rendered to pages, maps page names to +# template names. +#html_additional_pages = {} + +# If false, no module index is generated. +#html_domain_indices = True + +# If false, no index is generated. +#html_use_index = True + +# If true, the index is split into individual pages for each letter. +#html_split_index = False + +# If true, links to the reST sources are added to the pages. + +## I don't like links to page reST sources +html_show_sourcelink = True + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +#html_show_sphinx = True + +# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True. +#html_show_copyright = True + +# If true, an OpenSearch description file will be output, and all pages will +# contain a tag referring to it. The value of this option must be the +# base URL from which the finished HTML is served. +#html_use_opensearch = '' + +# This is the file name suffix for HTML files (e.g. ".xhtml"). +#html_file_suffix = None + +# Language to be used for generating the HTML full-text search index. +# Sphinx supports the following languages: +# 'da', 'de', 'en', 'es', 'fi', 'fr', 'h', 'it', 'ja' +# 'nl', 'no', 'pt', 'ro', 'r', 'sv', 'tr' +#html_search_language = 'en' + +# A dictionary with options for the search language support, empty by default. +# Now only 'ja' uses this config value +#html_search_options = {'type': 'default'} + +# The name of a javascript file (relative to the configuration directory) that +# implements a search results scorer. If empty, the default will be used. +#html_search_scorer = 'scorer.js' + +# Output file base name for HTML help builder. +htmlhelp_basename = 'SphinxApidocTurorialdoc' + +# -- Options for LaTeX output --------------------------------------------- + +latex_elements = { +# The paper size ('letterpaper' or 'a4paper'). +#'papersize': 'letterpaper', + +# The font size ('10pt', '11pt' or '12pt'). +#'pointsize': '10pt', + +# Additional stuff for the LaTeX preamble. +#'preamble': '', + +# Latex figure (float) alignment +#'figure_align': 'htbp', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, 'SphinxApidocTurorial.tex', 'Sphinx Apidoc Turorial Documentation', + 'Roman Miroshnychenko', 'manual'), +] + +# The name of an image file (relative to this directory) to place at the top of +# the title page. +#latex_logo = None + +# For "manual" documents, if this is true, then toplevel headings are parts, +# not chapters. +#latex_use_parts = False + +# If true, show page references after internal links. +#latex_show_pagerefs = False + +# If true, show URL addresses after external links. +#latex_show_urls = False + +# Documents to append as an appendix to all manuals. +#latex_appendices = [] + +# If false, no module index is generated. +#latex_domain_indices = True + + +# -- Options for manual page output --------------------------------------- + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, 'sphinxapidocturorial', 'Sphinx Apidoc Turorial Documentation', + [author], 1) +] + +# If true, show URL addresses after external links. +#man_show_urls = False + + +# -- Options for Texinfo output ------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, 'SphinxApidocTurorial', 'Sphinx Apidoc Turorial Documentation', + author, 'SphinxApidocTurorial', 'One line description of project.', + 'Miscellaneous'), +] + +# Documents to append as an appendix to all manuals. +#texinfo_appendices = [] + +# If false, no module index is generated. +#texinfo_domain_indices = True + +# How to display URL addresses: 'footnote', 'no', or 'inline'. +#texinfo_show_urls = 'footnote' + +# If true, do not generate a @detailmenu in the "Top" node's menu. +#texinfo_no_detailmenu = False + +# Example configuration for intersphinx: refer to the Python standard library. +## Add Python version number to the default address to corretcly reference +## the Python standard library +intersphinx_mapping = {'python': ('https://docs.python.org/3.7', None), + 'pynq': ('https://pynq.readthedocs.io/en/v2.7.0', None), + 'numpy': ('https://numpy.org/doc/1.26', None), + } + +extlinks = {'repofile': ('https://github.com/openquantumhardware/qick/blob/main/%s', + '%s')} + +extlinks_detect_hardcoded_links = True + +linkcheck_ignore = [r'^https://blogs.keysight.com/', # gives 403 error + ] + +def setup(app): + app.add_css_file("custom.css" ) diff --git a/docs/contact.rst b/docs/contact.rst new file mode 100644 index 000000000..da52e9ab6 --- /dev/null +++ b/docs/contact.rst @@ -0,0 +1,10 @@ +Support and community +--------------------- + +The main resource for communicating with developers and members of the QICK community is the Unitary Foundation Discord (use this `invite link `_): + +* Chat with us any time in the `#qick channel `_. + +* If you prefer voice chat, we also hold weekly office hours; check the `Unitary Foundation calendar `_ for details. + +We also welcome bug reports and feature requests via `GitHub Issues `_. diff --git a/docs/firmware.rst b/docs/firmware.rst new file mode 100644 index 000000000..401724bd1 --- /dev/null +++ b/docs/firmware.rst @@ -0,0 +1,75 @@ +Firmware +======== + +This system includes the following components: + +* 1 output channels connected to PMOD0-3 and triggers for Readout Block. +* 7 output channels connected to DACs. +* 2 input channels connected to ADCs. +* 1 instance of tProcessor 64-bit instructions, 32-bit registers. + +Sampling frequency of ADC blocks is given by the variable ``soc.fs_adc``. Sampling frequency of DACs is stored in variable ``soc.fs_adc``. Fast-speed buffers were removed to save memory space. Raw data can be captured after x8 down-sampling. + +Output channels driving DACs use the updated Signal Generator V4, which has the possibility to upload I/Q envelopes, and uses 32-bit resolution for both frequency and phase. The format of the control word was updated accordingly to accomodate the bits. See example asm files for a detailed description of the fields. The maximum length of the I/Q envelopes is given by the variable ``soc.gens[i].MAX_LENGTH``. + +The readout block is actually built around two IPs: readout and average + buffer. Readout block includes a digital down-convertion, FIR filtering and decimation by 8. DDS frequency is configured using a register of the readout block and it is not intended to support real-time frequency hopping as in the Signal Generator side. After frequency shifting, filtering and decimation, the data stream is sent to the Average + Buffer block, which internally can store raw samples or perform the sum of the specified number of samples. The process is started with the external trigger signal, connected to output Channel 0 of tProcessor. The user can opt to route the input, the DDS wave or the frequency shifted signal to the FIR and decimation by 8 stage. This is done using a output selection register of the readout block. Regarding the buffering capabilities, the average section of the block has a buffer of ``soc.avg_bufs[i].AVG_MAX_LENGTH``. + +.. figure:: ../graphics/qsystem-readout.svg + :width: 100% + :align: center + +The tProcessor +-------------- + +You also may want to learn more about how the QICK tProcessor works. +In this case, you can reference the `QICK assembly language documentation `_. +Note that this documentation is not up to date with the current version of the QICK tProcessor. +It is made available here as a learning tool for those interested in learning the principles of the tProcessor. +Those who have more specific questions can contact us. + +tProcessor channel assignment +----------------------------- + +tProcessor will be used to control the real-time operation of the experiment. Output channels (AXIS MASTER) of the tProcessor are assigned as follows: + +- Channel 0 : connected to PMOD0 0-3, and triggers for readout. Bits 0-3 are connected to PMOD0, bit 14 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH0. Bit 15 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH1. +- Channel 1 : connected to Signal Generator V4, which drives DAC 228 CH0. +- Channel 2 : connected to Signal Generator V4, which drives DAC 228 CH1. +- Channel 3 : connected to Signal Generator V4, which drives DAC 228 CH2. +- Channel 4 : connected to Signal Generator V4, which drives DAC 229 CH0. +- Channel 5 : connected to Signal Generator V4, which drives DAC 229 CH1. +- Channel 6 : connected to Signal Generator V4, which drives DAC 229 CH2. +- Channel 7 : connected to Signal Generator V4, which drives DAC 229 CH3. + +**Note** that if you are using the Xilinx XM500 daughter board that comes with the ZCU111, be aware of the filters that are put on that XM500 board: DAC 229 channels 0 and 1 are high pass filtered by a 1 GHz high pass filter, so ensure that signals coming out of channels 4 and 5 are at least 1 GHz. Also, DAC 229 channels 2 and 3 are low pass filtered by a 1 GHz low pass filter, so ensure that signals coming out of channels 6 and 7 are less than 1 GHz. DAC 228 channels 0, 1 and 2 are not filtered by the XM500 daughter board. + +The updated version of the tProcessor has 4 input (AXIS SLAVE) channels, which can be used for feedback. These are 64-bit, and the updated ``read`` instruction can specify channel number and upper/lower 32-bits to be read and written into an internal register. See example below on how to use this new capability. + +* Channel 0 : connected to readout 0, which is driven by ADC 224 CH0 +* Channel 1 : connected to readout 1, which is driven by ADC 224 CH1 + +**Note** that if you are using the Xilinx XM500 daughter board that comes with the ZCU111, be aware of the filters that are put on that XM500 board: ADC 224 channels 0 and 1 are low pass filtered by a 1 GHz low pass filter, so ensure that the signal coming into your XM500 board is less than 1 GHz so that it can be read in properly. + +Signal Generators are organized on the array ``soc.gens``, which is composed of 7 instances. Array index 0 is connected to tProcessor Channel 1, array index 1 is connected to tProcessor Channel 2, and so on. As way of example, let's assume the user needs to create a pulse on DAC 229 CH1 and DAC 229 CH3. These are connected to Channels 5, and 7 or the tProcessor, respectively. However, let's also assume that a gaussian envelope needs to be uploaded into the corresponding signal generator. ``soc.gens[3]`` drives DAC 229 CH1, and ``soc.gens[6]`` drives DAC 229 CH3. + +Similarly, average and buffer inputs blocks are organized on ``soc.avg_bufs`` array, which has two instances of the Average + Buffer block. The user can access them using index 0 and 1. + +Timing +------ + +The clock frequency of the FPGA is 384 MHz. Therefore, each clock cycle has a period of 2.6 ns. + +The DAC speed is ``384*16=6144 MHz`` (resolution ``~163 ps``) and the ADC speed is ``384*8 MHz`` but then the signal is decimated by a factor of ``8`` (resolution ``~2.6 ns``). The minimum DAC pulse length is 16 samples but if you want shorter pulses than that you can pad that pulse with zeros. + + +Firmware parameters +------------------- + +* Pulse memory length: 65536 per channel x2 (I,Q), i.e., 128k total +* Decimated ADC buffer length: 1024 samples per component (I,Q), 2k total +* Accumulated ADC buffer length: 16384 samples per component (I,Q), 32 k total +* tProc program memory length: 8k instructions of 64 bits, 64k Bytes total +* tProc data memory length: 4096 samples of 32 bits, 16k Bytes total +* tProc stack size: 256 samples of 32 bits, 1k Byte total +* Phase conversion from deg to reg: Phase resolution is 32-bit, that is :math:`\Delta \phi = 2 \pi /2^{32}` or :math:`360/2^{32}` +* Gain is 16-bit signed [-32768,32767] diff --git a/docs/images/papers/QICKpapers_count_Jan26.png b/docs/images/papers/QICKpapers_count_Jan26.png new file mode 100644 index 000000000..17ace1fd3 Binary files /dev/null and b/docs/images/papers/QICKpapers_count_Jan26.png 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Sphinx Apidoc Turorial documentation master file, created by + sphinx-quickstart on Fri Jan 8 20:52:00 2016. + You can adapt this file completely to your liking, but it should at least + contain the root `toctree` directive. + +.. toctree:: + :maxdepth: 2 + :hidden: + + quick_start + modules + topics/index + firmware + + contact + +Welcome to the QICK documentation! +================================================= + +.. figure:: ../graphics/QICK.jpg + :width: 100% + :align: center + +.. figure:: ../graphics/ZCU216Board.jpg + :width: 100% + :align: center + +The Quantum Instrumentation Control Kit (QICK for short) is a Xilinx RFSoC-based qubit controller which supports the direct synthesis of control and readout pulses. +The QICK consists of a digital board hosting an RFSoC (RF System-on-Chip) FPGA, custom firmware and software, and an optional companion custom-designed analog front-end board. +All of the schematics, firmware, and software are open-source and available on `Github `_. +We fully support the ZCU111, ZCU216, and RFSoC4x2 evaluation boards, and generally recommend using the newer generation of RFSoCs (ZCU216 and RFSoC4x2) for better overall performance. + +Getting started with QICK +------------------------- + +* First, for a global overview of the QICK and its capabilities, read `our instrumentation paper introducing the QICK `_. + +* If you have an RFSoC board and you want to configure it as a QICK board, follow :doc:`our quick start guide `. + +* After you configure your board, you can test it with `our demo notebooks `_. + These are intended as a tutorial. + The first demos explain important features of the QICK system and walk you through how to write working QICK programs. + The later demos provide examples of useful measurements you might make with the QICK. + We recommend that new users read and understand all of the demos. + +More examples and resources +--------------------------- + +Other examples and tutorials (compatibility with the current QICK software is not guaranteed): + +* `IEEE Quantum Week 2025 `_ +* `IEEE Quantum Week 2024 `_ +* `US QIS Summer School 2024 `_ +* `IEEE Quantum Week 2023 `_ + +Talk to us +------------ + +You can get in touch with the QICK core team and the user community through our :doc:`community contact channels `. + +QICK software +------------- + +`Source code `_ and :doc:`API documentation ` + +:doc:`/topics/index` + +QICK firmware +------------- + +Source code and instructions for compiling it yourself: `qick/firmware `_ + +:doc:`/firmware` + +Extensions beyond the core software and firmware +------------------------------------------------ + +If you want your board's state to persist between notebooks or scripts, you should install Pyro4 on your board and run QICK in a Pyro server: see `our Pyro4 demo notebooks `_ + +If you would like to save the instrument configuration for every measurement using `QCoDeS `_, you can also install `this QCoDeS driver `_. + +If you're interested in using QICK to control and read out NV centers or other quantum defects, you might be interested in `QICK-DAWG `_ which extends QICK with pulses and measurement programs specific to that application. + +If you want to use QICK for control and readout of solid-state spin qubits, `SpinQICK `_ extends the QICK API and provides high-level experiment code. + +QICK papers +------------- + +* For a list of academic papers produced using the QICK system, check out :doc:`our papers page ` + +.. toctree:: + :maxdepth: 2 + + papers diff --git a/docs/make.bat b/docs/make.bat new file mode 100644 index 000000000..0e7cecdff --- /dev/null +++ b/docs/make.bat @@ -0,0 +1,263 @@ +@ECHO OFF + +REM Command file for Sphinx documentation + +if "%SPHINXBUILD%" == "" ( + set SPHINXBUILD=sphinx-build +) +set BUILDDIR=_build +set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% . +set I18NSPHINXOPTS=%SPHINXOPTS% . +if NOT "%PAPER%" == "" ( + set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS% + set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS% +) + +if "%1" == "" goto help + +if "%1" == "help" ( + :help + echo.Please use `make ^` where ^ is one of + echo. html to make standalone HTML files + echo. dirhtml to make HTML files named index.html in directories + echo. singlehtml to make a single large HTML file + echo. pickle to make pickle files + echo. json to make JSON files + echo. htmlhelp to make HTML files and a HTML help project + echo. qthelp to make HTML files and a qthelp project + echo. devhelp to make HTML files and a Devhelp project + echo. epub to make an epub + echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter + echo. text to make text files + echo. man to make manual pages + echo. texinfo to make Texinfo files + echo. gettext to make PO message catalogs + echo. changes to make an overview over all changed/added/deprecated items + echo. xml to make Docutils-native XML files + echo. pseudoxml to make pseudoxml-XML files for display purposes + echo. linkcheck to check all external links for integrity + echo. doctest to run all doctests embedded in the documentation if enabled + echo. coverage to run coverage check of the documentation if enabled + goto end +) + +if "%1" == "clean" ( + for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i + del /q /s %BUILDDIR%\* + goto end +) + + +REM Check if sphinx-build is available and fallback to Python version if any +%SPHINXBUILD% 1>NUL 2>NUL +if errorlevel 9009 goto sphinx_python +goto sphinx_ok + +:sphinx_python + +set SPHINXBUILD=python -m sphinx.__init__ +%SPHINXBUILD% 2> nul +if errorlevel 9009 ( + echo. + echo.The 'sphinx-build' command was not found. Make sure you have Sphinx + echo.installed, then set the SPHINXBUILD environment variable to point + echo.to the full path of the 'sphinx-build' executable. Alternatively you + echo.may add the Sphinx directory to PATH. + echo. + echo.If you don't have Sphinx installed, grab it from + echo.http://sphinx-doc.org/ + exit /b 1 +) + +:sphinx_ok + + +if "%1" == "html" ( + %SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The HTML pages are in %BUILDDIR%/html. + goto end +) + +if "%1" == "dirhtml" ( + %SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml. + goto end +) + +if "%1" == "singlehtml" ( + %SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml. + goto end +) + +if "%1" == "pickle" ( + %SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle + if errorlevel 1 exit /b 1 + echo. + echo.Build finished; now you can process the pickle files. + goto end +) + +if "%1" == "json" ( + %SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json + if errorlevel 1 exit /b 1 + echo. + echo.Build finished; now you can process the JSON files. + goto end +) + +if "%1" == "htmlhelp" ( + %SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp + if errorlevel 1 exit /b 1 + echo. + echo.Build finished; now you can run HTML Help Workshop with the ^ +.hhp project file in %BUILDDIR%/htmlhelp. + goto end +) + +if "%1" == "qthelp" ( + %SPHINXBUILD% -b qthelp %ALLSPHINXOPTS% %BUILDDIR%/qthelp + if errorlevel 1 exit /b 1 + echo. + echo.Build finished; now you can run "qcollectiongenerator" with the ^ +.qhcp project file in %BUILDDIR%/qthelp, like this: + echo.^> qcollectiongenerator %BUILDDIR%\qthelp\SphinxApidocTurorial.qhcp + echo.To view the help file: + echo.^> assistant -collectionFile %BUILDDIR%\qthelp\SphinxApidocTurorial.ghc + goto end +) + +if "%1" == "devhelp" ( + %SPHINXBUILD% -b devhelp %ALLSPHINXOPTS% %BUILDDIR%/devhelp + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. + goto end +) + +if "%1" == "epub" ( + %SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The epub file is in %BUILDDIR%/epub. + goto end +) + +if "%1" == "latex" ( + %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex + if errorlevel 1 exit /b 1 + echo. + echo.Build finished; the LaTeX files are in %BUILDDIR%/latex. + goto end +) + +if "%1" == "latexpdf" ( + %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex + cd %BUILDDIR%/latex + make all-pdf + cd %~dp0 + echo. + echo.Build finished; the PDF files are in %BUILDDIR%/latex. + goto end +) + +if "%1" == "latexpdfja" ( + %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex + cd %BUILDDIR%/latex + make all-pdf-ja + cd %~dp0 + echo. + echo.Build finished; the PDF files are in %BUILDDIR%/latex. + goto end +) + +if "%1" == "text" ( + %SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The text files are in %BUILDDIR%/text. + goto end +) + +if "%1" == "man" ( + %SPHINXBUILD% -b man %ALLSPHINXOPTS% %BUILDDIR%/man + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The manual pages are in %BUILDDIR%/man. + goto end +) + +if "%1" == "texinfo" ( + %SPHINXBUILD% -b texinfo %ALLSPHINXOPTS% %BUILDDIR%/texinfo + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The Texinfo files are in %BUILDDIR%/texinfo. + goto end +) + +if "%1" == "gettext" ( + %SPHINXBUILD% -b gettext %I18NSPHINXOPTS% %BUILDDIR%/locale + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The message catalogs are in %BUILDDIR%/locale. + goto end +) + +if "%1" == "changes" ( + %SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes + if errorlevel 1 exit /b 1 + echo. + echo.The overview file is in %BUILDDIR%/changes. + goto end +) + +if "%1" == "linkcheck" ( + %SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck + if errorlevel 1 exit /b 1 + echo. + echo.Link check complete; look for any errors in the above output ^ +or in %BUILDDIR%/linkcheck/output.txt. + goto end +) + +if "%1" == "doctest" ( + %SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest + if errorlevel 1 exit /b 1 + echo. + echo.Testing of doctests in the sources finished, look at the ^ +results in %BUILDDIR%/doctest/output.txt. + goto end +) + +if "%1" == "coverage" ( + %SPHINXBUILD% -b coverage %ALLSPHINXOPTS% %BUILDDIR%/coverage + if errorlevel 1 exit /b 1 + echo. + echo.Testing of coverage in the sources finished, look at the ^ +results in %BUILDDIR%/coverage/python.txt. + goto end +) + +if "%1" == "xml" ( + %SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The XML files are in %BUILDDIR%/xml. + goto end +) + +if "%1" == "pseudoxml" ( + %SPHINXBUILD% -b pseudoxml %ALLSPHINXOPTS% %BUILDDIR%/pseudoxml + if errorlevel 1 exit /b 1 + echo. + echo.Build finished. The pseudo-XML files are in %BUILDDIR%/pseudoxml. + goto end +) + +:end diff --git a/docs/modules.rst b/docs/modules.rst new file mode 100644 index 000000000..d4752818a --- /dev/null +++ b/docs/modules.rst @@ -0,0 +1,22 @@ +Software API +============ + +.. autosummary:: + :toctree: _autosummary + + qick + qick.qick + qick.ip + qick.drivers.tproc + qick.drivers.generator + qick.drivers.readout + qick.helpers + qick.streamer + qick.pyro + qick.qick_asm + qick.asm_v1 + qick.parser + qick.averager_program + qick.asm_v2 + qick.tprocv2_assembler + qick.rfboard diff --git a/docs/papers.rst b/docs/papers.rst new file mode 100644 index 000000000..fffd004e0 --- /dev/null +++ b/docs/papers.rst @@ -0,0 +1,226 @@ +QICK papers +=========== + +In the news +----------- +* `QICK news articles `_ + +Commercial products based on QICK +--------------------------------- +* `RealDigital QICK box `_ +* `Safran QICK box `_ +* `iWave RFSoC SoM `_ +* `Mimothor `_ + +QICK and AMD +------------ +* `AMD quantum computing partnership with QICK `_ +* `AMD blog post about hybrid quantum-supercomputing `_ + +At a glance +----------- +**80 papers**: 3 on the QICK system itself, and 77 across 9 platforms and applications. + +*System & software* + +.. list-table:: + :widths: 40 8 + + * - `QICK system`_ + - 3 + +*Qubit & computing platforms* + +.. list-table:: + :widths: 40 8 + + * - `Superconducting circuits`_ + - 54 + * - `Spin defects`_ + - 7 + * - `Quantum dots`_ + - 4 + * - `Biological qubits`_ (new) + - 2 + * - `Neutral atoms`_ + - 1 + * - `Ultracold molecules`_ + - 1 + +*Quantum sensing & detection* + +.. list-table:: + :widths: 40 8 + + * - `Dark matter detection`_ + - 3 + * - `Single-photon detection`_ + - 3 + * - `Quantum sensors and MKIDs`_ + - 2 + +Paper counts +------------ +These stats were computed from the next section's list of QICK papers as of May 2, 2026. + +.. image:: images/papers/QICKpapers_count_May26.png + :alt: QICK papers, total count + +.. image:: images/papers/QICKpapers_qubit_types_May26.png + :alt: QICK papers, by qubit type + +.. image:: images/papers/QICKpapers_scaling_May26.png + :alt: QICK papers, superconducting qubits, by topic + +Papers using QICK +----------------- +This list of academic papers that used the QICK was last updated July 10, 2026. + +QICK system +^^^^^^^^^^^ +* `Martin, D. et al. XCOM: Full Mesh Network Synchronization and Low-Latency Communication for QICK (Quantum Instrumentation Control Kit). (2026) `_. +* `Ding, C. et al. Experimental advances with the QICK (Quantum Instrumentation Control Kit) for superconducting quantum hardware. (2023) `_. +* `Stefanazzi, L. et al. The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors. (2021) `_. + +Superconducting circuits +^^^^^^^^^^^^^^^^^^^^^^^^ + +Autonomous control with QICK +""""""""""""""""""""""""""""" +* `Li, S. et al. Large Language Model-Assisted Superconducting Qubit Experiments (2026) `_. + +Neural network + QICK +""""""""""""""""""""" +* `Guglielmo, G. et al. End-to-end workflow for machine learning-based qubit readout with QICK and hls4ml. (2025) `_. + +Scaling +""""""" +* `Hoyt, A. et al. QASMTrans: An End-to-End QASM Compilation Framework with Pulse Generation for Near-Term Quantum Devices (2026) `_. +* `Li, A. et al. NWQWorkflow: The Northwest Quantum Workflow (2026) `_. +* `Silva, A. et al. Manarat: A Scalable QICK-Based Control System for Superconducting Quantum Processors Supporting Synchronized Control of 10 Flux-Tunable Qubits. (2025) `_. + +Quantum error correction hardware +""""""""""""""""""""""""""""""""" +* `Huang, J. et al. Universal Jaynes-Cummings Control of an Oscillator. (2026) `_. +* `Cochran, J. et al. Experimental signatures of a sigma-z sigma-x beam-splitter interaction between a Kerr-cat and transmon qubit. (2025) `_. +* `Li, Z. et al. A Cascaded Random Access Quantum Memory. (2025) `_. +* `Huang, J. et al. Fast Sideband Control of a Weakly Coupled Multimode Bosonic Memory. (2025) `_. + +Quantum simulation +"""""""""""""""""" +* `Mucci, M. et al. A superconducting quantum circuit single artificial atom maser. (2026) `_. +* `Molinelli, M. et al. Chiral and bond-ordered phases in a triangular-ladder superconducting-qubit quantum simulator. (2026) `_. +* `Martinez, J.G.C. et al. Flat-band localization and interaction-induced delocalization of photons. (2023) `_. + +Gates/couplers +"""""""""""""" +* `Xia, M. et al. Exceeding the Parametric Drive Strength Threshold in Nonlinear Circuits. (2025) `_. +* `Miao, C. et al. Implementation of a quantum addressable router using superconducting qubits. (2025) `_. +* `Cao, X. et al. Parametrically controlled chiral interface for superconducting quantum devices. (2024) `_. +* `Ye, Y. et al. Near-ultrastrong nonlinear light-matter coupling in superconducting circuits. (2024) `_. +* `Zhang, H. et al. Tunable inductive coupler for high fidelity gates between fluxonium qubits. (2023) `_. +* `Xia, M. et al. Fast superconducting qubit control with subharmonic drives. (2023) `_. +* `Johnson, H. et al. Exploration of Optimizing FPGA-based Qubit Controller for Experiments on Superconducting Quantum Computing Hardware. (2023) `_. + +Coherence +""""""""" +* `Olszewski, M. et al. Krypton-sputtered tantalum films for scalable high-performance quantum devices. (2026) `_. +* `Wang, Q. et al. Spectroscopy and Coherent Control of Two-Level System Defect Ensembles Using a Broadband 3D Waveguide. (2025) `_. +* `Huang, S. et al. Towards a hybrid 3D transmon qubit with topological insulator-based Josephson junctions. (2025) `_. +* `Wang, Q. et al. Evidence of Memory Effects in the Dynamics of Two-Level System Defect Ensembles Using Broadband, Cryogenic Transient Dielectric Spectroscopy. (2025) `_. +* `Bland, M. et al. 2D transmons with lifetimes and coherence times exceeding 1 millisecond. (2025) `_. +* `Kumar, S. et al. Protomon: A Multimode Qubit in the Fluxonium Molecule. (2024) `_. +* `Chang, R.D. et al. Eliminating Surface Oxides of Superconducting Circuits with Noble Metal Encapsulation. (2024) `_. +* `McFadden, A. et al. Fabrication and characterization of low-loss Al/Si/Al parallel plate capacitors for superconducting quantum information applications. (2024) `_. +* `Tuokkola, M. et al. Methods to achieve near-millisecond energy relaxation and dephasing times for a superconducting transmon qubit. (2024) `_. +* `Oriani, A.E. et al. Niobium coaxial cavities with internal quality factors exceeding 1.5 billion for circuit quantum electrodynamics. (2024) `_. +* `Anferov, A. et al. Superconducting Qubits Above 20 GHz Operating over 200 mK. (2024) `_. +* `Anferov, A. et al. Improved Coherence in Optically-Defined Niobium Trilayer Junction Qubits. (2023) `_. + +Radiative loss +"""""""""""""" +* `De Dominicis, F. et al. Evaluating radiation impact on transmon qubits in above and underground facilities. (2024) `_. +* `Bratrud, G. et al. First Measurement of Correlated Charge Noise in Superconducting Qubits at an Underground Facility. (2024) `_. +* `Odeh, M. et al. Non-Markovian dynamics of a superconducting qubit in a phononic bandgap. (2023) `_. + +Readout +""""""" +* `Dixit, A. et al. Millimeter Wave Readout of a Superconducting Qubit. (2026) `_. +* `Gibson, J. et al. A scanning resonator for probing quantum coherent devices. (2025) `_. +* `Smitham, B. et al. Sub-resonant wideband superconducting Purcell filters. (2025) `_. +* `Johnson, H. et al. Demonstrating the Potential of Adaptive LMS Filtering on FPGA-Based Qubit Control Platforms for Improved Qubit Readout in 2D and 3D Quantum Processing Units. (2024) `_. +* `Yen, A. et al. Interferometric Purcell suppression of spontaneous emission in a superconducting qubit. (2024) `_. +* `Yen, A. et al. Directional emission of a readout resonator for qubit measurement. (2024) `_. +* `Bryon, J. et al. Experimental verification of the treatment of time-dependent flux in circuit quantization. (2022) `_. + +Parametric amplifiers +""""""""""""""""""""" +* `Hao, Z. et al. Wireless Josephson parametric amplifier above 20 GHz. (2025) `_. +* `Wang, J. et al. High-Efficiency, Low-Loss Floquet-Mode Traveling-Wave Parametric Amplifier. (2025) `_. +* `Bosellli, M. et al. Observation and mitigation of microwave echoes from dielectric defects in Josephson traveling wave amplifiers. (2025) `_. + +Transduction +"""""""""""" +* `Baptista, A.E. et al. Parametrically induced strong coupling between a superconducting quantum circuit and a solid-state spin ensemble. (2026) `_. +* `Warner, H.K. et al. Coherent control of a superconducting qubit using light. (2023) `_. + +Quantum acoustic systems +"""""""""""""""""""""""" +* `Undershute, C. et al. Decoherence of surface phonons in a quantum acoustic system. (2024) `_. + +Open source control with the Qibo/QICK stack (Qibolab/Qibosoq) +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" +* `Pasquale, A. et al. Qibocal: an open-source framework for calibration of self-hosted quantum devices. (2024) `_. +* `Moretti, R. et al. Transmon qubit modeling and characterization for Dark Matter search. (2024) `_. +* `Pedicillo, E. et al. An open-source framework for quantum hardware control. (2024) `_. +* `D'Elia, A. et al. Characterization of a Transmon Qubit in a 3D Cavity for Quantum Machine Learning and Photon Counting. (2024) `_. +* `Carobene, R. et al. Qibosoq: an open-source framework for quantum circuit RFSoC programming. (2023) `_. +* `Efthymiou, S. et al. Qibolab: an open-source hybrid quantum operating system. (2023) `_. +* `Cruz-Martinez, J.M. et al. Multi-variable integration with a variational quantum circuit. (2023) `_. + +Spin defects +^^^^^^^^^^^^ +* `Marcenac, V. et al. Sub-nanosecond control for spin-defect quantum memories with a low-cost, compact FPGA platform. (2026) `_. +* `Katsumi, R. et al. Chiral microwave metasurface for controlling spins in diamond. (2026) `_. +* `Elmslie, T. et al. Homogeneous Microwave Delivery for Quantum Sensing with Nitrogen-Vacancy Centers at High Pressures. (2026) `_. +* `Sadi, M. et al. Landau Zener Interaction Enhanced Quantum Sensing in Spin Defects of Hexagonal Boron Nitride. (2026) `_. +* `Sadi, M. et al. Spin-State Selective Excitation in Spin Defects of Hexagonal Boron Nitride. (2025) `_. +* `Ivory, M. et al. QCaMP: A 4-Week Summer Camp Introducing High School Students to Quantum Information Science and Technology. (2025) `_. +* `Riendeau, E.G. et al. Quantum Instrumentation Control Kit -- Defect Arbitrary Waveform Generator (QICK-DAWG): A Quantum Sensing Control Framework for Quantum Defects. (2023) `_. + +Quantum dots +^^^^^^^^^^^^ +* `El Hajj, D. et al. Preliminary Demonstration of Spin Qubit Control Using the Quantum Instrumentation Control Kit (QICK). (2026) `_. +* `Shinozaki, M. et al. Perfect impedance matching unlocks sensitive radio-frequency reflectometry in 2D material quantum dots. (2025) `_. +* `Koong, Z. et al. Coherent Control of Quantum-Dot Spins with Cyclic Optical Transitions. (2025) `_. +* `Shinozaki, M. et al. RFSoC-based radio-frequency reflectometry in gate-defined bilayer graphene quantum devices. (2025) `_. + +Biological qubits +^^^^^^^^^^^^^^^^^ +* `Ramos-Silva, J.N. et al. A Pulsed Live-Cell Quantum Microscope for Entangled Solid State and Biological Qubits. (2026) `_. +* `Feder, J. et al. A fluorescent-protein spin qubit. (2024) `_. + +Neutral atoms +^^^^^^^^^^^^^ +* `Zhang, B. et al. Leveraging erasure errors in logical qubits with metastable 171Yb atoms. (2025) `_. + +Ultracold molecules +^^^^^^^^^^^^^^^^^^^ +* `Raghuram, A.P. et al. Probing topological edge states in a molecular synthetic dimension. (2026) `_. + +Dark matter detection +^^^^^^^^^^^^^^^^^^^^^ +* `Hoshino, G. et al. First Axion-Like Particle Results from a Broadband Search for Wave-Like Dark Matter in the 44 to 52 ueV Range with a Coaxial Dish Antenna. (2025) `_. +* `Zhao, F. et al. A Flux-Tunable cavity for Dark matter detection. (2025) `_. +* `Knirck, S. et al. First Results from a Broadband Search for Dark Photon Dark Matter in the 44 to 52 ueV range with a coaxial dish antenna. (2023) `_. + +Single-photon detection +^^^^^^^^^^^^^^^^^^^^^^^ +* `Linne, K. et al. PhotonIDs: ML-Powered Photon Identification System for Dark Count Elimination. (2025) `_. +* `Linne, K. et al. SQuaD: Smart Quantum Detection for Photon Recognition and Dark Count Elimination. (2025) `_. +* `Xie, S. et al. Entangled Photon Pair Source Demonstrator using the Quantum Instrumentation Control Kit System. (2023) `_. + +Quantum sensors and MKIDs +^^^^^^^^^^^^^^^^^^^^^^^^^ +* `Magoon, H. et al. A First Demonstration of the SQUAT Detector Architecture: Direct Measurement of Resonator-Free Charge-Sensitive Transmons. (2026) `_. +* `Stifter, K. et al. Cryogenic optical beam steering for superconducting device calibration. (2024) `_. diff --git a/docs/quick_start.rst b/docs/quick_start.rst new file mode 100644 index 000000000..7ae6cdae9 --- /dev/null +++ b/docs/quick_start.rst @@ -0,0 +1,753 @@ +Quick-start guide +================= + +**Have questions? Contact us through any of the channels listed on** :doc:`our support page `. + +This guide will show you how to set up QICK after configuring your +computer and RFSoC board on a local area network (LAN). By the end of +this guide you will have run a QICK program in loopback mode (where +signals loop back from an RF-DAC directly into an RF-ADC)! + +Up to the QICK-specific steps, the setup instructions below run parallel +to the PYNQ and RFSoC documentation, and you might want to refer to that +as well: + +* https://www.rfsoc-pynq.io/getting_started.html +* https://www.rfsoc-pynq.io/rfsoc_4x2_getting_started.html +* https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/57606309/ZCU111+RFSoC+RF+Data+Converter+Evaluation+Tool+Getting+Started+Guide + +Get a board +----------- +The ZCU216, RFSoC4x2, and ZCU111 are all supported by QICK and have +identical FPGA logic capabilities; the differences are in the RF +DACs+ADCs and the design of the rest of the board. For new purchases we +generally recommend the current generation of RFSoC boards for the best +high-frequency performance: the ZCU216 or RFSoC4x2. The ZCU216 has a +higher channel count, allows for flexibility in AC- or DC-coupling your +signals, and can be used with custom frontend boards; the RFSoC4x2 is +available with academic pricing. But we highly recommend that you look +at the board specifications yourself. + +The Xilinx-produced ZCU216 and ZCU111 boards are available from most +major electronics distributors - check the “Authorized Distributors” +list on the board’s Xilinx page: + +* https://www.xilinx.com/products/boards-and-kits/zcu111.html +* https://www.xilinx.com/products/boards-and-kits/zcu216.html + +The RealDigital-produced RFSoC4x2 board is available directly from +RealDigital: https://www.realdigital.org/hardware/rfsoc-4x2. We +recommend that when communicating with RealDigital or AMD/Xilinx, that +you mention that you plan to use the board with QICK - this helps them +understand your needs. + +Prerequisites +------------- + +- Your RFSoC evaluation board kit, from which you will need the + following: + + - The RFSoC board itself, and any daughterboards: + + - For the ZCU216, you’ll need the CLK-104 clocking board and the + XM655 frontend board. + - For the ZCU111, you’ll need the XM500 frontend board. + + - RF cables: + + - An SMA cable that you will use to connect the system in + loopback mode. + - For the ZCU216, you’ll also need the two HC2-to-SMA patch + cables to connect the RF-DAC and RF-ADCs to baluns. + + - Power brick + - The micro-SD card (16 GB or larger) that you will flash the PYNQ + OS image onto; an adapter for full-size SD is also included + - Tools: + + - A 5/16” wrench for SMA connectors (a torque wrench is nice if + you have one, but the wrench in the kit is fine for these first + tests). + - For ZCU216/ZCU111, a Phillips-head screwdriver (size #1) and 4 + mm hex wrench to attach the daughterboard(s). + - For ZCU216, an 0.050” hex wrench for the HC2 connectors. + + - Ethernet cable + - Micro-USB cable (for debugging, or changing the network + configuration) + +- A personal computer, which should have: + + - An Ethernet port that you can free up temporarily + + - If you don’t have a free port, you can buy a USB-Ethernet + adapter - any reputable brand (TP-Link, StarTech) should be OK. + + - An SD or micro-SD card reader (such as IOGEAR SuperSpeed USB 3.0 + SD/Micro SD Card Reader/Writer (GFR304SD) which is available for + purchase at www.amazon.com). A reader that directly reads micro-SD + cards is recommended, to avoid confusion with adapters. + - This guide assumes a Windows PC with the following tools so as to + be accessible to users with little command-line programming + experience, but you can use whatever tools you’re comfortable + with. Linux and MacOS are also fine: you will be able to use their + native SSH/SCP clients, but you will need to find your own + utilities for writing SD card images. + + - The computer should have git installed. In this guide, Github + Desktop is used. + + - You can download Github Desktop here: + https://desktop.github.com/ + + - The computer should have either SSH or PuTTY/PSCP installed. + PuTTY is an open-source SSH client for the Windows operating + system. This guide uses PuTTY/PSCP for accessibility, as some + users are not familiar with the command line. + + - You can download PuTTY here: + https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html + (for instance ``putty-64bit-0.76-installer.msi``). This + installer will also install the ``pscp`` command. + + - The computer should have a utility for writing disk images to + SD cards. We recommend the Win32DiskImager utility, which is an + open-source tool for writing image files to disks. You will use + this utility to flash the PYNQ OS image onto your micro-SD + card. + + - You can download the Win32DiskImager utility here: + https://sourceforge.net/projects/win32diskimager/ + +Flash the PYNQ operating system image onto your micro SD card +------------------------------------------------------------- + +- Your RFSoC board kit comes with a micro SD card. QICK requires an + up-to-date PYNQ image (v2.6 through v3.0.1), so let’s update the + micro SD card with this version of the PYNQ image. The PYNQ + documentation for this step is also good: + https://pynq.readthedocs.io/en/latest/appendix/sdcard.html +- First, download the PYNQ image: + + - For ZCU111 and RFSoC4x2, v3.0.1 is the current recommended + version: http://www.pynq.io/boards.html + - For ZCU216, download the v2.7.0 version from the link in + https://github.com/sarafs1926/ZCU216-PYNQ/issues/1. + +- If you downloaded it as a .zip, you need to unzip it to get a .img + file. You will see that it’s quite a large file. + +.. image:: images/quick_start/largeimagefile.PNG + :alt: The PYNQ 2.6.0 image file + +- Plug your micro SD card into your computer. If you look in the + Windows File Explorer you will see a new disk drive pop up, for + example in my case it was the ``E:\`` drive. This is the drive + associated with your micro SD card. +- Now, open the Win32DiskImager utility and configure 1) the image file + to be your PYNQ image file and 2) the device to be the ``E:\`` drive, + as in the below picture. Before clicking ``Write``, double check that + you are not flashing the image file to the wrong drive (e.g. your + personal computer hard drive)! + +.. image:: images/quick_start/writetoEdrive.PNG + :alt: Writing the PYNQ 2.6.0 image onto the micro SD card + +- Click ``Write``. +- After the write completes, now look in the Windows File Explorer to + see what is now contained in the ``E:\`` drive. You can see several + files that are used to boot the RFSoC. The contents of the ``E:\`` + drive are lightweight and there is plenty more space on the disk + (about 6.8 GB!). So we are now ready to load this micro SD card into + the RFSoC board. + +.. image:: images/quick_start/Eafterwrite.PNG + :alt: The micro SD card drive after a successful write + +Assemble and power on your RFSoC board +-------------------------------------- + +- For the ZCU216 and ZCU111, assemble the board with daughterboard(s). + The 4 mm hex wrench is used to tighten the jackscrew nuts under the + frontend board screws, then the screwdriver is used to screw down the + board. For both the frontend board and the ZCU216’s CLK-104 board, be + careful to align the high-density connector before screwing down the + board. You may find these resources useful in addition to the kit + documentation: + + - For the ZCU216 board, the basic assembly section of this webpage: + https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/246153525/RF+DC+Evaluation+Tool+for+ZCU216+board+-+Quick+start. + - For the ZCU111 board, this video guide: + https://www.youtube.com/watch?v=4JfKlv8kWhs + +- Slide your micro SD card into its slot on the board. +- Make sure the board is in SD card boot mode. + + - For the RFSoC4x2, this is a simple slider switch with “SD” and + “JTAG” labels. + - For the ZCU216 and ZCU111, there’s a 4-position DIP switch (SW2 on + the ZCU216, SW6 on the ZCU111) which you must set as shown in the + photo below (of a ZCU111, but the switch is the same on the + ZCU216), with the first position set to “ON” and the rest to + “OFF.” Xilinx documentation: + `ZCU216 `__, + `ZCU111 `__. + +.. image:: images/quick_start/Bootmodeswitch.png + :alt: Boot mode switch + +- Use your wrench to wire an SMA cable between an RF-DAC channel and an + RF-ADC channel. + + - For the ZCU216, choose DAC 2_231 and ADC 0_226, which will be + generator 6 and readout 0. This is a two-step process, because the + XM655 directly exposes the differential ports of the RF-DACs and + RF-ADCs, and you must patch these through to the baluns that + convert them to regular (single-ended) signals: + + - First identify the gold HC2 connector you want; e.g. 2_231 is + labeled next to connector JHC3. Connect an HC2-SMA cable and + screw it down. + - Now identify the P/N pair of SMA pigtails you want; e.g. the + pair for 2_231 are the last two on this cable. Connect these to + the P and N ports of an available low-frequency (10 MHz-1 GHz) + balun. The third SMA connector next to this balun is the + single-ended port; your SMA cable will connect the single-ended + ports of the two baluns. + - See also + https://docs.amd.com/r/en-US/ug1390-zcu216-eval-bd/CoreHC2-Connector-Pinout-XM655-Only + + - For the RFSoC4x2, choose DAC_B and ADC_D, which will be generator + 0 and readout 0. (You will need to change the generator number in + the demo notebook later, since the demos assume generator 6.) + - For the ZCU111, choose DAC 229 CH3 and ADC 224 CH0, which will be + generator 6 and readout 0. These names are written directly on the + XM500 breakout board. See also + https://docs.amd.com/r/en-US/ug1271-zcu111-eval-bd/XM500-ADC/DAC-Data-and-Clock-SMA + - You’re doing this with the board powered down, but in general: + it’s OK to connect/disconnect RF cables with the board powered. + However, you should be very careful not to touch any of the + exposed electrical components with metal tools or connectors. + **This can cause immediate, permanent damage to your board which + cannot be repaired.** In particular: + - The frontend daughterboards of the ZCU216 and ZCU111 have rows of + header pins, some of which can destroy the board if shorted to + each other or to ground. + - If you have SMA cables with loose ends (for example, the unused + lines of a ZCU216’s HC2-to-SMA cable), always cover their + connectors completely with the rubber caps that came with the + cables. + - Observe general housekeeping and workplace hygiene principles - + don’t leave loose tools rolling around your lab bench, keep loose + adapters in bowls or drawers, be aware of where a tool might fall + if dropped. + +- Connect an Ethernet cable and/or USB cable, and configure your + computer, as specified in the next section. +- Connect the power cable to the RFSoC board. Flip the board power + switch on (it’s next to the power cable). You should hear the fan + above the RFSoC chip begin to whir, and you should see LED lights + blinking all over the board. You should also see lit or blinking LEDs + that indicate the Ethernet port is connected to your computer: two + LEDs built into the face of the port and a third LED next to the port + labeled “LINK.” +- Your board setup should look something like the below cartoon: + +.. image:: images/quick_start/boardpic_cartoon.PNG + :alt: An assembled ZCU111 board + +- The board will take a minute or two to boot up. Five minutes is more + than enough; if you can’t connect to the RFSoC after this time + something is wrong with your setup (check your cabling, check that + your SD card is properly inserted, retry with a serial connection + over USB as described below). + +Connect to your RFSoC over the network +-------------------------------------- + +You will normally connect to the RFSoC over a network connection, most +typical setups are one of the following: + +* Point-to-point: the RFSoC is directly connected to the PC through a single Ethernet cable. + This is the simplest but usually not a long-term solution, because it consumes an Ethernet port on the PC. + (The RFSoC4x2 also supports creating a point-to-point network connection over USB; refer to the 4x2 documentation.) +* LAN with static IPs: the RFSoC, PC, and other lab equipment are connected to a switch, which doesn’t assign IP addresses. + Each piece of equipment has a unique static IP configured internally; all IPs are in a common range. +* LAN with router: the RFSoC, PC, and other lab equipment are connected to a router, which assigns IP addresses automatically. + Other lab equipment might be connected to the router as well. + The router could additionally be configured as an Internet gateway, to allow the PC and RFSoC to access the Internet. + + * Your institution’s network is probably capable of playing this role, but this is not recommended because problems are difficult to debug, and because this exposes the RFSoC to all other users on the network. + Only do this if you have experience with Linux network configuration and security, know the network security rules for your institution, and follow all of the security recommendations below. + +Configure the network +~~~~~~~~~~~~~~~~~~~~~ + +The default network settings of the RFSoC are as follows (see the +section below for instructions on changing them): + +* If it’s connected to a router, it will use an assigned address. +* Otherwise it will use 192.168.2.99. + +It is sometimes difficult to tell what IP address the RFSoC is using. +Here are some ways: + +* If you’re using a router, the router will know what address it assigned to the RFSoC (see the section below). +* You can use the serial-over-USB connection to log in and check the network status (see the section below) +* The RFSoC4x2 has an OLED screen that displays the IP address. + +For a LAN with static IP +^^^^^^^^^^^^^^^^^^^^^^^^ + +The default settings are fine for point-to-point or router setups, but +for a static-IP LAN you will generally want an IP other than +192.168.2.99, because your other equipment is unlikely to be using the +192.168.2.xxx IP range. In that case you should make an initial +connection to change the RFSoC’s network settings, using one of the +other options (point-to-point network, router network, or +serial-over-USB). We recommend the point-to-point network, which is +usually the easiest to set up. + +- Once you have a terminal with root privileges, open + ``/etc/network/interfaces.d/eth0`` in a text editor such as ``vim`` + or ``nano``. +- If you’re not familiar with any command-line text editor, ``nano`` is + a good choice: +- Run ``nano /etc/network/interfaces.d/eth0`` to open the file. +- Make your change. You can cut entire lines with Control+k and paste + them with Control+u. A hash at the start of a line in an + ``interfaces`` file comments it, which you might use to stash old + settings or describe your changes. +- Save with Control+o (hit Enter to write to the same file you opened) +- Exit with Control+x. +- The file will look like this: + +:: + + auto eth0 + iface eth0 inet dhcp + + auto eth0:1 + iface eth0:1 inet static + address 192.168.2.99 + netmask 255.255.255.0 + +- Change the ``192.168.2.99`` to the desired static IP address, and + save the file. You can now close the terminal, power off the RFSoC + board, and connect it to the switch. +- Configure youe computer’s Ethernet port to connect to the LAN with a + static IP. + +For a point-to-point Ethernet connection +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- Connect your Ethernet cable from your computer to the RFSoC Ethernet + port. +- Configure your computer’s Ethernet port with a static IP in the + 192.168.2.xxx range, similar to below (see also + https://pynq.readthedocs.io/en/latest/appendix/assign_a_static_ip.html): + +.. image:: images/quick_start/static_ip.png + :alt: Setting a static IP in Windows + +- After powering up, the board should be online at ``192.168.2.99``. + You can now connect to it at this address using Jupyter or SSH (see + below). + +For a LAN with a router +^^^^^^^^^^^^^^^^^^^^^^^ + +Use a router (e.g. a Cisco RV160 VPN Router which is available for +purchase at www.amazon.com), which will automatically assign an IP +address to your RFSoC board. The router used in this guide has 4 LAN +ports. For instance, in a typical qubit control setup you can connect +one LAN port to your personal computer, a second LAN port to your +ZCU216, and a third point to an Ethernet switch (for example the NETGEAR +24-Port Gigabit Ethernet Unmanaged Switch (JGS524) which is available +for purchase at www.amazon.com). That Ethernet switch can place 24 more +devices (such as external trigger sources, local oscillators, +programmable attenuators or other lab equipment) on the router’s subnet, +making them accessible to your personal computer. + +- Connect both your computer and the RFSoC to the router with Ethernet + cables. +- Unlike the point-to-point case, you won’t set a static IP on your + computer’s Ethernet port; you’ll leave it on its default + configuration, where it will let the router auto-configure its + address. +- Log into your router via a web browser. In the case of the router + used in this guide, doing so is straightforward and is explained + here: + https://www.cisco.com/c/dam/en/us/td/docs/routers/csbr/RV160/Quick_Start_Guide/EN/RV160_qsg_en.pdf +- After powering up, look at the list of devices found by your router. + You should see two devices; your PC and your RFSoC (id ``pynq``). + Take note of the IP address that was assigned to the RFSoC (in my + case it was assigned the address ``192.168.1.146``). You can now + connect to the board at this address using Jupyter or SSH (see + below). + +.. image:: images/quick_start/ciscorouter.PNG + :alt: Devices found by the router + +- Most routers will allow you to assign a permanent IP address to the + RFSoC based on its MAC address, which you can get by running the + ``ifconfig`` command in a terminal and looking for ``ether``. The + ZCU216 and ZCU111 have a sticker with the MAC address, and you should + check that this matches the output of ``ifconfig`` (if not, see + https://github.com/openquantumhardware/qick/issues/182). + +Log in +~~~~~~ + +You can connect to the RFSoC over the network in two ways: through the +RFSoC’s Jupyter server, which you access using a web browser and Jupyter +password, and through the RFSoC’s SSH server, which you access using SSH +and SCP clients and Linux password. Jupyter will probably be your main +interface, and you will use it to run the QICK demos. SSH gives you a +terminal and SCP is used for file transfers; you can also create +terminals and upload/download files in Jupyter, but it’s not as +flexible. You will use SCP to upload the QICK software and firmware to +the RFSoC. + +The Jupyter server and the Linux operating system have separate access +credentials, with the following defaults: + +* Jupyter: password is ``xilinx``. +* Linux OS: username is ``xilinx``, password is ``xilinx``. + There is also a root (admin) account, password ``xilinx``, but the ``xilinx`` user can become root using ``sudo -s`` (you will need to enter the user password). + +**These defaults are very insecure.** You must change them if your RFSoC +will be connected to a network accessible to people outside your lab +group. Some of the default settings have alternatives that add no +inconvenience, and we recommend that everyone should change those even +if the network is safe. See the section below on “Secure your RFSoC” for +details. + +Over the network, via Jupyter +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- Now you are prepared to connect to your RFSoC. Before you clone the + ``qick`` repository and copy it onto the RFSoC, let’s see what is + initially on the RFSoC’s operating system (this was determined by the + contents of the PYNQ image). To do so, simply enter the IP address + assigned to the RFSoC into a web browser on your personal computer: + ``192.168.1.146``. The username and password for the ZCU111 are by + default ``xilinx`` and ``xilinx``, respectively. You can change those + by entering ``sudo`` mode once you’ve logged into the RFSoC via SSH + (you will log in via SSH in the next part of this guide). +- You should see this default Jupyter notebook browser: + +.. image:: images/quick_start/pynqstartup.PNG + :alt: PYNQ startup + +- You can see that there are a few demo Jupyter notebooks already + loaded onto the RFSoC which you can feel free to explore. But now + let’s connect to the RFSoC via SSH, where you will have more + flexibility and control. For instance, only after you have + established an SSH connection can you copy the ``qick`` repo onto the + RFSoC and do the upcoming QICK loopback demo. +- If you need to open a root terminal for changing network settings, + click the “New” button at the upper right and open a terminal. + +Over the network, via SSH +^^^^^^^^^^^^^^^^^^^^^^^^^ + +- To connect via SSH, open the PuTTY application and input the IP + address assigned to the RFSoC (``192.168.1.146``) as below: + +.. image:: images/quick_start/putty1.PNG + :alt: Using PuTTY (1) + +- Click ``Open``. You will see the following login screen on a new + terminal. Use the Linux username and password (by default, ``xilinx`` + and ``xilinx``). + +.. image:: images/quick_start/putty2.PNG + :alt: Using PuTTY (2) + +- After successfully logging in you will see a Linux terminal. You have + now remotely logged on to the RFSoC. + +.. image:: images/quick_start/putty3.PNG + :alt: Using PuTTY (3) + +- If you need root privileges for changing settings, run ``sudo -s`` + and enter the user password again. +- It’s convenient to save these session settings; you can also set the + username as part of the hostname e.g. ``xilinx@192.168.1.146``. + +Through a serial connection over USB, for debugging or changing the configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You can also log in to the RFSoC using a serial connection. + +* Connect a PC to the board via the micro-USB port. + Under the Device Manager under COM ports the RFSoC should show up as three COM connections. + Usually, the port you should use is the first of those three. +* Power up the RFSoC board. + It is important to boot the board after the USB cable has been connected between the board and your PC. +* Using PuTTY, select “Serial” connection type, enter the port number (e.g. ``COM4``), and the serial speed, ``115200``. +* This will open a terminal that directly connects to the RFSoC CPU. + You may need to log in with Linux credentials. + +These are things you might check: + +* For debugging network issues, ``ifconfig`` will give the assigned IP address. +* If the RFSoC is having trouble accessing network devices outside the LAN, the default gateway may not be set; this can be checked with ``ip route``. + There should be an IP address marked as ``default``. + If this is not present, a default must be set using ``sudo ip route add default via xxx.xxx.xxx.1``, replacing the IP address with the local network address. +* Finally, the RFSoC may need to be configured to properly access the internet. + Open ``/etc/resolv.conf`` in a text editor such as ``vim`` or ``nano``, and ensure that it contains ``nameserver 8.8.8.8``, ``options eth0``. + Note that ``resolv.conf`` may be re-generated when the board is power-cycled. + +Secure your RFSoC +~~~~~~~~~~~~~~~~~ + +As mentioned above, the default settings for accessing the RFSoC are +quite insecure. If you change nothing, anybody with access to the +RFSoC’s network will be able to get full access without much difficulty. +The significance of this depends on your network configuration and the +harm that could be caused by a breach. In other words: + +* How much do you trust the people and devices on the RFSoC’s network? + If you have a point-to-point connection, the RFSoC is only connected to your PC, so the network is as secure as your PC. + If you put the RFSoC on your institution’s network, you can trust the network only as much as you trust every user and device on the network - if an attacker compromises any computer at your institution, they could then attack your RFSoC. +* What harm could an attacker do? + If the security of your RFSoC is compromised, they could read, delete, or modify anything on the SD card, run arbitrary malware on the RFSoC, or control any equipment controlled by the RFSoC. + So you should judge the consequences of this. +* Are there any rules you need to follow? + Your institution may have rules about securing computers that are connected to the institution’s network, connected to expensive equipment, or used for important/sensitive research. + These rules may apply, and may be stricter than what you would arrive at by taking a “common sense” approach to the two points above. + +You should weigh these factors and the recommendations below. + +Disable root login +^^^^^^^^^^^^^^^^^^ + +Brute-force password-guessing attacks against SSH servers are extremely +common, and the root account is a common target because the username is +standard and the account has maximum privileges. The default root +password of ``xilinx`` is easily guessed. You could set a stronger root +password, or block SSH login for the root account, but given that +``sudo`` is just as easy a way to get root privileges, you never +actually need to use the root password and it’s easier to disable it +completely. In other words, this improves security and adds no +inconvenience; **everyone should make this change.** + +- Log in via SSH using the ``xilinx`` username and that account’s + password (``xilinx``, unless you’ve changed it). +- Run ``su`` and enter the root password (``xilinx``) to become root. +- Run ``passwd -l root`` to lock the root password. This makes it + impossible to log in as root over SSH or using ``su``, but you can + still get root access through Jupyter or ``sudo``. +- Run ``exit`` (or use the keyboard shortcut Control-d) to exit your + root session and get back to being a regular user. +- Run ``su`` and enter the ``xilinx`` password again. This should fail! +- Run ``sudo -s`` and enter the user password to check that you can + still use ``sudo`` to become root. + +The terminal output from these steps should look like this: + +:: + + xilinx@pynq:~$ su + Password: + root@pynq:/home/xilinx# passwd -l root + passwd: password expiry information changed. + root@pynq:/home/xilinx# exit + exit + xilinx@pynq:~$ su + Password: + su: Authentication failure + xilinx@pynq:~$ sudo -s + [sudo] password for xilinx: + root@pynq:/home/xilinx# + +Change the Linux user password +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The default username and password are both ``xilinx``, and this is +easily guessed if an attacker knows the board is running PYNQ OS. +Because this account has ``sudo`` rights, knowing this account’s +password is as good as having root access. Changing the password doesn’t +add significant inconvenience. **We strongly recommend that you change +this password.** + +Choose the strength and style (random characters, random words, etc.) of +the password based on what is natural to you and your lab group, how +secure you need your RFSoC to be, and how dangerous the network +environment is. +A password manager or password generator can help with generating a high-quality password. +You should store the password in a secure and resilient +way; again this will depend on how your lab group operates, but could +mean a lab notebook, a file on a secure shared disk, or a password manager. + +- Choose a new password and make a record of it. +- Log in via SSH using the ``xilinx`` username and that account’s + password (``xilinx``). +- Run ``passwd``; enter the current password (``xilinx`` again) and + then enter your desired password twice. +- Disconnect and check that you can log in via SSH using the new + password. + +The terminal output from these steps should look like this: + +:: + + xilinx@pynq:~$ passwd + Changing password for xilinx. + Current password: + New password: + Retype new password: + passwd: password updated successfully + xilinx@pynq:~$ + +Restrict remote Jupyter access +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Because the Jupyter server runs with root privileges, having access to +Jupyter is as good as having root access. The default password +``xilinx`` is easily guessed; also, because the Jupyter server uses HTTP +and not HTTPS, an attacker listening to traffic on your network could +get a hash of your password when you log in (not as bad as getting the +password, but this is still considered a risk). The preferred solution +is to block remote access to Jupyter, and only access Jupyter through +SSH. This adds a step when connecting to Jupyter, but is easy to set up +(easier than changing the Jupyter password, and more effective for +security). **We strongly recommend this if your RFSoC is on an untrusted +network.** + +To set this up, get a terminal with root privileges and open +``/root/.jupyter/jupyter_notebook_config.py`` in a text editor (such as +``nano`` - see the section above on setting up a static IP). Page down +to the bottom, where you should see something like this: + +:: + + # c.TerminalManager.cull_interval = 300 + c.NotebookApp.ip = '0.0.0.0' + c.NotebookApp.notebook_dir = '/home/xilinx/jupyter_notebooks' + c.NotebookApp.password = 'sha1:46c5ef4fa52f:ee46dad5008c6270a52f6272828a51b16336b492' + +Put a hash at the beginning of the line with ``c.NotebookApp.ip``, to +comment out that setting. Now reboot. Point your browser to the RFSoC’s +IP address (for example 192.168.1.146): it should redirect to port 9090 +(i.e. the address bar should show ``192.168.1.146:9090``) as usual, but +the page should not load. + +To access Jupyter after making this change, you will need to use SSH +port forwarding: + +* Add port forwarding to your SSH configuration. + The example below shows how you would tell PuTTY to forward port 5678 on your PC to port 9090 on the RFSoC (the Jupyter server’s port). + The choice of 5678 is arbitrary, and if you connect to multiple RFSoCs from the same computer in this way you need to use different ports. + (If using macOS or Linux, you would specify port forwarding as part of the command, e.g. ``ssh xilinx@192.168.1.146 -L 5678:localhost:9090``.) + +.. image:: images/quick_start/port_forward.png + :alt: PuTTY configuration for port forwarding + +- Make the SSH connection. You will need to leave the connection open + while using the Jupyter server. +- Point your browser to ``localhost:5678``. You should get the Jupyter + server. +- You might need to open port 5678 in your firewall: one way to do this + is to enable the checkbox “Local ports accept connections from other + hosts” in the PuTTY configuration shown above and make the + connection, which should trigger Windows to ask if you want to open + the port. Once you’ve done this, you should disable that checkbox + (since you’re otherwise exposing the Jupyter server to the network + again, just through your PC instead of directly from the RFSoC). + +Copy the QICK tools onto your RFSoC +----------------------------------- + +- Use Github Desktop to clone the ``qick`` repo onto your personal + computer (Google around for resources if you are not sure how to do + this). +- Open the Command Prompt application in Windows and, after navigating + to the directory containing your cloned ``qick`` repo, type in the + following command (substituting the IP address that was assigned to + your RFSoC): + +.. image:: images/quick_start/pushingdatatotheboard.PNG + :alt: Pushing data to the RFSoC with pscp + +- This copied the ``qick`` repository into the ``jupyter_notebooks`` + folder in the ``/home/xilinx/`` directory of the RFSoC. +- Your Jupyter notebook browser has now updated to include the ``qick`` + repository, as shown below: + +.. image:: images/quick_start/jupyternotebook1.PNG + :alt: Jupyter notebook main folder + +Install the ``qick`` Python package and running a QICK program in loopback mode +------------------------------------------------------------------------------- + +.. * Navigate to the `qick` directory and run: `sudo python3 -m pip install .` + This will install the qick Python package. + +- Navigate to the ``qick_demos`` subfolder within the ``qick`` + directory and run the Jupyter notebook + ``000_Install_qick_package.ipynb``. This will walk you through + installing and testing the ``qick`` package. +- Open ``00_Send_receive_pulse.ipynb`` (also in the ``qick_demos`` + directory) and run the Jupyter notebook cells in order. You should + see very similar output to that posted here: + https://github.com/openquantumhardware/qick/blob/main/qick_demos/00_Send_receive_pulse.ipynb. + You are seeing pulses being sent out of the RFSoC RF-DACs and looping + back to the RFSoC RF-ADCs! In future tutorials you will learn the + meaning of all the variables and parameters defined within the + Jupyter notebook cells. + +.. ## Running a QICK program in loopback mode + + * You can also take the opportunity to check that you have flashed the correct PYNQ version: + +

+ The correct PYNQ version +

+ +Copy data off of your RFSoC and onto your personal computer +----------------------------------------------------------- + +- Let’s say that you have created a ``quick_start_demo`` directory with + your work and you want a local copy of the entire directory (for + example, you exported your data to ``.png`` plots that are within the + ``quick_start_demo`` directory on the RFSoC, and you want to move + those plots back to your personal computer). To do this, you do + something analogous to when you copied the ``qick`` repository onto + the RFSoC earlier in this guide: +- Open the Command Prompt application in Windows and, after navigating + to your local directory where you want the files to go, type in the + following command (substituting the IP address that was assigned to + your RFSoC): + +.. image:: images/quick_start/pullingdataofftheboard.PNG + :alt: Pulling data off the RFSoC with pscp + +- Now the ``quick_start_demo`` directory has been copied to your local + directory. + +Next steps +---------- + +- You should work through the demo notebooks in ``qick_demos`` to learn how QICK works and see some example programs for making measurements with QICK. +- It's recommended, but not essential, to set up Pyro4 to allow the firmware state to persist between notebooks or scripts. + The demo notebooks (and QICK in general) can be used with or without Pyro4. + See the `Pyro4 demo notebooks `_ for more information. + +**Hopefully this guide was a helpful introduction to QICK!** diff --git a/docs/requirements.txt b/docs/requirements.txt new file mode 100644 index 000000000..f8cfa6adc --- /dev/null +++ b/docs/requirements.txt @@ -0,0 +1,3 @@ +numpy>=1.14.2 +tqdm +sphinx-rtd-theme diff --git a/docs/topics/asmv1_cheatsheet.rst b/docs/topics/asmv1_cheatsheet.rst new file mode 100644 index 000000000..252b66875 --- /dev/null +++ b/docs/topics/asmv1_cheatsheet.rst @@ -0,0 +1,58 @@ +tProc v1 ASM cheatsheet +======================= + +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - Python calls + - + * - ``soc.tproc.single_write(addr=imm, data=variable)`` + - writes the value ``variable`` to the data memory address ``imm``. + +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - ASM_Program calls + - + * - ``p.memri(p, r, imm, 'comment')`` + - reads the data memory at the address specified by ``imm`` and writes the result into page ``p``, register ``r``. + * - ``p.regwi(p,r,value)`` + - writes the ``value`` to page ``p``, register ``r``. + * - ``p.bitwi(p, rDst, rSrc, operation, value)`` + - performs the bitwise ``operation`` on the contents of page ``p``, register ``rSrc`` and ``value`` and writes the result in page ``p``, register ``rDst``. ``rSrc`` and ``rDst`` may be the same or different. + * - ``p.bitw(p, rDst, rSrc1, operation, rSrc2`` + - performs the bitwise ``operation`` on two source registers (``rSrc1`` and ``rSrc2``) and puts the result in the destination register ``rDst``, where all three registers are on the same page ``p``. + * - ``p.seti(channel, p, rSrc, time)`` + - takes the value at page ``p``, register ``rSrc`` and sends it to ``channel`` that the specified ``time``. + * - ``p.label(labelName)`` + - marks this location in the program, for use by the ``loopz`` and ``condj`` commands. + * - ``p.set(channel, p, ra, rb,rc,rd,re,time)`` + - sends the values on page ``p`` registers ``ra``, ``rb``, ``rc``, ``rd``, ``re`` to ``channel`` at ``time``. The registers ``ra`` through ``re`` contain, in order, 16-bit values of frequency, phase, address, gain, and ( ``nsamp`` , ``outsel`` , ``mode`` , ``stdysel`` ). + * - ``p.sync(p,r)`` + - synchronizes the internal time offset to the value specified by page ``p``,register ``r``. + * - ``p.synci(p,timeOffset)`` + - synchronizes the internal time offset by ``timeOffset``. + +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - QickProgram bitwise operations + - + * - ``<<`` + - shifts bits left by ``value`` bits, ignores ``rSrc`` + * - ``|`` + - or + * - ``&`` + - and + * - ``^`` + - exclusive or + * - ``~`` + - not ``value``, ignores ``rSrc`` + +tProcessor register information +------------------------------- + +The tproc contains 8 pages of 32 registers each, making 256 registers in total. Each register is 32 bits wide. diff --git a/docs/topics/changing_fs.rst b/docs/topics/changing_fs.rst new file mode 100644 index 000000000..15cb9bc96 --- /dev/null +++ b/docs/topics/changing_fs.rst @@ -0,0 +1,59 @@ +Changing sample rates +===================== + +You may want to use DAC and ADC sample rates (often abbreviated as "fs") different from what's compiled into the firmware. +This may be useful for optimizing DAC output power, or for avoiding Nyquist zone boundaries of the DAC or ADC. + +It is therefore possible, with limitations, to apply custom sample rates when loading firmware. +The firmware configuration (as printed by :class:`.QickConfig`, and used to convert pulse/readout frequencies to firmware units) will be updated to reflect your changes, so you should be able to use QICK as if the firmware had been compiled with your custom rates. + +This feature is experimental and may have unpredictable side effects. +In particular, it is possible that large changes in sample rates will lead to instability in the firmware logic, which may have subtle effects or crash the OS completely. +It is also possible that some exotic custom firmwares might have sample rate restrictions that the QICK software doesn't adequately check for. + +Limitations +----------- + +* All channels in a given DAC or ADC tile share the same sample rate. +* Sample rates can only be set to certain discrete values, determined by the tile PLL. +* The minimum and maximum sample rates are subject to various constraints which depend on the RFSoC chip, the generator or readout block, and the clock distribution scheme in the firmware. +* The firmware may be designed so some tiles share a logic clock. + If this is the case, those tiles must have their sample rates scaled by the same factor. +* The QICK software won't allow you to increase any sample rate, because the firmware logic may become unstable if run faster than originally compiled. + +API +--- + +Use :meth:`.QickSoc.valid_sample_rates()` to list all the valid sample rates for a given tile: + +>>> soc.valid_sample_rates(tiletype='dac', tile=0) +array([ 500.62222222, 501.76 , 502.69090909, 503.46666667, +... + +Use :meth:`.QickSoc.round_sample_rate()` to round a value of your choice to the nearest valid sample rate: + +>>> soc.round_sample_rate(tiletype='dac', tile=0, fs_target=5000) +5017.6 + +If you print the firmware configuration, there is a line that lists tiles that share clocks: + +>>> print(soccfg) +... +Groups of related clocks: [tProc timing clock, DAC tile 0, DAC tile 1], [ADC tile 0, ADC tile 2] +... + +The optional ``dac_sample_rates`` and ``adc_sample_rates`` parameters to :class:`.QickSoc()` are used to set custom sample rates. +These parameters should be dictionaries specifying the desired sample rates. +You can omit either parameter to leave that side of the RFSoC alone; similarly you can omit individual tiles from either dictionary. + +The values you supply will be rounded to valid values, but you will get an error or warning if the rounded value was too far from what you supplied. + +>>> soc = QickSoc('/data/fw/2024-09-29_111_tprocv2r21_standard/qick_111.bit', +... dac_sample_rates={0: 5017.6, 1: 5017.6}, +... adc_sample_rates={0: 3072.0, 2: 3072.0}) + +You might find :meth:`.QickSoc.get_sample_rates()` convenient to get the sample rates of the currently loaded firmware, in the format needed for ``dac_sample_rates`` and ``adc_sample_rates``. + +>>> soc.get_sample_rates() +{'dac': {0: 6144.0, 1: 6144.0}, 'adc': {0: 4096.0, 2: 4096.0}} + diff --git a/docs/topics/freq_matching.rst b/docs/topics/freq_matching.rst new file mode 100644 index 000000000..f32b31c42 --- /dev/null +++ b/docs/topics/freq_matching.rst @@ -0,0 +1,20 @@ +How to ensure frequency matching +================================ + +Generators and readouts have different frequency units, and the frequencies used in the two systems must be exactly equal. +If they are not, there will be a small difference between the upconversion and downconversion frequencies - this will manifest as a sliding phase, and so you will not see a consistent phase between acquisitions. + +There are two ways to ensure frequency matching: + +* When converting a frequency to an integer value (often with :meth:`.QickConfig.freq2reg()` or :meth:`.AbsQickProgram.declare_readout()`), specify not only the channel you are configuring, but the channel you want to be frequency-matched to. +* Before doing any conversion, round the frequency to the closest frequency that is valid on both channels using :meth:`.QickConfig.adcfreq()`. + +Frequency-matching makes your frequency resolution worse, since the smallest possible frequency step is now the LCM of the two channels' frequency steps. +Usually this doesn't matter - O(10 Hz) resolution is ample for most applications - but you can disable frequency-matching by specifying None as the other channel. + +You may have a generator that does not itself drive any readouts, but needs to be phase-locked to a generator that does. +In this case you will want to frequency-match both generators to that readout, otherwise the two generators will have slightly different frequencies and you will have a sliding phase between them. + +If you have multiple generators (or readouts) of the same type and sampling frequency, it doesn't matter which you use to specify the matched channel. +In many QICK firmwares, all generator and readout channels are the same and it's OK to just use ch 0 for the matched channel. +But it's a good habit to do this consistently correctly. diff --git a/docs/topics/gen_config.rst b/docs/topics/gen_config.rst new file mode 100644 index 000000000..571b7c827 --- /dev/null +++ b/docs/topics/gen_config.rst @@ -0,0 +1,22 @@ +Pulse configuration options +=========================== + +Use ``stdysel`` to select what value is output continuously by the signal generator after the generation of a pulse. + +* 0: the last calculated sample of the pulse +* 1: a zero value + +Use ``mode`` to select whether the output is periodic or one-shot. Here is what happens after generating the specified number of samples. Look in the queue to see if there is a new waveform to generate. If there is a new waveform in the queue, remove it from the queue and generate it. If there is not, use the value of ``mode`` to decide what to do. + +* 0: stop +* 1: repeat the current waveform + +Then continue looking for a new waveform. + +Use ``outsel`` to select the output source. The output is complex. Tables define envelopes for I and Q. + +* 0: product of table and DDS +* 1: DDS +* 2: from the table for the real part, and zeros for the imaginary part +* 3: always zero + diff --git a/docs/topics/index.rst b/docs/topics/index.rst new file mode 100644 index 000000000..068111449 --- /dev/null +++ b/docs/topics/index.rst @@ -0,0 +1,14 @@ +Specific topics +=============== + +.. toctree:: + :maxdepth: 1 + + asmv1_cheatsheet + timing + freq_matching + playing_pulses + gen_config + units + changing_fs + reference_clock diff --git a/docs/topics/playing_pulses.rst b/docs/topics/playing_pulses.rst new file mode 100644 index 000000000..4e9ca76e9 --- /dev/null +++ b/docs/topics/playing_pulses.rst @@ -0,0 +1,41 @@ +How to play pulses +================== + +There are three steps to playing a pulse: + +Loading a waveform +------------------ + +(You skip this step for rectangular "const" pulses, which have no envelope.) + +Each signal generator has an internal waveform memory, which stores the I/Q data for the pulse envelope. +Multiple waveforms can be stored in the same signal generator, and a single waveform can be used for different pulses (e.g. a Gaussian waveform can be used for Gaussian pulses and the ramp-up/ramp-down of flat-top pulses with different flat-top duration, each with its own gain and carrier frequency). + +:meth:`.AbsQickProgram.add_envelope()` writes an arbitrary waveform to the specified channel's waveform memory. +:meth:`.AbsQickProgram.add_gauss()`, :meth:`.AbsQickProgram.add_triangle()`, and :meth:`.AbsQickProgram.add_DRAG()` write commonly-used standard pulse waveforms, with duration units of fabric clock cycles. The name is used in the next step. + +Setting registers +----------------- + +There are a lot of parameters that need to be specified when playing a pulse - more than can be specified inline in a tProcessor instruction. +So all the parameters must be written to registers first, and when we fire the pulse we just tell the tProcessor which registers to read. + +:meth:`.QickProgram.set_pulse_registers()` writes the settings for a pulse to registers. +All arguments to this method must be integers in the native units of the signal generator. +This can happen immediately before you fire the pulse, but if a signal generator is only used for one type of pulse you will save time for the tProcessor by setting registers in initialization, before the program loop. +If you have some parameters that change from pulse to pulse, and some that never change, you can write the fixed parameters in initialization using :meth:`.QickProgram.default_pulse_registers()` and the varying parameters in the body with :meth:`.QickProgram.set_pulse_registers()`. + +If you want to modify pulse parameters on the fly (for example, you might want to sweep the frequency of the qubit drive pulse), you will set the registers in two steps (you can see an example in the demo :repofile:`qick_demos/02_Sweeping_variables.ipynb` ): + +First, use :meth:`.QickProgram.set_pulse_registers()` to write initial values for all parameters. You could do this in initialization, or right before the following step. +Second, overwrite the register(s) you want to update. +You need to get the page and address of the register using :meth:`.QickProgram.ch_page()` and :meth:`.QickProgram.sreg()`. +Then you can use assembly instructions to change the value of that register. + +Firing the pulse +---------------- + +:meth:`.QickProgram.pulse()` fires a pulse on the specified channel at the specified time, using whatever values are loaded in the registers. + +Often you will want to trigger the readout at the same time: :meth:`.QickProgram.measure()` is a wrapper around :meth:`.QickProgram.trigger()` and :meth:`.QickProgram.pulse()`. +But it's good to remember and understand the building blocks inside this wrapper. diff --git a/docs/topics/reference_clock.rst b/docs/topics/reference_clock.rst new file mode 100644 index 000000000..43a65a74b --- /dev/null +++ b/docs/topics/reference_clock.rst @@ -0,0 +1,38 @@ +Reference clock generation +========================== + +It's an advantage of the RFSoC that all of the DAC and ADC clocks are synthesized from a common reference and are always phase-locked with respect to each other. +This reference is generated by dedicated clock synthesizer chips which are normally locked to an on-board reference oscillator. +The on-board oscillator is pretty good (sub-ppm stability, check the board schematics), better than the linewidths of most devices. + +The clock chips are configured the first time you initialize :class:`.QickSoc()` after powering on your board; after that, they are normally only reconfigured if you are specifying a certain configuration (such as external clock, see below). +You will see some LEDs come on when the clocks are configured; they should then stay on continously without flickering, except when reconfigured. +On the ZCU216/ZCU208, the clock chips and their status LEDs are on the CLK104 daughterboard. For the other boards, the clock chips and LEDs are on the main board. + +* ZCU111: four LEDs in a row, labeled "4208 STATUS" and "MUXOUT RF1/2/3" +* ZCU216/ZCU208: the clock chips and LEDs are on the CLK104 daughterboard; one LED is a power indicator and three are status +* RFSoC4x2: four LEDs in a row, labeled "CLOCK STATUS" + +External clock +-------------- + +You might want to lock your board to an external clock source for two reasons: + +* Frequency stability: the on-board reference oscillator is good but not perfect. + If you play a continuous tone from a DAC into a spectrum analyzer and put your finger on the oscillator's metal can, you will see the frequency shift by hundreds of Hz. + You might need better stability, such as what you get from a rubidium reference. +* Synchronization: you may need the RFSoC to be phase- or frequency-locked to other instrumentation or other RFSoCs. + +QICK, and all of the supported RFSoC boards, accept an external reference clock. +To make your board lock to a reference, use the ``external_clk=True`` argument to :class:`.QickSoc()`. +See the API documentation for the connector and the needed frequency. +To figure out the needed power in whatever unit makes sense to you, the input circuit is as follows: + +* ZCU111: 3 dB attenuator to single-ended AC-coupled LMK04208 input. +* ZCU216/ZCU208 (the clock references are on the CLK104 daughterboard): 3 dB attenuator to single-ended AC-coupled LMK04828B input. +* RFSoC4x2: no attenuation, to single-ended AC-coupled LMK04828B input. + +The LMK04208/LMK04828B data sheets specify an input signal of 0.25/0.35 to 2.4 Vpp. You can work out the details, but 0-10 dBm is a safe range. + +There is also an ``clk_output=True`` argument that you can use to output a reference signal (you can use this independently of whether you're using an external clock). +This is at a frequency that's not likely to be useful to you, except as a way to monitor the lock. diff --git a/docs/topics/timing.rst b/docs/topics/timing.rst new file mode 100644 index 000000000..686079323 --- /dev/null +++ b/docs/topics/timing.rst @@ -0,0 +1,62 @@ +Timing +====== + +* Every generator contains a timed FIFO queue. + There is only one master clock time `t_master`, which is shared by all timed queues. + + * Treat :meth:`.QickProgram.trigger()` as a generator channel, i.e. equivalent to :meth:`.QickProgram.pulse()` in terms of clocks. + +* The tproc executes commands as soon as possible, meaning it has no concept of the master time (aside from wait commands, explained later). + It only cares about what point it is at in your code. + There is a master time offset `t_off`, which is incremented by sync commands. + When executed by the tproc, ``trigger(t)`` and ``pulse(t)`` commands are appended to the appropriate queue with a timestamp of ``t_off + t``. + +* A generator plays pulses in the order received. + It waits to play each pulse until the previous pulse is complete and the master clock time equals (or exceeds) the command timestamp. + +* ``pulse(ch,t)`` will play the pulse at ``t`` relative to the clock as defined by the sync command that has been most recently executed by the tproc, UNLESS it is delayed by a wait command (the generator can't play a pulse before the tproc executes the command) or another pulse command (the generator can't cut one pulse short to play the next one). + In that case, it will play at time ``t`` or at the end of the wait time/previous pulse, whatever is latest. + + * To make life easier, you can just always call ``pulse(ch, t=0)``, which will just play the pulse at the next earliest possible time. Then insert simple waits between pulses using ``sync_all(t=wait_time)``. + +* wait commands pause the tproc (i.e. pauses execution of commands). + They do not affect the master time. + Any commands lower down in your code, even if scheduled for some time (defined by the master time) during the wait period, will execute, at the earliest, immediately after the end of the wait period. + + * wait commands are necessary to use with readout/data acquisition timing management, as the tproc does not know when pulses/readout finish and you need to force it to wait for readout to finish. + In other words, you should have a wait at the end of a loop (or the tproc will tell the software to read data from the buffer too soon), or before a ``read`` command (e.g. for feedback). + `This is the only reason to use wait commands.` + + * ``waiti(t)`` is the generic form of wait, which pauses the tproc until the master clock time equals ``t_off + t``. Note ``waiti`` has a channel argument, but the channel argument does nothing! + + * :meth:`.QickProgram.wait_all()` calculates the end of all readout pulses and waits until that time + ``t``. + +* sync commands increment the master time offset (used by all gen channels). + The effect is to push back the play time of subsequent commands by that increment. + + * ``synci(t)`` is the generic form of sync. + + * The safer version :meth:`.QickProgram.sync_all()` calculates the end of the last pulse played + ``t``, and sets the master time offset to that value. + +How to avoid timing problems +---------------------------- + +Timed instructions are executed in two steps: first when the control core of the tProcessor pushes the instruction into the timed queue, and second when the instruction pops off the timed queue. + +* The control core executes all instructions in order and (except ``wait``/``waiti``) as quickly as possible. + If you have a non-timed instruction with external effects, it will generally execute before the timed instructions before and after it. + Specifically, programs (like the AveragerProgram framework we're using here) typically use ``memwi`` to update a data counter, and then read that counter to know how many data samples to get from the buffers - if the ``memwi`` happens before the readout is triggered or completed, you will read invalid data. + +* If the instruction is pushed later than the specified time, it will execute later than specified - this can lead to variations in the relative timing of pulses and readout windows. You are responsible for keeping the control core running ahead of the instruction times. + +Things you should do in your programs: + +* Your initialization should contain a ``synci`` instruction which gives the tProcessor time to get ahead of the clock. + +* Put a :meth:`.QickProgram.sync_all()` somewhere in your loop body, probably at the end. This ensures that you don't have pulses or readouts that exceed the loop length. + +* Put a ``waiti`` instruction after the last readout in your loop body, to make sure the tProcessor doesn't prematurely update the data counter. + +* Follow the ``waiti`` with a ``synci`` that exceeds the ``waiti``, to allow the tProcessor to get ahead of the clock. + +* The last three points are automatically addressed if the last timed instruction in your loop body is a :meth:`.QickProgram.measure()` instruction that specifies ``wait=True`` and a nonzero ``syncdelay``. diff --git a/docs/topics/units.rst b/docs/topics/units.rst new file mode 100644 index 000000000..1bff8ed52 --- /dev/null +++ b/docs/topics/units.rst @@ -0,0 +1,13 @@ +Time units +========== + +Time durations are generally specified in units of clock cycles. +The relevant clocks are the tProcessor clock and the fabric clocks of the generators and readouts. +In general these can all be different (and can even vary among generators or readouts). + +For convenience, the :meth:`.QickConfig.us2cycles()` and :meth:`.QickConfig.cycles2us()` methods will convert between floating-point times and integer cycles. +You should be careful to specify which clock you are using, and set the appropriate parameter in :meth:`.QickConfig.us2cycles()`: + +Pulse parameters (the length parameter to :meth:`.QickProgram.set_pulse_registers()`, the length and sigma parameters to :meth:`.AbsQickProgram.add_gauss()`) use the generator clock and you should specify ``gen_ch``. +Readout parameters (the length parameter to :meth:`.AbsQickProgram.declare_readout()`) use the readout clock and you should specify ``ro_ch``. +All other values will use the tProc clock. This includes ``sync`` and ``wait`` commands, and any sort of delay (``t``, ``adc_trig_offset``). Don't use a channel ID parameter. diff --git a/firmware/.gitignore b/firmware/.gitignore new file mode 100644 index 000000000..83fdbfcdc --- /dev/null +++ b/firmware/.gitignore @@ -0,0 +1,4 @@ +top*/ +**/axi_mst_0/* +!**/axi_mst_0/*.xci + diff --git a/firmware/README.md b/firmware/README.md index 5cdd820c2..5e36a0d0e 100644 --- a/firmware/README.md +++ b/firmware/README.md @@ -1,57 +1,240 @@ QICK firmware ================================================= -This system includes the following components: +For a description of the firmware design, see the [documentation](https://qick-docs.readthedocs.io/latest/firmware.html). -* 1 output channels connected to PMOD0-3 and triggers for Readout Block. -* 7 output channels connected to DACs. -* 2 input channels connected to ADCs. -* 1 instance of tProcessor 64-bit instructions, 32-bit registers. +# Building the firmware yourself -Sampling frequency of ADC blocks is given by the variable ``soc.fs_adc``. Sampling frequency of DACs is stored in variable ``soc.fs_adc``. Fast-speed buffers were removed to save memory space. Raw data can be captured after x8 down-sampling. +If you want to make changes to the firmware, or you just want to look at the design and dig around: -Output channels driving DACs use the updated Signal Generator V4, which has the possibility to upload I/Q envelopes, and uses 32-bit resolution for both frequency and phase. The format of the control word was updated accordingly to accomodate the bits. See example asm files for a detailed description of the fields. The maximum length of the I/Q envelopes is given by the variable ``soc.gens[i].MAX_LENGTH``. +* Pick the firmware project you want to build. The projects for the standard images for ZCU111, ZCU216, and RFSoC4x2 (`qick_111.bit`, `qick_216.bit`, `qick_4x2.bit`) are in subdirectories of the `projects` directory, as are projects for ZCU111 images with support for the v1 and v2 RF boards. You will find a project script (`proj.tcl`) and a block design script (`bd_2022-1.tcl` or similar). +* Install the version of Vivado specified by the block design filename (e.g. 2022.1 - older or newer will fail!), with a license that is valid for the FPGA you are using (you will have received such a license with your board). Start Vivado. +* In the Tcl console at the bottom of the screen navigate to this directory, then run the project script (e.g. `source ./proj.tcl`). This will create the firmware project and will end by showing you a block diagram of the firmware. +* Now click "Generate Bitstream" in the navigation menu at the left: this will compile the firmware. +* You need the .bit and .hwh files. These are not easy to find but the `out` directory has symlinks to their locations. -The readout block is actually built around two IPs: readout and average + buffer. Readout block includes a digital down-convertion, FIR filtering and decimation by 8. DDS frequency is configured using a register of the readout block and it is not intended to support real-time frequency hopping as in the Signal Generator side. After frequency shifting, filtering and decimation, the data stream is sent to the Average + Buffer block, which internally can store raw samples or perform the sum of the specified number of samples. The process is started with the external trigger signal, connected to output Channel 0 of tProcessor. The user can opt to route the input, the DDS wave or the frequency shifted signal to the FIR and decimation by 8 stage. This is done using a output selection register of the readout block. Regarding the buffering capabilities, the average section of the block has a buffer of ``soc.avg_bufs[i].AVG_MAX_LENGTH``. +To save your block design: -

- QICK readout -

+``` +write_bd_tcl -force -include_layout bd.tcl +``` -# tProcessor channel assignment +## Generators and readouts +Block RAM (1080 tiles total) is always the limiting resource. It is only used for our own IPs as listed below, with the exception of DMA cores which use 1-8 tiles each and the DDR4 interface which uses ~25.5 tiles. +High BRAM utilization will often make it harder for a design to meet timing. +### standard readout (`axis_readout_v2`): -tProcessor will be used to control the real-time operation of the experiment. Output channels (AXIS MASTER) of the tProcessor are assigned as follows: +RFDC ADC settings: +* Digital Output Data: Real +* Decimation Mode: 1x +* Samples per AXI4-Stream Cycle: 8 +* Mixer Type: Coarse +* Mixer Mode: Real->Real -- Channel 0 : connected to PMOD0 0-3, and triggers for readout. Bits 0-3 are connected to PMOD0, bit 14 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH0. Bit 15 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH1. -- Channel 1 : connected to Signal Generator V4, which drives DAC 228 CH0. -- Channel 2 : connected to Signal Generator V4, which drives DAC 228 CH1. -- Channel 3 : connected to Signal Generator V4, which drives DAC 228 CH2. -- Channel 4 : connected to Signal Generator V4, which drives DAC 229 CH0. -- Channel 5 : connected to Signal Generator V4, which drives DAC 229 CH1. -- Channel 6 : connected to Signal Generator V4, which drives DAC 229 CH2. -- Channel 7 : connected to Signal Generator V4, which drives DAC 229 CH3. +connect: RFDC -> axis register slice (optional, defaults) -> readout -The updated version of the tProcessor has 4 input (AXIS SLAVE) channels, which can be used for feedback. These are 64-bit, and the updated ``read`` instruction can specify channel number and upper/lower 32-bits to be read and written into an internal register. See example below on how to use this new capability. +BRAM: 16 tiles -* Channel 0 : connected to readout 0, which is driven by ADC 224 CH0 -* Channel 1 : connected to readout 1, which is driven by ADC 224 CH1 +### tProc-configured readout (`axis_readout_v3`): -Signal Generators are organized on the array ``soc.gens``, which is composed of 7 instances. Array index 0 is connected to tProcessor Channel 1, array index 1 is connected to tProcessor Channel 2, and so on. As way of example, let's assume the user needs to create a pulse on DAC 229 CH1 and DAC 229 CH3. These are connected to Channels 5, and 7 or the tProcessor, respectively. However, let's also assume that a gaussian envelope needs to be uploaded into the corresponding signal generator. ``soc.gens[3]`` drives DAC 229 CH1, and ``soc.gens[6]`` drives DAC 229 CH3. +RFDC ADC settings: same as standard -Similarly, average and buffer inputs blocks are organized on ``soc.avg_bufs`` array, which has two instances of the Average + Buffer block. The user can access them using index 0 and 1. +connect: +* RFDC -> axis clock converter (optional, defaults) -> axis resampler (B=16, N=8) -> axis register slice (optional, fully-registered) -> readout, s1_axis +* tProc -> axis clock converter or cdcsync -> readout, s0_axis -# Timing +BRAM: 8 tiles -The DAC speed is ``384*16=6144 MHz`` (resolution ``~163 ps``) and the ADC speed is ``384*8 MHz`` but then the signal is decimated by a factor of ``8`` (resolution ``~2.6 ns``). The minimum DAC pulse length is 16 samples but if you want shorter pulses than that you can pad that pulse with zeros. +### mux readout (`axis_pfb_readout_v2`) on 111: -# Firmware parameters +RFDC ADC settings: +* Digital Output Data: I/Q +* Decimation Mode: 2x +* Samples per AXI4-Stream Cycle: 4 +* Mixer Type: Coarse +* Mixer Mode: Real->I/Q +* Frequency: -Fs/4 + +connect: RFDC -> axis combiner (default settings) -> axis register slice (optional, defaults) -> PFB readout ("interleaved input" unchecked) + +need a clock wizard to double the clock coming out of the RFDC + +### mux readout (`axis_pfb_readout_v2`) on 216: + +RFDC ADC settings: +* Digital Output Data: I/Q +* Decimation Mode: 2x +* Samples per AXI4-Stream Cycle: 8 +* Mixer Type: Coarse +* Mixer Mode: Real->I/Q +* Frequency: -Fs/4 + +connect: RFDC -> axis register slice (optional, defaults) -> PFB readout ("interleaved input" checked) + +### mux readout (`axis_pfb_readout_v3`) on 216: +Same RFDC settings and connectivity as v2; this readout always expects interleaved input, and for dual-ADC systems (ZCU111, RFSoC4x2) you need to use an axis combiner and `axis_reorder_iq_v1` + +BRAM: 8 tiles + +### full-speed gen (`axis_signal_gen_v6`): + +gen settings: N Dds=16, N is up to you (buffer size will be `16*2^N`) + +RFDC DAC settings: +* Interpolation Mode: 1x +* Samples per AXI4-Stream Cycle: 16 +* Datapath Mode: No DUC 0 to Fs/2 +* Mixer Type: Coarse +* Mixer Mode: Real->Real + +BRAM: 32 tiles for the DDSes, 64 tiles for our typical buffer size of N=12 + +### mux4 gen (`axis_sg_mux4`) v1 or v2: + +gen settings: N_DDS=4 + +RFDC DAC settings: +* Interpolation Mode: 4x +* Samples per AXI4-Stream Cycle: 8 +* Datapath Mode: DUC 0 to Fs/2 +* Mixer Type: Fine +* Mixer Mode: I/Q->Real + +BRAM: 32 tiles + +### mux4 gen v3 (`axis_sg_mux4_v3`): + +gen settings: N Dds=16 + +RFDC DAC settings: same as full-speed + +BRAM: 128 tiles + +### mux8 gen v1 (`axis_sg_mux8_v1`): + +gen settings: N Dds=16 + +RFDC DAC settings: same as full-speed + +BRAM: 256 tiles + +### I/Q gen (`axis_constant_iq`): + +gen settings: B=16, N=8 + +RFDC DAC settings: +* Interpolation Mode: 2x +* Samples per AXI4-Stream Cycle: 16 +* Datapath Mode: DUC 0 to Fs/2 +* Mixer Type: Fine +* Mixer Mode: I/Q->Real + +### int4 gen (`axis_sg_int4_v1`): + +gen settings: N is up to you (buffer size will be `2^N`) + +RFDC DAC settings: +* Interpolation Mode: 4x +* Samples per AXI4-Stream Cycle: 8 +* Datapath Mode: DUC 0 to Fs/2 +* Mixer Type: Fine +* Mixer Mode: I/Q->Real + +BRAM: 8 tiles for DDSes, 4 tiles for our typical N=12 + +### standard buffer (`axis_avg_buffer`): + +* s_axis input: decimated data stream from readout +* m0_axis output: accumulated buffer to DMA, typically through a switch +* m1_axis output: decimated buffer to DMA, typically through a switch +* m2_axis output: individual accumulated data points to tProc input (for fast feedback), typically through a clock converter + +buffer settings: N_AVG and N_BUF are up to you, setting the accumulated and decimated buffer lengths (buffer size will be `2^N`) + +BRAM: 28.5 tiles for accumulated at typical N_AVG=14, 1 tile for decimated at typical N_BUF=10 + +### weighted buffer (`axis_weighted_buffer`): + +same configuration as the standard buffer, adds the following port: + +* s1_axis_weights: weights from DMA, typically through a switch (this can be the same switch that is used for generator envelopes) + +buffer settings: N_AVG, N_BUF, N_WGT are up to you, setting the accumulated and decimated buffer lengths and the weights memory (size will be `2^N`) + +BRAM: 28.5 tiles for accumulated at typical N_AVG=14, 1 tile each for decimated and weights at typical N_BUF=N_WGT=10 + +### multi-rate buffer (`mr_buffer_et`): + +buffer settings: NM is samples per fabric clock, use 8; B is bits per sample, use 32; N is buffer size, up to you (buffer size will be `NM*2^N` samples) +BRAM: 8 tiles for typical N=10 + +### resonator emulator (`axis_pfba_pr_4x256_v1`, `axis_kidsim_v3`, `axis_pfbs_pr_4x256_v1`): + +RFDC ADC settings on 216: +* Digital Output Data: I/Q +* Decimation Mode: 2x +* Samples per AXI4-Stream Cycle: 8 +* Mixer Type: Coarse +* Mixer Mode: Real->I/Q +* Frequency: -Fs/4 + +on 4x2/111, 4 samples per cycle; between RFDC and analysis chain need a combiner then reorder IQ (B=16 L=4) + +kidsim L=8 + +RFDC DAC settings: +* Interpolation Mode: 2x +* Samples per AXI4-Stream Cycle: 8 +* Datapath Mode: DUC 0 to Fs/2 +* Mixer Type: Coarse +* Mixer Mode: I/Q->Real +* Frequency: Fs/4 + +### time tagger (`qick_time_tagger`): +* qick_peripheral: to tProc v2 QPeriphA/B +* c_clk/c_aresetn: tProc core clock +* adc_clk/adc_aresetn: ADC fabric clock +* ps_clk/ps_aresetn: AXI clock +* m_axis_dma: to S_AXIS_S2MM port of a DMA + +If IO ARM control is enabled, arm_i input can be connected to a tProc trigger bit. + +DMA should have: +* buffer length width 18, address width 32 +* write enabled, 1 channel, width 32 (auto), burst 16 + +### tProc v1 (`axis_tproc64x32_x8`): + +BRAM: 0.5 tile base, 1 tile for data memory, 2 tiles for standard program memory of 1k words (8 kB in address map) + +### tProc v2 (`qick_processor`): +* s0_axis: feedback inputs +* dma: to DMA AXIS ports +* t_clk: timing clock (typically one of the DAC clocks) +* c_clk: core clock (can be anything, but max ~200 MHz, doubling the PL clock makes sense) +* ps_clk: AXI clock, from PS + +need a DMA: +* buffer length width 26, address width 32 +* read enabled, 1 channel, width 256, burst 2 +* write enabled, 1 channel, width 256, burst 16 + +BRAM: 1 tile per trigger output, 3 tiles per wave output, 8/4/5 tiles for P/D/W memories with AW=12/12/10 + +## Expanding the program memory (tProc v1) + +In theory you just need to change it in the address editor and it will propagate to the block design, but there is some bug in Vivado which leads to an error message that complains about asymmetry between the two memory ports: + +https://support.xilinx.com/s/question/0D52E00007GSLhKSAX/block-memory-generator-asymmetry-error + +This will even cause a saved bd.tcl script to fail: if you make a big memory with the workaround below, and save the bd.tcl, you will not be able to regenerate the project using that bd.tcl. So we give you a bd.tcl with a small program memory. + +THe solution is similar to what is suggested in the forum post: + +* reconfigure the memory controller for 2 ports +* disconnect the port B signals from the memory +* connect the memory controller port B to the memory port B +* now you can expand the memory and validate the design +* put things back the way they were - disconnect and remove controller port B, reconnect the memory to the tProc -* Pulse memory length: 65536 per channel x2 (I,Q), i.e., 128k total -* Decimated ADC buffer length: 1024 samples per component (I,Q), 2k total -* Accumulated ADC buffer length: 1024 samples per component (I,Q), 2 k total -* tProc program memory length: 8k instructions of 64 bits, 64k Bytes total -* tProc data memory length: 4096 samples of 32 bits, 16k Bytes total -* tProc stack size: 256 samples of 32 bits, 1k Byte total -* Phase conversion from deg to reg: Phase resolution is 32-bit, that is \Delta \phi = 2 \pi /2^{32} or 360/2^{32} -* Gain is 16-bit signed [-32768,32767] diff --git a/firmware/bd/README.bd b/firmware/bd/README.bd deleted file mode 100644 index b6d6030d6..000000000 --- a/firmware/bd/README.bd +++ /dev/null @@ -1,23 +0,0 @@ -Todo if bd is re-written: - -Replace this original lines... - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - ] $axi_bram_ctrl_0_bram - - -With these modified lines... - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.WRITE_WIDTH_B {64} \ - CONFIG.READ_WIDTH_B {64} \ - ] $axi_bram_ctrl_0_bram - diff --git a/firmware/bd/bd-2019-1.tcl b/firmware/bd/bd-2019-1.tcl deleted file mode 100644 index 1dfc3fec0..000000000 --- a/firmware/bd/bd-2019-1.tcl +++ /dev/null @@ -1,1649 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2019.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_4 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-2-e - set_property BOARD_PART xilinx.com:zcu111:part0:1.1 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v4:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_terminator:1.0\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:system_ila:1.1\ -xilinx.com:ip:usp_rf_data_converter:2.1\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_4\ -" - - set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] - - set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] - - set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] - - set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] - - set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] - - set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] - - set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] - - set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] - - set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] - - - # Create ports - set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] - set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] - set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] - set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Write_Width_B {64} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {1} \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - - # Create instance: axis_clk_cnvrt_avg_0, and set properties - set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] - - # Create instance: axis_clk_cnvrt_avg_1, and set properties - set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] - - # Create instance: axis_clk_cnvrt_gen_3, and set properties - set axis_clk_cnvrt_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_3 ] - - # Create instance: axis_clk_cnvrt_gen_4, and set properties - set axis_clk_cnvrt_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_4 ] - - # Create instance: axis_clk_cnvrt_gen_5, and set properties - set axis_clk_cnvrt_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_5 ] - - # Create instance: axis_clk_cnvrt_gen_6, and set properties - set axis_clk_cnvrt_gen_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_6 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v4_0, and set properties - set axis_signal_gen_v4_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_0 ] - - # Create instance: axis_signal_gen_v4_1, and set properties - set axis_signal_gen_v4_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_1 ] - - # Create instance: axis_signal_gen_v4_2, and set properties - set axis_signal_gen_v4_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_2 ] - - # Create instance: axis_signal_gen_v4_3, and set properties - set axis_signal_gen_v4_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_3 ] - - # Create instance: axis_signal_gen_v4_4, and set properties - set axis_signal_gen_v4_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_4 ] - - # Create instance: axis_signal_gen_v4_5, and set properties - set axis_signal_gen_v4_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_5 ] - - # Create instance: axis_signal_gen_v4_6, and set properties - set axis_signal_gen_v4_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_6 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {7} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_terminator_0, and set properties - set axis_terminator_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_0 - - # Create instance: axis_terminator_1, and set properties - set axis_terminator_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_1 - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - set_property -dict [ list \ - CONFIG.DMEM_N {12} \ - CONFIG.PMEM_N {20} \ - ] $axis_tproc64x32_x8_0 - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {81.938} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {384} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.125} \ - ] $clk_adc0_x2 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {21} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: system_ila_0, and set properties - set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {0.5} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_0 - - # Create instance: system_ila_1, and set properties - set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {1.5} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_1 - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Enable {1} \ - CONFIG.ADC0_Fabric_Freq {384.000} \ - CONFIG.ADC0_Outclk_Freq {192.000} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {204.800} \ - CONFIG.ADC0_Sampling_Rate {3.072} \ - CONFIG.ADC_Decimation_Mode00 {1} \ - CONFIG.ADC_Decimation_Mode01 {1} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type00 {0} \ - CONFIG.ADC_Mixer_Type01 {0} \ - CONFIG.ADC_Mixer_Type02 {0} \ - CONFIG.ADC_Mixer_Type03 {0} \ - CONFIG.ADC_Slice00_Enable {true} \ - CONFIG.ADC_Slice01_Enable {true} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {384.000} \ - CONFIG.DAC0_Outclk_Freq {384.000} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {204.800} \ - CONFIG.DAC0_Sampling_Rate {6.144} \ - CONFIG.DAC1_Enable {1} \ - CONFIG.DAC1_Fabric_Freq {384.000} \ - CONFIG.DAC1_Outclk_Freq {384.000} \ - CONFIG.DAC1_PLL_Enable {true} \ - CONFIG.DAC1_Refclk_Freq {204.800} \ - CONFIG.DAC1_Sampling_Rate {6.144} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode01 {1} \ - CONFIG.DAC_Interpolation_Mode02 {1} \ - CONFIG.DAC_Interpolation_Mode10 {1} \ - CONFIG.DAC_Interpolation_Mode11 {1} \ - CONFIG.DAC_Interpolation_Mode12 {1} \ - CONFIG.DAC_Interpolation_Mode13 {1} \ - CONFIG.DAC_Mixer_Type00 {0} \ - CONFIG.DAC_Mixer_Type01 {0} \ - CONFIG.DAC_Mixer_Type02 {0} \ - CONFIG.DAC_Mixer_Type10 {0} \ - CONFIG.DAC_Mixer_Type11 {0} \ - CONFIG.DAC_Mixer_Type12 {0} \ - CONFIG.DAC_Mixer_Type13 {0} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice01_Enable {true} \ - CONFIG.DAC_Slice02_Enable {true} \ - CONFIG.DAC_Slice10_Enable {true} \ - CONFIG.DAC_Slice11_Enable {true} \ - CONFIG.DAC_Slice12_Enable {true} \ - CONFIG.DAC_Slice13_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_4_0, and set properties - set block_name vect2bits_4 - set block_cell_name vect2bits_4_0 - if { [catch {set vect2bits_4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_4_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {15} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ - CONFIG.PSU__DDRC__CWL {14} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {33} \ - CONFIG.PSU__DDRC__T_RC {47.06} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {1} \ - CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ - CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ - CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD1_COHERENCY {0} \ - CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ - CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ - CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ - CONFIG.PSU__SD1__RESET__ENABLE {0} \ - CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ - CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ - CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__UART0__BAUD_RATE {115200} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_avg_buffer_0_m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_clk_cnvrt_avg_0_M_AXIS] [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins system_ila_1/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_clock_converter_3_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_3/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_3/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_4_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_4/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_4/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_5_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_5/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_5/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_6_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_6/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_6/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_terminator_0/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_terminator_1/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] - connect_bd_intf_net -intf_net axis_signal_gen_v4_0_m_axis [get_bd_intf_pins axis_signal_gen_v4_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_1_m_axis [get_bd_intf_pins axis_signal_gen_v4_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s01_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_2_m_axis [get_bd_intf_pins axis_signal_gen_v4_2/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s02_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_3_m_axis [get_bd_intf_pins axis_signal_gen_v4_3/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s10_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_4_m_axis [get_bd_intf_pins axis_signal_gen_v4_4/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s11_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_5_m_axis [get_bd_intf_pins axis_signal_gen_v4_5/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s12_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_6_m_axis [get_bd_intf_pins axis_signal_gen_v4_6/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s13_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v4_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v4_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v4_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v4_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v4_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v4_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v4_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_signal_gen_v4_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_signal_gen_v4_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_signal_gen_v4_2/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_clk_cnvrt_gen_3/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_clk_cnvrt_gen_4/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_clk_cnvrt_gen_5/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_clk_cnvrt_gen_6/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac1_clk_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac1_clk] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v4_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v4_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v4_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v4_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v4_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v4_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v4_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout01 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout01] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout02 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout02] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout10 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout10] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout11 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout11] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout12 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout12] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout13 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout13] - connect_bd_intf_net -intf_net vin0_1 [get_bd_intf_ports vin0] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin1_1 [get_bd_intf_ports vin1] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_4_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_terminator_0/s_axis_aclk] [get_bd_pins axis_terminator_1/s_axis_aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net rst_adc0_peripheral_reset [get_bd_pins clk_adc0_x2/reset] [get_bd_pins rst_adc0/peripheral_reset] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_terminator_0/s_axis_aresetn] [get_bd_pins axis_terminator_1/s_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v4_0/aresetn] [get_bd_pins axis_signal_gen_v4_1/aresetn] [get_bd_pins axis_signal_gen_v4_2/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins system_ila_1/resetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aresetn] [get_bd_pins axis_signal_gen_v4_3/aresetn] [get_bd_pins axis_signal_gen_v4_4/aresetn] [get_bd_pins axis_signal_gen_v4_5/aresetn] [get_bd_pins axis_signal_gen_v4_6/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s1_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins system_ila_0/resetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v4_0/aclk] [get_bd_pins axis_signal_gen_v4_1/aclk] [get_bd_pins axis_signal_gen_v4_2/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins system_ila_1/clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac1 [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aclk] [get_bd_pins axis_signal_gen_v4_3/aclk] [get_bd_pins axis_signal_gen_v4_4/aclk] [get_bd_pins axis_signal_gen_v4_5/aclk] [get_bd_pins axis_signal_gen_v4_6/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac1] [get_bd_pins usp_rf_data_converter_0/s1_axis_aclk] - connect_bd_net -net vect2bits_4_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_4_0/dout0] - connect_bd_net -net vect2bits_4_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_4_0/dout1] - connect_bd_net -net vect2bits_4_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_4_0/dout2] - connect_bd_net -net vect2bits_4_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_4_0/dout3] - connect_bd_net -net vect2bits_4_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins system_ila_0/probe0] [get_bd_pins system_ila_1/probe0] [get_bd_pins vect2bits_4_0/dout14] - connect_bd_net -net vect2bits_4_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_4_0/dout15] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins axis_tproc64x32_x8_0/start] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins system_ila_0/clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x00010000 -offset 0xA0000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0040000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] SEG_axi_dma_avg_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0041000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] SEG_axi_dma_buf_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0042000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] SEG_axi_dma_gen_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0043000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] SEG_axi_dma_tproc_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0044000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] SEG_axis_avg_buffer_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0045000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] SEG_axis_avg_buffer_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0046000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] SEG_axis_readout_v2_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0047000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] SEG_axis_readout_v2_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0048000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_0/s_axi/reg0] SEG_axis_signal_gen_v4_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0049000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_1/s_axi/reg0] SEG_axis_signal_gen_v4_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004A000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_2/s_axi/reg0] SEG_axis_signal_gen_v4_2_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004B000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_3/s_axi/reg0] SEG_axis_signal_gen_v4_3_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004C000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_4/s_axi/reg0] SEG_axis_signal_gen_v4_4_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004D000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_5/s_axi/reg0] SEG_axis_signal_gen_v4_5_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004E000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_6/s_axi/reg0] SEG_axis_signal_gen_v4_6_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004F000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] SEG_axis_switch_avg_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0050000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] SEG_axis_switch_buf_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0051000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] SEG_axis_switch_gen_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x000400000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] SEG_axis_tproc64x32_x8_0_reg0 - create_bd_addr_seg -range 0x00040000 -offset 0xA0080000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] SEG_usp_rf_data_converter_0_Reg - - # Exclude Address Segments - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_avg/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_buf/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_gen/Data_MM2S/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_tproc/Data_MM2S/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_tproc/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0.19 2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 9 -x 2750 -y 940 -defaultsOSRD -right -preplace port dac0_clk -pg 1 -lvl 9 -x 2750 -y 980 -defaultsOSRD -right -preplace port dac1_clk -pg 1 -lvl 9 -x 2750 -y 960 -defaultsOSRD -right -preplace port sysref_in -pg 1 -lvl 9 -x 2750 -y 920 -defaultsOSRD -right -preplace port vin0 -pg 1 -lvl 9 -x 2750 -y 840 -defaultsOSRD -right -preplace port vin1 -pg 1 -lvl 9 -x 2750 -y 860 -defaultsOSRD -right -preplace port vout0 -pg 1 -lvl 9 -x 2750 -y 490 -defaultsOSRD -preplace port vout1 -pg 1 -lvl 9 -x 2750 -y 510 -defaultsOSRD -preplace port vout2 -pg 1 -lvl 9 -x 2750 -y 530 -defaultsOSRD -preplace port vout3 -pg 1 -lvl 9 -x 2750 -y 550 -defaultsOSRD -preplace port vout4 -pg 1 -lvl 9 -x 2750 -y 570 -defaultsOSRD -preplace port vout5 -pg 1 -lvl 9 -x 2750 -y 590 -defaultsOSRD -preplace port vout6 -pg 1 -lvl 9 -x 2750 -y 610 -defaultsOSRD -preplace port PMOD0_0_LS -pg 1 -lvl 9 -x 2750 -y 100 -defaultsOSRD -preplace port PMOD0_1_LS -pg 1 -lvl 9 -x 2750 -y 120 -defaultsOSRD -preplace port PMOD0_2_LS -pg 1 -lvl 9 -x 2750 -y 140 -defaultsOSRD -preplace port PMOD0_3_LS -pg 1 -lvl 9 -x 2750 -y 160 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x -940 -y 530 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x -490 -y 850 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 2 -x -490 -y -1060 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 2 -x -490 -y -840 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x -490 -y -540 -defaultsOSRD -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x -490 -y -200 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 2 -x -490 -y -3260 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 7 -x 2120 -y 2870 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 7 -x 2120 -y 3750 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_3 -pg 1 -lvl 3 -x 160 -y 1220 -defaultsOSRD -preplace inst axis_clk_cnvrt_gen_4 -pg 1 -lvl 3 -x 160 -y 1480 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_5 -pg 1 -lvl 3 -x 160 -y 1740 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_6 -pg 1 -lvl 3 -x 160 -y 2000 -defaultsOSRD -resize 220 156 -preplace inst axis_register_slice_0 -pg 1 -lvl 4 -x 660 -y 2690 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 4 -x 660 -y 3570 -defaultsOSRD -resize 180 116 -preplace inst axis_switch_avg -pg 1 -lvl 7 -x 2120 -y 3100 -defaultsOSRD -preplace inst axis_switch_buf -pg 1 -lvl 7 -x 2120 -y 3320 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 160 -y -500 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 3 -x 160 -y -1580 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 1170 -y -3230 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 3 -x 160 -y -2540 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 3 -x 160 -y -2360 -defaultsOSRD -resize 320 156 -preplace inst rst_adc0_x2 -pg 1 -lvl 3 -x 160 -y -2180 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 3 -x 160 -y -2000 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 3 -x 160 -y -1820 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 8 -x 2550 -y 570 -defaultsOSRD -preplace inst vect2bits_4_0 -pg 1 -lvl 7 -x 2120 -y 150 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x -940 -y 820 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x -940 -y 930 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x -940 -y 1050 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x -940 -y 1160 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 3 -x 160 -y -3090 -defaultsOSRD -preplace inst axis_constant_0 -pg 1 -lvl 1 -x -940 -y 10 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x -940 -y 130 -defaultsOSRD -resize 220 96 -preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 1170 -y 150 -defaultsOSRD -preplace inst axis_terminator_0 -pg 1 -lvl 6 -x 1680 -y 2430 -defaultsOSRD -preplace inst axis_terminator_1 -pg 1 -lvl 6 -x 1680 -y 3570 -defaultsOSRD -resize 160 116 -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x -490 -y 200 -defaultsOSRD -preplace inst system_ila_1 -pg 1 -lvl 7 -x 2120 -y 4230 -defaultsOSRD -resize 157 152 -preplace inst system_ila_0 -pg 1 -lvl 7 -x 2120 -y 4030 -defaultsOSRD -resize 157 152 -preplace inst axis_avg_buffer_0 -pg 1 -lvl 6 -x 1680 -y 2910 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 6 -x 1680 -y 3790 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_0 -pg 1 -lvl 5 -x 1170 -y 500 -defaultsOSRD -preplace inst axis_signal_gen_v4_1 -pg 1 -lvl 5 -x 1170 -y 760 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_2 -pg 1 -lvl 5 -x 1170 -y 1020 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_3 -pg 1 -lvl 5 -x 1170 -y 1280 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_4 -pg 1 -lvl 5 -x 1170 -y 1540 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_5 -pg 1 -lvl 5 -x 1170 -y 1800 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_6 -pg 1 -lvl 5 -x 1170 -y 2060 -defaultsOSRD -resize 220 236 -preplace inst axis_readout_v2_0 -pg 1 -lvl 5 -x 1170 -y 2740 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 5 -x 1170 -y 3620 -defaultsOSRD -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 -720 350n -preplace netloc axis_set_reg_0_dout 1 5 2 N 150 N -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 -710 410 -310 -preplace netloc clk_adc0_x2_clk_out1 1 2 6 -170 -1670 510 2600 780 2600 1490 700 N 700 N -preplace netloc clk_adc0_x2_locked 1 2 2 -180 -2650 480 -preplace netloc rst_adc0_peripheral_reset 1 2 2 -200 -2640 470 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 3 5 520 2610 770 2610 1470 680 NJ 680 NJ -preplace netloc rst_dac0_peripheral_aresetn 1 0 8 -1250 200 -750 -10 -270J -10 500 -10 820 330 NJ 330 1810J 720 N -preplace netloc rst_dac1_peripheral_aresetn 1 2 6 -170 340 490 340 870 340 NJ 340 NJ 340 2310J -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 8 -1250 270 -770 -1690 -230 -2660 520J -2660 790 2890 1340 3070 1880 660 N -preplace netloc usp_rf_data_converter_0_clk_adc0 1 2 7 -190 -1650 NJ -1650 810 -2650 NJ -2650 1880J -640 NJ -640 2730 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 -1260 -60 -780 -40 -250 210 NJ 210 920 350 NJ 350 1830J 350 2340J 290 2720 -preplace netloc usp_rf_data_converter_0_clk_dac1 1 2 7 -220 360 NJ 360 860 360 NJ 360 NJ 360 2320J 300 2710 -preplace netloc vect2bits_4_0_dout0 1 7 2 N 100 N -preplace netloc vect2bits_4_0_dout1 1 7 2 N 120 N -preplace netloc vect2bits_4_0_dout2 1 7 2 N 140 N -preplace netloc vect2bits_4_0_dout3 1 7 2 N 160 N -preplace netloc vect2bits_4_0_dout14 1 5 3 1510 3060 1840J 2980 2270 -preplace netloc vect2bits_4_0_dout15 1 5 3 1500 290 NJ 290 2260 -preplace netloc xlconstant_0_dout 1 1 1 -800 820n -preplace netloc xlconstant_1_dout 1 1 1 -770 890n -preplace netloc xlconstant_2_dout 1 1 1 -790 330n -preplace netloc xlconstant_3_dout 1 1 1 -750 930n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 8 -1260 250 -800 -1700 -240 -3180 480 -3110 880 2870 1460 3080 1870 640 N -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 2 2 -210 -2780 470 -preplace netloc axis_clock_converter_6_M_AXIS 1 3 2 N 2000 N -preplace netloc usp_rf_data_converter_0_vout11 1 8 1 N 570 -preplace netloc axi_smc_M00_AXI 1 2 1 -250 -3260n -preplace netloc axis_avg_buffer_1_m0_axis 1 6 1 1850 3060n -preplace netloc usp_rf_data_converter_0_vout13 1 8 1 N 610 -preplace netloc axis_avg_buffer_0_m2_axis 1 6 1 1920 2830n -preplace netloc ps8_0_axi_periph_M18_AXI 1 5 2 NJ -3070 1860 -preplace netloc axis_clock_converter_3_M_AXIS 1 3 2 N 1220 N -preplace netloc ps8_0_axi_periph_M10_AXI 1 5 1 1430 -3230n -preplace netloc ps8_0_axi_periph_M12_AXI 1 4 2 980 -2710 1370 -preplace netloc axi_dma_0_M_AXI_S2MM 1 1 2 -710 -3380 -280J -preplace netloc axis_avg_buffer_0_m0_axis 1 6 1 1850 2890n -preplace netloc vin0_1 1 7 2 2380J 840 N -preplace netloc axis_constant_0_m_axis 1 1 1 -760 10n -preplace netloc axi_dma_avg_M_AXI_S2MM 1 1 2 -720 -3140 -290 -preplace netloc usp_rf_data_converter_0_vout01 1 8 1 N 510 -preplace netloc axis_avg_buffer_0_m1_axis 1 6 1 1820 2910n -preplace netloc usp_rf_data_converter_0_vout02 1 8 1 N 530 -preplace netloc axis_avg_buffer_1_m2_axis 1 6 1 1910 3710n -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 3 2 NJ -3120 800 -preplace netloc axi_dma_1_M_AXI_MM2S 1 1 2 -730 -1710 -310J -preplace netloc dac0_clk_1 1 7 2 2350J 890 2690 -preplace netloc axis_clock_converter_4_M_AXIS 1 3 2 N 1480 N -preplace netloc axi_dma_0_M_AXI_MM2S 1 1 2 -770 -3390 -270 -preplace netloc ps8_0_axi_periph_M11_AXI 1 4 2 970 -3750 1320 -preplace netloc ps8_0_axi_periph_M09_AXI 1 5 1 1450 -3250n -preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 -710 -80 -310 -preplace netloc axi_dma_1_M_AXIS_MM2S 1 2 1 N -550 -preplace netloc ps8_0_axi_periph_M15_AXI 1 4 2 1000 -2690 1350 -preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 3 NJ 170 N 170 780 -preplace netloc ps8_0_axi_periph_M05_AXI 1 4 2 960 -3760 1330 -preplace netloc axis_constant_1_m_axis 1 1 1 N 130 -preplace netloc ps8_0_axi_periph_M02_AXI 1 4 2 930 -3790 1390 -preplace netloc dac1_clk_1 1 7 2 2370J 880 2700 -preplace netloc axis_switch_0_M00_AXIS 1 3 2 N -560 910 -preplace netloc ps8_0_axi_periph_M08_AXI 1 5 3 N -3270 1920 -650 2330J -preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 -290 250n -preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 3 NJ 190 N 190 800 -preplace netloc usp_rf_data_converter_0_vout10 1 8 1 N 550 -preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 -260 210n -preplace netloc axis_switch_avg_M00_AXIS 1 1 7 -720 -630 NJ -630 NJ -630 N -630 NJ -630 NJ -630 2300 -preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 -710 -730 N -730 NJ -730 N -730 1400 -preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 -280 230n -preplace netloc ps8_0_axi_periph_M03_AXI 1 4 2 940 -3780 1350 -preplace netloc axis_signal_gen_v4_4_m_axis 1 5 3 1420 460 N 460 NJ -preplace netloc axis_signal_gen_v4_0_m_axis 1 5 3 1330 380 N 380 NJ -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 -300 270n -preplace netloc usp_rf_data_converter_0_vout00 1 8 1 N 490 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 N 130 N 130 N -preplace netloc ps8_0_axi_periph_M00_AXI 1 1 5 -730 -740 N -740 NJ -740 920 -2640 1410J -preplace netloc axis_signal_gen_v4_2_m_axis 1 5 3 1390 420 N 420 NJ -preplace netloc usp_rf_data_converter_0_vout12 1 8 1 N 590 -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 -720 -60 -310 -preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 -720 -50 N -50 NJ -50 N -50 1420 -preplace netloc axis_signal_gen_v4_5_m_axis 1 5 3 1440 480 N 480 NJ -preplace netloc axis_switch_0_M05_AXIS 1 3 2 N -460 810 -preplace netloc axis_switch_buf_M00_AXIS 1 1 7 -740 -360 NJ -360 NJ -360 N -360 NJ -360 NJ -360 2290 -preplace netloc axis_switch_0_M01_AXIS 1 3 2 N -540 900 -preplace netloc axis_switch_0_M03_AXIS 1 3 2 N -500 840 -preplace netloc axis_signal_gen_v4_6_m_axis 1 5 3 1460 500 N 500 NJ -preplace netloc axis_switch_0_M02_AXIS 1 3 2 N -520 890 -preplace netloc axis_switch_0_M04_AXIS 1 3 2 N -480 830 -preplace netloc axis_signal_gen_v4_3_m_axis 1 5 3 1410 440 N 440 NJ -preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 -730 -1660 NJ -1660 NJ -1660 800 -2660 1320 -preplace netloc ps8_0_axi_periph_M04_AXI 1 4 2 950 -3770 1340 -preplace netloc axis_signal_gen_v4_1_m_axis 1 5 3 1360 400 N 400 NJ -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 3 NJ 150 N 150 850 -preplace netloc axis_switch_0_M06_AXIS 1 3 2 N -440 770 -preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 7 -730 3050 NJ 3050 NJ 3050 N 3050 NJ 3050 1900J 2970 2260 -preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 -170 -620 NJ -620 N -620 1390 -preplace netloc ps8_0_axi_periph_M14_AXI 1 4 2 990 -2700 1360 -preplace netloc axis_clock_converter_5_M_AXIS 1 3 2 N 1740 N -preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 -1270 -70 N -70 NJ -70 NJ -70 N -70 1380 -preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 -740 -1680 NJ -1680 NJ -1680 770 -2670 1330 -preplace netloc axi_dma_buf_M_AXI_S2MM 1 1 2 -710 -3130 -300 -preplace netloc ps8_0_axi_periph_M17_AXI 1 5 2 NJ -3090 1890 -preplace netloc vin1_1 1 7 2 2390J 850 2730 -preplace netloc sysref_in_1 1 7 2 2400 860 2720 -preplace netloc usp_rf_data_converter_0_m02_axis 1 3 6 540 280 NJ 280 NJ 280 NJ 280 NJ 280 2690 -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 -800 530n -preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 7 -740 -320 NJ -320 NJ -320 N -320 NJ -320 NJ -320 2280 -preplace netloc axis_avg_buffer_1_m1_axis 1 6 1 1820 3280n -preplace netloc usp_rf_data_converter_0_m00_axis 1 3 6 530 40 NJ 40 NJ 40 NJ 40 NJ 40 2700 -preplace netloc adc0_clk_1 1 7 2 2360J 870 2710 -preplace netloc axis_readout_v2_0_m0_axis 1 5 1 1460 2410n -preplace netloc axis_register_slice_0_M_AXIS 1 4 1 N 2690 -preplace netloc ps8_0_axi_periph_M16_AXI 1 4 2 1010 -2680 1340 -preplace netloc axis_readout_v2_1_m0_axis 1 5 1 1480 3550n -preplace netloc axis_readout_v2_1_m1_axis 1 5 1 1370 3630n -preplace netloc axis_readout_v2_0_m1_axis 1 5 1 1440 2750n -preplace netloc axis_register_slice_1_M_AXIS 1 4 1 N 3570 -levelinfo -pg 1 -1290 -940 -490 160 660 1170 1680 2120 2550 2750 -pagesize -pg 1 -db -bbox -sgen -1290 -3800 2900 4350 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/firmware/board_files/rfsoc4x2/1.0/LICENSE b/firmware/board_files/rfsoc4x2/1.0/LICENSE new file mode 100644 index 000000000..1097dfe3d --- /dev/null +++ b/firmware/board_files/rfsoc4x2/1.0/LICENSE @@ -0,0 +1,15 @@ +######################################################################### +Copyright (C) 2019, Xilinx Inc - All rights reserved + +Licensed under the Apache License, Version 2.0 (the "License"). You may +not use this file except in compliance with the License. A copy of the +License is located at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +License for the specific language governing permissions and limitations +under the License. +######################################################################### diff --git a/firmware/board_files/rfsoc4x2/1.0/board.xml b/firmware/board_files/rfsoc4x2/1.0/board.xml new file mode 100644 index 000000000..f12184bc8 --- /dev/null +++ b/firmware/board_files/rfsoc4x2/1.0/board.xml @@ -0,0 +1,328 @@ + + + + + + RFSoC 4x2 Board File Image + + + + Rev 1.0 + + 1.0 + Zynq UltraScale+ RFSoC 4x2 Development Board + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + 4-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CPU Reset Push Button, Active Low + + + DIP Switches 3 to 0 + + + LEDs, 3 to 0, Active Low + + + Push Buttons, Active Low + + + RGBLED0, Active Low + + + RGBLED1, Active Low + + + Pmod0 Connector + + + Pmod1 Connector + + + Pmod01 Connector + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml b/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml new file mode 100644 index 000000000..a92f689a1 --- /dev/null +++ b/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/board_files/rfsoc4x2/1.0/preset.xml b/firmware/board_files/rfsoc4x2/1.0/preset.xml new file mode 100644 index 000000000..8012c7905 --- /dev/null +++ b/firmware/board_files/rfsoc4x2/1.0/preset.xml @@ -0,0 +1,573 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png b/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png new file mode 100644 index 000000000..40058914d Binary files /dev/null and b/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png differ diff --git a/firmware/board_files/rfsoc4x2/1.0/xitem.json b/firmware/board_files/rfsoc4x2/1.0/xitem.json new file mode 100644 index 000000000..befb202e8 --- /dev/null +++ b/firmware/board_files/rfsoc4x2/1.0/xitem.json @@ -0,0 +1,37 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "rfsoc4x2", + "display": "Zynq UltraScale+ RFSoC 4x2 Development Board", + "revision": "1.0", + "description": "Zynq UltraScale+ RFSoC 4x2 Development Board", + "company": "realdigital.org", + "company_display": "Real Digital", + "author": "rhoover", + "contributors": [ + { + "group": "RealDigital", + "url": "https://www.realdigital.org/" + "group": "Xilinx", + "url": "https://www.xilinx.com/" + } + ], + "category": "Single Part", + "website": "https://www.rfsoc-pynq.io", + "logo": "rfsoc4x2_board.png", + "search-keywords": [ + "rfsoc4x2", + "realdigital.org", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} diff --git a/firmware/common_ip_files/ip_logos/logoQICK_128x128.png b/firmware/common_ip_files/ip_logos/logoQICK_128x128.png new file mode 100644 index 000000000..209264ba8 Binary files /dev/null and b/firmware/common_ip_files/ip_logos/logoQICK_128x128.png differ diff --git a/firmware/hdl/bram_dp_xpm.sv b/firmware/hdl/bram_dp_xpm.sv new file mode 100644 index 000000000..c8829a86d --- /dev/null +++ b/firmware/hdl/bram_dp_xpm.sv @@ -0,0 +1,531 @@ +// Dual Port Dual Clock Block RAM using XPM_MACRO +module bram_dp_xpm #( + integer OUT_REG_ENA = 0, // set to 1 for output reg + integer N = 16, // Memory address size. + integer B = 16 // Data width. +) ( + input wire clka, + input wire clkb, + input wire ena, + input wire enb, + input wire wea, + input wire web, + input wire [N-1:0] addra, + input wire [N-1:0] addrb, + input wire [B-1:0] dia, + input wire [B-1:0] dib, + output logic [B-1:0] doa, + output logic [B-1:0] dob +); + +// XPM_MEMORY instantiation template for True Dual Port RAM configurations +// Refer to the targeted device family architecture libraries guide for XPM_MEMORY documentation +// ======================================================================================================================= + +// Parameter usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Parameter name | Data type | Restrictions, if applicable | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | ADDR_WIDTH_A | Integer | Range: 1 - 20. Default value = 6. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port A address port addra, in bits. | +// | Must be large enough to access the entire memory from port A, i.e. >= $clog2(MEMORY_SIZE/[WRITE|READ]_DATA_WIDTH_A).| +// +---------------------------------------------------------------------------------------------------------------------+ +// | ADDR_WIDTH_B | Integer | Range: 1 - 20. Default value = 6. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port B address port addrb, in bits. | +// | Must be large enough to access the entire memory from port B, i.e. >= $clog2(MEMORY_SIZE/[WRITE|READ]_DATA_WIDTH_B).| +// +---------------------------------------------------------------------------------------------------------------------+ +// | AUTO_SLEEP_TIME | Integer | Range: 0 - 15. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Number of clk[a|b] cycles to auto-sleep, if feature is available in architecture | +// | 0 - Disable auto-sleep feature | +// | 3-15 - Number of auto-sleep latency cycles | +// | Do not change from the value provided in the template instantiation | +// +---------------------------------------------------------------------------------------------------------------------+ +// | BYTE_WRITE_WIDTH_A | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | To enable byte-wide writes on port A, specify the byte width, in bits- | +// | 8- 8-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 8 | +// | 9- 9-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 9 | +// | Or to enable word-wide writes on port A, specify the same value as for WRITE_DATA_WIDTH_A. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | BYTE_WRITE_WIDTH_B | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | To enable byte-wide writes on port B, specify the byte width, in bits- | +// | 8- 8-bit byte-wide writes, legal when WRITE_DATA_WIDTH_B is an integer multiple of 8 | +// | 9- 9-bit byte-wide writes, legal when WRITE_DATA_WIDTH_B is an integer multiple of 9 | +// | Or to enable word-wide writes on port B, specify the same value as for WRITE_DATA_WIDTH_B. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | CASCADE_HEIGHT | Integer | Range: 0 - 64. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- No Cascade Height, Allow Vivado Synthesis to choose. | +// | 1 or more - Vivado Synthesis sets the specified value as Cascade Height. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | CLOCKING_MODE | String | Allowed values: common_clock, independent_clock. Default value = common_clock.| +// |---------------------------------------------------------------------------------------------------------------------| +// | Designate whether port A and port B are clocked with a common clock or with independent clocks- | +// | "common_clock"- Common clocking; clock both port A and port B with clka | +// | "independent_clock"- Independent clocking; clock port A with clka and port B with clkb | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ECC_BIT_RANGE | String | Default value = 7:0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | This parameter is only used by synthesis. Specify the ECC bit range on the provided data. | +// | "7:0" - it specifies lower 8 bits are ECC bits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ECC_MODE | String | Allowed values: no_ecc, both_encode_and_decode, decode_only, encode_only. Default value = no_ecc.| +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | "no_ecc" - Disables ECC | +// | "encode_only" - Enables ECC Encoder only | +// | "decode_only" - Enables ECC Decoder only | +// | "both_encode_and_decode" - Enables both ECC Encoder and Decoder | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ECC_TYPE | String | Allowed values: none, ECCHSIAO32-7, ECCHSIAO64-8, ECCHSIAO128-9, ECCH32-7, ECCH64-8. Default value = none.| +// |---------------------------------------------------------------------------------------------------------------------| +// | This parameter is only used by synthesis. Specify the algorithm used to generate the ecc bits outside the XPM Memory.| +// | XPM Memory does not performs ECC operation with this parameter. | +// | | +// | "none" - No ECC | +// | "ECCH32-7" - 32 bit ECC Hamming algorithm is used | +// | "ECCH64-8" - 64 bit ECC Hamming algorithm is used | +// | "ECCHSIAO32-7" - 32 bit ECC HSIAO algorithm is used | +// | "ECCHSIAO64-8" - 64 bit ECC HSIAO algorithm is used | +// | "ECCHSIAO128-9" - 128 bit ECC HSIAO algorithm is used | +// +---------------------------------------------------------------------------------------------------------------------+ +// | IGNORE_INIT_SYNTH | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0 - Initiazation file if specified will applies for both simulation and synthesis | +// | 1 - Initiazation file if specified will applies for only simulation and will ignore for synthesis | +// +---------------------------------------------------------------------------------------------------------------------+ +// | MEMORY_INIT_FILE | String | Default value = none. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file-| +// | Enter only the name of the file with .mem extension, including quotes but without path (e.g. "my_file.mem"). | +// | File format must be ASCII and consist of only hexadecimal values organized into the specified depth by | +// | narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter| +// | MEMORY_INIT_PARAM value is equal to "". | | +// | When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | MEMORY_INIT_PARAM | String | Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string | +// | containing the hex characters. Enter only hex characters with each location separated by delimiter (,). | +// | Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by | +// | narrowest data width generic value of the memory.For example, if the narrowest data width is 8, and the depth of | +// | memory is 8 locations, then the parameter value should be passed as shown below. | +// | parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78" | +// | Where "AB" is the 0th location and "78" is the 7th location. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | MEMORY_OPTIMIZATION | String | Allowed values: true, false. Default value = true. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to | +// | disable the optimization of unused memory or bits in the memory structure. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | MEMORY_PRIMITIVE | String | Allowed values: auto, block, distributed, mixed, ultra. Default value = auto.| +// |---------------------------------------------------------------------------------------------------------------------| +// | Designate the memory primitive (resource type) to use- | +// | "auto"- Allow Vivado Synthesis to choose | +// | "distributed"- Distributed memory | +// | "block"- Block memory | +// | "ultra"- Ultra RAM memory | +// | "mixed"- Mixed memory | +// | NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with MEMORY_PRIMITIVE set to "auto".| +// +---------------------------------------------------------------------------------------------------------------------+ +// | MEMORY_SIZE | Integer | Range: 2 - 150994944. Default value = 2048. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the total memory array size, in bits. | +// | For example, enter 65536 for a 2kx32 RAM. | +// | When ECC is enabled and set to "encode_only", then the memory size has to be multiples of READ_DATA_WIDTH_[A|B] | +// | When ECC is enabled and set to "decode_only", then the memory size has to be multiples of WRITE_DATA_WIDTH_[A|B]. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | MESSAGE_CONTROL | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting| +// +---------------------------------------------------------------------------------------------------------------------+ +// | RAM_DECOMP | String | Allowed values: auto, area, power. Default value = auto. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the decomposition of the memory. | +// | "auto" - Synthesis selects default. | +// | "power" - Synthesis selects a strategy to reduce switching activity of RAMs and maps using widest configuration possible.| +// | "area" - Synthesis selects a strategy to reduce RAM resource count. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_DATA_WIDTH_A | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port A read data output port douta, in bits. | +// | The values of READ_DATA_WIDTH_A and WRITE_DATA_WIDTH_A must be equal. | +// | When ECC is enabled and set to "encode_only", then READ_DATA_WIDTH_A has to be multiples of 72-bits | +// | When ECC is enabled and set to "decode_only" or "both_encode_and_decode", then READ_DATA_WIDTH_A has to be | +// | multiples of 64-bits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_DATA_WIDTH_B | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port B read data output port doutb, in bits. | +// | The values of READ_DATA_WIDTH_B and WRITE_DATA_WIDTH_B must be equal. | +// | When ECC is enabled and set to "encode_only", then READ_DATA_WIDTH_B has to be multiples of 72-bits | +// | When ECC is enabled and set to "decode_only" or "both_encode_and_decode", then READ_DATA_WIDTH_B has to be | +// | multiples of 64-bits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_LATENCY_A | Integer | Range: 0 - 100. Default value = 2. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the number of register stages in the port A read data pipeline. Read data output to port douta takes this | +// | number of clka cycles. | +// | To target block memory, a value of 1 or larger is required- 1 causes use of memory latch only; 2 causes use of | +// | output register. To target distributed memory, a value of 0 or larger is required- 0 indicates combinatorial output.| +// | Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_LATENCY_B | Integer | Range: 0 - 100. Default value = 2. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the number of register stages in the port B read data pipeline. Read data output to port doutb takes this | +// | number of clkb cycles (clka when CLOCKING_MODE is "common_clock"). | +// | To target block memory, a value of 1 or larger is required- 1 causes use of memory latch only; 2 causes use of | +// | output register. To target distributed memory, a value of 0 or larger is required- 0 indicates combinatorial output.| +// | Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_RESET_VALUE_A | String | Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the reset value of the port A final output register stage in response to rsta input port is assertion. | +// | As this parameter is a string, please specify the hex values inside double quotes. As an example, | +// | If the read data width is 8, then specify READ_RESET_VALUE_A = "EA"; | +// | When ECC is enabled, then reset value is not supported. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_RESET_VALUE_B | String | Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the reset value of the port B final output register stage in response to rstb input port is assertion. | +// | As this parameter is a string, please specify the hex values inside double quotes. As an example, | +// | If the read data width is 8, then specify READ_RESET_VALUE_B = "EA"; | +// | When ECC is enabled, then reset value is not supported. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | RST_MODE_A | String | Allowed values: SYNC, ASYNC. Default value = SYNC. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Describes the behaviour of the reset | +// | | +// | "SYNC" - when reset is applied, synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A| +// | "ASYNC" - when reset is applied, asynchronously resets output port douta to zero | +// +---------------------------------------------------------------------------------------------------------------------+ +// | RST_MODE_B | String | Allowed values: SYNC, ASYNC. Default value = SYNC. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Describes the behaviour of the reset | +// | | +// | "SYNC" - when reset is applied, synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B| +// | "ASYNC" - when reset is applied, asynchronously resets output port doutb to zero | +// +---------------------------------------------------------------------------------------------------------------------+ +// | SIM_ASSERT_CHK | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. | +// | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | USE_EMBEDDED_CONSTRAINT| Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify 1 to enable the set_false_path constraint addition between clka of Distributed RAM and doutb_reg on clkb | +// +---------------------------------------------------------------------------------------------------------------------+ +// | USE_MEM_INIT | Integer | Range: 0 - 1. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify 1 to enable the generation of below message and 0 to disable generation of the following message completely.| +// | "INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. | +// | Initial memory contents will be all 0s." | +// | NOTE: This message gets generated only when there is no Memory Initialization specified either through file or | +// | Parameter. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | USE_MEM_INIT_MMI | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify 1 to expose this memory information to be written out in the MMI file. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WAKEUP_TIME | String | Allowed values: disable_sleep, use_sleep_pin. Default value = disable_sleep.| +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the | +// | dynamic power saving option | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_DATA_WIDTH_A | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port A write data input port dina, in bits. | +// | The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal. | +// | When ECC is enabled and set to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_A has to be | +// | multiples of 64-bits | +// | When ECC is enabled and set to "decode_only", then WRITE_DATA_WIDTH_A has to be multiples of 72-bits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_DATA_WIDTH_B | Integer | Range: 1 - 4608. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specify the width of the port B write data input port dinb, in bits. | +// | The values of WRITE_DATA_WIDTH_B and READ_DATA_WIDTH_B must be equal. | +// | When ECC is enabled and set to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_B has to be | +// | multiples of 64-bits | +// | When ECC is enabled and set to "decode_only", then WRITE_DATA_WIDTH_B has to be multiples of 72-bits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_MODE_A | String | Allowed values: no_change, read_first, write_first. Default value = no_change.| +// |---------------------------------------------------------------------------------------------------------------------| +// | Write mode behavior for port A output data port, douta. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_MODE_B | String | Allowed values: no_change, read_first, write_first. Default value = no_change.| +// |---------------------------------------------------------------------------------------------------------------------| +// | Write mode behavior for port B output data port, doutb. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_PROTECT | Integer | Range: 0 - 1. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Default value is 1, means write is protected through enable and write enable and hence the LUT is placed before the memory. This is the default behaviour to access memory.| +// | When 0, disables write protection. Write enable (WE) directly connected to memory. | +// | NOTE: Disable this option only if the advanced users can guarantee that the write enable (WE) cannot be given without enable (EN).| +// +---------------------------------------------------------------------------------------------------------------------+ + +// Port usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | addra | Input | ADDR_WIDTH_A | clka | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Address for port A write and read operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | addrb | Input | ADDR_WIDTH_B | clkb | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Address for port B write and read operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | clka | Input | 1 | NA | Rising edge | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock". | +// +---------------------------------------------------------------------------------------------------------------------+ +// | clkb | Input | 1 | NA | Rising edge | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". | +// | Unused when parameter CLOCKING_MODE is "common_clock". | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dbiterra | Output | 1 | clka | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Status signal to indicate double bit error occurrence on the data output of port A. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dbiterrb | Output | 1 | clkb | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Status signal to indicate double bit error occurrence on the data output of port A. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dina | Input | WRITE_DATA_WIDTH_A | clka | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Data input for port A write operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dinb | Input | WRITE_DATA_WIDTH_B | clkb | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Data input for port B write operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | douta | Output | READ_DATA_WIDTH_A | clka | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Data output for port A read operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | doutb | Output | READ_DATA_WIDTH_B | clkb | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Data output for port B read operations. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ena | Input | 1 | clka | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Memory enable signal for port A. | +// | Must be high on clock cycles when read or write operations are initiated. Pipelined internally. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | enb | Input | 1 | clkb | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Memory enable signal for port B. | +// | Must be high on clock cycles when read or write operations are initiated. Pipelined internally. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectdbiterra | Input | 1 | clka | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Controls double bit error injection on input data when ECC enabled (Error injection capability is not available in | +// | "decode_only" mode). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectdbiterrb | Input | 1 | clkb | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Controls double bit error injection on input data when ECC enabled (Error injection capability is not available in | +// | "decode_only" mode). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectsbiterra | Input | 1 | clka | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Controls single bit error injection on input data when ECC enabled (Error injection capability is not available in | +// | "decode_only" mode). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectsbiterrb | Input | 1 | clkb | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Controls single bit error injection on input data when ECC enabled (Error injection capability is not available in | +// | "decode_only" mode). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | regcea | Input | 1 | clka | Active-high | Tie to 1'b1 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Clock Enable for the last register stage on the output data path. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | regceb | Input | 1 | clkb | Active-high | Tie to 1'b1 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Clock Enable for the last register stage on the output data path. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rsta | Input | 1 | clka | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset signal for the final port A output register stage. | +// | Synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rstb | Input | 1 | clkb | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset signal for the final port B output register stage. | +// | Synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | sbiterra | Output | 1 | clka | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Status signal to indicate single bit error occurrence on the data output of port A. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | sbiterrb | Output | 1 | clkb | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Status signal to indicate single bit error occurrence on the data output of port B. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | sleep | Input | 1 | NA | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | sleep signal to enable the dynamic power saving feature. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wea | Input | WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A | clka | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write enable vector for port A input data port dina. 1 bit wide when word-wide writes are used. | +// | In byte-wide write configurations, each bit controls the writing one byte of dina to address addra. | +// | For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea would be 4'b0010. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | web | Input | WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B | clkb | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write enable vector for port B input data port dinb. 1 bit wide when word-wide writes are used. | +// | In byte-wide write configurations, each bit controls the writing one byte of dinb to address addrb. | +// | For example, to synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B is 32, web would be 4'b0010. | +// +---------------------------------------------------------------------------------------------------------------------+ + + +// xpm_memory_tdpram : In order to incorporate this function into the design, +// Verilog : the following instance declaration needs to be placed +// instance : in the body of the design code. The instance name +// declaration : (xpm_memory_tdpram_inst) and/or the port declarations within the +// code : parenthesis may be changed to properly reference and +// : connect this function to the design. All inputs +// : and outputs must be connected. + +// Please reference the appropriate libraries guide for additional information on the XPM modules. + +// <-----Cut code below this line----> + + // xpm_memory_tdpram: True Dual Port RAM + // Xilinx Parameterized Macro, version 2023.1 + + xpm_memory_tdpram #( + .ADDR_WIDTH_A (N), // DECIMAL + .ADDR_WIDTH_B (N), // DECIMAL + .AUTO_SLEEP_TIME (0), // DECIMAL + .BYTE_WRITE_WIDTH_A (B), // DECIMAL + .BYTE_WRITE_WIDTH_B (B), // DECIMAL + .CASCADE_HEIGHT (0), // DECIMAL + .CLOCKING_MODE ("independent_clock"), // String + .ECC_BIT_RANGE ("7:0"), // String + .ECC_MODE ("no_ecc"), // String + .ECC_TYPE ("none"), // String + .IGNORE_INIT_SYNTH (0), // DECIMAL + .MEMORY_INIT_FILE ("none"), // String + .MEMORY_INIT_PARAM ("0"), // String + .MEMORY_OPTIMIZATION ("true"), // String + .MEMORY_PRIMITIVE ("auto"), // String + .MEMORY_SIZE (B*2**N), // DECIMAL + .MESSAGE_CONTROL (0), // DECIMAL + .RAM_DECOMP ("auto"), // String + .READ_DATA_WIDTH_A (B), // DECIMAL + .READ_DATA_WIDTH_B (B), // DECIMAL + .READ_LATENCY_A (1+OUT_REG_ENA), // DECIMAL + .READ_LATENCY_B (1+OUT_REG_ENA), // DECIMAL + .READ_RESET_VALUE_A ("0"), // String + .READ_RESET_VALUE_B ("0"), // String + .RST_MODE_A ("SYNC"), // String + .RST_MODE_B ("SYNC"), // String + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .USE_EMBEDDED_CONSTRAINT (0), // DECIMAL + .USE_MEM_INIT (1), // DECIMAL + .USE_MEM_INIT_MMI (0), // DECIMAL + .WAKEUP_TIME ("disable_sleep"), // String + .WRITE_DATA_WIDTH_A (B), // DECIMAL + .WRITE_DATA_WIDTH_B (B), // DECIMAL + .WRITE_MODE_A ("no_change"), // String + .WRITE_MODE_B ("no_change"), // String + .WRITE_PROTECT (1) // DECIMAL + ) + xpm_memory_tdpram_inst ( + .dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence + // on the data output of port A. + + .dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence + // on the data output of port A. + + .douta(doa), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations. + .doutb(dob), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations. + .sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence + // on the data output of port A. + + .sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence + // on the data output of port B. + + .addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write and read operations. + .addrb(addrb), // ADDR_WIDTH_B-bit input: Address for port B write and read operations. + .clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when + // parameter CLOCKING_MODE is "common_clock". + + .clkb(clkb), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is + // "independent_clock". Unused when parameter CLOCKING_MODE is + // "common_clock". + + .dina(dia), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations. + .dinb(dib), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations. + .ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock + // cycles when read or write operations are initiated. Pipelined + // internally. + + .enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock + // cycles when read or write operations are initiated. Pipelined + // internally. + + .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when + // ECC enabled (Error injection capability is not available in + // "decode_only" mode). + + .injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when + // ECC enabled (Error injection capability is not available in + // "decode_only" mode). + + .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when + // ECC enabled (Error injection capability is not available in + // "decode_only" mode). + + .injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when + // ECC enabled (Error injection capability is not available in + // "decode_only" mode). + + .regcea(1'b1), // 1-bit input: Clock Enable for the last register stage on the output + // data path. + + .regceb(1'b1), // 1-bit input: Clock Enable for the last register stage on the output + // data path. + + .rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage. + // Synchronously resets output port douta to the value specified by + // parameter READ_RESET_VALUE_A. + + .rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage. + // Synchronously resets output port doutb to the value specified by + // parameter READ_RESET_VALUE_B. + + .sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature. + .wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector + // for port A input data port dina. 1 bit wide when word-wide writes are + // used. In byte-wide write configurations, each bit controls the + // writing one byte of dina to address addra. For example, to + // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A + // is 32, wea would be 4'b0010. + + .web(web) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector + // for port B input data port dinb. 1 bit wide when word-wide writes are + // used. In byte-wide write configurations, each bit controls the + // writing one byte of dinb to address addrb. For example, to + // synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B + // is 32, web would be 4'b0010. + + ); + + // End of xpm_memory_tdpram_inst instantiation + +endmodule \ No newline at end of file diff --git a/firmware/hdl/fifo_dc_axi_xpm.sv b/firmware/hdl/fifo_dc_axi_xpm.sv new file mode 100644 index 000000000..b7ddb0419 --- /dev/null +++ b/firmware/hdl/fifo_dc_axi_xpm.sv @@ -0,0 +1,465 @@ +//------------------------------------------------------------------------------ +// Company: Fermilab +// File: fifo_dc_axi_xpm.sv +// Description: FIFO Dual-Clock with Compatible AXI-S interface +//------------------------------------------------------------------------------ + +module fifo_dc_axi_xpm + #( + // Data width. + parameter B = 16, + + // Fifo depth. + parameter N = 4 + ) ( + input wire wr_rstn, + input wire wr_clk, + + input wire rd_rstn, + input wire rd_clk, + + // Write I/F. + input wire wr_en, + input wire [B-1:0] din, + + // Read I/F. + input wire rd_en, + output logic [B-1:0] dout, + + // Flags. + output logic full, + output logic empty + ); + + logic wr_rst; + + // Invert RST for FIFO Macro + assign wr_rst = ~ wr_rstn; + + + + + +// XPM_FIFO instantiation template for Asynchronous FIFO configurations +// Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation +// ======================================================================================================================= + +// Parameter usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Parameter name | Data type | Restrictions, if applicable | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | CASCADE_HEIGHT | Integer | Range: 0 - 64. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- No Cascade Height, Allow Vivado Synthesis to choose. | +// | 1 or more - Vivado Synthesis sets the specified value as Cascade Height. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | CDC_SYNC_STAGES | Integer | Range: 2 - 8. Default value = 2. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the number of synchronization stages on the CDC path | +// | | +// | Must be < 5 if FIFO_WRITE_DEPTH = 16 | +// +---------------------------------------------------------------------------------------------------------------------+ +// | DOUT_RESET_VALUE | String | Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset value of read data path. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ECC_MODE | String | Allowed values: no_ecc, en_ecc. Default value = no_ecc. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | "no_ecc" - Disables ECC | +// | "en_ecc" - Enables both ECC Encoder and Decoder | +// | | +// | NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_MEMORY_TYPE | String | Allowed values: auto, block, distributed. Default value = auto. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Designate the fifo memory primitive (resource type) to use. | +// | | +// | "auto"- Allow Vivado Synthesis to choose | +// | "block"- Block RAM FIFO | +// | "distributed"- Distributed RAM FIFO | +// | | +// | NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".| +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_READ_LATENCY | Integer | Range: 0 - 10. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Number of output register stages in the read data path. | +// | | +// | If READ_MODE = "fwft", then the only applicable value is 0. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_WRITE_DEPTH | Integer | Range: 16 - 4194304. Default value = 2048. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the FIFO Write Depth, must be power of two. | +// | | +// | In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH-1 | +// | In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+1 | +// | | +// | NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | FULL_RESET_VALUE | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset | +// +---------------------------------------------------------------------------------------------------------------------+ +// | PROG_EMPTY_THRESH | Integer | Range: 3 - 4194301. Default value = 10. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted. | +// | | +// | Min_Value = 3 + (READ_MODE_VAL*2) | +// | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2) | +// | | +// | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | +// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | +// | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | PROG_FULL_THRESH | Integer | Range: 5 - 4194301. Default value = 10. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. | +// | | +// | Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))+CDC_SYNC_STAGES | +// | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) | +// | | +// | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | +// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | +// | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | RD_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1. | +// | | +// | FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the width of the read data port, dout | +// | | +// | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | +// | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | +// | | +// | NOTE: | +// | | +// | READ_DATA_WIDTH should be equal to WRITE_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | +// | The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_MODE | String | Allowed values: std, fwft. Default value = std. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | "std"- standard read mode | +// | "fwft"- First-Word-Fall-Through read mode | +// +---------------------------------------------------------------------------------------------------------------------+ +// | RELATED_CLOCKS | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios | +// +---------------------------------------------------------------------------------------------------------------------+ +// | SIM_ASSERT_CHK | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. | +// | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | USE_ADV_FEATURES | String | Default value = 0707. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, | +// | prog_full, overflow features. | +// | | +// | Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0 | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WAKEUP_TIME | Integer | Range: 0 - 2. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | 0 - Disable sleep | +// | 2 - Use Sleep Pin | +// | | +// | NOTE: WAKEUP_TIME should be 0 if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the width of the write data port, din | +// | | +// | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | +// | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | +// | | +// | NOTE: | +// | | +// | WRITE_DATA_WIDTH should be equal to READ_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | +// | The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WR_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1. | +// +---------------------------------------------------------------------------------------------------------------------+ + +// Port usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | almost_empty | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to| +// | empty. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | almost_full | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | data_valid | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | din | Input | WRITE_DATA_WIDTH | wr_clk | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Data: The input data bus used when writing the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dout | Output | READ_DATA_WIDTH | rd_clk | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data: The output data bus is driven when reading the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | empty | Output | 1 | rd_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Empty Flag: When asserted, this signal indicates that the FIFO is empty. | +// | Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | full | Output | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Full Flag: When asserted, this signal indicates that the FIFO is full. | +// | Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive | +// | to the contents of the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectdbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or | +// | UltraRAM macros. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectsbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or | +// | UltraRAM macros. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | overflow | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, | +// | because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | prog_empty | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal | +// | to the programmable empty threshold value. | +// | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | prog_full | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal | +// | to the programmable full threshold value. | +// | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_clk | Input | 1 | NA | Rising edge | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read clock: Used for read operation. rd_clk must be a free running clock. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_data_count | Output | RD_DATA_COUNT_WIDTH | rd_clk | NA | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data Count: This bus indicates the number of words read from the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_en | Input | 1 | rd_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO. | +// | | +// | Must be held active-low when rd_rst_busy is active high. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_rst_busy | Output | 1 | rd_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rst | Input | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | sbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | sleep | Input | 1 | NA | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | underflow | Output | 1 | rd_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected | +// | because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_ack | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_clk | Input | 1 | NA | Rising edge | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write clock: Used for write operation. wr_clk must be a free running clock. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Data Count: This bus indicates the number of words written into the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_en | Input | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO. | +// | | +// | Must be held active-low when rst or wr_rst_busy is active high. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_rst_busy | Output | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. | +// +---------------------------------------------------------------------------------------------------------------------+ + + +// xpm_fifo_async : In order to incorporate this function into the design, +// Verilog : the following instance declaration needs to be placed +// instance : in the body of the design code. The instance name +// declaration : (xpm_fifo_async_inst) and/or the port declarations within the +// code : parenthesis may be changed to properly reference and +// : connect this function to the design. All inputs +// : and outputs must be connected. + +// Please reference the appropriate libraries guide for additional information on the XPM modules. + +// <-----Cut code below this line----> + + // xpm_fifo_async: Asynchronous FIFO + // Xilinx Parameterized Macro, version 2023.1 + + xpm_fifo_async #( + .CASCADE_HEIGHT(0), // DECIMAL + .CDC_SYNC_STAGES(2), // DECIMAL + .DOUT_RESET_VALUE("0"), // String + .ECC_MODE("no_ecc"), // String + .FIFO_MEMORY_TYPE("auto"), // String + .FIFO_READ_LATENCY(1), // DECIMAL + .FIFO_WRITE_DEPTH(N), // DECIMAL + .FULL_RESET_VALUE(0), // DECIMAL + .PROG_EMPTY_THRESH(10), // DECIMAL + .PROG_FULL_THRESH(10), // DECIMAL + .RD_DATA_COUNT_WIDTH(1), // DECIMAL + .READ_DATA_WIDTH(B), // DECIMAL + // .READ_MODE("std"), // String + .READ_MODE("fwft"), // String + .RELATED_CLOCKS(0), // DECIMAL + .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + // .USE_ADV_FEATURES("0707"), // String + .USE_ADV_FEATURES("0000"), // String + .WAKEUP_TIME(0), // DECIMAL + .WRITE_DATA_WIDTH(B), // DECIMAL + .WR_DATA_COUNT_WIDTH(1) // DECIMAL + ) + xpm_fifo_async_inst ( + .almost_empty(), // 1-bit output: Almost Empty : When asserted, this signal indicates that + // only one more read can be performed before the FIFO goes to empty. + + .almost_full(), // 1-bit output: Almost Full: When asserted, this signal indicates that + // only one more write can be performed before the FIFO is full. + + .data_valid(), // 1-bit output: Read Data Valid: When asserted, this signal indicates + // that valid data is available on the output bus (dout). + + .dbiterr(), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected + // a double-bit error and data in the FIFO core is corrupted. + + .dout(dout), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven + // when reading the FIFO. + + .empty(empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the + // FIFO is empty. Read requests are ignored when the FIFO is empty, + // initiating a read while empty is not destructive to the FIFO. + + .full(full), // 1-bit output: Full Flag: When asserted, this signal indicates that the + // FIFO is full. Write requests are ignored when the FIFO is full, + // initiating a write when the FIFO is full is not destructive to the + // contents of the FIFO. + + .overflow(), // 1-bit output: Overflow: This signal indicates that a write request + // (wren) during the prior clock cycle was rejected, because the FIFO is + // full. Overflowing the FIFO is not destructive to the contents of the + // FIFO. + + .prog_empty(), // 1-bit output: Programmable Empty: This signal is asserted when the + // number of words in the FIFO is less than or equal to the programmable + // empty threshold value. It is de-asserted when the number of words in + // the FIFO exceeds the programmable empty threshold value. + + .prog_full(), // 1-bit output: Programmable Full: This signal is asserted when the + // number of words in the FIFO is greater than or equal to the + // programmable full threshold value. It is de-asserted when the number of + // words in the FIFO is less than the programmable full threshold value. + + .rd_data_count(), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the + // number of words read from the FIFO. + + .rd_rst_busy(), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read + // domain is currently in a reset state. + + .sbiterr(), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected + // and fixed a single-bit error. + + .underflow(), // 1-bit output: Underflow: Indicates that the read request (rd_en) during + // the previous clock cycle was rejected because the FIFO is empty. Under + // flowing the FIFO is not destructive to the FIFO. + + .wr_ack(), // 1-bit output: Write Acknowledge: This signal indicates that a write + // request (wr_en) during the prior clock cycle is succeeded. + + .wr_data_count(), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates + // the number of words written into the FIFO. + + .wr_rst_busy(), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO + // write domain is currently in a reset state. + + .din(din), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when + // writing the FIFO. + + .injectdbiterr(1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .injectsbiterr(1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .rd_clk(rd_clk), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free + // running clock. + + .rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this + // signal causes data (on dout) to be read from the FIFO. Must be held + // active-low when rd_rst_busy is active high. + + .rst(wr_rst), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be + // unstable at the time of applying reset, but reset must be released only + // after the clock(s) is/are stable. + + .sleep(1'b0), // 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo + // block is in power saving mode. + + .wr_clk(wr_clk), // 1-bit input: Write clock: Used for write operation. wr_clk must be a + // free running clock. + + .wr_en(wr_en) // 1-bit input: Write Enable: If the FIFO is not full, asserting this + // signal causes data (on din) to be written to the FIFO. Must be held + // active-low when rst or wr_rst_busy is active high. + + ); + + // End of xpm_fifo_async_inst instantiation + +endmodule diff --git a/firmware/hdl/fifo_xpm.sv b/firmware/hdl/fifo_xpm.sv new file mode 100644 index 000000000..2a26b67d1 --- /dev/null +++ b/firmware/hdl/fifo_xpm.sv @@ -0,0 +1,437 @@ +module fifo_xpm #( + integer B = 16, // Data width + integer N = 4 // Fifo depth. +) +( + input wire rstn, + input wire clk, + + // Write I/F. + input wire wr_en, + input wire [B-1:0] din, + + // Read I/F. + input wire rd_en, + output logic [B-1:0] dout, + + // Flags. + output logic full, + output logic empty +); + +// XPM_FIFO instantiation template for Synchronous FIFO configurations +// Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation +// ======================================================================================================================= + +// Parameter usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Parameter name | Data type | Restrictions, if applicable | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | CASCADE_HEIGHT | Integer | Range: 0 - 64. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- No Cascade Height, Allow Vivado Synthesis to choose. | +// | 1 or more - Vivado Synthesis sets the specified value as Cascade Height. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | DOUT_RESET_VALUE | String | Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset value of read data path. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | ECC_MODE | String | Allowed values: no_ecc, en_ecc. Default value = no_ecc. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | "no_ecc" - Disables ECC | +// | "en_ecc" - Enables both ECC Encoder and Decoder | +// | | +// | NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_MEMORY_TYPE | String | Allowed values: auto, block, distributed, ultra. Default value = auto. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Designate the fifo memory primitive (resource type) to use- | +// | | +// | "auto"- Allow Vivado Synthesis to choose | +// | "block"- Block RAM FIFO | +// | "distributed"- Distributed RAM FIFO | +// | "ultra"- URAM FIFO | +// | | +// | NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".| +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_READ_LATENCY | Integer | Range: 0 - 100. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Number of output register stages in the read data path | +// | | +// | If READ_MODE = "fwft", then the only applicable value is 0 | +// +---------------------------------------------------------------------------------------------------------------------+ +// | FIFO_WRITE_DEPTH | Integer | Range: 16 - 4194304. Default value = 2048. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the FIFO Write Depth, must be power of two | +// | | +// | In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH | +// | In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+2 | +// | | +// | NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | FULL_RESET_VALUE | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset | +// +---------------------------------------------------------------------------------------------------------------------+ +// | PROG_EMPTY_THRESH | Integer | Range: 3 - 4194304. Default value = 10. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted. | +// | | +// | Min_Value = 3 + (READ_MODE_VAL*2) | +// | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2) | +// | | +// | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | +// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | +// | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | PROG_FULL_THRESH | Integer | Range: 3 - 4194301. Default value = 10. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. | +// | | +// | Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) | +// | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) | +// | | +// | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | +// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | +// | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | RD_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1. | +// | | +// | FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the width of the read data port, dout | +// | | +// | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | +// | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | +// | | +// | NOTE: | +// | | +// | READ_DATA_WIDTH should be equal to WRITE_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | +// | The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | READ_MODE | String | Allowed values: std, fwft. Default value = std. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | "std"- standard read mode | +// | "fwft"- First-Word-Fall-Through read mode | +// +---------------------------------------------------------------------------------------------------------------------+ +// | SIM_ASSERT_CHK | Integer | Range: 0 - 1. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. | +// | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | USE_ADV_FEATURES | String | Default value = 0707. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, | +// | prog_full, overflow features. | +// | | +// | Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1 | +// | Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0 | +// | Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0 | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WAKEUP_TIME | Integer | Range: 0 - 2. Default value = 0. | +// |---------------------------------------------------------------------------------------------------------------------| +// | | +// | 0 - Disable sleep | +// | 2 - Use Sleep Pin | +// | | +// | NOTE: WAKEUP_TIME should be 0 if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WRITE_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Defines the width of the write data port, din | +// | | +// | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | +// | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | +// | | +// | NOTE: | +// | | +// | WRITE_DATA_WIDTH should be equal to READ_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.| +// | The maximum FIFO size (width x depth) is limited to 150-Megabits. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | WR_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | +// |---------------------------------------------------------------------------------------------------------------------| +// | Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1. | +// +---------------------------------------------------------------------------------------------------------------------+ + +// Port usage table, organized as follows: +// +---------------------------------------------------------------------------------------------------------------------+ +// | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused | +// |---------------------------------------------------------------------------------------------------------------------| +// | Description | +// +---------------------------------------------------------------------------------------------------------------------+ +// +---------------------------------------------------------------------------------------------------------------------+ +// | almost_empty | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to| +// | empty. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | almost_full | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | data_valid | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout). | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dbiterr | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | din | Input | WRITE_DATA_WIDTH | wr_clk | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Data: The input data bus used when writing the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | dout | Output | READ_DATA_WIDTH | wr_clk | NA | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data: The output data bus is driven when reading the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | empty | Output | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Empty Flag: When asserted, this signal indicates that the FIFO is empty. | +// | Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | full | Output | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Full Flag: When asserted, this signal indicates that the FIFO is full. | +// | Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive | +// | to the contents of the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectdbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or | +// | UltraRAM macros. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | injectsbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or | +// | UltraRAM macros. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | overflow | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, | +// | because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | prog_empty | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal | +// | to the programmable empty threshold value. | +// | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | prog_full | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal | +// | to the programmable full threshold value. | +// | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_data_count | Output | RD_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Data Count: This bus indicates the number of words read from the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_en | Input | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO. | +// | | +// | Must be held active-low when rd_rst_busy is active high. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rd_rst_busy | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | rst | Input | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable.| +// +---------------------------------------------------------------------------------------------------------------------+ +// | sbiterr | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | sleep | Input | 1 | NA | Active-high | Tie to 1'b0 | +// |---------------------------------------------------------------------------------------------------------------------| +// | Dynamic power saving- If sleep is High, the memory/fifo block is in power saving mode. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | underflow | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected | +// | because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_ack | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_clk | Input | 1 | NA | Rising edge | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write clock: Used for write operation. wr_clk must be a free running clock. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Data Count: This bus indicates the number of words written into the FIFO. | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_en | Input | 1 | wr_clk | Active-high | Required | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO | +// | | +// | Must be held active-low when rst or wr_rst_busy or rd_rst_busy is active high | +// +---------------------------------------------------------------------------------------------------------------------+ +// | wr_rst_busy | Output | 1 | wr_clk | Active-high | DoNotCare | +// |---------------------------------------------------------------------------------------------------------------------| +// | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. | +// +---------------------------------------------------------------------------------------------------------------------+ + +//-------------------------------------------------------- +// NOTE: workaround to work identically to custom fifo.vhd +logic [B-1:0] dout_int, dout_r; + +assign dout = (rd_en & ~empty) ? dout_int : dout_r; + +always @(posedge clk) begin + if (rd_en & ~empty) begin + dout_r <= dout_int; + end +end +//-------------------------------------------------------- + +// xpm_fifo_sync : In order to incorporate this function into the design, +// Verilog : the following instance declaration needs to be placed +// instance : in the body of the design code. The instance name +// declaration : (xpm_fifo_sync_inst) and/or the port declarations within the +// code : parenthesis may be changed to properly reference and +// : connect this function to the design. All inputs +// : and outputs must be connected. + +// Please reference the appropriate libraries guide for additional information on the XPM modules. + +// <-----Cut code below this line----> + + // xpm_fifo_sync: Synchronous FIFO + // Xilinx Parameterized Macro, version 2023.1 + + xpm_fifo_sync #( + .CASCADE_HEIGHT (0), // DECIMAL + .DOUT_RESET_VALUE ("0"), // String + .ECC_MODE ("no_ecc"), // String + .FIFO_MEMORY_TYPE ("auto"), // String + .FIFO_READ_LATENCY (1), // DECIMAL + .FIFO_WRITE_DEPTH (N), // DECIMAL + .FULL_RESET_VALUE (0), // DECIMAL + .PROG_EMPTY_THRESH (10), // DECIMAL + .PROG_FULL_THRESH (10), // DECIMAL + .RD_DATA_COUNT_WIDTH (1), // DECIMAL + .READ_DATA_WIDTH (B), // DECIMAL + // .READ_MODE ("std"), // String + .READ_MODE ("fwft"), // String + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .USE_ADV_FEATURES ("0000"), // String + .WAKEUP_TIME (0), // DECIMAL + .WRITE_DATA_WIDTH (B), // DECIMAL + .WR_DATA_COUNT_WIDTH (1) // DECIMAL + ) + xpm_fifo_sync_inst ( + .almost_empty(), // 1-bit output: Almost Empty : When asserted, this signal indicates that + // only one more read can be performed before the FIFO goes to empty. + + .almost_full(), // 1-bit output: Almost Full: When asserted, this signal indicates that + // only one more write can be performed before the FIFO is full. + + .data_valid(), // 1-bit output: Read Data Valid: When asserted, this signal indicates + // that valid data is available on the output bus (dout). + + .dbiterr(), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected + // a double-bit error and data in the FIFO core is corrupted. + + .dout(dout_int), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven + // when reading the FIFO. + + .empty(empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the + // FIFO is empty. Read requests are ignored when the FIFO is empty, + // initiating a read while empty is not destructive to the FIFO. + + .full(full), // 1-bit output: Full Flag: When asserted, this signal indicates that the + // FIFO is full. Write requests are ignored when the FIFO is full, + // initiating a write when the FIFO is full is not destructive to the + // contents of the FIFO. + + .overflow(), // 1-bit output: Overflow: This signal indicates that a write request + // (wren) during the prior clock cycle was rejected, because the FIFO is + // full. Overflowing the FIFO is not destructive to the contents of the + // FIFO. + + .prog_empty(), // 1-bit output: Programmable Empty: This signal is asserted when the + // number of words in the FIFO is less than or equal to the programmable + // empty threshold value. It is de-asserted when the number of words in + // the FIFO exceeds the programmable empty threshold value. + + .prog_full(), // 1-bit output: Programmable Full: This signal is asserted when the + // number of words in the FIFO is greater than or equal to the + // programmable full threshold value. It is de-asserted when the number of + // words in the FIFO is less than the programmable full threshold value. + + .rd_data_count(), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the + // number of words read from the FIFO. + + .rd_rst_busy(), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read + // domain is currently in a reset state. + + .sbiterr(), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected + // and fixed a single-bit error. + + .underflow(), // 1-bit output: Underflow: Indicates that the read request (rd_en) during + // the previous clock cycle was rejected because the FIFO is empty. Under + // flowing the FIFO is not destructive to the FIFO. + + .wr_ack(), // 1-bit output: Write Acknowledge: This signal indicates that a write + // request (wr_en) during the prior clock cycle is succeeded. + + .wr_data_count(), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates + // the number of words written into the FIFO. + + .wr_rst_busy(), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO + // write domain is currently in a reset state. + + .din(din), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when + // writing the FIFO. + + .injectdbiterr(1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .injectsbiterr(1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this + // signal causes data (on dout) to be read from the FIFO. Must be held + // active-low when rd_rst_busy is active high. + + .rst(~rstn), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be + // unstable at the time of applying reset, but reset must be released only + // after the clock(s) is/are stable. + + .sleep(1'b0), // 1-bit input: Dynamic power saving- If sleep is High, the memory/fifo + // block is in power saving mode. + + .wr_clk(clk), // 1-bit input: Write clock: Used for write operation. wr_clk must be a + // free running clock. + + .wr_en(wr_en) // 1-bit input: Write Enable: If the FIFO is not full, asserting this + // signal causes data (on din) to be written to the FIFO Must be held + // active-low when rst or wr_rst_busy or rd_rst_busy is active high + + ); + + // End of xpm_fifo_sync_inst instantiation + +endmodule \ No newline at end of file diff --git a/firmware/hdl/lo_spi_mux.vhd b/firmware/hdl/lo_spi_mux.vhd new file mode 100644 index 000000000..da514c53f --- /dev/null +++ b/firmware/hdl/lo_spi_mux.vhd @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11/16/2017 02:49:57 PM +-- Design Name: +-- Module Name: lo_spi_mux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity lo_spi_mux is + Port ( ss_in : in STD_LOGIC_VECTOR (1 downto 0); + ss0_out : out STD_LOGIC; + ss1_out : out STD_LOGIC; + sdo0_in : in STD_LOGIC; + sdo1_in : in STD_LOGIC; + sdo_out : out STD_LOGIC); +end lo_spi_mux; + +architecture Behavioral of lo_spi_mux is + +begin + +-- Assign ss outputs. +ss0_out <= ss_in(0); +ss1_out <= ss_in(1); + +sdo_out <= sdo0_in when (ss_in(1) = '1' and ss_in(0) = '0') else + sdo1_in when (ss_in(1) = '0' and ss_in(0) = '1') else + '1'; + +end Behavioral; diff --git a/firmware/hdl/lo_spi_mux_v2.vhd b/firmware/hdl/lo_spi_mux_v2.vhd new file mode 100644 index 000000000..3da62c9a2 --- /dev/null +++ b/firmware/hdl/lo_spi_mux_v2.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11/16/2017 02:49:57 PM +-- Design Name: +-- Module Name: lo_spi_mux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity lo_spi_mux_v2 is + Port ( ss_in : in STD_LOGIC_VECTOR (2 downto 0); + ss0_out : out STD_LOGIC; + ss1_out : out STD_LOGIC; + ss2_out : out STD_LOGIC; + sdo0_in : in STD_LOGIC; + sdo1_in : in STD_LOGIC; + sdo2_in : in STD_LOGIC; + sdo_out : out STD_LOGIC); +end lo_spi_mux_v2; + +architecture Behavioral of lo_spi_mux_v2 is + +begin + +-- Assign ss outputs. +ss0_out <= ss_in(0); +ss1_out <= ss_in(1); +ss2_out <= ss_in(2); + +sdo_out <= sdo0_in when (ss_in(2) = '1' and ss_in(1) = '1' and ss_in(0) = '0') else + sdo1_in when (ss_in(2) = '1' and ss_in(1) = '0' and ss_in(0) = '1') else + sdo2_in when (ss_in(2) = '0' and ss_in(1) = '1' and ss_in(0) = '1') else + '1'; + +end Behavioral; diff --git a/firmware/hdl/vect2bits_4.v b/firmware/hdl/vect2bits_16.v similarity index 52% rename from firmware/hdl/vect2bits_4.v rename to firmware/hdl/vect2bits_16.v index 1d87ff8e5..4b9a9d399 100644 --- a/firmware/hdl/vect2bits_4.v +++ b/firmware/hdl/vect2bits_16.v @@ -5,7 +5,7 @@ // // Create Date: 12/14/2020 04:56:49 PM // Design Name: -// Module Name: vect2bits_4 +// Module Name: vect2bits_16 // Project Name: // Target Devices: // Tool Versions: @@ -20,20 +20,40 @@ ////////////////////////////////////////////////////////////////////////////////// -module vect2bits_4( +module vect2bits_16( input [159:0] din, output dout0, output dout1, output dout2, output dout3, + output dout4, + output dout5, + output dout6, + output dout7, + output dout8, + output dout9, + output dout10, + output dout11, + output dout12, + output dout13, output dout14, output dout15 ); - assign dout0 = din[0]; - assign dout1 = din[1]; - assign dout2 = din[2]; - assign dout3 = din[3]; + assign dout0 = din[0]; + assign dout1 = din[1]; + assign dout2 = din[2]; + assign dout3 = din[3]; + assign dout4 = din[4]; + assign dout5 = din[5]; + assign dout6 = din[6]; + assign dout7 = din[7]; + assign dout8 = din[8]; + assign dout9 = din[9]; + assign dout10 = din[10]; + assign dout11 = din[11]; + assign dout12 = din[12]; + assign dout13 = din[13]; assign dout14 = din[14]; assign dout15 = din[15]; endmodule diff --git a/firmware/ip/axis_avg_buffer/component.xml b/firmware/ip/axis_avg_buffer/component.xml index ef0f4f924..a0bb2050d 100644 --- a/firmware/ip/axis_avg_buffer/component.xml +++ b/firmware/ip/axis_avg_buffer/component.xml @@ -1,9 +1,9 @@ - user.org - user + QICK + QICK axis_avg_buffer - 1.0 + 1.2 m0_axis @@ -303,6 +303,10 @@ ASSOCIATED_RESET s_axi_aresetn + + FREQ_HZ + + @@ -351,6 +355,10 @@ ASSOCIATED_RESET s_axis_aresetn + + FREQ_HZ + + @@ -399,6 +407,10 @@ ASSOCIATED_BUSIF m0_axis:m1_axis:m2_axis + + FREQ_HZ + + @@ -482,7 +494,7 @@ viewChecksum - 7ebfc17e + 155b9075 @@ -498,7 +510,7 @@ viewChecksum - 7ebfc17e + d91f78e5 @@ -516,6 +528,35 @@ + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 1bf6db59 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -1140,12 +1181,12 @@ N_AVG N Avg - 10 + 14 N_BUF N Buf - 10 + 12 B @@ -1185,7 +1226,7 @@ systemVerilogSource - src/axi_slv.vhd + src/axi_slv_avg_buf.vhd vhdlSource @@ -1217,8 +1258,8 @@ vhdlSource - src/fifo/fifo_dc_axi.vhd - vhdlSource + ../../hdl/fifo_dc_axi_xpm.sv + systemVerilogSource src/fifo/gray2bin.vhd @@ -1239,7 +1280,8 @@ src/axis_avg_buffer.v verilogSource - CHECKSUM_34e77db7 + CHECKSUM_83e615b1 + xil_defaultlib @@ -1247,26 +1289,27 @@ src/avg_buffer.v verilogSource + xil_defaultlib src/avg_top.v verilogSource + xil_defaultlib src/buffer_top.v verilogSource + xil_defaultlib src/avg.sv systemVerilogSource + xil_defaultlib src/buffer.sv systemVerilogSource - - - src/axi_slv.vhd - vhdlSource + xil_defaultlib src/fifo/bin2gray.vhd @@ -1297,8 +1340,8 @@ vhdlSource - src/fifo/fifo_dc_axi.vhd - vhdlSource + ../../hdl/fifo_dc_axi_xpm.sv + systemVerilogSource src/fifo/gray2bin.vhd @@ -1316,32 +1359,52 @@ src/fifo/synchronizer_vect.vhd vhdlSource - - src/axis_avg_buffer.v - verilogSource - xilinx_xpgui_view_fileset - xgui/axis_avg_buffer_v1_0.tcl + xgui/axis_avg_buffer_v1_2.tcl tclSource CHECKSUM_be680c07 XGUI_VERSION_2 + + xilinx_testbench_view_fileset + + src/tb/tb_avg_buffer.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + xil_defaultlib + + + src/tb/tb_waves.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + - AXIS Average + Buffer block with external trigger. + AXIS Average + Buffer block with external trigger and edge-counting mode. N_AVG N Avg - 10 + 14 N_BUF N Buf - 10 + 12 B @@ -1355,119 +1418,29 @@ - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - /UserIP + /QICK/Miscellaneous AXIS Average + Buffer + level_2 package_project - 6 - 2021-06-15T19:18:03Z - - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 4 + + QICK:QICK:axis_avg_buffer:1.0 + QICK:QICK:axis_avg_buffer:1.1 + + 2025-09-02T22:17:40Z - 2019.1 - + 2023.1 + - + - - + + diff --git a/firmware/ip/axis_avg_buffer/src/avg.sv b/firmware/ip/axis_avg_buffer/src/avg.sv index 6772e9e73..787e49f33 100644 --- a/firmware/ip/axis_avg_buffer/src/avg.sv +++ b/firmware/ip/axis_avg_buffer/src/avg.sv @@ -1,3 +1,13 @@ +// Description: +// AVG block is a FSM that receives an input stream of samples (din), and controls the interface to a memory to capture and store them. It has two different work modes. +// If PHOTON_MODE=0, the data stored is the accumulated value of the input data during a determined number of samples. +// If PHOTON_MODE=1, the data stored is the number of times the data has gone over and below configurable thresholds (H & L THRSH REGs) - edge counter mode +// Capturing is initiated by an external trigger after the buffer has been enabled. Number of processed samples and address where to store them are configurable. +// When number of captured samples is reached, it can be triggered again. +// +// Parameters: +// N: memory depth as 2**N; B: memory data width + // Data is I,Q. // I: lower B bits. // Q: upper B bits. @@ -10,6 +20,7 @@ module avg ( trigger_i , // Data input. + din_valid_i , din_i , // Memory interface. @@ -20,7 +31,10 @@ module avg ( // Registers. START_REG , ADDR_REG , - LEN_REG + LEN_REG , + PHOTON_MODE_REG, + H_THRSH_REG , + L_THRSH_REG ); //////////////// @@ -40,6 +54,7 @@ input clk; input trigger_i; +input din_valid_i; input [2*B-1:0] din_i; output mem_we_o; @@ -49,6 +64,9 @@ output [4*B-1:0] mem_di_o; input START_REG; input [N-1:0] ADDR_REG; input [31:0] LEN_REG; +input PHOTON_MODE_REG; +input [B-1:0] H_THRSH_REG; +input [B-1:0] L_THRSH_REG; ////////////////////// // Internal signals // @@ -72,21 +90,29 @@ reg avg_state; reg qout_state; reg write_mem_state; +// Edge counter states. +reg high_state; +reg high_state_reg; + // Counter. reg [31:0] cnt; // Registers. reg [N-1:0] addr_r; reg [31:0] len_r; +reg photon_mode_r; +reg signed [B-1:0] h_thrsh_r; +reg signed [B-1:0] l_thrsh_r; // Input data. wire signed [B-1:0] din_ii, din_qq; // Accumulators. reg signed [2*B-1:0] acc_i, acc_q; +reg [4*B-1:0] acc_photon; // Quantized outputs. -reg signed [2*B-1:0] out_i_r, out_q_r; +reg [4*B-1:0] out_result_r; ////////////////// @@ -108,14 +134,20 @@ always @(posedge clk) begin // Registers. addr_r <= 0; len_r <= 0; + photon_mode_r <= 1'b0; + h_thrsh_r <= 0; + l_thrsh_r <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; // Accumulators. acc_i <= 0; acc_q <= 0; + acc_photon <= 0; // Quantized outputs. - out_i_r <= 0; - out_q_r <= 0; + out_result_r <= 0; + end else begin // State register. @@ -134,7 +166,7 @@ always @(posedge clk) begin state <= AVG_ST; AVG_ST: - if ( cnt == len_r-1 ) + if ( cnt == len_r && din_valid_i == 1'b1 ) state <= QOUT_ST; QOUT_ST: @@ -152,35 +184,57 @@ always @(posedge clk) begin endcase // Counter. - if ( avg_state == 1'b1 ) - cnt <= cnt + 1; - else + if ( avg_state == 1'b1 ) begin + if ( din_valid_i == 1'b1) + cnt <= cnt + 1; + end + else begin cnt <= 0; + end // Registers. if ( start_state == 1'b1 ) begin addr_r <= ADDR_REG; - len_r <= LEN_REG; + len_r <= LEN_REG - 1; + photon_mode_r <= PHOTON_MODE_REG; + h_thrsh_r <= H_THRSH_REG; + l_thrsh_r <= L_THRSH_REG; end else if ( write_mem_state == 1'b1 ) begin addr_r <= addr_r + 1; end // Accumulators. - if ( trigger_state == 1'b1) begin - acc_i <= 0; - acc_q <= 0; + if ( trigger_state == 1'b1 ) begin + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; end - else if ( avg_state == 1'b1 ) begin - acc_i <= acc_i + din_ii; - acc_q <= acc_q + din_qq; + else if ( avg_state == 1'b1 && din_valid_i == 1'b1 ) begin + // Accumulator counter. + if ( photon_mode_r == 1'b0 ) begin + acc_i <= acc_i + din_ii; + acc_q <= acc_q + din_qq; + end + // Rising edge counter. + else if ( high_state == 1'b1 && high_state_reg == 1'b0) + acc_photon <= acc_photon + 1; end + + // Edge counter detect. + high_state_reg <= high_state; + if ( din_ii > h_thrsh_r ) + high_state <= 1'b1; + else if ( din_ii < l_thrsh_r ) + high_state <= 1'b0; // Quantized outputs. - if ( qout_state == 1'b1) begin - out_i_r <= acc_i; - out_q_r <= acc_q; - end + if ( photon_mode_r == 1'b0 ) + out_result_r <= {acc_q,acc_i}; + else + out_result_r <= acc_photon; end end @@ -218,7 +272,7 @@ end // Assign outputs. assign mem_we_o = write_mem_state; assign mem_addr_o = addr_r; -assign mem_di_o = {out_q_r,out_i_r}; +assign mem_di_o = out_result_r; endmodule diff --git a/firmware/ip/axis_avg_buffer/src/avg_buffer.v b/firmware/ip/axis_avg_buffer/src/avg_buffer.v index 1373d0ab1..49e1c884c 100644 --- a/firmware/ip/axis_avg_buffer/src/avg_buffer.v +++ b/firmware/ip/axis_avg_buffer/src/avg_buffer.v @@ -1,8 +1,16 @@ +// Description: +// AVG_BUFFER is a block that receives an input stream of samples (s_axis) and generates three output streams, one with processed averaged data (m0_axis) and one with raw captured data (m1_axis) and one with averaged data but prior to be stored in internal memory (sent to tProc register) (m2_axis) Captured samples are internally stored in PL memory. +// Capture is configured and controlled with Registers and is initiated by an external trigger after the buffer has been enabled. Number of captured samples and address where to store them are configurable. +// Output stream generation is configured and controlled with Registers where the address to start reading data and the number of samples can be configured. Output stream can be interfaced to an AXIS-DMA module +// +// Parameters: +// N_AVG & N_BUF: memory depth as 2**N; B: memory data width +// // Data is I,Q. // I: lower B bits. // Q: upper B bits. module avg_buffer ( - // Reset and clock for s. + // Reset and clock for s_axis s_axis_aclk , s_axis_aresetn , @@ -14,7 +22,7 @@ module avg_buffer ( s_axis_tready , s_axis_tdata , - // Reset and clock for m0, m1 and m2. + // Reset and clock for m0_axis, m1_axis and m2_axis. m_axis_aclk , m_axis_aresetn , @@ -39,6 +47,9 @@ module avg_buffer ( AVG_START_REG , AVG_ADDR_REG , AVG_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG , AVG_DR_START_REG , AVG_DR_ADDR_REG , AVG_DR_LEN_REG , @@ -92,6 +103,9 @@ output [4*B-1:0] m2_axis_tdata; input AVG_START_REG; input [N_AVG-1:0] AVG_ADDR_REG; input [31:0] AVG_LEN_REG; +input AVG_PHOTON_MODE_REG; +input [B-1:0] AVG_H_THRSH_REG; +input [B-1:0] AVG_L_THRSH_REG; input AVG_DR_START_REG; input [N_AVG-1:0] AVG_DR_ADDR_REG; input [N_AVG-1:0] AVG_DR_LEN_REG; @@ -140,6 +154,7 @@ avg_top .trigger_i (trigger_resync ), // Data input. + .din_valid_i (s_axis_tvalid ), .din_i (s_axis_tdata ), // Reset and clock for M_AXIS_* @@ -156,14 +171,17 @@ avg_top .m1_axis_tvalid (m2_axis_tvalid ), .m1_axis_tready (m2_axis_tready ), .m1_axis_tdata (m2_axis_tdata ), - + // Registers. .AVG_START_REG (AVG_START_REG ), .AVG_ADDR_REG (AVG_ADDR_REG ), .AVG_LEN_REG (AVG_LEN_REG ), .DR_START_REG (AVG_DR_START_REG ), .DR_ADDR_REG (AVG_DR_ADDR_REG ), - .DR_LEN_REG (AVG_DR_LEN_REG ) + .DR_LEN_REG (AVG_DR_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ) ); // Buffer block. @@ -182,6 +200,7 @@ buffer_top .trigger_i (trigger_resync ), // Data input. + .din_valid_i (s_axis_tvalid ), .din_i (s_axis_tdata ), // AXIS Master for output. diff --git a/firmware/ip/axis_avg_buffer/src/avg_top.v b/firmware/ip/axis_avg_buffer/src/avg_top.v index a5c22c4b3..665c4c517 100644 --- a/firmware/ip/axis_avg_buffer/src/avg_top.v +++ b/firmware/ip/axis_avg_buffer/src/avg_top.v @@ -1,3 +1,12 @@ +// Description: +// AVG_TOP block receives an input stream of samples (s_axis), captures and stores them in an internal memory when indicated and generates two output streams, one with averaged data stored in internal memory (m0_axis) and one with averaged data as soon as it's calculated prior to internal memory (m1_axis) +// Capturing flow is controlled by the AVG FSM block and is initiated by an external trigger after the buffer has been enabled. Number of captured samples and address where to store them are configurable. +// Captured samples are internally stored in BRAM memory. +// Output stream is generated and controlled from the DATA_READER FSM block. Address to start reading and number of samples are configurable. It can be interfaced with an AXIS DMA module. +// +// Parameters: +// N: memory depth as 2**N; B: memory data width +// module avg_top ( // Reset and clock. rstn , @@ -7,9 +16,10 @@ module avg_top ( trigger_i , // Data input. + din_valid_i , din_i , - // Reset and clock for M_AXIS_* + // Reset and clock for m0_axis and m1_axis m_axis_aclk , m_axis_aresetn , @@ -30,7 +40,10 @@ module avg_top ( AVG_LEN_REG , DR_START_REG , DR_ADDR_REG , - DR_LEN_REG + DR_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG ); //////////////// @@ -50,6 +63,7 @@ input clk; input trigger_i; +input din_valid_i; input [2*B-1:0] din_i; input m_axis_aclk; @@ -70,6 +84,9 @@ input [31:0] AVG_LEN_REG; input DR_START_REG; input [N-1:0] DR_ADDR_REG; input [N-1:0] DR_LEN_REG; +input AVG_PHOTON_MODE_REG; +input [B-1:0] AVG_H_THRSH_REG; +input [B-1:0] AVG_L_THRSH_REG; ////////////////////// // Internal signals // @@ -120,24 +137,28 @@ avg avg_i ( // Reset and clock. - .rstn (rstn ), - .clk (clk ), + .rstn (rstn ), + .clk (clk ), // Trigger input. - .trigger_i (trigger_i ), + .trigger_i (trigger_i ), // Data input. - .din_i (din_i ), + .din_valid_i (din_valid_i ), + .din_i (din_i ), // Memory interface. - .mem_we_o (mem_we_int ), - .mem_addr_o (mem_addra_int ), - .mem_di_o (mem_di_int ), + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), // Registers. - .START_REG (AVG_START_REG_resync ), - .ADDR_REG (AVG_ADDR_REG ), - .LEN_REG (AVG_LEN_REG ) + .START_REG (AVG_START_REG_resync ), + .ADDR_REG (AVG_ADDR_REG ), + .LEN_REG (AVG_LEN_REG ), + .PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .H_THRSH_REG (AVG_H_THRSH_REG ), + .L_THRSH_REG (AVG_L_THRSH_REG ) ); // Dual port BRAM. @@ -193,13 +214,13 @@ data_reader ); // Output data register (dc fifo to cross domain). -fifo_dc_axi +fifo_dc_axi_xpm #( // Data width. .B (4*B ), // Fifo depth. - .N (4 ) + .N (16 ) ) fifo_i ( diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo index 5f3313504..7265fca4e 100644 --- a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo @@ -1,21 +1,21 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. // // This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable +// AMD, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, +// (2) AMD shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these @@ -24,11 +24,11 @@ // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the +// reasonably foreseeable or AMD had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- +// AMD products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, @@ -37,7 +37,7 @@ // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical +// liability of any use of AMD products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // @@ -47,7 +47,7 @@ // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 +// IP Revision: 14 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho index 5c4d9a9f7..00b58d6f9 100644 --- a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho @@ -1,21 +1,21 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. -- -- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable +-- AMD, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, +-- (2) AMD shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these @@ -24,11 +24,11 @@ -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the +-- reasonably foreseeable or AMD had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- +-- AMD products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, @@ -37,7 +37,7 @@ -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical +-- liability of any use of AMD products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- @@ -45,9 +45,8 @@ -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. - -- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 +-- IP Revision: 14 -- The following code must appear in the VHDL architecture header. @@ -74,7 +73,7 @@ COMPONENT axi_mst_0 m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC + m_axi_rready : OUT STD_LOGIC ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -113,3 +112,5 @@ your_instance_name : axi_mst_0 -- the core, axi_mst_0. When compiling the wrapper file, be sure to -- reference the VHDL simulation library. + + diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci index 34f0b1287..350ae6412 100644 --- a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci @@ -1,187 +1,215 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - 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"long", "usage": "all" } ], + "C_AXI_HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu49dr" } ], + "PACKAGE": [ { "value": "ffvf1760" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "14" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "." } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0" } ], + "aresetn": [ { "direction": "in", "driver_value": "1" } ], + "m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out" } ], + "m_axi_awready": [ { "direction": "in", "driver_value": "0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out" } ], + "m_axi_wready": [ { "direction": "in", "driver_value": "0" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "m_axi_bvalid": [ { "direction": "in", "driver_value": "0" } ], + "m_axi_bready": [ { "direction": "out" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out" } ], + "m_axi_arready": [ { "direction": "in", "driver_value": "0" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "m_axi_rvalid": [ { "direction": "in", "driver_value": "0" } ], + "m_axi_rready": [ { "direction": "out" } ] + }, + "interfaces": { + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "address_space_ref": "Master_AXI", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "address_spaces": { + "Master_AXI": { + "range": "4294967296", + "width": "32" + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml index 58db142ae..ce88989a2 100644 --- a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml @@ -593,7 +593,7 @@ PHASE - 0.000 + 0.0 simulation.tlm @@ -1249,7 +1249,7 @@ PHASE - 0.000 + 0.0 simulation.tlm @@ -1419,9 +1419,18 @@ FREQ_HZ 100000000 + + FREQ_TOLERANCE_HZ + 0 + + + none + + + PHASE - 0.000 + 0.0 none @@ -1437,6 +1446,15 @@ + + ASSOCIATED_PORT + + + + none + + + INSERT_VIP 0 @@ -1533,214 +1551,196 @@ - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints - xilinx_veriloginstantiationtemplate_view_fileset + xilinx_synthesisconstraints_view_fileset GENtimestamp - Thu Dec 17 22:05:33 UTC 2020 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:564fbf77 + 9:9d34f5c8 - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi_vip_v1_1_5_top - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + axi_vip - xilinx_verilogsynthesis_view_fileset + xilinx_systemcsimulation_view_fileset GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:564fbf77 + 9:c4ac87bc - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + sim_type + tlm - outputProductCRC - 9:564fbf77 + use_subcore_outputs + false - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc axi_mst_0 - xilinx_verilogsynthesiswrapper_view_fileset + xilinx_systemcsimulationwrapper_view_fileset GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:564fbf77 + 9:c4ac87bc + + + sim_type + tlm - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_5_top + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + axi_vip_v1_1_14_top - xilinx_versioninformation_view_fileset + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:564fbf77 + 9:39b4649f - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog - xilinx_externalfiles_view_fileset + xilinx_veriloginstantiationtemplate_view_fileset GENtimestamp - Thu Dec 17 22:06:13 UTC 2020 + Tue Mar 05 15:15:54 UTC 2024 outputProductCRC - 9:564fbf77 + 9:9d34f5c8 - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper verilog - axi_vip_v1_1_5_top - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - + axi_mst_0 - xilinx_verilogbehavioralsimulation_view_fileset + xilinx_verilogsimulationwrapper_view_fileset GENtimestamp - Wed Jun 09 17:20:00 UTC 2021 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:eaaf4dfa + 9:39b4649f - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - axi_vip + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + axi_vip_v1_1_14_top - xilinx_systemcsimulation_view_fileset + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset GENtimestamp - Wed Jun 09 17:20:00 UTC 2021 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:6d8e49fa - - - sim_type - tlm - - - use_subcore_outputs - false + 9:9d34f5c8 - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper verilog axi_mst_0 - xilinx_verilogsimulationwrapper_view_fileset + xilinx_verilogsynthesiswrapper_view_fileset GENtimestamp - Wed Jun 09 17:20:00 UTC 2021 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:eaaf4dfa + 9:9d34f5c8 - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - axi_mst_0 + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + axi_vip_v1_1_14_top - xilinx_systemcsimulationwrapper_view_fileset + xilinx_versioninformation_view_fileset GENtimestamp - Wed Jun 09 17:20:00 UTC 2021 + Tue Mar 05 15:15:58 UTC 2024 outputProductCRC - 9:6d8e49fa - - - sim_type - tlm + 9:9d34f5c8 @@ -4260,105 +4260,73 @@ - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - + xilinx_synthesisconstraints_view_fileset - axi_mst_0.veo - verilogTemplate + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + xilinx_systemcsimulation_view_fileset - hdl/axi_infrastructure_v1_1_0.vh - verilogSource + sysc/axi_vip.h + systemCSource true - axi_infrastructure_v1_1_0 - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_14 - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_5 + sysc/sim_ipc_aximm_master.cpp + systemCSource + axi_vip_v1_1_14 - - - xilinx_synthesisconstraints_view_fileset - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis + sysc/sim_ipc_aximm_slave.cpp + systemCSource + axi_vip_v1_1_14 - - - xilinx_verilogsynthesiswrapper_view_fileset - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib + sysc/sim_ipc_aximm_master.h + systemCSource + true + axi_vip_v1_1_14 - - - xilinx_versioninformation_view_fileset - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_5 + sysc/sim_ipc_aximm_slave.h + systemCSource + true + axi_vip_v1_1_14 - xilinx_externalfiles_view_fileset + xilinx_systemcsimulationwrapper_view_fileset - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib + sim/axi_mst_0_sc.h + systemCSource + true - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib + sim/axi_mst_0_sc.cpp + systemCSource - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib + sim/axi_mst_0.h + systemCSource + true - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib + sim/axi_mst_0.cpp + systemCSource - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib + sim/axi_mst_0_stub.sv + systemVerilogSource @@ -4394,21 +4362,18 @@ hdl/axi_vip_v1_1_vl_rfs.sv systemVerilogSource USED_IN_ipstatic - axi_vip_v1_1_5 + axi_vip_v1_1_14 - xilinx_systemcsimulation_view_fileset + xilinx_veriloginstantiationtemplate_view_fileset - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_5 + axi_mst_0.vho + vhdlTemplate - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 + axi_mst_0.veo + verilogTemplate @@ -4420,28 +4385,48 @@ - xilinx_systemcsimulationwrapper_view_fileset + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - sim/axi_mst_0_sc.h - systemCSource + hdl/axi_infrastructure_v1_1_0.vh + verilogSource true + axi_infrastructure_v1_1_0 - sim/axi_mst_0_sc.cpp - systemCSource + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + xilinx_verilogsynthesis_view_fileset - sim/axi_mst_0.h - systemCSource - true + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + xilinx_verilogsynthesiswrapper_view_fileset - sim/axi_mst_0.cpp - systemCSource + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + xilinx_versioninformation_view_fileset - sim/axi_mst_0_stub.sv - systemVerilogSource + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 @@ -4470,7 +4455,7 @@ ADDR_WIDTH ADDRESS WIDTH - 32 + 32 DATA_WIDTH @@ -4699,14 +4684,21 @@ HAS ARESETN 1 + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + AXI Verification IP xtlm + xtlm_ipc_v1_0 + protobuf - 5 + 14 true @@ -4738,14 +4730,14 @@ - 2019.1 + 2023.1 - + - + diff --git a/firmware/ip/axis_avg_buffer/src/axi_slv.vhd b/firmware/ip/axis_avg_buffer/src/axi_slv_avg_buf.vhd similarity index 98% rename from firmware/ip/axis_avg_buffer/src/axi_slv.vhd rename to firmware/ip/axis_avg_buffer/src/axi_slv_avg_buf.vhd index a1be63e1f..9a720a0f8 100644 --- a/firmware/ip/axis_avg_buffer/src/axi_slv.vhd +++ b/firmware/ip/axis_avg_buffer/src/axi_slv_avg_buf.vhd @@ -1,8 +1,11 @@ +-- Description: +-- AXI_SLV Register Map for AXIS_AVG_BUFFER block + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity axi_slv is +entity axi_slv_avg_buf is Generic ( DATA_WIDTH : integer := 32; @@ -46,6 +49,9 @@ entity axi_slv is AVG_START_REG : out std_logic; AVG_ADDR_REG : out std_logic_vector (31 downto 0); AVG_LEN_REG : out std_logic_vector (31 downto 0); + AVG_PHOTON_MODE_REG : out std_logic; + AVG_H_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_L_THRSH_REG : out std_logic_vector (31 downto 0); AVG_DR_START_REG: out std_logic; AVG_DR_ADDR_REG : out std_logic_vector (31 downto 0); AVG_DR_LEN_REG : out std_logic_vector (31 downto 0); @@ -56,9 +62,9 @@ entity axi_slv is BUF_DR_ADDR_REG : out std_logic_vector (31 downto 0); BUF_DR_LEN_REG : out std_logic_vector (31 downto 0) ); -end axi_slv; +end axi_slv_avg_buf; -architecture rtl of axi_slv is +architecture rtl of axi_slv_avg_buf is -- AXI4LITE signals signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); @@ -529,6 +535,9 @@ begin BUF_DR_START_REG <= slv_reg9(0); BUF_DR_ADDR_REG <= slv_reg10; BUF_DR_LEN_REG <= slv_reg11; + AVG_PHOTON_MODE_REG <= slv_reg12(0); + AVG_H_THRSH_REG <= slv_reg13; + AVG_L_THRSH_REG <= slv_reg14; end rtl; diff --git a/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v b/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v index f891daac1..0bae358b9 100644 --- a/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v +++ b/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v @@ -1,12 +1,15 @@ -// AXIS AVG BUFFER. -// s_axi_aclk : clock for s_axi_* -// s_axis_aclk : clock for s_axis_* -// m_axis_aclk : clock for m0_axis_* and m1_axis_* +// Description: +// AXIS_AVG_BUFFER is a block that receives an input stream of samples (s_axis) and generates three output streams, one with processed averaged data (m0_axis) and one with raw captured data (m1_axis) and one with averaged data but prior to be stored in internal memory (sent to tProc register) (m2_axis) Captured samples are internally stored in PL memory. +// Capture is initiated by an external trigger after the buffer has been enabled. Number of captured samples and address where to store them are configurable. +// Output stream generation is controlled with a register where the address to start reading data and the number of samples can be configured. Output stream can be interfaced to an AXIS-DMA module +// +// Parameters: +// N_AVG & N_BUF: memory depth as 2**N; B: memory data width // module axis_avg_buffer ( // AXI Slave I/F for configuration. - s_axi_aclk , + s_axi_aclk , // clock for s_axi_* s_axi_aresetn , s_axi_awaddr , @@ -37,14 +40,14 @@ module axis_avg_buffer trigger , // AXIS Slave for input data. - s_axis_aclk , + s_axis_aclk , // clock for s_axis_* s_axis_aresetn , s_axis_tvalid , s_axis_tready , s_axis_tdata , // Reset and clock for m0 and m1. - m_axis_aclk , + m_axis_aclk , // clock for m0_axis_* and m1_axis_* and m2_axis_* m_axis_aresetn , // AXIS Master for averaged output. @@ -62,7 +65,7 @@ module axis_avg_buffer // AXIS Master for register output. m2_axis_tvalid , m2_axis_tready , - m2_axis_tdata + m2_axis_tdata ); /**************/ @@ -138,6 +141,9 @@ output [4*B-1:0] m2_axis_tdata; wire AVG_START_REG; wire [N_AVG-1:0] AVG_ADDR_REG; wire [31:0] AVG_LEN_REG; +wire AVG_PHOTON_MODE_REG; +wire [B-1:0] AVG_H_THRSH_REG; +wire [B-1:0] AVG_L_THRSH_REG; wire AVG_DR_START_REG; wire [N_AVG-1:0] AVG_DR_ADDR_REG; wire [N_AVG-1:0] AVG_DR_LEN_REG; @@ -152,8 +158,10 @@ wire [N_BUF-1:0] BUF_DR_LEN_REG; /**********************/ /* Begin Architecture */ /**********************/ +// `uselib lib=lib_axis_avg_buffer // AXI Slave. -axi_slv axi_slv_i +// axi_slv axi_slv_i +axi_slv_avg_buf axi_slv_i ( .aclk (s_axi_aclk ), .aresetn (s_axi_aresetn ), @@ -191,6 +199,9 @@ axi_slv axi_slv_i .AVG_START_REG (AVG_START_REG ), .AVG_ADDR_REG (AVG_ADDR_REG ), .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), .AVG_DR_START_REG (AVG_DR_START_REG ), .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), @@ -248,6 +259,9 @@ avg_buffer .AVG_START_REG (AVG_START_REG ), .AVG_ADDR_REG (AVG_ADDR_REG ), .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), .AVG_DR_START_REG (AVG_DR_START_REG ), .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), diff --git a/firmware/ip/axis_avg_buffer/src/buffer.sv b/firmware/ip/axis_avg_buffer/src/buffer.sv index 6606de7d3..57f63a40a 100644 --- a/firmware/ip/axis_avg_buffer/src/buffer.sv +++ b/firmware/ip/axis_avg_buffer/src/buffer.sv @@ -1,3 +1,11 @@ +// Description: +// BUFFER block is a FSM that receives an input stream of samples (din), and controls the interface to a memory to capture and store them. +// Capturing is initiated by an external trigger after the buffer has been enabled. Number of captured samples and address where to store them are configurable. +// When number of captured samples is reached, it can be triggered again. +// +// Parameters: +// N: memory depth as 2**N; B: memory data width + // Data is I,Q. // I: lower B bits. // Q: upper B bits. @@ -10,6 +18,7 @@ module buffer ( trigger_i , // Data input. + din_valid_i , din_i , // Memory interface. @@ -40,6 +49,7 @@ input clk; input trigger_i; +input din_valid_i; input [2*B-1:0] din_i; output mem_we_o; @@ -109,7 +119,7 @@ always @(posedge clk) begin state <= MEMW_ST; MEMW_ST: - if ( cnt == len_r-1 ) + if ( cnt == len_r && din_valid_i == 1'b1 ) state <= WAIT_TRIGGER_ST; WAIT_TRIGGER_ST: @@ -121,17 +131,20 @@ always @(posedge clk) begin endcase // Counter. - if ( memw_state == 1'b1 ) - cnt <= cnt + 1; - else + if ( memw_state == 1'b1 ) begin + if (din_valid_i == 1'b1) + cnt <= cnt + 1; + end + else begin cnt <= 0; + end // Registers. if ( start_state == 1'b1 ) begin addr_r <= ADDR_REG; - len_r <= LEN_REG; + len_r <= LEN_REG - 1; end - else if ( memw_state == 1'b1 ) begin + else if ( memw_state == 1'b1 && din_valid_i == 1'b1) begin addr_r <= addr_r + 1; end end @@ -161,7 +174,7 @@ always_comb begin end // Assign outputs. -assign mem_we_o = memw_state; +assign mem_we_o = memw_state & din_valid_i; assign mem_addr_o = addr_r; assign mem_di_o = din_i; diff --git a/firmware/ip/axis_avg_buffer/src/buffer_top.v b/firmware/ip/axis_avg_buffer/src/buffer_top.v index b9af09fab..497062e2a 100644 --- a/firmware/ip/axis_avg_buffer/src/buffer_top.v +++ b/firmware/ip/axis_avg_buffer/src/buffer_top.v @@ -1,3 +1,12 @@ +// Description: +// BUFFER_TOP block receives an input stream of samples (s_axis), captures and stores them in an internal memory when indicated and generates one output stream with raw captured data (m_axis) +// Capturing flow is controlled by the BUFFER FSM block and is initiated by an external trigger after the buffer has been enabled. Number of captured samples and address where to store them are configurable. +// Captured samples are internally stored in BRAM memory. +// Output stream is generated and controlled from the DATA_READER FSM block. Address to start reading and number of samples are configurable. It can be interfaced with an AXIS DMA module. +// +// Parameters: +// N: memory depth as 2**N; B: memory data width +// module buffer_top ( // Reset and clock. rstn , @@ -7,6 +16,7 @@ module buffer_top ( trigger_i , // Data input. + din_valid_i , din_i , // AXIS Master for output. @@ -43,6 +53,7 @@ input clk; input trigger_i; +input din_valid_i; input [2*B-1:0] din_i; input m_axis_aclk; @@ -106,27 +117,29 @@ buffer buffer_i ( // Reset and clock. - .rstn (rstn ), - .clk (clk ), + .rstn (rstn ), + .clk (clk ), // Trigger input. - .trigger_i (trigger_i ), + .trigger_i (trigger_i ), // Data input. - .din_i (din_i ), + .din_valid_i (din_valid_i ), + .din_i (din_i ), // Memory interface. - .mem_we_o (mem_we_int ), - .mem_addr_o (mem_addra_int ), - .mem_di_o (mem_di_int ), + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), // Registers. - .START_REG (BUF_START_REG_resync ), - .ADDR_REG (BUF_ADDR_REG ), - .LEN_REG (BUF_LEN_REG ) + .START_REG (BUF_START_REG_resync ), + .ADDR_REG (BUF_ADDR_REG ), + .LEN_REG (BUF_LEN_REG ) ); // Dual port BRAM. +// BRAM depth is 2**N. BRAM word with is B. bram_dp #( .N (N ), diff --git a/firmware/ip/axis_avg_buffer/src/data_reader.vhd b/firmware/ip/axis_avg_buffer/src/data_reader.vhd index a566ef51f..fa640f235 100644 --- a/firmware/ip/axis_avg_buffer/src/data_reader.vhd +++ b/firmware/ip/axis_avg_buffer/src/data_reader.vhd @@ -4,36 +4,36 @@ use IEEE.MATH_REAL.ALL; use IEEE.NUMERIC_STD.ALL; entity data_reader is - Generic - ( - -- Address map of memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - rstn : in std_logic; - clk : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_dout : in std_logic_vector (B-1 downto 0); - - -- Data out. - dout : out std_logic_vector (B-1 downto 0); - dready : in std_logic; - dvalid : out std_logic; - dlast : out std_logic; - - -- Registers. - START_REG : in std_logic; - ADDR_REG : in std_logic_vector (N-1 downto 0); - LEN_REG : in std_logic_vector (N-1 downto 0) - ); + Generic + ( + -- Address map of memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic; + ADDR_REG : in std_logic_vector (N-1 downto 0); + LEN_REG : in std_logic_vector (N-1 downto 0) + ); end entity; architecture rtl of data_reader is @@ -42,250 +42,251 @@ constant NPOW : Integer := 2**N; -- Fifo to drive AXI Stream Master I/F. component fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); end component; -type fsm_state is ( INIT_ST, - REGS_ST, - READ_ST, - WRITE_ST, - READ_LAST_ST, - WRITE_LAST_ST, - FIFO_ST, - END_ST); +type fsm_state is ( INIT_ST, + REGS_ST, + READ_BRAM_ST, + WRITE_FIFO_ST, + -- READ_LAST_ST, + -- WRITE_LAST_ST, + FIFO_ST, + END_ST); signal current_state, next_state : fsm_state; signal init_state : std_logic; -signal regs_state : std_logic; +signal regs_state : std_logic; signal read_state : std_logic; signal write_state : std_logic; signal fifo_state : std_logic; signal read_en : std_logic; -- Counter for memory address and samples. -signal cnt : unsigned(N-1 downto 0); -signal addr_cnt : unsigned(N-1 downto 0); +signal cnt_wr : unsigned(N-1 downto 0); +signal cnt_rd : unsigned(N-1 downto 0); +signal addr_cnt : unsigned(N-1 downto 0); -- Length register. -signal len_r : unsigned(N-1 downto 0); +signal len_r : unsigned(N-1 downto 0); -- Fifo signals. signal fifo_wr_en : std_logic; signal fifo_rd_en : std_logic; signal fifo_din : std_logic_vector (B-1 downto 0); signal fifo_dout : std_logic_vector (B-1 downto 0); -signal fifo_full : std_logic; +signal fifo_full : std_logic; signal fifo_empty : std_logic; --- Fifof pipeline. -signal fifo_dout_r : std_logic_vector (B-1 downto 0); -signal fifo_empty_r : std_logic; - -signal mem_dout_r : std_logic_vector (B-1 downto 0); - -signal dlast_i : std_logic; +-- Fifo pipeline. +-- signal fifo_dout_r : std_logic_vector (B-1 downto 0); +-- signal fifo_empty_r : std_logic; begin -- Fifo to drive AXI Stream Master I/F. fifo_i : fifo_axi - Generic map - ( - -- Data width. - B => B , - - -- Fifo depth. - N => 4 - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => fifo_wr_en , - din => fifo_din , - - -- Read I/F. - rd_en => fifo_rd_en , - dout => fifo_dout , - - -- Flags. - full => fifo_full , - empty => fifo_empty - ); - --- Fifo connections. -fifo_wr_en <= write_state; -fifo_din <= mem_dout_r; -fifo_rd_en <= dready when read_en = '1' else - '0'; - --- dlast generation. -dlast_i <= fifo_state and fifo_empty; + Generic map + ( + -- Data width. + B => B , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => fifo_wr_en , + din => fifo_din , + + -- Read I/F. + rd_en => fifo_rd_en , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections - write +fifo_wr_en <= write_state and not fifo_full; +fifo_din <= mem_dout; + +-- Fifo connections - read +fifo_rd_en <= read_en and not fifo_empty and dready; process(clk) begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- State register. - current_state <= INIT_ST; - - -- Counter for memory address and samples. - cnt <= (others => '0'); - addr_cnt <= (others => '0'); - mem_dout_r <= (others => '0'); - - -- Length register. - len_r <= (others => '0'); - - -- Fifo pipeline. - fifo_dout_r <= (others => '0'); - fifo_empty_r <= '1'; - else - -- State register. - current_state <= next_state; - - -- Memory address and data. - if ( init_state = '1' ) then - mem_dout_r <= (others => '0'); - cnt <= (others => '0'); - addr_cnt <= (others => '0'); - len_r <= (others => '0'); - elsif ( regs_state = '1' ) then - cnt <= (others => '0'); - addr_cnt <= unsigned(ADDR_REG); - len_r <= unsigned(LEN_REG); - elsif ( read_state = '1' ) then - mem_dout_r <= mem_dout; - cnt <= cnt + 1; - addr_cnt <= addr_cnt + 1; - end if; - - -- Fifo pipeline. - if ( dready = '1' ) then - fifo_dout_r <= fifo_dout; - fifo_empty_r <= fifo_empty; - end if; - end if; - end if; + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counter for memory address and samples. + cnt_wr <= (others => '0'); + cnt_rd <= (others => '0'); + addr_cnt <= (others => '0'); + + -- Length register. + len_r <= (others => '0'); + + -- Fifo pipeline. + -- fifo_dout_r <= (others => '0'); + -- fifo_empty_r <= '1'; + else + -- State register. + current_state <= next_state; + + -- Memory address and data. + if ( init_state = '1' ) then + cnt_wr <= (others => '0'); + addr_cnt <= (others => '0'); + len_r <= (others => '0'); + elsif ( regs_state = '1' ) then + cnt_wr <= (others => '0'); + addr_cnt <= unsigned(ADDR_REG); + len_r <= unsigned(LEN_REG); + cnt_rd <= unsigned(LEN_REG)-1; + end if; + if ( read_state = '1' ) then + cnt_wr <= cnt_wr + 1; + end if; + if ( fifo_rd_en = '1' ) then + cnt_rd <= cnt_rd - 1; + end if; + if ( write_state = '1' and fifo_full = '0') then + addr_cnt <= addr_cnt + 1; + end if; + + -- Fifo pipeline. + -- if ( dready = '1' ) then + -- fifo_dout_r <= fifo_dout; + -- fifo_empty_r <= fifo_empty; + -- end if; + + end if; + end if; end process; -- Next state logic. -process (current_state, START_REG, len_r, cnt, addr_cnt, fifo_full, fifo_empty, dready) +process (current_state, START_REG, len_r, cnt_wr, fifo_full, cnt_rd, fifo_rd_en) begin - case current_state is - when INIT_ST => - if (START_REG = '0') then - next_state <= INIT_ST; - else - next_state <= REGS_ST; - end if; - - when REGS_ST => - next_state <= READ_ST; - - when READ_ST => - next_state <= WRITE_ST; - - when WRITE_ST => - if ( fifo_full = '1' ) then - next_state <= WRITE_ST; - elsif ( cnt < len_r-1 ) then - next_state <= READ_ST; - else - next_state <= READ_LAST_ST; - end if; - - when READ_LAST_ST => - next_state <= WRITE_LAST_ST; - - when WRITE_LAST_ST => - if ( fifo_full = '1' ) then - next_state <= WRITE_LAST_ST; - else - next_state <= FIFO_ST; - end if; - - when FIFO_ST => - if ( fifo_empty = '1' and dready = '1' ) then - next_state <= END_ST; - else - next_state <= FIFO_ST; - end if; - - when END_ST => - if ( START_REG = '1' ) then - next_state <= END_ST; - else - next_state <= INIT_ST; - end if; - end case; + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= REGS_ST; + end if; + + when REGS_ST => + next_state <= READ_BRAM_ST; + + when READ_BRAM_ST => + next_state <= WRITE_FIFO_ST; + + when WRITE_FIFO_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_FIFO_ST; + elsif ( cnt_wr < len_r ) then + next_state <= READ_BRAM_ST; + else + next_state <= FIFO_ST; + end if; + + -- when READ_LAST_ST => + -- next_state <= WRITE_LAST_ST; + + -- when WRITE_LAST_ST => + -- if ( fifo_full = '1' ) then + -- next_state <= WRITE_LAST_ST; + -- else + -- next_state <= FIFO_ST; + -- end if; + + when FIFO_ST => + if ( cnt_rd = 0 and fifo_rd_en = '1' ) then + next_state <= END_ST; + else + next_state <= FIFO_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; end process; -- Output logic. process (current_state) begin -init_state <= '0'; -regs_state <= '0'; -read_state <= '0'; -write_state <= '0'; -fifo_state <= '0'; -read_en <= '0'; - case current_state is - when INIT_ST => - init_state <= '1'; - - when REGS_ST => - regs_state <= '1'; - - when READ_ST => - read_state <= '1'; - read_en <= '1'; - - when WRITE_ST => - write_state <= '1'; - read_en <= '1'; - - when READ_LAST_ST => - read_state <= '1'; - read_en <= '1'; - - when WRITE_LAST_ST => - write_state <= '1'; - read_en <= '1'; - - when FIFO_ST => - fifo_state <= '1'; - read_en <= '1'; - - when END_ST => - - end case; + init_state <= '0'; + regs_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when REGS_ST => + regs_state <= '1'; + + when READ_BRAM_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_FIFO_ST => + write_state <= '1'; + read_en <= '1'; + + -- when READ_LAST_ST => + -- read_state <= '1'; + -- read_en <= '1'; + + -- when WRITE_LAST_ST => + -- write_state <= '1'; + -- read_en <= '1'; + + when FIFO_ST => + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + + end case; end process; -- Assign outputs. @@ -293,8 +294,8 @@ mem_en <= '1'; mem_we <= '0'; mem_addr <= std_logic_vector(addr_cnt); -dout <= fifo_dout_r; -dvalid <= not(fifo_empty_r); -dlast <= dlast_i; +dout <= fifo_dout; +dvalid <= fifo_rd_en and dready; +dlast <= '1' when (cnt_rd = 0) else '0'; --fifo_state and fifo_empty; end rtl; diff --git a/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd index 2fbb69667..ff87e9d21 100644 --- a/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd +++ b/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd @@ -29,6 +29,9 @@ architecture rtl of synchronizer_vect is type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); signal data_int_reg : reg_t; +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd b/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd index 925425de9..a29bd9be1 100644 --- a/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd +++ b/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd @@ -22,6 +22,9 @@ architecture rtl of synchronizer_n is -- Internal register. signal data_int_reg : std_logic_vector (N-1 downto 0); +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_avg_buffer/src/tb/tb.sv b/firmware/ip/axis_avg_buffer/src/tb/tb.sv index be78bacc9..f4af6a8d5 100644 --- a/firmware/ip/axis_avg_buffer/src/tb/tb.sv +++ b/firmware/ip/axis_avg_buffer/src/tb/tb.sv @@ -242,7 +242,7 @@ initial begin // Start sending input data. tb_input <= 1; - trigger_gen(5,1280); + trigger_gen(5,4*1280); wait (tb_input_done); @@ -316,7 +316,7 @@ initial begin int fd; int vali, valq; - s_axis_tvalid <= 1; + s_axis_tvalid <= 0; s_axis_tdata <= 0; tb_input_done <= 0; @@ -327,8 +327,13 @@ initial begin while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin $display("Time %t: I = %d, Q = %d", $time, vali, valq); @(posedge s_axis_aclk); + s_axis_tvalid <= 1; s_axis_tdata[0 +: 16] <= vali; s_axis_tdata[16 +: 16] <= valq; + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + @(posedge s_axis_aclk); + @(posedge s_axis_aclk); end @(posedge s_axis_aclk); diff --git a/firmware/ip/axis_avg_buffer/src/tb/tb_avg_buffer.sv b/firmware/ip/axis_avg_buffer/src/tb/tb_avg_buffer.sv index 07af33cee..1bc097a5c 100644 --- a/firmware/ip/axis_avg_buffer/src/tb/tb_avg_buffer.sv +++ b/firmware/ip/axis_avg_buffer/src/tb/tb_avg_buffer.sv @@ -8,186 +8,201 @@ parameter N_BUF = 10; parameter B = 16; // Ports. -reg s_axis_aclk; -reg s_axis_aresetn; - -reg trigger; - -reg s_axis_tvalid; -wire s_axis_tready; -reg [2*B-1:0] s_axis_tdata; - -reg m_axis_aclk; -reg m_axis_aresetn; - -wire m0_axis_tvalid; -reg m0_axis_tready; -wire [4*B-1:0] m0_axis_tdata; -wire m0_axis_tlast; - -wire m1_axis_tvalid; -reg m1_axis_tready; -wire [2*B-1:0] m1_axis_tdata; -wire m1_axis_tlast; - -reg AVG_START_REG; -reg [N_AVG-1:0] AVG_ADDR_REG; -reg [N_AVG-1:0] AVG_LEN_REG; -reg AVG_DR_START_REG; -reg [N_AVG-1:0] AVG_DR_ADDR_REG; -reg [N_AVG-1:0] AVG_DR_LEN_REG; -reg BUF_START_REG; -reg [N_BUF-1:0] BUF_ADDR_REG; -reg [N_BUF-1:0] BUF_LEN_REG; -reg BUF_DR_START_REG; -reg [N_BUF-1:0] BUF_DR_ADDR_REG; -reg [N_BUF-1:0] BUF_DR_LEN_REG; +reg s_axis_aclk; +reg s_axis_aresetn; + +reg trigger; + +reg s_axis_tvalid; +wire s_axis_tready; +reg [2*B-1:0] s_axis_tdata; + +reg m_axis_aclk; +reg m_axis_aresetn; + +wire m0_axis_tvalid; +reg m0_axis_tready; +wire [4*B-1:0] m0_axis_tdata; +wire m0_axis_tlast; + +wire m1_axis_tvalid; +reg m1_axis_tready; +wire [2*B-1:0] m1_axis_tdata; +wire m1_axis_tlast; + +reg AVG_START_REG; +reg [N_AVG-1:0] AVG_ADDR_REG; +reg [31:0] AVG_LEN_REG; +reg AVG_DR_START_REG; +reg [N_AVG-1:0] AVG_DR_ADDR_REG; +reg [N_AVG-1:0] AVG_DR_LEN_REG; +reg BUF_START_REG; +reg [N_BUF-1:0] BUF_ADDR_REG; +reg [N_BUF-1:0] BUF_LEN_REG; +reg BUF_DR_START_REG; +reg [N_BUF-1:0] BUF_DR_ADDR_REG; +reg [N_BUF-1:0] BUF_DR_LEN_REG; +reg [N_BUF-1:0] DEBUG_REG; // Input data. -reg [B-1:0] di_r,dq_r; +reg [B-1:0] di_r,dq_r; // DUT. avg_buffer - #( - .N_AVG (N_AVG ), - .N_BUF (N_BUF ), - .B (B ) - ) - DUT - ( - // Reset and clock for s. - .s_axis_aclk (s_axis_aclk ), - .s_axis_aresetn (s_axis_aresetn ), - - // Trigger input. - .trigger (trigger ), - - // AXIS Slave for input data. - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - .s_axis_tdata (s_axis_tdata ), - - // Reset and clock for m0 and m1. - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - - // AXIS Master for averaged output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tdata (m0_axis_tdata ), - .m0_axis_tlast (m0_axis_tlast ), - - // AXIS Master for raw output. - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tdata (m1_axis_tdata ), - .m1_axis_tlast (m1_axis_tlast ), - - // Registers. - .AVG_START_REG (AVG_START_REG ), - .AVG_ADDR_REG (AVG_ADDR_REG ), - .AVG_LEN_REG (AVG_LEN_REG ), - .AVG_DR_START_REG (AVG_DR_START_REG ), - .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), - .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), - .BUF_START_REG (BUF_START_REG ), - .BUF_ADDR_REG (BUF_ADDR_REG ), - .BUF_LEN_REG (BUF_LEN_REG ), - .BUF_DR_START_REG (BUF_DR_START_REG ), - .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), - .BUF_DR_LEN_REG (BUF_DR_LEN_REG ) - ); + #( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .B (B ) + ) + DUT + ( + // Reset and clock for s. + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG ('d0 ), + .AVG_H_THRSH_REG ('d0 ), + .AVG_L_THRSH_REG ('d0 ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG )/*, + .DEBUG_REG (DEBUG_REG )*/ + ); assign s_axis_tdata = {dq_r,di_r}; initial begin - s_axis_aresetn <= 0; - trigger <= 0; - s_axis_tvalid <= 1; - di_r <= 0; - dq_r <= 0; - AVG_START_REG <= 0; - AVG_ADDR_REG <= 0; - AVG_LEN_REG <= 0; - BUF_START_REG <= 0; - BUF_ADDR_REG <= 0; - BUF_LEN_REG <= 0; - #200; - s_axis_aresetn <= 1; - - #200; - - @(posedge s_axis_aclk); - AVG_ADDR_REG <= 0; - AVG_LEN_REG <= 10; - BUF_ADDR_REG <= 0; - BUF_LEN_REG <= 10; - - #200; - - @(posedge s_axis_aclk); - AVG_START_REG <= 1; - BUF_START_REG <= 1; - - #1000; - - for (int i=0; i<10; i = i + 1) begin - @(posedge s_axis_aclk); - di_r <= 2*i; - dq_r <= -5*i; - trigger <= 1; - @(posedge s_axis_aclk); - trigger <= 0; - - #1000; - end - - @(posedge s_axis_aclk); - AVG_START_REG <= 0; - BUF_START_REG <= 0; - - #10000; + s_axis_aresetn <= 0; + trigger <= 0; + s_axis_tvalid <= 0; + di_r <= 0; + dq_r <= 0; + AVG_START_REG <= 0; + AVG_ADDR_REG <= 0; + AVG_LEN_REG <= 0; + BUF_START_REG <= 0; + BUF_ADDR_REG <= 0; + BUF_LEN_REG <= 0; + #200; + s_axis_aresetn <= 1; + + #200; + + @(posedge s_axis_aclk); + AVG_ADDR_REG <= 5; + AVG_LEN_REG <= 10; + BUF_ADDR_REG <= 0; + BUF_LEN_REG <= 10; + + #200; + + @(posedge s_axis_aclk); + AVG_START_REG <= 1; + BUF_START_REG <= 1; + + #1000; + + s_axis_tvalid <= 1; + + for (int i=1; i<=10; i = i + 1) begin + @(posedge s_axis_aclk); + di_r <= i; + dq_r <= -i; + trigger <= 1; + @(posedge s_axis_aclk); + trigger <= 0; + + #1000; + end + + @(posedge s_axis_aclk); + AVG_START_REG <= 0; + BUF_START_REG <= 0; + + #10000; + + $finish(); end initial begin - m_axis_aresetn <= 0; - m0_axis_tready <= 1; - m1_axis_tready <= 1; - AVG_DR_START_REG <= 0; - AVG_DR_ADDR_REG <= 0; - AVG_DR_LEN_REG <= 0; - BUF_DR_START_REG <= 0; - BUF_DR_ADDR_REG <= 0; - BUF_DR_LEN_REG <= 0; - #200; - m_axis_aresetn <= 1; - - #20000; - - @(posedge m_axis_aclk); - AVG_DR_ADDR_REG <= 0; - AVG_DR_LEN_REG <= 10; - BUF_DR_ADDR_REG <= 0; - BUF_DR_LEN_REG <= 100; - - @(posedge m_axis_aclk); - AVG_DR_START_REG <= 1; - BUF_DR_START_REG <= 1; + m_axis_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + AVG_DR_START_REG <= 0; + AVG_DR_ADDR_REG <= 0; + AVG_DR_LEN_REG <= 0; + BUF_DR_START_REG <= 0; + BUF_DR_ADDR_REG <= 0; + BUF_DR_LEN_REG <= 0; + DEBUG_REG <= 0; + #200; + m_axis_aresetn <= 1; + + #20000; + + @(posedge m_axis_aclk); + AVG_DR_ADDR_REG <= 5; + AVG_DR_LEN_REG <= 7; + BUF_DR_ADDR_REG <= 0; + BUF_DR_LEN_REG <= 100; + + @(posedge m_axis_aclk); + AVG_DR_START_REG <= 1; + BUF_DR_START_REG <= 1; + + for (int i=1; i<=100; i = i + 1) begin + @(posedge m_axis_aclk); + m0_axis_tready <= i[3:0] <= 4; + end end always begin - s_axis_aclk <= 0; - #15; - s_axis_aclk <= 1; - #15; + s_axis_aclk <= 0; + #15; + s_axis_aclk <= 1; + #15; end always begin - m_axis_aclk <= 0; - #4; - m_axis_aclk <= 1; - #4; + m_axis_aclk <= 0; + #4; + m_axis_aclk <= 1; + #4; end endmodule diff --git a/firmware/ip/axis_avg_buffer/src/tb/tb_waves.wcfg b/firmware/ip/axis_avg_buffer/src/tb/tb_waves.wcfg new file mode 100644 index 000000000..0a396ec4c --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/tb/tb_waves.wcfg @@ -0,0 +1,673 @@ + + + + + + + + + + + + + + + + + + + + + + + + Input AXIS + label + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_tvalid + s_axis_tvalid + #FFFF00 + true + + + s_axis_tdata[31:0] + s_axis_tdata[31:0] + #FFFF00 + true + + + s_axis_tdata_imag + label + SIGNEDDECRADIX + #FFFF00 + true + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + + s_axis_tdata_real + label + SIGNEDDECRADIX + #FFFF00 + true + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + + trigger + trigger + + + AVG_FSM + label + + AVG_START_REG + AVG_START_REG + + + AVG_ADDR_REG[9:0] + AVG_ADDR_REG[9:0] + + + AVG_LEN_REG[31:0] + AVG_LEN_REG[31:0] + + + state[31:0] + state[31:0] + + + cnt[31:0] + cnt[31:0] + UNSIGNEDDECRADIX + + + mem_we_o + mem_we_o + + + mem_addr_o[9:0] + mem_addr_o[9:0] + + + mem_di_o[63:0] + mem_di_o[63:0] + + + + AVG_MEMORY + label + + clka + clka + + + clkb + clkb + + + wea + wea + + + web + web + + + addra[9:0] + addra[9:0] + UNSIGNEDDECRADIX + + + addrb[9:0] + addrb[9:0] + UNSIGNEDDECRADIX + + + dia[63:0] + dia[63:0] + + + doa[63:0] + doa[63:0] + + + dob[63:0] + dob[63:0] + + + + DATA_READ_FSM + label + + + START_REG + START_REG + + + ADDR_REG[9:0] + ADDR_REG[9:0] + + + LEN_REG[9:0] + LEN_REG[9:0] + UNSIGNEDDECRADIX + #FFFF00 + true + + + current_state + current_state + + + mem_en + mem_en + + + mem_we + mem_we + + + mem_addr[9:0] + mem_addr[9:0] + UNSIGNEDDECRADIX + + + mem_dout[63:0] + mem_dout[63:0] + + + fifo_wr_en + fifo_wr_en + + + fifo_din[63:0] + fifo_din[63:0] + + + dready + dready + #00FFFF + true + + + dvalid + dvalid + #00FFFF + true + + + dout[63:0] + dout[63:0] + #00FFFF + true + + + dout_imag + label + SIGNEDDECRADIX + #00FFFF + true + + [63] + [63] + + + [62] + [62] + + + [61] + [61] + + + [60] + [60] + + + [59] + [59] + + + [58] + [58] + + + [57] + [57] + + + [56] + [56] + + + [55] + [55] + + + [54] + [54] + + + [53] + [53] + + + [52] + [52] + + + [51] + [51] + + + [50] + [50] + + + [49] + [49] + + + [48] + [48] + + + [47] + [47] + + + [46] + [46] + + + [45] + [45] + + + [44] + [44] + + + [43] + [43] + + + [42] + [42] + + + [41] + [41] + + + [40] + [40] + + + [39] + [39] + + + [38] + [38] + + + [37] + [37] + + + [36] + [36] + + + [35] + [35] + + + [34] + [34] + + + [33] + [33] + + + [32] + [32] + + + + dout_real + label + SIGNEDDECRADIX + #00FFFF + true + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + dlast + dlast + #00FFFF + true + + + + DATA_READ_FIFO + label + + + clk + clk + + + wr_en + wr_en + + + din[63:0] + din[63:0] + + + full + full + + + rd_en + rd_en + + + rd_en_i + rd_en_i + + + dout[63:0] + dout[63:0] + + + empty + empty + + + + cnt_wr[9:0] + cnt_wr[9:0] + UNSIGNEDDECRADIX + + + cnt_rd[9:0] + cnt_rd[9:0] + UNSIGNEDDECRADIX + + + addr_cnt[9:0] + addr_cnt[9:0] + UNSIGNEDDECRADIX + + + len_r[9:0] + len_r[9:0] + UNSIGNEDDECRADIX + + diff --git a/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_1.tcl b/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_1.tcl new file mode 100644 index 000000000..778e109f0 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_1.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N_AVG" -parent ${Page_0} + ipgui::add_param $IPINST -name "N_BUF" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N_AVG { PARAM_VALUE.N_AVG } { + # Procedure called to update N_AVG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_AVG { PARAM_VALUE.N_AVG } { + # Procedure called to validate N_AVG + return true +} + +proc update_PARAM_VALUE.N_BUF { PARAM_VALUE.N_BUF } { + # Procedure called to update N_BUF when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_BUF { PARAM_VALUE.N_BUF } { + # Procedure called to validate N_BUF + return true +} + + +proc update_MODELPARAM_VALUE.N_AVG { MODELPARAM_VALUE.N_AVG PARAM_VALUE.N_AVG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_AVG}] ${MODELPARAM_VALUE.N_AVG} +} + +proc update_MODELPARAM_VALUE.N_BUF { MODELPARAM_VALUE.N_BUF PARAM_VALUE.N_BUF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_BUF}] ${MODELPARAM_VALUE.N_BUF} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + diff --git a/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_2.tcl b/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_2.tcl new file mode 100644 index 000000000..778e109f0 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/xgui/axis_avg_buffer_v1_2.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N_AVG" -parent ${Page_0} + ipgui::add_param $IPINST -name "N_BUF" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N_AVG { PARAM_VALUE.N_AVG } { + # Procedure called to update N_AVG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_AVG { PARAM_VALUE.N_AVG } { + # Procedure called to validate N_AVG + return true +} + +proc update_PARAM_VALUE.N_BUF { PARAM_VALUE.N_BUF } { + # Procedure called to update N_BUF when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_BUF { PARAM_VALUE.N_BUF } { + # Procedure called to validate N_BUF + return true +} + + +proc update_MODELPARAM_VALUE.N_AVG { MODELPARAM_VALUE.N_AVG PARAM_VALUE.N_AVG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_AVG}] ${MODELPARAM_VALUE.N_AVG} +} + +proc update_MODELPARAM_VALUE.N_BUF { MODELPARAM_VALUE.N_BUF PARAM_VALUE.N_BUF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_BUF}] ${MODELPARAM_VALUE.N_BUF} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + diff --git a/firmware/ip/axis_buffer_ddr/component.xml b/firmware/ip/axis_buffer_ddr/component.xml new file mode 100644 index 000000000..9e60fb1d9 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/component.xml @@ -0,0 +1,2265 @@ + + + QICK + QICK + axis_buffer_ddr + 1.1 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TSTRB + + + m_axis_tstrb + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + m_axi + + + + + + + + + AWID + + + m_axi_awid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWLEN + + + m_axi_awlen + + + + + AWSIZE + + + m_axi_awsize + + + + + AWBURST + + + m_axi_awburst + + + + + AWLOCK + + + m_axi_awlock + + + + + AWCACHE + + + m_axi_awcache + + + + + AWPROT + + + m_axi_awprot + + + + + AWREGION + + + m_axi_awregion + + + + + AWQOS + + + m_axi_awqos + + + + + AWVALID + + + m_axi_awvalid + + + + + AWREADY + + + m_axi_awready + + + + + WDATA + + + m_axi_wdata + + + + + WSTRB + + + m_axi_wstrb + + + + + WLAST + + + m_axi_wlast + + + + + WVALID + + + m_axi_wvalid + + + + + WREADY + + + m_axi_wready + + + + + BID + + + m_axi_bid + + + + + BRESP + + + m_axi_bresp + + + + + BVALID + + + m_axi_bvalid + + + + + BREADY + + + m_axi_bready + + + + + ARID + + + m_axi_arid + + + + + ARADDR + + + m_axi_araddr + + + + + ARLEN + + + m_axi_arlen + + + + + ARSIZE + + + m_axi_arsize + + + + + ARBURST + + + m_axi_arburst + + + + + ARLOCK + + + m_axi_arlock + + + + + ARCACHE + + + m_axi_arcache + + + + + ARPROT + + + m_axi_arprot + + + + + ARREGION + + + m_axi_arregion + + + + + ARQOS + + + m_axi_arqos + + + + + ARVALID + + + m_axi_arvalid + + + + + ARREADY + + + m_axi_arready + + + + + RID + + + m_axi_rid + + + + + RDATA + + + m_axi_rdata + + + + + RRESP + + + m_axi_rresp + + + + + RLAST + + + m_axi_rlast + + + + + RVALID + + + m_axi_rvalid + + + + + RREADY + + + m_axi_rready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis:m_axi + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + m_axi + m_axi + 0x100000000 + 256 + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_buffer_ddr + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b03576f5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_buffer_ddr + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b03576f5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e2380ff4 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + b3deedbe + + + + + + + trigger + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mst_write_probe_dbg + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + mst_read_probe_dbg + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + TARGET_SLAVE_BASE_ADDR + Target Slave Base Addr + 0x40000000 + + + ID_WIDTH + Id Width + 1 + + + DATA_WIDTH + Data Width + 256 + + + BURST_SIZE + Burst Size + 15 + + + DEBUG + Debug + 0 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axi_slv.v + verilogSource + + + src/axi_mst.sv + systemVerilogSource + + + src/axi_mst_read.sv + systemVerilogSource + + + src/axi_mst_write.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_buffer_ddr.sv + systemVerilogSource + CHECKSUM_8ee2c571 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axi_slv.v + verilogSource + + + src/axi_mst.sv + systemVerilogSource + + + src/axi_mst_read.sv + systemVerilogSource + + + src/axi_mst_write.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_buffer_ddr.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_buffer_ddr_v1_1.tcl + tclSource + CHECKSUM_e2380ff4 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + + + src/tb/axi_slv_0/axi_slv_0.xci + xci + + + src/tb/axi_mst_0/axi_mst_0.xci + xci + USED_IN_simulation + USED_IN_testbench + + + src/tb/tb_axis_buffer_ddr_behav.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + + AXIS Buffer for DDR4 + + + TARGET_SLAVE_BASE_ADDR + Target Slave Base Addr + 0x40000000 + + + ID_WIDTH + Id Width + 1 + + + DATA_WIDTH + Data Width + 256 + + + Component_Name + axis_buffer_ddr_v1_v1_0 + + + BURST_SIZE + Burst Size + 15 + + + DEBUG + Debug + 0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /QICK/Miscellaneous + + AXIS Buffer DDR + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + + QICK:QICK:axis_buffer_ddr_v1:1.0 + + 2025-11-18T18:56:54Z + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/axis_buffer_ddr/src/axi_mst.sv b/firmware/ip/axis_buffer_ddr/src/axi_mst.sv new file mode 100644 index 000000000..02a2d9db6 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/axi_mst.sv @@ -0,0 +1,208 @@ +module axi_mst + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 512 , + parameter BURST_SIZE = 15 + ) + ( + // Trigger. + input wire trigger , + + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + input wire m_axi_aclk , + input wire m_axi_aresetn , + + // Write Address Channel. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + // Write Data Channel. + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + // Write Response Channel. + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // Read Address Channel. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + // Read Data Channel. + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // Registers. + input wire RSTART_REG , + input wire [31:0] RADDR_REG , + input wire [31:0] RLENGTH_REG , + input wire WSTART_REG , + input wire [31:0] WADDR_REG , + input wire [31:0] WNBURST_REG + ); + +/*************/ +/* Internals */ +/*************/ + + +/****************/ +/* Architecture */ +/****************/ + +// AXI Master Read. +axi_mst_read + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + axi_mst_read_i + ( + .clk (m_axi_aclk ), + .rstn (m_axi_aresetn ), + + // AXI Master Interface. + .m_axi_arid (m_axi_arid ), + .m_axi_araddr (m_axi_araddr ), + .m_axi_arlen (m_axi_arlen ), + .m_axi_arsize (m_axi_arsize ), + .m_axi_arburst (m_axi_arburst ), + .m_axi_arlock (m_axi_arlock ), + .m_axi_arcache (m_axi_arcache ), + .m_axi_arprot (m_axi_arprot ), + .m_axi_arregion (m_axi_arregion ), + .m_axi_arqos (m_axi_arqos ), + .m_axi_arvalid (m_axi_arvalid ), + .m_axi_arready (m_axi_arready ), + + .m_axi_rid (m_axi_rid ), + .m_axi_rdata (m_axi_rdata ), + .m_axi_rresp (m_axi_rresp ), + .m_axi_rlast (m_axi_rlast ), + .m_axi_rvalid (m_axi_rvalid ), + .m_axi_rready (m_axi_rready ), + + // AXIS Master Interfase. + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tstrb (m_axis_tstrb ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tready (m_axis_tready ), + + // Registers. + .START_REG (RSTART_REG ), + .ADDR_REG (RADDR_REG ), + .LENGTH_REG (RLENGTH_REG ) + ); + +// AXI Master Write. +axi_mst_write + #( + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .BURST_SIZE (BURST_SIZE ) + ) + axi_mst_write_i + ( + .clk (m_axi_aclk ), + .rstn (m_axi_aresetn ), + + // Trigger. + .trigger (trigger ), + + // AXI Master Interface. + .m_axi_awid (m_axi_awid ), + .m_axi_awaddr (m_axi_awaddr ), + .m_axi_awlen (m_axi_awlen ), + .m_axi_awsize (m_axi_awsize ), + .m_axi_awburst (m_axi_awburst ), + .m_axi_awlock (m_axi_awlock ), + .m_axi_awcache (m_axi_awcache ), + .m_axi_awprot (m_axi_awprot ), + .m_axi_awregion (m_axi_awregion ), + .m_axi_awqos (m_axi_awqos ), + .m_axi_awvalid (m_axi_awvalid ), + .m_axi_awready (m_axi_awready ), + + .m_axi_wdata (m_axi_wdata ), + .m_axi_wstrb (m_axi_wstrb ), + .m_axi_wlast (m_axi_wlast ), + .m_axi_wvalid (m_axi_wvalid ), + .m_axi_wready (m_axi_wready ), + + .m_axi_bid (m_axi_bid ), + .m_axi_bresp (m_axi_bresp ), + .m_axi_bvalid (m_axi_bvalid ), + .m_axi_bready (m_axi_bready ), + + // AXIS Slave Interfase. + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + .s_axis_tstrb (s_axis_tstrb ), + .s_axis_tlast (s_axis_tlast ), + .s_axis_tvalid (s_axis_tvalid ), + + // Registers. + .START_REG (WSTART_REG ), + .ADDR_REG (WADDR_REG ), + .NBURST_REG (WNBURST_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr/src/axi_mst_read.sv b/firmware/ip/axis_buffer_ddr/src/axi_mst_read.sv new file mode 100644 index 000000000..a10abb16d --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/axi_mst_read.sv @@ -0,0 +1,262 @@ +module axi_mst_read + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 512 + ) + ( + input wire rstn , + input wire clk , + + // AXI Master Interface. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + // AXIS Master Interfase. + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + // Registers. + input wire START_REG , + input wire [31:0] ADDR_REG , + input wire [31:0] LENGTH_REG , + + // Debug + output wire [31:0] mst_read_probe_dbg1 + ); + +/*************/ +/* Internals */ +/*************/ + +// Maximum burst size (4kB boundary). +localparam BYTES_PER_AXI_TRANSFER = DATA_WIDTH/8; +localparam MAX_BURST_SIZE = 4096/BYTES_PER_AXI_TRANSFER; + +// States. +typedef enum { INIT_ST , + START_ST , + READ_REGS_ST , + ADDR_ST , + DATA_ST , + END_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// FSM Signals. +reg read_regs_state ; + +// START_REG resync. +wire start_reg_resync ; + +// Registers. +reg [31:0] addr_reg_r ; +reg [31:0] len_reg_m1_r ; + +// Fifo. +wire fifo_full ; +wire fifo_empty ; + +// AXI Master. +reg axi_arvalid_i ; + +// Address. +wire [31:0] addr_base ; + +// Burst length. +wire [7:0] burst_length ; + +/****************/ +/* Architecture */ +/****************/ + +// start_reg_resync. +synchronizer_n start_reg_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_REG ), + .data_out (start_reg_resync ) + ); + +// Single-clock fifo. +fifo_axi + #( + // Data width. + .B (DATA_WIDTH ), + + // Fifo depth. + .N (64 ) + ) + fifo_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (m_axi_rvalid ), + .din (m_axi_rdata ), + + // Read I/F. + .rd_en (m_axis_tready ), + .dout (m_axis_tdata ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +assign m_axi_rready = ~fifo_full; +assign m_axis_tvalid = ~fifo_empty; + +// Burst lenth. +assign burst_length = len_reg_m1_r; + +// Base address. +assign addr_base = addr_reg_r; + +// Registers. +always @(posedge clk) begin + if (rstn == 1'b0) begin + // State register. + state <= INIT_ST; + + // Registers. + addr_reg_r <= 0; + len_reg_m1_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if (start_reg_resync == 1'b1) + state <= READ_REGS_ST; + + READ_REGS_ST: + state <= ADDR_ST; + + ADDR_ST: + if (m_axi_arready == 1'b1) + state <= DATA_ST; + + DATA_ST: + if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1 && fifo_full == 1'b0) + state <= END_ST; + + END_ST: + if (start_reg_resync == 1'b0) + state <= START_ST; + endcase + + // Registers. + if (read_regs_state == 1'b1) begin + addr_reg_r <= ADDR_REG + TARGET_SLAVE_BASE_ADDR; + len_reg_m1_r <= LENGTH_REG - 1; + end + + end +end + +// Read Address Channel. +// Same ID for all transactions (execute them in order). +assign m_axi_arid = 0; + +// Burst length (must substract 1). +assign m_axi_arlen = burst_length; + +// Size set to transfer complete data bits per beat (64 bytes/transfer). +assign m_axi_arsize = (BYTES_PER_AXI_TRANSFER == 1 )? 3'b000 : + (BYTES_PER_AXI_TRANSFER == 2 )? 3'b001 : + (BYTES_PER_AXI_TRANSFER == 4 )? 3'b010 : + (BYTES_PER_AXI_TRANSFER == 8 )? 3'b011 : + (BYTES_PER_AXI_TRANSFER == 16 )? 3'b100 : + (BYTES_PER_AXI_TRANSFER == 32 )? 3'b101 : + (BYTES_PER_AXI_TRANSFER == 64 )? 3'b110 : + (BYTES_PER_AXI_TRANSFER == 128 )? 3'b111 : + 3'b000 ; + +// Set arburst to INCR type. +assign m_axi_arburst = 2'b01; + +// Normal access. +assign m_axi_arlock = 1'b0; + +// Device Non-bufferable. +assign m_axi_arcache = 4'b0000; + +// Data, non-secure, unprivileged. +assign m_axi_arprot = 3'b010; + +// Not-used. +assign m_axi_arregion = 4'b0000; + +// Not-used qos. +assign m_axi_arqos = 4'b0000; + +// FSM outputs. +always_comb begin + // Default. + read_regs_state = 1'b0; + axi_arvalid_i = 1'b0; + + case (state) + //INIT_ST: + + //START_ST: + + READ_REGS_ST: + read_regs_state = 1'b1; + + ADDR_ST: + axi_arvalid_i = 1'b1; + + //DATA_ST: + + //END_ST: + + endcase +end + +// Assign outputs. +assign m_axi_araddr = addr_base; +assign m_axi_arvalid = axi_arvalid_i; + +assign m_axis_tstrb = '1; +assign m_axis_tlast = 1'b0; + + +// DEBUG + +assign mst_read_probe_dbg1[31:24] = {burst_length[7:0]}; +assign mst_read_probe_dbg1[23:16] = {3'b000, m_axi_rlast, m_axi_rvalid, m_axis_tready, fifo_full, fifo_empty}; +assign mst_read_probe_dbg1[15:8] = {7'b0000_000, start_reg_resync}; +assign mst_read_probe_dbg1[7:0] = {state}; + + +endmodule diff --git a/firmware/ip/axis_buffer_ddr/src/axi_mst_write.sv b/firmware/ip/axis_buffer_ddr/src/axi_mst_write.sv new file mode 100644 index 000000000..0a9be8aed --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/axi_mst_write.sv @@ -0,0 +1,369 @@ +module axi_mst_write + #( + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 32 , + parameter BURST_SIZE = 15 + ) + ( + input wire clk , + input wire rstn , + + // Trigger. + input wire trigger , + + // AXI Master Interface. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // AXIS Slave Interfase. + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // Registers. + input wire START_REG , + input wire [31:0] ADDR_REG , + input wire [31:0] NBURST_REG , + + // Debug + output wire [31:0] mst_write_probe_dbg1 + ); + +// Maximum burst size (4kB boundary). +localparam BYTES_PER_AXI_TRANSFER = DATA_WIDTH/8; +localparam MAX_BURST_SIZE = 4096/BYTES_PER_AXI_TRANSFER; +//localparam BURST_SIZE = (MAX_BURST_SIZE >= 256)? 255 : MAX_BURST_SIZE-1; +localparam BYTES_PER_BURST = (BURST_SIZE + 1)*BYTES_PER_AXI_TRANSFER; + +/*************/ +/* Internals */ +/*************/ + +// States. +typedef enum { INIT_ST , + TRIGGER_ST , + READ_REGS_ST , + INIT_ADDR_ST , + INCR_ADDR_ST , + ADDR_ST , + DATA_ST , + RESP_ST , + NBURST_ST , + END_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// FSM Signals. +reg read_regs_state ; +reg init_addr_state ; +reg incr_addr_state ; +reg addr_state ; +reg data_state ; +reg resp_state ; + +// trigger resync. +wire trigger_resync ; + +// START_REG resync. +wire start_reg_resync ; + +// Registers. +reg [31:0] addr_reg_r ; +reg [31:0] nburst_reg_r ; + +// Fifo signals. +wire fifo_wr_en ; +wire fifo_rd_en ; +wire [DATA_WIDTH-1:0] fifo_dout ; +reg [DATA_WIDTH-1:0] fifo_dout_r ; +wire fifo_full ; +wire fifo_empty ; +reg fifo_empty_r ; + +// Address generation. +wire [31:0] addr_base ; +wire [31:0] addr_acc ; +reg [31:0] addr_r ; + +// Burst counter. +reg [7:0] cnt_burst ; +reg [31:0] cnt_nburst ; + +/****************/ +/* Architecture */ +/****************/ + +// trigger_resync. +synchronizer_n trigger_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + +// start_reg_resync. +synchronizer_n start_reg_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_REG ), + .data_out (start_reg_resync ) + ); + +// Single-clock fifo. +fifo_axi + #( + // Data width. + .B (DATA_WIDTH ), + + // Fifo depth. + .N (64 ) + ) + fifo_in_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (s_axis_tdata ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +assign fifo_wr_en = s_axis_tvalid & (incr_addr_state | addr_state | data_state | resp_state); +assign fifo_rd_en = m_axi_wready & data_state || (state == END_ST); +assign s_axis_tready = ~fifo_full; + +// Write Address Channel. +// Same ID for all transactions (execute them in order). +assign m_axi_awid = 0; + +// Burst size (transactions). +assign m_axi_awlen = BURST_SIZE; + +// Size set to transfer complete data bits per beat. +assign m_axi_awsize = (BYTES_PER_AXI_TRANSFER == 1 )? 3'b000 : + (BYTES_PER_AXI_TRANSFER == 2 )? 3'b001 : + (BYTES_PER_AXI_TRANSFER == 4 )? 3'b010 : + (BYTES_PER_AXI_TRANSFER == 8 )? 3'b011 : + (BYTES_PER_AXI_TRANSFER == 16 )? 3'b100 : + (BYTES_PER_AXI_TRANSFER == 32 )? 3'b101 : + (BYTES_PER_AXI_TRANSFER == 64 )? 3'b110 : + (BYTES_PER_AXI_TRANSFER == 128 )? 3'b111 : + 3'b000 ; + +// Set arburst to INCR type. +assign m_axi_awburst = 2'b01; + +// Normal access. +assign m_axi_awlock = 1'b0; + +// Device Non-bufferable. +assign m_axi_awcache = 4'b0000; + +// Data, non-secure, unprivileged. +assign m_axi_awprot = 3'b010; + +// Not-used. +assign m_axi_awregion = 4'b0000; + +// Not-used qos. +assign m_axi_awqos = 4'b0000; + +// Write Data Channel. +// All bytes are written. +assign m_axi_wstrb = '1; + +// Address generation. +assign addr_base = TARGET_SLAVE_BASE_ADDR + addr_reg_r; +assign addr_acc = addr_r + BYTES_PER_BURST; + +// Registers. +always @(posedge clk) begin + if (rstn == 1'b0) begin + // State register. + state <= INIT_ST; + + // Registers. + addr_reg_r <= 0; + nburst_reg_r <= 0; + addr_r <= 0; + + // Fifo signals. + fifo_dout_r <= 0; + fifo_empty_r <= 1; + + // Burst counter. + cnt_burst <= 0; + cnt_nburst <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + if (start_reg_resync == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if (trigger_resync == 1'b1) + state <= READ_REGS_ST; + + READ_REGS_ST: + state <= INIT_ADDR_ST; + + INIT_ADDR_ST: + state <= ADDR_ST; + + INCR_ADDR_ST: + state <= ADDR_ST; + + ADDR_ST: + if (m_axi_awready == 1'b1) + state <= DATA_ST; + + DATA_ST: + if ( (m_axi_wready == 1'b1) && (m_axi_wvalid == 1'b1) && (cnt_burst == BURST_SIZE) ) + state <= RESP_ST; + + RESP_ST: + if (m_axi_bvalid == 1'b1) + state <= NBURST_ST; + + NBURST_ST: + if (cnt_nburst == nburst_reg_r) + state <= END_ST; + else + state <= INCR_ADDR_ST; + + END_ST: + if (start_reg_resync == 1'b0 && trigger_resync == 1'b0 && fifo_empty) + state <= INIT_ST; + + endcase + + // Registers. + if (read_regs_state == 1'b1) begin + addr_reg_r <= ADDR_REG; + nburst_reg_r <= NBURST_REG; + end + + // Address generation. + if (init_addr_state == 1'b1) + addr_r <= addr_base; + else if (incr_addr_state == 1'b1) + addr_r <= addr_acc; + + // Fifo signals. + if (fifo_rd_en == 1'b1) begin + fifo_dout_r <= fifo_dout; + fifo_empty_r <= fifo_empty; + end + + // Burst counter. + if (addr_state == 1'b1) + cnt_burst <= 0; + else if (m_axi_wvalid == 1'b1 && m_axi_wready == 1'b1) + cnt_burst <= cnt_burst + 1; + if (read_regs_state == 1'b1) + cnt_nburst <= 0; + else if (m_axi_bvalid == 1'b1 && m_axi_bready == 1'b1) + cnt_nburst <= cnt_nburst + 1; + end +end + +// FSM outputs. +always_comb begin + // Default. + read_regs_state = 1'b0; + init_addr_state = 1'b0; + incr_addr_state = 1'b0; + addr_state = 1'b0; + data_state = 1'b0; + resp_state = 1'b0; + + case (state) + //INIT_ST: + + //TRIGGER_ST: + + READ_REGS_ST: + read_regs_state = 1'b1; + + INIT_ADDR_ST: + init_addr_state = 1'b1; + + INCR_ADDR_ST: + incr_addr_state = 1'b1; + + ADDR_ST: + addr_state = 1'b1; + + DATA_ST: + data_state = 1'b1; + + RESP_ST: + resp_state = 1'b1; + + //NBURST_ST: + + // TRIGGER_END_ST: + + //END_ST: + + endcase +end + +// Assign outputs. +assign m_axi_awaddr = addr_r; +assign m_axi_awvalid = addr_state; + +assign m_axi_wdata = fifo_dout_r; +assign m_axi_wlast = (cnt_burst == BURST_SIZE)? 1'b1 : 1'b0; +assign m_axi_wvalid = ~fifo_empty_r & data_state; + +assign m_axi_bready = resp_state; + + +// DEBUG + +assign mst_write_probe_dbg1[31:24] = {cnt_burst[7:0]}; +assign mst_write_probe_dbg1[23:16] = {cnt_nburst[3:0], fifo_rd_en, fifo_full, s_axis_tvalid, fifo_empty}; +assign mst_write_probe_dbg1[15:11] = {3'b000, trigger_resync, start_reg_resync}; +assign mst_write_probe_dbg1[10:0] = {state}; + +endmodule diff --git a/firmware/ip/axis_buffer_ddr/src/axi_slv.v b/firmware/ip/axis_buffer_ddr/src/axi_slv.v new file mode 100644 index 000000000..0c5696602 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/axi_slv.v @@ -0,0 +1,1032 @@ +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire RSTART_REG , + output wire [31:0] RADDR_REG , + output wire [31:0] RLENGTH_REG , + output wire WSTART_REG , + output wire [31:0] WADDR_REG , + output wire [31:0] WNBURST_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign RSTART_REG = slv_reg0 [0]; +assign RADDR_REG = slv_reg1 [31:0]; +assign RLENGTH_REG = slv_reg2 [31:0]; +assign WSTART_REG = slv_reg3 [0]; +assign WADDR_REG = slv_reg4 [31:0]; +assign WNBURST_REG = slv_reg5 [31:0]; + +endmodule diff --git a/firmware/ip/axis_buffer_ddr/src/axis_buffer_ddr.sv b/firmware/ip/axis_buffer_ddr/src/axis_buffer_ddr.sv new file mode 100644 index 000000000..9b3c85f81 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/axis_buffer_ddr.sv @@ -0,0 +1,285 @@ +module axis_buffer_ddr + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 256 , + parameter BURST_SIZE = 15, + parameter DEBUG = 0 + ) + ( + // Trigger. + input wire trigger , + + /***********************************/ + /* AXI Slave I/F for configuration */ + /***********************************/ + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Reset and Clock (m_axi, s_axis, m_axis). + input wire aclk , + input wire aresetn , + + /***********************/ + /* AXI Master for DDR4 */ + /***********************/ + + // Write Address Channel. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + // Write Data Channel. + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + // Write Response Channel. + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // Read Address Channel. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + // Read Data Channel. + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // Debug + output wire [31:0] mst_write_probe_dbg, + output wire [31:0] mst_read_probe_dbg + ); + +/********************/ +/* Internal signals */ +/********************/ + +// Registers. +wire RSTART_REG ; +wire [31:0] RADDR_REG ; +wire [31:0] RLENGTH_REG ; +wire WSTART_REG ; +wire [31:0] WADDR_REG ; +wire [31:0] WNBURST_REG ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .RSTART_REG (RSTART_REG ), + .RADDR_REG (RADDR_REG ), + .RLENGTH_REG (RLENGTH_REG ), + .WSTART_REG (WSTART_REG ), + .WADDR_REG (WADDR_REG ), + .WNBURST_REG (WNBURST_REG ) + ); + +axi_mst + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .BURST_SIZE (BURST_SIZE ) + ) + axi_mst_i + ( + // Trigger. + .trigger (trigger ), + + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + .m_axi_aclk (aclk ), + .m_axi_aresetn (aresetn ), + + // Write Address Channel. + .m_axi_awid (m_axi_awid ), + .m_axi_awaddr (m_axi_awaddr ), + .m_axi_awlen (m_axi_awlen ), + .m_axi_awsize (m_axi_awsize ), + .m_axi_awburst (m_axi_awburst ), + .m_axi_awlock (m_axi_awlock ), + .m_axi_awcache (m_axi_awcache ), + .m_axi_awprot (m_axi_awprot ), + .m_axi_awregion(m_axi_awregion ), + .m_axi_awqos (m_axi_awqos ), + .m_axi_awvalid (m_axi_awvalid ), + .m_axi_awready (m_axi_awready ), + + // Write Data Channel. + .m_axi_wdata (m_axi_wdata ), + .m_axi_wstrb (m_axi_wstrb ), + .m_axi_wlast (m_axi_wlast ), + .m_axi_wvalid (m_axi_wvalid ), + .m_axi_wready (m_axi_wready ), + + // Write Response Channel. + .m_axi_bid (m_axi_bid ), + .m_axi_bresp (m_axi_bresp ), + .m_axi_bvalid (m_axi_bvalid ), + .m_axi_bready (m_axi_bready ), + + // Read Address Channel. + .m_axi_arid (m_axi_arid ), + .m_axi_araddr (m_axi_araddr ), + .m_axi_arlen (m_axi_arlen ), + .m_axi_arsize (m_axi_arsize ), + .m_axi_arburst (m_axi_arburst ), + .m_axi_arlock (m_axi_arlock ), + .m_axi_arcache (m_axi_arcache ), + .m_axi_arprot (m_axi_arprot ), + .m_axi_arregion(m_axi_arregion ), + .m_axi_arqos (m_axi_arqos ), + .m_axi_arvalid (m_axi_arvalid ), + .m_axi_arready (m_axi_arready ), + + // Read Data Channel. + .m_axi_rid (m_axi_rid ), + .m_axi_rdata (m_axi_rdata ), + .m_axi_rresp (m_axi_rresp ), + .m_axi_rlast (m_axi_rlast ), + .m_axi_rvalid (m_axi_rvalid ), + .m_axi_rready (m_axi_rready ), + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tstrb (m_axis_tstrb ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tready (m_axis_tready ), + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + .s_axis_tstrb (s_axis_tstrb ), + .s_axis_tlast (s_axis_tlast ), + .s_axis_tvalid (s_axis_tvalid ), + + // Registers. + .RSTART_REG (RSTART_REG ), + .RADDR_REG (RADDR_REG ), + .RLENGTH_REG (RLENGTH_REG ), + .WSTART_REG (WSTART_REG ), + .WADDR_REG (WADDR_REG ), + .WNBURST_REG (WNBURST_REG ) + ); + + // DEBUG + assign mst_write_probe_dbg = axi_mst_i.axi_mst_write_i.mst_write_probe_dbg1; + assign mst_read_probe_dbg = axi_mst_i.axi_mst_read_i.mst_read_probe_dbg1; + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/bin2gray.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/bram_dp.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/fifo.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/fifo_axi.vhd similarity index 80% rename from firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd rename to firmware/ip/axis_buffer_ddr/src/fifo/fifo_axi.vhd index eb83d1a5d..e1f76f7f7 100644 --- a/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd +++ b/firmware/ip/axis_buffer_ddr/src/fifo/fifo_axi.vhd @@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; use IEEE.NUMERIC_STD.ALL; -entity fifo_dc_axi is +entity fifo_axi is Generic ( -- Data width. @@ -14,12 +14,9 @@ entity fifo_dc_axi is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -32,12 +29,12 @@ entity fifo_dc_axi is full : out std_logic; empty : out std_logic ); -end fifo_dc_axi; +end fifo_axi; -architecture rtl of fifo_dc_axi is +architecture rtl of fifo_axi is --- Dual-clock FIFO. -component fifo_dc is +-- FIFO. +component fifo is Generic ( -- Data width. @@ -48,12 +45,9 @@ component fifo_dc is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -98,8 +92,8 @@ signal empty_i : std_logic; begin --- Dual-clock FIFO. -fifo_i : fifo_dc +-- FIFO. +fifo_i : fifo Generic map ( -- Data width. @@ -110,12 +104,9 @@ fifo_i : fifo_dc ) Port map ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , + rstn => rstn , + clk => clk , - rd_rstn => rd_rstn , - rd_clk => rd_clk , - -- Write I/F. wr_en => wr_en , din => din , @@ -138,8 +129,8 @@ rd2axi_i : rd2axi ) Port map ( - rstn => rd_rstn , - clk => rd_clk , + rstn => rstn , + clk => clk , -- FIFO Read I/F. fifo_rd_en => rd_en_i , diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/fifo_dc.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/gray2bin.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/rd2axi.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_buffer_ddr/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/synchronizer_n.vhd b/firmware/ip/axis_buffer_ddr/src/synchronizer_n.vhd new file mode 100644 index 000000000..a29bd9be1 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/synchronizer_n.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..88ccced05 --- /dev/null +++ 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[ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "memory_maps": { + "S_AXI": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "65536", + "access": "read-write" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_buffer_ddr/src/tb/tb.sv b/firmware/ip/axis_buffer_ddr/src/tb/tb.sv new file mode 100644 index 000000000..987f5f8db --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/tb/tb.sv @@ -0,0 +1,507 @@ +import axi_vip_pkg::*; +import axi_slv_0_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000; +parameter ID_WIDTH = 1; +parameter DATA_WIDTH = 256; + +integer wnburst_n = 0; +integer rlength_n = 0; + +// Trigger. +reg trigger ; + +/***********************************/ +/* AXI Slave I/F for configuration */ +/***********************************/ +reg s_axi_aclk ; +reg s_axi_aresetn ; + +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; + +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; + +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; + +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; + +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +// Reset and Clock (m_axi, s_axis, m_axis). +reg aclk ; +reg aresetn ; + +/***********************/ +/* AXI Master for DDR4 */ +/***********************/ + +// Write Address Channel. +wire [ID_WIDTH-1:0] m_axi_awid ; +wire [31:0] m_axi_awaddr ; +wire [7:0] m_axi_awlen ; +wire [2:0] m_axi_awsize ; +wire [1:0] m_axi_awburst ; +wire m_axi_awlock ; +wire [3:0] m_axi_awcache ; +wire [2:0] m_axi_awprot ; +wire [3:0] m_axi_awregion ; +wire [3:0] m_axi_awqos ; +wire m_axi_awvalid ; +wire m_axi_awready ; + +// Write Data Channel. +wire [DATA_WIDTH-1:0] m_axi_wdata ; +wire [DATA_WIDTH/8-1:0] m_axi_wstrb ; +wire m_axi_wlast ; +wire m_axi_wvalid ; +wire m_axi_wready ; + +// Write Response Channel. +wire [ID_WIDTH-1:0] m_axi_bid ; +wire [1:0] m_axi_bresp ; +wire m_axi_bvalid ; +wire m_axi_bready ; + +// Read Address Channel. +wire [ID_WIDTH-1:0] m_axi_arid ; +wire [31:0] m_axi_araddr ; +wire [7:0] m_axi_arlen ; +wire [2:0] m_axi_arsize ; +wire [1:0] m_axi_arburst ; +wire m_axi_arlock ; +wire [3:0] m_axi_arcache ; +wire [2:0] m_axi_arprot ; +wire [3:0] m_axi_arregion ; +wire [3:0] m_axi_arqos ; +wire m_axi_arvalid ; +wire m_axi_arready ; + +// Read Data Channel. +wire [ID_WIDTH-1:0] m_axi_rid ; +wire [DATA_WIDTH-1:0] m_axi_rdata ; +wire [1:0] m_axi_rresp ; +wire m_axi_rlast ; +wire m_axi_rvalid ; +wire m_axi_rready ; + +/*************************/ +/* AXIS Master Interfase */ +/*************************/ +wire m_axis_tvalid ; +wire [DATA_WIDTH-1:0] m_axis_tdata ; +wire [DATA_WIDTH/8-1:0] m_axis_tstrb ; +wire m_axis_tlast ; +reg m_axis_tready ; + +/************************/ +/* AXIS Slave Interfase */ +/************************/ +wire s_axis_tready ; +reg [DATA_WIDTH-1:0] s_axis_tdata ; +reg [DATA_WIDTH/8-1:0] s_axis_tstrb ; +reg s_axis_tlast ; +reg s_axis_tvalid ; + +xil_axi_prot_t prot = 0; +reg[31:0] data; +reg [DATA_WIDTH-1:0] data_mem; +xil_axi_resp_t resp; + +// AXI VIP master address. +xil_axi_ulong RSTART_REG_ADDR = 0 * 4; +xil_axi_ulong RADDR_REG_ADDR = 1 * 4; +xil_axi_ulong RLENGTH_REG_ADDR = 2 * 4; +xil_axi_ulong WSTART_REG_ADDR = 3 * 4; +xil_axi_ulong WADDR_REG_ADDR = 4 * 4; +xil_axi_ulong WNBURST_REG_ADDR = 5 * 4; + + +// TB control. +reg tb_din_start = 0; +reg tb_dout_start = 0; + +// AXI Slave ("DDR" model) +axi_slv_0 axi_ddr_model + ( + .aclk (aclk ), + .aresetn (aresetn ), + + .s_axi_araddr (m_axi_araddr ), + .s_axi_arburst (m_axi_arburst ), + .s_axi_arcache (m_axi_arcache ), + .s_axi_arid (m_axi_arid ), + .s_axi_arlen (m_axi_arlen ), + .s_axi_arlock (m_axi_arlock ), + .s_axi_arprot (m_axi_arprot ), + .s_axi_arqos (m_axi_arqos ), + .s_axi_arready (m_axi_arready ), + .s_axi_arregion (m_axi_arregion ), + .s_axi_arsize (m_axi_arsize ), + .s_axi_arvalid (m_axi_arvalid ), + + .s_axi_awaddr (m_axi_awaddr ), + .s_axi_awburst (m_axi_awburst ), + .s_axi_awcache (m_axi_awcache ), + .s_axi_awid (m_axi_awid ), + .s_axi_awlen (m_axi_awlen ), + .s_axi_awlock (m_axi_awlock ), + .s_axi_awprot (m_axi_awprot ), + .s_axi_awqos (m_axi_awqos ), + .s_axi_awready (m_axi_awready ), + .s_axi_awregion (m_axi_awregion ), + .s_axi_awsize (m_axi_awsize ), + .s_axi_awvalid (m_axi_awvalid ), + + .s_axi_bid (m_axi_bid ), + .s_axi_bready (m_axi_bready ), + .s_axi_bresp (m_axi_bresp ), + .s_axi_bvalid (m_axi_bvalid ), + + .s_axi_rdata (m_axi_rdata ), + .s_axi_rid (m_axi_rid ), + .s_axi_rlast (m_axi_rlast ), + .s_axi_rready (m_axi_rready ), + .s_axi_rresp (m_axi_rresp ), + .s_axi_rvalid (m_axi_rvalid ), + + .s_axi_wdata (m_axi_wdata ), + .s_axi_wlast (m_axi_wlast ), + .s_axi_wready (m_axi_wready ), + .s_axi_wstrb (m_axi_wstrb ), + .s_axi_wvalid (m_axi_wvalid ) + ); + +// AXI Master. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +// DUT. +axis_buffer_ddr + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + DUT + ( + // Trigger. + .trigger , + + /***********************************/ + /* AXI Slave I/F for configuration */ + /***********************************/ + .s_axi_aclk , + .s_axi_aresetn , + + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awvalid , + .s_axi_awready , + + .s_axi_wdata , + .s_axi_wstrb , + .s_axi_wvalid , + .s_axi_wready , + + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_bready , + + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arvalid , + .s_axi_arready , + + .s_axi_rdata , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_rready , + + // Reset and Clock (m_axi, s_axis, m_axis). + .aclk , + .aresetn , + + /***********************/ + /* AXI Master for DDR4 */ + /***********************/ + + // Write Address Channel. + .m_axi_awid , + .m_axi_awaddr , + .m_axi_awlen , + .m_axi_awsize , + .m_axi_awburst , + .m_axi_awlock , + .m_axi_awcache , + .m_axi_awprot , + .m_axi_awregion , + .m_axi_awqos , + .m_axi_awvalid , + .m_axi_awready , + + // Write Data Channel. + .m_axi_wdata , + .m_axi_wstrb , + .m_axi_wlast , + .m_axi_wvalid , + .m_axi_wready , + + // Write Response Channel. + .m_axi_bid , + .m_axi_bresp , + .m_axi_bvalid , + .m_axi_bready , + + // Read Address Channel. + .m_axi_arid , + .m_axi_araddr , + .m_axi_arlen , + .m_axi_arsize , + .m_axi_arburst , + .m_axi_arlock , + .m_axi_arcache , + .m_axi_arprot , + .m_axi_arregion , + .m_axi_arqos , + .m_axi_arvalid , + .m_axi_arready , + + // Read Data Channel. + .m_axi_rid , + .m_axi_rdata , + .m_axi_rresp , + .m_axi_rlast , + .m_axi_rvalid , + .m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid , + .m_axis_tdata , + .m_axis_tstrb , + .m_axis_tlast , + .m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready , + .s_axis_tdata , + .s_axis_tstrb , + .s_axis_tlast , + .s_axis_tvalid + ); + +// VIP Agents +axi_slv_0_slv_mem_t axi_slv_0_agent; +axi_mst_0_mst_t axi_mst_0_agent; + +// Main TB. +initial begin + // Create agents. + axi_slv_0_agent = new("axi_slv_0 VIP Agent",tb.axi_ddr_model.inst.IF); + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // AXI Slave (memory model) beat gap. + axi_slv_0_agent.mem_model.set_inter_beat_gap_delay_policy(XIL_AXI_MEMORY_DELAY_RANDOM); + axi_slv_0_agent.mem_model.set_inter_beat_gap_range(10,20); + + // Set tag for agents. + axi_slv_0_agent.set_agent_tag("axi_slv_0 VIP"); + axi_mst_0_agent.set_agent_tag("axi_mst_0 VIP"); + + // Start agents. + axi_slv_0_agent.start_slave(); + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + trigger <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #2us; + + /**************************/ + /* Write data into memory */ + /**************************/ + // WNBURST_REG. + wnburst_n = 3; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(WNBURST_REG_ADDR, prot, wnburst_n, resp); + + // WADDR_REG_ADDR + axi_mst_0_agent.AXI4LITE_WRITE_BURST(WADDR_REG_ADDR, prot, 1 * (DATA_WIDTH/8), resp); + + repeat (2) begin + // WSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(WSTART_REG_ADDR, prot, 1, resp); + + tb_din_start <= 1; + + #2us; + + trigger <= 1; + + #2us; + + // Backdoor memory read. + rlength_n = 3 * 16; + for (int addr = TARGET_SLAVE_BASE_ADDR+0; addr < TARGET_SLAVE_BASE_ADDR+DATA_WIDTH; addr = addr + DATA_WIDTH) begin + data_mem = axi_slv_0_agent.mem_model.backdoor_memory_read(addr); + end + + #2us; + + trigger <= 0; + + #2us; + + // WSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(WSTART_REG_ADDR, prot, 0, resp); + + #2us; + + tb_din_start <= 0; + + /********************/ + /* Read from memory */ + /********************/ + // RLENGTH_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(RLENGTH_REG_ADDR, prot, rlength_n, resp); + + // RADDR_REG_ADDR. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(RADDR_REG_ADDR, prot, 1 * (DATA_WIDTH/8), resp); + + // RSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(RSTART_REG_ADDR, prot, 1, resp); + + tb_dout_start <= 1; + + #10us; + + axi_mst_0_agent.AXI4LITE_WRITE_BURST(RSTART_REG_ADDR, prot, 0, resp); + end + + $finish(); + +end + +// Data input process. +initial begin + int i=0; + + s_axis_tdata <= 0; + s_axis_tstrb <= '1; + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + forever begin + int i = 0; + wait (tb_din_start); + wait (s_axis_tready); + + + fork + begin + wait (tb_din_start); + wait (~tb_din_start); + end + begin + while (tb_din_start) begin + // for (int i=0; i<100; i=i+1) begin + i = i + 1; + @(negedge aclk); + s_axis_tdata <= i; + s_axis_tvalid <= 1; + // @(posedge aclk); + //s_axis_tvalid <= 0; + // @(posedge aclk); + wait (s_axis_tready); + @(posedge aclk); + end + end + join_any + + + @(posedge aclk); + s_axis_tvalid <= 0; + + + wait (~tb_din_start); + + + end +end + +// Data output process. +initial begin + m_axis_tready <= 0; + + wait (tb_dout_start); + + @(posedge aclk); + m_axis_tready <= 1; + + wait (~tb_dout_start); +end + +always begin + s_axi_aclk <= 0; + #7; + s_axi_aclk <= 1; + #7; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr/src/tb/tb_axi_mst.sv b/firmware/ip/axis_buffer_ddr/src/tb/tb_axi_mst.sv new file mode 100644 index 000000000..ae26f8a20 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/tb/tb_axi_mst.sv @@ -0,0 +1,340 @@ +import axi_vip_pkg::*; +import axi_slv_0_pkg::*; + +module tb(); + +// DUT generics. +parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000; +parameter ID_WIDTH = 1; +parameter DATA_WIDTH = 256; + +// Reset and Clock. +reg m_axi_aclk ; +reg m_axi_aresetn ; + +// Write Address Channel. +wire [ID_WIDTH-1:0] m_axi_awid ; +wire [31:0] m_axi_awaddr ; +wire [7:0] m_axi_awlen ; +wire [2:0] m_axi_awsize ; +wire [1:0] m_axi_awburst ; +wire m_axi_awlock ; +wire [3:0] m_axi_awcache ; +wire [2:0] m_axi_awprot ; +wire [3:0] m_axi_awregion ; +wire [3:0] m_axi_awqos ; +wire m_axi_awvalid ; +wire m_axi_awready ; + +// Write Data Channel. +wire [DATA_WIDTH-1:0] m_axi_wdata ; +wire [DATA_WIDTH/8-1:0] m_axi_wstrb ; +wire m_axi_wlast ; +wire m_axi_wvalid ; +wire m_axi_wready ; + +// Write Response Channel. +wire [ID_WIDTH-1:0] m_axi_bid ; +wire [1:0] m_axi_bresp ; +wire m_axi_bvalid ; +wire m_axi_bready ; + +// Read Address Channel. +wire [ID_WIDTH-1:0] m_axi_arid ; +wire [31:0] m_axi_araddr ; +wire [7:0] m_axi_arlen ; +wire [2:0] m_axi_arsize ; +wire [1:0] m_axi_arburst ; +wire m_axi_arlock ; +wire [3:0] m_axi_arcache ; +wire [2:0] m_axi_arprot ; +wire [3:0] m_axi_arregion ; +wire [3:0] m_axi_arqos ; +wire m_axi_arvalid ; +wire m_axi_arready ; + +// Read Data Channel. +wire [ID_WIDTH-1:0] m_axi_rid ; +wire [DATA_WIDTH-1:0] m_axi_rdata ; +wire [1:0] m_axi_rresp ; +wire m_axi_rlast ; +wire m_axi_rvalid ; +wire m_axi_rready ; + +/*************************/ +/* AXIS Master Interfase */ +/*************************/ +wire m_axis_tvalid ; +wire [DATA_WIDTH-1:0] m_axis_tdata ; +wire [DATA_WIDTH/8-1:0] m_axis_tstrb ; +wire m_axis_tlast ; +reg m_axis_tready ; + +/************************/ +/* AXIS Slave Interfase */ +/************************/ +wire s_axis_tready ; +reg [DATA_WIDTH-1:0] s_axis_tdata ; +reg [DATA_WIDTH/8-1:0] s_axis_tstrb ; +reg s_axis_tlast ; +reg s_axis_tvalid ; + +// Registers. +reg RSTART_REG ; +reg [31:0] RADDR_REG ; +reg [31:0] RLENGTH_REG ; +reg WSTART_REG ; +reg [31:0] WADDR_REG ; + +xil_axi_prot_t prot = 0; +reg [31:0] data_wr = 32'h12345678; +reg [31:0] data; +reg [DATA_WIDTH-1:0] data_mem; +xil_axi_resp_t resp; + +reg tb_din_start = 0; +reg tb_dout_start = 0; + +axi_mst + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + axi_mst_i + ( + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + .m_axi_aclk , + .m_axi_aresetn , + + // Write Address Channel. + .m_axi_awid , + .m_axi_awaddr , + .m_axi_awlen , + .m_axi_awsize , + .m_axi_awburst , + .m_axi_awlock , + .m_axi_awcache , + .m_axi_awprot , + .m_axi_awregion , + .m_axi_awqos , + .m_axi_awvalid , + .m_axi_awready , + + // Write Data Channel. + .m_axi_wdata , + .m_axi_wstrb , + .m_axi_wlast , + .m_axi_wvalid , + .m_axi_wready , + + // Write Response Channel. + .m_axi_bid , + .m_axi_bresp , + .m_axi_bvalid , + .m_axi_bready , + + // Read Address Channel. + .m_axi_arid , + .m_axi_araddr , + .m_axi_arlen , + .m_axi_arsize , + .m_axi_arburst , + .m_axi_arlock , + .m_axi_arcache , + .m_axi_arprot , + .m_axi_arregion , + .m_axi_arqos , + .m_axi_arvalid , + .m_axi_arready , + + // Read Data Channel. + .m_axi_rid , + .m_axi_rdata , + .m_axi_rresp , + .m_axi_rlast , + .m_axi_rvalid , + .m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid , + .m_axis_tdata , + .m_axis_tstrb , + .m_axis_tlast , + .m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready , + .s_axis_tdata , + .s_axis_tstrb , + .s_axis_tlast , + .s_axis_tvalid , + + // Registers. + .RSTART_REG , + .RADDR_REG , + .RLENGTH_REG , + .WSTART_REG , + .WADDR_REG + ); + +axi_slv_0 axi_slv_0_i + ( + .aclk (m_axi_aclk ), + .aresetn (m_axi_aresetn ), + + .s_axi_araddr (m_axi_araddr ), + .s_axi_arburst (m_axi_arburst ), + .s_axi_arcache (m_axi_arcache ), + .s_axi_arid (m_axi_arid ), + .s_axi_arlen (m_axi_arlen ), + .s_axi_arlock (m_axi_arlock ), + .s_axi_arprot (m_axi_arprot ), + .s_axi_arqos (m_axi_arqos ), + .s_axi_arready (m_axi_arready ), + .s_axi_arregion (m_axi_arregion ), + .s_axi_arsize (m_axi_arsize ), + .s_axi_arvalid (m_axi_arvalid ), + + .s_axi_awaddr (m_axi_awaddr ), + .s_axi_awburst (m_axi_awburst ), + .s_axi_awcache (m_axi_awcache ), + .s_axi_awid (m_axi_awid ), + .s_axi_awlen (m_axi_awlen ), + .s_axi_awlock (m_axi_awlock ), + .s_axi_awprot (m_axi_awprot ), + .s_axi_awqos (m_axi_awqos ), + .s_axi_awready (m_axi_awready ), + .s_axi_awregion (m_axi_awregion ), + .s_axi_awsize (m_axi_awsize ), + .s_axi_awvalid (m_axi_awvalid ), + + .s_axi_bid (m_axi_bid ), + .s_axi_bready (m_axi_bready ), + .s_axi_bresp (m_axi_bresp ), + .s_axi_bvalid (m_axi_bvalid ), + + .s_axi_rdata (m_axi_rdata ), + .s_axi_rid (m_axi_rid ), + .s_axi_rlast (m_axi_rlast ), + .s_axi_rready (m_axi_rready ), + .s_axi_rresp (m_axi_rresp ), + .s_axi_rvalid (m_axi_rvalid ), + + .s_axi_wdata (m_axi_wdata ), + .s_axi_wlast (m_axi_wlast ), + .s_axi_wready (m_axi_wready ), + .s_axi_wstrb (m_axi_wstrb ), + .s_axi_wvalid (m_axi_wvalid ) + ); + +// VIP Agents +axi_slv_0_slv_mem_t axi_slv_0_agent; + +initial begin + // Create agents. + axi_slv_0_agent = new("axi_slv_0 VIP Agent",tb.axi_slv_0_i.inst.IF); + + // AXI Slave (memory model) beat gap. + axi_slv_0_agent.mem_model.set_inter_beat_gap_delay_policy(XIL_AXI_MEMORY_DELAY_RANDOM); + axi_slv_0_agent.mem_model.set_inter_beat_gap_range(10,20); + + // Set tag for agents. + axi_slv_0_agent.set_agent_tag("axi_slv_0 VIP"); + + // Start agents. + axi_slv_0_agent.start_slave(); + + // Reset sequence. + m_axi_aresetn <= 0; + RSTART_REG <= 0; + RADDR_REG <= 0; + RLENGTH_REG <= 10; + WSTART_REG <= 0; + WADDR_REG <= 0; + #5000; + m_axi_aresetn <= 1; + + #1000; + + $display("##############"); + $display("### Test 0 ###"); + $display("##############"); + + #1000; + + // Write data into memory. + WSTART_REG <= 1; + tb_din_start <= 1; + + #1000; + + // Backdoor memory read. + for (int addr = TARGET_SLAVE_BASE_ADDR+0; addr < TARGET_SLAVE_BASE_ADDR+0+160; addr = addr + DATA_WIDTH/8) begin + data_mem = axi_slv_0_agent.mem_model.backdoor_memory_read(addr); + $display("Addr: 0x%04X, Data: 0x%04X", addr, data_mem); + end + + #1000; + + WSTART_REG <= 0; + + #1000; + + // Read from memory. + RSTART_REG <= 1; + tb_dout_start <= 1; +end + +// Data input process. +initial begin + s_axis_tdata <= 0; + s_axis_tstrb <= '1; + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + wait (tb_din_start); + + for (int i=0; i<1000; i=i+1) begin + wait (s_axis_tready); + + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + s_axis_tdata <= i; + s_axis_tvalid <= 1; + @(posedge m_axi_aclk); + s_axis_tvalid <= 0; + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + end +end + +// Data output process. +initial begin + m_axis_tready <= 0; + + wait (tb_dout_start); + + @(posedge m_axi_aclk); + m_axis_tready <= 1; +end + +always begin + m_axi_aclk <= 0; + #1.7; + m_axi_aclk <= 1; + #1.7; +end + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr/src/tb/tb_axis_buffer_ddr_behav.wcfg b/firmware/ip/axis_buffer_ddr/src/tb/tb_axis_buffer_ddr_behav.wcfg new file mode 100644 index 000000000..e88052a35 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/src/tb/tb_axis_buffer_ddr_behav.wcfg @@ -0,0 +1,1230 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ID_WIDTH[31:0] + ID_WIDTH[31:0] + UNSIGNEDDECRADIX + + + DATA_WIDTH[31:0] + DATA_WIDTH[31:0] + UNSIGNEDDECRADIX + + + BURST_SIZE[31:0] + BURST_SIZE[31:0] + UNSIGNEDDECRADIX + + + tb_din_start + tb_din_start + #FFFF00 + true + + + tb_dout_start + tb_dout_start + #FFFF00 + true + + + REGS + label + + + WSTART_REG + WSTART_REG + + + WADDR_REG[31:0] + WADDR_REG[31:0] + + + WNBURST_REG[31:0] + WNBURST_REG[31:0] + UNSIGNEDDECRADIX + + + RSTART_REG + RSTART_REG + + + RADDR_REG[31:0] + RADDR_REG[31:0] + + + RLENGTH_REG[31:0] + RLENGTH_REG[31:0] + UNSIGNEDDECRADIX + + + + aclk + aclk + + + aresetn + aresetn + + + trigger + trigger + + + S_AXIS + label + + s_axis_tready + s_axis_tready + #FFFF00 + true + + + s_axis_tvalid + s_axis_tvalid + #FFFF00 + true + + + s_axis_tdata[255:0] + s_axis_tdata[255:0] + #FFFF00 + true + + + data_15_0 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + #FFFF00 + true + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + s_axis_tstrb[31:0] + s_axis_tstrb[31:0] + #FFFF00 + true + + + s_axis_tlast + s_axis_tlast + #FFFF00 + true + + + + AXI_WRITE + label + + state[31:0] + state[31:0] + #FFA500 + true + + + cnt_burst[7:0] + cnt_burst[7:0] + UNSIGNEDDECRADIX + + + cnt_nburst[31:0] + cnt_nburst[31:0] + UNSIGNEDDECRADIX + + + FIFO_WR + label + + + wr_en + wr_en + + + din[255:0] + din[255:0] + + + wrdata_15_0 + label + UNSIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + full + full + + + rd_en + rd_en + + + dout[255:0] + dout[255:0] + + + rddata_15_0 + label + UNSIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + empty + empty + + + + + M_AXI_WR + label + + m_axi_aclk + m_axi_aclk + + + m_axi_aresetn + m_axi_aresetn + + + m_axi_awready + m_axi_awready + + + m_axi_awvalid + m_axi_awvalid + + + m_axi_awaddr[31:0] + m_axi_awaddr[31:0] + + + m_axi_awlen[7:0] + m_axi_awlen[7:0] + + + m_axi_awsize[2:0] + m_axi_awsize[2:0] + + + m_axi_awburst[1:0] + m_axi_awburst[1:0] + + + m_axi_awcache[3:0] + m_axi_awcache[3:0] + + + m_axi_awprot[2:0] + m_axi_awprot[2:0] + + + m_axi_awregion[3:0] + m_axi_awregion[3:0] + + + m_axi_awqos[3:0] + m_axi_awqos[3:0] + + + m_axi_wready + m_axi_wready + + + m_axi_wvalid + m_axi_wvalid + + + m_axi_wdata[255:0] + m_axi_wdata[255:0] + + + wdata_15_0 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + m_axi_wlast + m_axi_wlast + + + m_axi_bready + m_axi_bready + + + m_axi_bvalid + m_axi_bvalid + + + m_axi_bid[0:0] + m_axi_bid[0:0] + + + m_axi_bresp[1:0] + m_axi_bresp[1:0] + + + + AXI_READ + label + + + state[31:0] + state[31:0] + #D2691E + true + + + FIFO_RD + label + + + wr_en + wr_en + + + din[255:0] + din[255:0] + + + wdata_15_0 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + full + full + + + rd_en + rd_en + + + dout[255:0] + dout[255:0] + + + rdata_15_0 + label + SIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + empty + empty + + + + + M_AXI_RD + label + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + + + m_axi_arsize[2:0] + m_axi_arsize[2:0] + + + m_axi_arburst[1:0] + m_axi_arburst[1:0] + + + m_axi_arcache[3:0] + m_axi_arcache[3:0] + + + m_axi_arprot[2:0] + m_axi_arprot[2:0] + + + m_axi_arregion[3:0] + m_axi_arregion[3:0] + + + m_axi_arqos[3:0] + m_axi_arqos[3:0] + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + + + m_axi_rready + m_axi_rready + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rdata[255:0] + m_axi_rdata[255:0] + + + rdata_15_0 + label + UNSIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + m_axi_rlast + m_axi_rlast + + + + M_AXIS + label + + m_axis_tready + m_axis_tready + #00FFFF + true + + + m_axis_tvalid + m_axis_tvalid + #00FFFF + true + + + m_axis_tdata[255:0] + m_axis_tdata[255:0] + #00FFFF + true + + + data_15_0 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + #00FFFF + true + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + m_axis_tstrb[31:0] + m_axis_tstrb[31:0] + #00FFFF + true + + + m_axis_tlast + m_axis_tlast + #00FFFF + true + + + + AXI_DDR_MODEL + label + + aclk + aclk + + + aresetn + aresetn + + + s_axi_awaddr[31:0] + s_axi_awaddr[31:0] + + + s_axi_awlen[7:0] + s_axi_awlen[7:0] + + + s_axi_awsize[2:0] + s_axi_awsize[2:0] + + + s_axi_awburst[1:0] + s_axi_awburst[1:0] + + + s_axi_awready + s_axi_awready + + + s_axi_awvalid + s_axi_awvalid + + + s_axi_wdata[255:0] + s_axi_wdata[255:0] + + + wdata_15_0 + label + UNSIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + s_axi_wstrb[31:0] + s_axi_wstrb[31:0] + + + s_axi_wready + s_axi_wready + + + s_axi_wvalid + s_axi_wvalid + + + s_axi_wlast + s_axi_wlast + + + s_axi_bready + s_axi_bready + + + s_axi_bvalid + s_axi_bvalid + + + s_axi_bresp[1:0] + s_axi_bresp[1:0] + + + s_axi_arready + s_axi_arready + + + s_axi_arvalid + s_axi_arvalid + + + s_axi_araddr[31:0] + s_axi_araddr[31:0] + + + s_axi_arlen[7:0] + s_axi_arlen[7:0] + + + s_axi_arsize[2:0] + s_axi_arsize[2:0] + + + s_axi_arburst[1:0] + s_axi_arburst[1:0] + + + s_axi_arprot[2:0] + s_axi_arprot[2:0] + + + s_axi_rready + s_axi_rready + + + s_axi_rvalid + s_axi_rvalid + + + s_axi_rdata[255:0] + s_axi_rdata[255:0] + + + rdata_15_0 + label + UNSIGNEDDECRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + s_axi_rlast + s_axi_rlast + + + diff --git a/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_1.tcl b/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_1.tcl new file mode 100644 index 000000000..9b6ba344d --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_1.tcl @@ -0,0 +1,83 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "TARGET_SLAVE_BASE_ADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to update BURST_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to validate BURST_SIZE + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to update ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to validate ID_WIDTH + return true +} + +proc update_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to update TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to validate TARGET_SLAVE_BASE_ADDR + return true +} + + +proc update_MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR} +} + +proc update_MODELPARAM_VALUE.ID_WIDTH { MODELPARAM_VALUE.ID_WIDTH PARAM_VALUE.ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID_WIDTH}] ${MODELPARAM_VALUE.ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.BURST_SIZE { MODELPARAM_VALUE.BURST_SIZE PARAM_VALUE.BURST_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BURST_SIZE}] ${MODELPARAM_VALUE.BURST_SIZE} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_v1_0.tcl b/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_v1_0.tcl new file mode 100644 index 000000000..8284acc88 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr/xgui/axis_buffer_ddr_v1_v1_0.tcl @@ -0,0 +1,69 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "TARGET_SLAVE_BASE_ADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to update BURST_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to validate BURST_SIZE + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to update ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to validate ID_WIDTH + return true +} + +proc update_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to update TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to validate TARGET_SLAVE_BASE_ADDR + return true +} + + +proc update_MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR} +} + +proc update_MODELPARAM_VALUE.ID_WIDTH { MODELPARAM_VALUE.ID_WIDTH PARAM_VALUE.ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID_WIDTH}] ${MODELPARAM_VALUE.ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.BURST_SIZE { MODELPARAM_VALUE.BURST_SIZE PARAM_VALUE.BURST_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BURST_SIZE}] ${MODELPARAM_VALUE.BURST_SIZE} +} + diff --git a/firmware/ip/axis_cdcsync_v1/component.xml b/firmware/ip/axis_cdcsync_v1/component.xml new file mode 100644 index 000000000..17c85fc26 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/component.xml @@ -0,0 +1,3183 @@ + + + QICK + QICK + axis_cdcsync_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + + true + + + + + + m2_axis + + + + true + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + + false + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + TREADY + + + m3_axis_tready + + + + + + + false + + + + + + m4_axis + + + + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + TREADY + + + m4_axis_tready + + + + + + + false + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + TREADY + + + m5_axis_tready + + + + + + + false + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + TREADY + + + m6_axis_tready + + + + + + + false + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + TREADY + + + m7_axis_tready + + + + + + + false + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + 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src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/cdcsync.sv + systemVerilogSource + + + src/axis_cdcsync_v1.sv + systemVerilogSource + CHECKSUM_aa11abf8 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + ../../hdl/fifo_dc_axi_xpm.sv + systemVerilogSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/cdcsync.sv + systemVerilogSource + xil_defaultlib + + + src/axis_cdcsync_v1.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/axis_cdcsync_v1_v1_0.tcl + tclSource + CHECKSUM_5752b26c + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + xil_defaultlib + + + + AXIS CDC Synchronous, V1. + + + N + N + 2 + + + B + B + 8 + + + Component_Name + axis_cdcsync_v1_v1_0 + + + + + + zynquplus + + + /QICK/Miscellaneous + + AXIS CDCSYNC V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 11 + 2025-08-29T16:24:49Z + + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + + + + 2023.1 + + + + + + + + diff --git a/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_ooc.xdc b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_ooc.xdc new file mode 100644 index 000000000..cd7f30913 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_ooc.xdc @@ -0,0 +1,2 @@ +create_clock -period 5.000 -name s_axis_aclk -waveform {0.000 2.500} [get_ports s_axis_aclk] +create_clock -period 2.000 -name m_axis_aclk -waveform {0.000 1.000} [get_ports m_axis_aclk] diff --git a/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv new file mode 100644 index 000000000..114ca2f8d --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv @@ -0,0 +1,298 @@ +module axis_cdcsync_v1 + #( + // Number of inputs/outputs. + parameter N = 2 , + + // Number of data bits. + parameter B = 8 + ) + ( + // S_AXIS for input data. + input wire s_axis_aresetn , + input wire s_axis_aclk , + + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [B-1:0] s0_axis_tdata , + + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [B-1:0] s1_axis_tdata , + + output wire s2_axis_tready , + input wire s2_axis_tvalid , + input wire [B-1:0] s2_axis_tdata , + + output wire s3_axis_tready , + input wire s3_axis_tvalid , + input wire [B-1:0] s3_axis_tdata , + + output wire s4_axis_tready , + input wire s4_axis_tvalid , + input wire [B-1:0] s4_axis_tdata , + + output wire s5_axis_tready , + input wire s5_axis_tvalid , + input wire [B-1:0] s5_axis_tdata , + + output wire s6_axis_tready , + input wire s6_axis_tvalid , + input wire [B-1:0] s6_axis_tdata , + + output wire s7_axis_tready , + input wire s7_axis_tvalid , + input wire [B-1:0] s7_axis_tdata , + + output wire s8_axis_tready , + input wire s8_axis_tvalid , + input wire [B-1:0] s8_axis_tdata , + + output wire s9_axis_tready , + input wire s9_axis_tvalid , + input wire [B-1:0] s9_axis_tdata , + + output wire s10_axis_tready , + input wire s10_axis_tvalid , + input wire [B-1:0] s10_axis_tdata , + + output wire s11_axis_tready , + input wire s11_axis_tvalid , + input wire [B-1:0] s11_axis_tdata , + + output wire s12_axis_tready , + input wire s12_axis_tvalid , + input wire [B-1:0] s12_axis_tdata , + + output wire s13_axis_tready , + input wire s13_axis_tvalid , + input wire [B-1:0] s13_axis_tdata , + + output wire s14_axis_tready , + input wire s14_axis_tvalid , + input wire [B-1:0] s14_axis_tdata , + + output wire s15_axis_tready , + input wire s15_axis_tvalid , + input wire [B-1:0] s15_axis_tdata , + + // M_AXIS for output data. + input wire m_axis_aresetn , + input wire m_axis_aclk , + + input wire m0_axis_tready , + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + input wire m1_axis_tready , + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + input wire m2_axis_tready , + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + input wire m3_axis_tready , + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + input wire m4_axis_tready , + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + input wire m5_axis_tready , + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + input wire m6_axis_tready , + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + input wire m7_axis_tready , + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata , + + input wire m8_axis_tready , + output wire m8_axis_tvalid , + output wire [B-1:0] m8_axis_tdata , + + input wire m9_axis_tready , + output wire m9_axis_tvalid , + output wire [B-1:0] m9_axis_tdata , + + input wire m10_axis_tready , + output wire m10_axis_tvalid , + output wire [B-1:0] m10_axis_tdata , + + input wire m11_axis_tready , + output wire m11_axis_tvalid , + output wire [B-1:0] m11_axis_tdata , + + input wire m12_axis_tready , + output wire m12_axis_tvalid , + output wire [B-1:0] m12_axis_tdata , + + input wire m13_axis_tready , + output wire m13_axis_tvalid , + output wire [B-1:0] m13_axis_tdata , + + input wire m14_axis_tready , + output wire m14_axis_tvalid , + output wire [B-1:0] m14_axis_tdata , + + input wire m15_axis_tready , + output wire m15_axis_tvalid , + output wire [B-1:0] m15_axis_tdata + ); + +/**********************/ +/* Begin Architecture */ +/**********************/ +cdcsync + #( + // Number of inputs/outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + cdcsync_i + ( + // S_AXIS for input data. + .s_axis_aresetn (s_axis_aresetn ), + .s_axis_aclk (s_axis_aclk ), + + .s0_axis_tready (s0_axis_tready ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tdata (s0_axis_tdata ), + + .s1_axis_tready (s1_axis_tready ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tdata (s1_axis_tdata ), + + .s2_axis_tready (s2_axis_tready ), + .s2_axis_tvalid (s2_axis_tvalid ), + .s2_axis_tdata (s2_axis_tdata ), + + .s3_axis_tready (s3_axis_tready ), + .s3_axis_tvalid (s3_axis_tvalid ), + .s3_axis_tdata (s3_axis_tdata ), + + .s4_axis_tready (s4_axis_tready ), + .s4_axis_tvalid (s4_axis_tvalid ), + .s4_axis_tdata (s4_axis_tdata ), + + .s5_axis_tready (s5_axis_tready ), + .s5_axis_tvalid (s5_axis_tvalid ), + .s5_axis_tdata (s5_axis_tdata ), + + .s6_axis_tready (s6_axis_tready ), + .s6_axis_tvalid (s6_axis_tvalid ), + .s6_axis_tdata (s6_axis_tdata ), + + .s7_axis_tready (s7_axis_tready ), + .s7_axis_tvalid (s7_axis_tvalid ), + .s7_axis_tdata (s7_axis_tdata ), + + .s8_axis_tready (s8_axis_tready ), + .s8_axis_tvalid (s8_axis_tvalid ), + .s8_axis_tdata (s8_axis_tdata ), + + .s9_axis_tready (s9_axis_tready ), + .s9_axis_tvalid (s9_axis_tvalid ), + .s9_axis_tdata (s9_axis_tdata ), + + .s10_axis_tready (s10_axis_tready ), + .s10_axis_tvalid (s10_axis_tvalid ), + .s10_axis_tdata (s10_axis_tdata ), + + .s11_axis_tready (s11_axis_tready ), + .s11_axis_tvalid (s11_axis_tvalid ), + .s11_axis_tdata (s11_axis_tdata ), + + .s12_axis_tready (s12_axis_tready ), + .s12_axis_tvalid (s12_axis_tvalid ), + .s12_axis_tdata (s12_axis_tdata ), + + .s13_axis_tready (s13_axis_tready ), + .s13_axis_tvalid (s13_axis_tvalid ), + .s13_axis_tdata (s13_axis_tdata ), + + .s14_axis_tready (s14_axis_tready ), + .s14_axis_tvalid (s14_axis_tvalid ), + .s14_axis_tdata (s14_axis_tdata ), + + .s15_axis_tready (s15_axis_tready ), + .s15_axis_tvalid (s15_axis_tvalid ), + .s15_axis_tdata (s15_axis_tdata ), + + // M_AXIS for output data. + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_aclk (m_axis_aclk ), + + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + .m3_axis_tready (m3_axis_tready ), + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + .m4_axis_tready (m4_axis_tready ), + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + .m5_axis_tready (m5_axis_tready ), + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + .m6_axis_tready (m6_axis_tready ), + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + .m7_axis_tready (m7_axis_tready ), + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ), + + .m8_axis_tready (m8_axis_tready ), + .m8_axis_tvalid (m8_axis_tvalid ), + .m8_axis_tdata (m8_axis_tdata ), + + .m9_axis_tready (m9_axis_tready ), + .m9_axis_tvalid (m9_axis_tvalid ), + .m9_axis_tdata (m9_axis_tdata ), + + .m10_axis_tready (m10_axis_tready ), + .m10_axis_tvalid (m10_axis_tvalid ), + .m10_axis_tdata (m10_axis_tdata ), + + .m11_axis_tready (m11_axis_tready ), + .m11_axis_tvalid (m11_axis_tvalid ), + .m11_axis_tdata (m11_axis_tdata ), + + .m12_axis_tready (m12_axis_tready ), + .m12_axis_tvalid (m12_axis_tvalid ), + .m12_axis_tdata (m12_axis_tdata ), + + .m13_axis_tready (m13_axis_tready ), + .m13_axis_tvalid (m13_axis_tvalid ), + .m13_axis_tdata (m13_axis_tdata ), + + .m14_axis_tready (m14_axis_tready ), + .m14_axis_tvalid (m14_axis_tvalid ), + .m14_axis_tdata (m14_axis_tdata ), + + .m15_axis_tready (m15_axis_tready ), + .m15_axis_tvalid (m15_axis_tvalid ), + .m15_axis_tdata (m15_axis_tdata ) + ); + +endmodule + diff --git a/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv b/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv new file mode 100644 index 000000000..54faeb85b --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv @@ -0,0 +1,345 @@ +module cdcsync + #( + // Number of inputs/outputs. + parameter N = 2 , + + // Number of data bits. + parameter B = 8 + ) + ( + // S_AXIS for input data. + input wire s_axis_aresetn , + input wire s_axis_aclk , + + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [B-1:0] s0_axis_tdata , + + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [B-1:0] s1_axis_tdata , + + output wire s2_axis_tready , + input wire s2_axis_tvalid , + input wire [B-1:0] s2_axis_tdata , + + output wire s3_axis_tready , + input wire s3_axis_tvalid , + input wire [B-1:0] s3_axis_tdata , + + output wire s4_axis_tready , + input wire s4_axis_tvalid , + input wire [B-1:0] s4_axis_tdata , + + output wire s5_axis_tready , + input wire s5_axis_tvalid , + input wire [B-1:0] s5_axis_tdata , + + output wire s6_axis_tready , + input wire s6_axis_tvalid , + input wire [B-1:0] s6_axis_tdata , + + output wire s7_axis_tready , + input wire s7_axis_tvalid , + input wire [B-1:0] s7_axis_tdata , + + output wire s8_axis_tready , + input wire s8_axis_tvalid , + input wire [B-1:0] s8_axis_tdata , + + output wire s9_axis_tready , + input wire s9_axis_tvalid , + input wire [B-1:0] s9_axis_tdata , + + output wire s10_axis_tready , + input wire s10_axis_tvalid , + input wire [B-1:0] s10_axis_tdata , + + output wire s11_axis_tready , + input wire s11_axis_tvalid , + input wire [B-1:0] s11_axis_tdata , + + output wire s12_axis_tready , + input wire s12_axis_tvalid , + input wire [B-1:0] s12_axis_tdata , + + output wire s13_axis_tready , + input wire s13_axis_tvalid , + input wire [B-1:0] s13_axis_tdata , + + output wire s14_axis_tready , + input wire s14_axis_tvalid , + input wire [B-1:0] s14_axis_tdata , + + output wire s15_axis_tready , + input wire s15_axis_tvalid , + input wire [B-1:0] s15_axis_tdata , + + // M_AXIS for output data. + input wire m_axis_aresetn , + input wire m_axis_aclk , + + input wire m0_axis_tready , + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + input wire m1_axis_tready , + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + input wire m2_axis_tready , + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + input wire m3_axis_tready , + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + input wire m4_axis_tready , + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + input wire m5_axis_tready , + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + input wire m6_axis_tready , + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + input wire m7_axis_tready , + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata , + + input wire m8_axis_tready , + output wire m8_axis_tvalid , + output wire [B-1:0] m8_axis_tdata , + + input wire m9_axis_tready , + output wire m9_axis_tvalid , + output wire [B-1:0] m9_axis_tdata , + + input wire m10_axis_tready , + output wire m10_axis_tvalid , + output wire [B-1:0] m10_axis_tdata , + + input wire m11_axis_tready , + output wire m11_axis_tvalid , + output wire [B-1:0] m11_axis_tdata , + + input wire m12_axis_tready , + output wire m12_axis_tvalid , + output wire [B-1:0] m12_axis_tdata , + + input wire m13_axis_tready , + output wire m13_axis_tvalid , + output wire [B-1:0] m13_axis_tdata , + + input wire m14_axis_tready , + output wire m14_axis_tvalid , + output wire [B-1:0] m14_axis_tdata , + + input wire m15_axis_tready , + output wire m15_axis_tvalid , + output wire [B-1:0] m15_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Total bits. +localparam BD = B + 1; +localparam BT = N*BD; + +// Input data to vector. +wire [B-1:0] din_data_v [16] ; +wire [15:0] din_valid_v ; +wire [15:0] din_ready_v ; + +// Output vector to data. +wire [B-1:0] dout_data_v [16] ; +wire [15:0] dout_valid_v ; +wire [15:0] dout_ready_v ; + +wire fifo_wr_en ; +wire [BT-1:0] fifo_din ; +wire [BT-1:0] fifo_dout ; +wire fifo_full ; +wire fifo_empty ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Input data to vector. +assign din_data_v [0] = s0_axis_tdata ; +assign din_data_v [1] = s1_axis_tdata ; +assign din_data_v [2] = s2_axis_tdata ; +assign din_data_v [3] = s3_axis_tdata ; +assign din_data_v [4] = s4_axis_tdata ; +assign din_data_v [5] = s5_axis_tdata ; +assign din_data_v [6] = s6_axis_tdata ; +assign din_data_v [7] = s7_axis_tdata ; +assign din_data_v [8] = s8_axis_tdata ; +assign din_data_v [9] = s9_axis_tdata ; +assign din_data_v [10] = s10_axis_tdata ; +assign din_data_v [11] = s11_axis_tdata ; +assign din_data_v [12] = s12_axis_tdata ; +assign din_data_v [13] = s13_axis_tdata ; +assign din_data_v [14] = s14_axis_tdata ; +assign din_data_v [15] = s15_axis_tdata ; + +assign din_valid_v [0] = s0_axis_tvalid && N >= 1; +assign din_valid_v [1] = s1_axis_tvalid && N >= 2; +assign din_valid_v [2] = s2_axis_tvalid && N >= 3; +assign din_valid_v [3] = s3_axis_tvalid && N >= 4; +assign din_valid_v [4] = s4_axis_tvalid && N >= 5; +assign din_valid_v [5] = s5_axis_tvalid && N >= 6; +assign din_valid_v [6] = s6_axis_tvalid && N >= 7; +assign din_valid_v [7] = s7_axis_tvalid && N >= 8; +assign din_valid_v [8] = s8_axis_tvalid && N >= 9; +assign din_valid_v [9] = s9_axis_tvalid && N >= 10; +assign din_valid_v [10] = s10_axis_tvalid && N >= 11; +assign din_valid_v [11] = s11_axis_tvalid && N >= 12; +assign din_valid_v [12] = s12_axis_tvalid && N >= 13; +assign din_valid_v [13] = s13_axis_tvalid && N >= 14; +assign din_valid_v [14] = s14_axis_tvalid && N >= 15; +assign din_valid_v [15] = s15_axis_tvalid && N >= 16; + +assign s0_axis_tready = din_ready_v [0] ; +assign s1_axis_tready = din_ready_v [1] ; +assign s2_axis_tready = din_ready_v [2] ; +assign s3_axis_tready = din_ready_v [3] ; +assign s4_axis_tready = din_ready_v [4] ; +assign s5_axis_tready = din_ready_v [5] ; +assign s6_axis_tready = din_ready_v [6] ; +assign s7_axis_tready = din_ready_v [7] ; +assign s8_axis_tready = din_ready_v [8] ; +assign s9_axis_tready = din_ready_v [9] ; +assign s10_axis_tready = din_ready_v [10]; +assign s11_axis_tready = din_ready_v [11]; +assign s12_axis_tready = din_ready_v [12]; +assign s13_axis_tready = din_ready_v [13]; +assign s14_axis_tready = din_ready_v [14]; +assign s15_axis_tready = din_ready_v [15]; + +assign din_ready_v [0] = ~fifo_full || N < 1; +assign din_ready_v [1] = ~fifo_full || N < 2; +assign din_ready_v [2] = ~fifo_full || N < 3; +assign din_ready_v [3] = ~fifo_full || N < 4; +assign din_ready_v [4] = ~fifo_full || N < 5; +assign din_ready_v [5] = ~fifo_full || N < 6; +assign din_ready_v [6] = ~fifo_full || N < 7; +assign din_ready_v [7] = ~fifo_full || N < 8; +assign din_ready_v [8] = ~fifo_full || N < 9; +assign din_ready_v [9] = ~fifo_full || N < 10; +assign din_ready_v [10] = ~fifo_full || N < 11; +assign din_ready_v [11] = ~fifo_full || N < 12; +assign din_ready_v [12] = ~fifo_full || N < 13; +assign din_ready_v [13] = ~fifo_full || N < 14; +assign din_ready_v [14] = ~fifo_full || N < 15; +assign din_ready_v [15] = ~fifo_full || N < 16; + +// Output vector to data. +assign m0_axis_tdata = dout_data_v [0] ; +assign m1_axis_tdata = dout_data_v [1] ; +assign m2_axis_tdata = dout_data_v [2] ; +assign m3_axis_tdata = dout_data_v [3] ; +assign m4_axis_tdata = dout_data_v [4] ; +assign m5_axis_tdata = dout_data_v [5] ; +assign m6_axis_tdata = dout_data_v [6] ; +assign m7_axis_tdata = dout_data_v [7] ; +assign m8_axis_tdata = dout_data_v [8] ; +assign m9_axis_tdata = dout_data_v [9] ; +assign m10_axis_tdata = dout_data_v [10] ; +assign m11_axis_tdata = dout_data_v [11] ; +assign m12_axis_tdata = dout_data_v [12] ; +assign m13_axis_tdata = dout_data_v [13] ; +assign m14_axis_tdata = dout_data_v [14] ; +assign m15_axis_tdata = dout_data_v [15] ; + +assign m0_axis_tvalid = dout_valid_v [0] & ~fifo_empty; +assign m1_axis_tvalid = dout_valid_v [1] & ~fifo_empty; +assign m2_axis_tvalid = dout_valid_v [2] & ~fifo_empty; +assign m3_axis_tvalid = dout_valid_v [3] & ~fifo_empty; +assign m4_axis_tvalid = dout_valid_v [4] & ~fifo_empty; +assign m5_axis_tvalid = dout_valid_v [5] & ~fifo_empty; +assign m6_axis_tvalid = dout_valid_v [6] & ~fifo_empty; +assign m7_axis_tvalid = dout_valid_v [7] & ~fifo_empty; +assign m8_axis_tvalid = dout_valid_v [8] & ~fifo_empty; +assign m9_axis_tvalid = dout_valid_v [9] & ~fifo_empty; +assign m10_axis_tvalid = dout_valid_v [10] & ~fifo_empty; +assign m11_axis_tvalid = dout_valid_v [11] & ~fifo_empty; +assign m12_axis_tvalid = dout_valid_v [12] & ~fifo_empty; +assign m13_axis_tvalid = dout_valid_v [13] & ~fifo_empty; +assign m14_axis_tvalid = dout_valid_v [14] & ~fifo_empty; +assign m15_axis_tvalid = dout_valid_v [15] & ~fifo_empty; + +assign dout_ready_v [0] = m0_axis_tready || N < 1; +assign dout_ready_v [1] = m1_axis_tready || N < 2; +assign dout_ready_v [2] = m2_axis_tready || N < 3; +assign dout_ready_v [3] = m3_axis_tready || N < 4; +assign dout_ready_v [4] = m4_axis_tready || N < 5; +assign dout_ready_v [5] = m5_axis_tready || N < 6; +assign dout_ready_v [6] = m6_axis_tready || N < 7; +assign dout_ready_v [7] = m7_axis_tready || N < 8; +assign dout_ready_v [8] = m8_axis_tready || N < 9; +assign dout_ready_v [9] = m9_axis_tready || N < 10; +assign dout_ready_v [10] = m10_axis_tready || N < 11; +assign dout_ready_v [11] = m11_axis_tready || N < 12; +assign dout_ready_v [12] = m12_axis_tready || N < 13; +assign dout_ready_v [13] = m13_axis_tready || N < 14; +assign dout_ready_v [14] = m14_axis_tready || N < 15; +assign dout_ready_v [15] = m15_axis_tready || N < 16; + + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd similarity index 80% rename from firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd rename to firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd index eb83d1a5d..e1f76f7f7 100644 --- a/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd @@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; use IEEE.NUMERIC_STD.ALL; -entity fifo_dc_axi is +entity fifo_axi is Generic ( -- Data width. @@ -14,12 +14,9 @@ entity fifo_dc_axi is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -32,12 +29,12 @@ entity fifo_dc_axi is full : out std_logic; empty : out std_logic ); -end fifo_dc_axi; +end fifo_axi; -architecture rtl of fifo_dc_axi is +architecture rtl of fifo_axi is --- Dual-clock FIFO. -component fifo_dc is +-- FIFO. +component fifo is Generic ( -- Data width. @@ -48,12 +45,9 @@ component fifo_dc is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -98,8 +92,8 @@ signal empty_i : std_logic; begin --- Dual-clock FIFO. -fifo_i : fifo_dc +-- FIFO. +fifo_i : fifo Generic map ( -- Data width. @@ -110,12 +104,9 @@ fifo_i : fifo_dc ) Port map ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , + rstn => rstn , + clk => clk , - rd_rstn => rd_rstn , - rd_clk => rd_clk , - -- Write I/F. wr_en => wr_en , din => din , @@ -138,8 +129,8 @@ rd2axi_i : rd2axi ) Port map ( - rstn => rd_rstn , - clk => rd_clk , + rstn => rstn , + clk => clk , -- FIFO Read I/F. fifo_rd_en => rd_en_i , diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl b/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl new file mode 100644 index 000000000..f41c02824 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + diff --git a/firmware/ip/axis_constant/component.xml b/firmware/ip/axis_constant/component.xml index 7347f1e7d..e5db7e36a 100644 --- a/firmware/ip/axis_constant/component.xml +++ b/firmware/ip/axis_constant/component.xml @@ -1,7 +1,7 @@ - user.org - user + QICK + QICK axis_constant 1.0 @@ -150,6 +150,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -295,6 +309,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS Constant IP to properly terminate inputs. @@ -335,10 +356,12 @@ kintexu - /UserIP + /QICK/AXI_Peripheral AXIS Constant package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ 2 2021-06-10T13:34:21Z diff --git a/firmware/ip/axis_constant_iq/component.xml b/firmware/ip/axis_constant_iq/component.xml new file mode 100644 index 000000000..39bce7ef9 --- /dev/null +++ b/firmware/ip/axis_constant_iq/component.xml @@ -0,0 +1,909 @@ + + + QICK + QICK + axis_constant_iq + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_constant_iq + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 05173ec9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_constant_iq + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 05173ec9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + B + B + 16 + + + N + N + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axi_slv.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_constant_iq.vhd + vhdlSource + CHECKSUM_d08b65cf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axi_slv.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_constant_iq.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_constant_iq_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Constant IQ with parallel outputs for DAC. + + + B + B + 16 + + + N + N + 4 + + + Component_Name + axis_constant_iq_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /QICK/AXI_Peripheral + + AXIS Constant IQ + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + 2021-09-02T14:55:11Z + + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + + + + 2019.1 + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..5f3313504 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..5c4d9a9f7 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..34f0b1287 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..0a6987bec --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4751 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + 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xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_slv.vhd b/firmware/ip/axis_constant_iq/src/axi_slv.vhd new file mode 100644 index 000000000..208a6d4bf --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_slv.vhd @@ -0,0 +1,517 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + REAL_REG : out std_logic_vector (31 downto 0); + IMAG_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + REAL_REG <= slv_reg0(31 downto 0); + IMAG_REG <= slv_reg1(31 downto 0); + WE_REG <= slv_reg2(0); + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd b/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd new file mode 100644 index 000000000..616a40838 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd @@ -0,0 +1,219 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity axis_constant_iq is + Generic + ( + -- Number of bits of I/Q. + B : Integer := 16; + -- Number of parallel outputs. + N : Integer := 4 + ); + Port + ( + -- AXI-Lite Slave I/F. + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + + s_axi_awaddr : in std_logic_vector(5 downto 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + + s_axi_araddr : in std_logic_vector(5 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + + -- AXIS Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tdata : out std_logic_vector(2*B*N-1 downto 0); + m_axis_tvalid : out std_logic + ); +end axis_constant_iq; + +architecture rtl of axis_constant_iq is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- AXI Slave. +component axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + REAL_REG : out std_logic_vector (31 downto 0); + IMAG_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end component; + +-- Number of bits of IQ combined. +constant BIQ : Integer := 2*B; + +-- Registers. +signal REAL_REG : std_logic_vector (31 downto 0); +signal IMAG_REG : std_logic_vector (31 downto 0); +signal WE_REG : std_logic; + +-- we. +signal we : std_logic; +signal we_r : std_logic; +signal we_int : std_logic; + +-- i/q. +signal real_r : std_logic_vector (B-1 downto 0); +signal imag_r : std_logic_vector (B-1 downto 0); + +begin + +-- Synchronizer. +WE_REG_resync_i : synchronizer_n + port map ( + rstn => m_axis_aresetn , + clk => m_axis_aclk , + data_in => WE_REG , + data_out => we + ); + +-- AXI Slave. +axi_slv_i : axi_slv + Port map + ( + aclk => s_axi_aclk , + aresetn => s_axi_aresetn , + + -- Write Address Channel. + awaddr => s_axi_awaddr , + awprot => s_axi_awprot , + awvalid => s_axi_awvalid , + awready => s_axi_awready , + + -- Write Data Channel. + wdata => s_axi_wdata , + wstrb => s_axi_wstrb , + wvalid => s_axi_wvalid , + wready => s_axi_wready , + + -- Write Response Channel. + bresp => s_axi_bresp , + bvalid => s_axi_bvalid , + bready => s_axi_bready , + + -- Read Address Channel. + araddr => s_axi_araddr , + arprot => s_axi_arprot , + arvalid => s_axi_arvalid , + arready => s_axi_arready , + + -- Read Data Channel. + rdata => s_axi_rdata , + rresp => s_axi_rresp , + rvalid => s_axi_rvalid , + rready => s_axi_rready , + + -- Registers. + REAL_REG => REAL_REG , + IMAG_REG => IMAG_REG , + WE_REG => WE_REG + ); + +process (m_axis_aclk) +begin + if (rising_edge(m_axis_aclk)) then + if ( m_axis_aresetn = '0' ) then + -- we. + we_r <= '0'; + + -- i/q. + real_r <= (others => '0'); + imag_r <= (others => '0'); + else + -- we. + we_r <= we; + + -- i/q. + if (we_int = '1') then + real_r <= REAL_REG(B-1 downto 0); + imag_r <= IMAG_REG(B-1 downto 0); + end if; + end if; + end if; +end process; + +-- we generation. +we_int <= not(we_r) and we; + +-- Output generation. +GEN_OUT: for I in 0 to N-1 generate + m_axis_tdata ( B + BIQ*I-1 downto BIQ*I ) <= real_r; + m_axis_tdata (2*B + BIQ*I-1 downto BIQ*I + B ) <= imag_r; +end generate GEN_OUT; + +m_axis_tvalid <= '1'; + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd b/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd new file mode 100644 index 000000000..a29bd9be1 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/tb.sv b/firmware/ip/axis_constant_iq/src/tb.sv new file mode 100644 index 000000000..9ed93fc9f --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/tb.sv @@ -0,0 +1,198 @@ +// VIP: axi_mst_0 +// DUT: axis_chsel_pfb +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter B = 16; +parameter N = 8; + +// s_axi interfase. +reg s_axi_aclk; +wire [5:0] s_axi_araddr; +reg s_axi_aresetn; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// m_axis interfase. +reg m_axis_aclk; +reg m_axis_aresetn; +wire [2*B*N-1:0] m_axis_tdata; +wire m_axis_tvalid; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data_rd; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_start; + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk), + .aresetn (s_axi_aresetn), + .m_axi_araddr (s_axi_araddr), + .m_axi_arprot (s_axi_arprot), + .m_axi_arready (s_axi_arready), + .m_axi_arvalid (s_axi_arvalid), + .m_axi_awaddr (s_axi_awaddr), + .m_axi_awprot (s_axi_awprot), + .m_axi_awready (s_axi_awready), + .m_axi_awvalid (s_axi_awvalid), + .m_axi_bready (s_axi_bready), + .m_axi_bresp (s_axi_bresp), + .m_axi_bvalid (s_axi_bvalid), + .m_axi_rdata (s_axi_rdata), + .m_axi_rready (s_axi_rready), + .m_axi_rresp (s_axi_rresp), + .m_axi_rvalid (s_axi_rvalid), + .m_axi_wdata (s_axi_wdata), + .m_axi_wready (s_axi_wready), + .m_axi_wstrb (s_axi_wstrb), + .m_axi_wvalid (s_axi_wvalid) + ); + +axis_constant_iq + #( + .B(B), + .N(N) + ) + axis_constant_iq + ( + // s_axi interfase. + .s_axi_aclk (s_axi_aclk), + .s_axi_araddr (s_axi_araddr), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_arprot (s_axi_arprot), + .s_axi_arready (s_axi_arready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_awready (s_axi_awready), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_wdata (s_axi_wdata), + .s_axi_wready (s_axi_wready), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + + // m_axis interfase. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tvalid (m_axis_tvalid ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + /* ************* */ + /* Main TB Start */ + /* ************* */ + + // Reset sequence. + s_axi_aresetn <= 0; + m_axis_aresetn <= 0; + tb_start <= 0; + #500; + s_axi_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + // Start data. + tb_start <= 1; + + // REAL_REG + data_wr = 123; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // IMAG_REG + data_wr = 14; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + #1000; + + // REAL_REG + data_wr = 55; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // IMAG_REG + data_wr = 66; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; +end + +endmodule + diff --git a/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl b/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl new file mode 100644 index 000000000..1717489f3 --- /dev/null +++ b/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_dyn_readout_v1/component.xml b/firmware/ip/axis_dyn_readout_v1/component.xml new file mode 100644 index 000000000..d331d37a8 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/component.xml @@ -0,0 +1,669 @@ + + + QICK + QICK + axis_dyn_readout_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + + true + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:s0_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis + + + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + TDATA + + + s0_axis_tdata + + + + + + s1_axis + + + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + TDATA + + + s1_axis_tdata + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_dyn_readout_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b20c0562 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_dyn_readout_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b20c0562 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f835ce2d + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 87 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir.coe + coe + + + src/fir_compiler_0/fir_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl_dyn_ro_v1.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_dyn_readout_v1.v + verilogSource + CHECKSUM_6896ccdb + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir.coe + coe + + + src/fir_compiler_0/fir_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl_dyn_ro_v1.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_dyn_readout_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_dyn_readout_v1_v1_0.tcl + tclSource + CHECKSUM_f835ce2d + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS readout block with digital down-conversion (32-bit, phase coherent), filtering and 8x decimation, configured through AXIS + + + Component_Name + axis_dyn_readout_v1_v1_0 + + + FULLSPEED_OUTPUT + Fullspeed Output + true + + + + + + zynquplus + + + /QICK/Readout + + AXIS Dynamic Readout V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 4 + 2025-09-11T21:42:36Z + + /home/meeg/Soft/qick/firmware/ip/axis_dyn_readout_v1 + + + + 2023.1 + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v b/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v new file mode 100644 index 000000000..3591d5813 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v @@ -0,0 +1,105 @@ +module axis_dyn_readout_v1 + ( + + // Reset and clock (s_axis, m0_axis, m1_axis). + aresetn , + aclk , + + // s0_axis: for pushing configurations. + s0_axis_tready , + s0_axis_tvalid , + s0_axis_tdata , + + // s0_axis: for input data (8x samples per clock). + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ + +input aresetn; +input aclk; + +output s0_axis_tready; +input s0_axis_tvalid; +input [87:0] s0_axis_tdata; + +output s1_axis_tready; +input s1_axis_tvalid; +input [N_DDS*16-1:0] s1_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ + +// Fifo. +wire fifo_wr_en ; +wire [87:0] fifo_din ; +wire fifo_full ; + +// Fifo connections. +assign fifo_wr_en = s0_axis_tvalid; +assign fifo_din = s0_axis_tdata; + +// Readout Top. +readout_top readout_top_i + ( + // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_wr_en (fifo_wr_en ), + .fifo_full (fifo_full ), + .fifo_din (fifo_din ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s1_axis_tdata ), + .s_axis_tvalid (s1_axis_tvalid ), + .s_axis_tready (s1_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ) + ); + +// Assign outputs. +assign s0_axis_tready = ~fifo_full; + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/ctrl_dyn_ro_v1.sv b/firmware/ip/axis_dyn_readout_v1/src/ctrl_dyn_ro_v1.sv new file mode 100644 index 000000000..6f9841c06 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/ctrl_dyn_ro_v1.sv @@ -0,0 +1,377 @@ +//Format of waveform interface: +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// phrst : 1 bit +module ctrl_dyn_ro_v1 + #( + parameter N = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // Fifo interface. + output wire fifo_rd_en , + input wire fifo_empty , + input wire [87:0] fifo_dout , + + // dds control. + output wire [N*72-1:0] dds_ctrl , + + // Output source selection. + output wire [1:0] outsel + + // Output enable. +// output wire en + ); + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [87:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [N]; +reg [31:0] phase_v0_r1 [N]; +reg [31:0] phase_v0_r2 [N]; +reg [31:0] phase_v0_r3 [N]; +reg [31:0] phase_v0_r4 [N]; +wire [31:0] phase_v1 [N]; +reg [31:0] phase_v1_r1 [N]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +//reg en_reg; +//reg en_reg_r1; +//reg en_reg_r2; +//reg en_reg_r3; +//reg en_reg_r4; +//reg en_reg_r5; +//reg en_reg_r6; +//reg en_reg_r7; +//reg en_reg_r8; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. +// en_reg <= 0; +// en_reg_r1 <= 0; +// en_reg_r2 <= 0; +// en_reg_r3 <= 0; +// en_reg_r4 <= 0; +// en_reg_r5 <= 0; +// en_reg_r6 <= 0; +// en_reg_r7 <= 0; +// en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. +// if (~mode_int && rd_en_int) +// if (~fifo_empty) +// en_reg <= 1; +// else +// en_reg <= 0; + +// en_reg_r1 <= en_reg; +// en_reg_r2 <= en_reg_r1; +// en_reg_r3 <= en_reg_r2; +// en_reg_r4 <= en_reg_r3; +// en_reg_r5 <= en_reg_r4; +// en_reg_r6 <= en_reg_r5; +// en_reg_r7 <= en_reg_r6; +// en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign phrst_int = fifo_dout_r[83]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge aclk) begin + if (~aresetn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty; + +// Assign outputs. +assign fifo_rd_en = rd_en_int; +assign outsel = outsel_r7; +//assign en = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..7bf3bc5ed --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..8bdeb4aa1 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..3c5321ff6 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,358 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "dds_compiler_0", + "cell_name": "readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i", + "component_reference": "xilinx.com:ip:dds_compiler:6.0", + "ip_revision": "22", + "gen_directory": "../../../../projects/qick_tprocv2_216_demo/top/top.tmp/axis_dyn_readout_v1_v1_0_project/axis_dyn_readout_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "dds_compiler_0", "resolve_type": "user", "usage": "all" } ], + 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10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + + + choice_pairs_0079eeec + Twos_Complement + Sign_and_Magnitude + + + choice_pairs_27d1d409 + Auto + Distributed_ROM + Block_ROM + + + choice_pairs_65a5252d + Full_Range + Unit_Circle + + + choice_pairs_6bdc34ae + System_Parameters + Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 8 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v b/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v new file mode 100644 index 000000000..9cbc9b018 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v @@ -0,0 +1,230 @@ +module down_conversion ( + // Reset and clock. + rstn , + clk , + + // S_AXIS for input. + s_axis_tready_o , + s_axis_tvalid_i , + s_axis_tdata_i , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [15:0] N_DDS = 16; + +// 0.5 for rounding. +localparam [31:0] RND_0P5 = 2**15; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output s_axis_tready_o; +input s_axis_tvalid_i; +input [N_DDS*16-1:0] s_axis_tdata_i; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*32-1:0] m_axis_tdata_o; + +output fifo_rd_en_o; +input fifo_empty_i; +input [87:0] fifo_dout_i; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// Output selection. +wire [1:0] outsel_int; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +reg [31:0] dds_dout_r1 [0:N_DDS-1]; +reg [31:0] dds_dout_r2 [0:N_DDS-1]; +reg [31:0] dds_dout_r3 [0:N_DDS-1]; +reg [31:0] dds_dout_r4 [0:N_DDS-1]; + +// Input data. +reg [15:0] din_r1 [0:N_DDS-1]; +reg signed [15:0] din_r2 [0:N_DDS-1]; +reg [15:0] din_r3 [0:N_DDS-1]; +reg [15:0] din_r4 [0:N_DDS-1]; + +// Product. +wire signed [15:0] pa_real [0:N_DDS-1]; +wire signed [15:0] pa_imag [0:N_DDS-1]; +wire signed [31:0] py_full_real [0:N_DDS-1]; +wire signed [31:0] py_full_imag [0:N_DDS-1]; +reg signed [31:0] py_full_real_r [0:N_DDS-1]; +reg signed [31:0] py_full_imag_r [0:N_DDS-1]; +wire signed [31:0] py_round_real [0:N_DDS-1]; +wire signed [31:0] py_round_imag [0:N_DDS-1]; +wire [15:0] py_real [0:N_DDS-1]; +wire [15:0] py_imag [0:N_DDS-1]; +wire [31:0] py [0:N_DDS-1]; +reg [31:0] py_r [0:N_DDS-1]; + +// Muxed output. +wire [31:0] dout_mux [0:N_DDS-1]; +reg [31:0] dout_mux_r [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// `uselib lib=lib_axis_dyn_readout_v1 +// Control block. +ctrl_dyn_ro_v1 + #( + .N (N_DDS ) + ) + ctrl_i + ( + // Reset and clock. + .aresetn (rstn ), + .aclk (clk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en_o ), + .fifo_empty (fifo_empty_i ), + .fifo_dout (fifo_dout_i ), + + // dds control. + .dds_ctrl (dds_ctrl_int ), + + // Output source selection. + .outsel (outsel_int ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd similarity index 80% rename from firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd rename to firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd index eb83d1a5d..e1f76f7f7 100644 --- a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd @@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; use IEEE.NUMERIC_STD.ALL; -entity fifo_dc_axi is +entity fifo_axi is Generic ( -- Data width. @@ -14,12 +14,9 @@ entity fifo_dc_axi is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -32,12 +29,12 @@ entity fifo_dc_axi is full : out std_logic; empty : out std_logic ); -end fifo_dc_axi; +end fifo_axi; -architecture rtl of fifo_dc_axi is +architecture rtl of fifo_axi is --- Dual-clock FIFO. -component fifo_dc is +-- FIFO. +component fifo is Generic ( -- Data width. @@ -48,12 +45,9 @@ component fifo_dc is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -98,8 +92,8 @@ signal empty_i : std_logic; begin --- Dual-clock FIFO. -fifo_i : fifo_dc +-- FIFO. +fifo_i : fifo Generic map ( -- Data width. @@ -110,12 +104,9 @@ fifo_i : fifo_dc ) Port map ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , + rstn => rstn , + clk => clk , - rd_rstn => rd_rstn , - rd_clk => rd_clk , - -- Write I/F. wr_en => wr_en , din => din , @@ -138,8 +129,8 @@ rd2axi_i : rd2axi ) Port map ( - rstn => rd_rstn , - clk => rd_clk , + rstn => rstn , + clk => clk , -- FIFO Read I/F. fifo_rd_en => rd_en_i , diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir.coe b/firmware/ip/axis_dyn_readout_v1/src/fir.coe new file mode 100644 index 000000000..458482dbc --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -56,-4,13,47,97,166,252,353,463,573,674,754,801,804,753,643,473,249,-20,-314,-611,-885,-1107,-1248,-1285,-1201,-989,-651,-206,318,878,1425,1903,2254,2428,2383,2094,1556,786,-172,-1251,-2364,-3408,-4271,-4839,-5010,-4696,-3838,-2410,-422,2076,4993,8205,11560,14889,18012,20758,22971,24523,25322,25322,24523,22971,20758,18012,14889,11560,8205,4993,2076,-422,-2410,-3838,-4696,-5010,-4839,-4271,-3408,-2364,-1251,-172,786,1556,2094,2383,2428,2254,1903,1425,878,318,-206,-651,-989,-1201,-1285,-1248,-1107,-885,-611,-314,-20,249,473,643,753,804,801,754,674,573,463,353,252,166,97,47,13,-4,-56 \ No newline at end of file diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v new file mode 100644 index 000000000..aab131139 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v @@ -0,0 +1,15 @@ +module fir_compiler_0 + ( + input aclk , + input s_axis_data_tvalid , + output s_axis_data_tready , + input [255:0] s_axis_data_tdata , + output m_axis_data_tvalid , + output [31:0] m_axis_data_tdata +); + +assign s_axis_data_tready = 1'b1; +assign m_axis_data_tvalid = s_axis_data_tvalid; +assign m_axis_data_tdata = s_axis_data_tdata[31:0]; + +endmodule diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo new file mode 100644 index 000000000..e66a3e880 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [255 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_compiler_0.v when simulating +// the core, fir_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho new file mode 100644 index 000000000..a87716732 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_compiler_0.vhd when simulating +-- the core, fir_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci new file mode 100644 index 000000000..b157ab253 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci @@ -0,0 +1,351 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "fir_compiler_0", + "component_reference": "xilinx.com:ip:fir_compiler:7.2", + "ip_revision": "19", + "gen_directory": "../../../../qick_fw_sho/qick_tprocv2_216_kidsim/top/top.tmp/axis_dyn_readout_v1_v1_0_project/axis_dyn_readout_v1_v1_0_project.gen/sources_1/ip/fir_compiler_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "fir_compiler_0", "resolve_type": "user", "usage": "all" } ], + "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ], + 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-0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_OP_PATH_PSAMP_SRC + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_NUM_MADDS + 60 + + + C_OPT_MADDS + none + + + C_OVERSAMPLING_RATE + 1 + + + C_INPUT_RATE + 1 + + + C_OUTPUT_RATE + 1 + + + C_DATA_MEMTYPE + 0 + + + C_COEF_MEMTYPE + 2 + + + C_IPBUFF_MEMTYPE + 2 + + + C_OPBUFF_MEMTYPE + 0 + + + C_DATAPATH_MEMTYPE + 2 + + + C_MEM_ARRANGEMENT + 1 + + + C_DATA_MEM_PACKING + 0 + + + C_COEF_MEM_PACKING + 0 + + + C_FILTS_PACKED + 0 + + + C_LATENCY + 67 + + + C_HAS_ARESETn + 0 + + + C_HAS_ACLKEN + 0 + + + C_DATA_HAS_TLAST + 0 + + + C_S_DATA_HAS_FIFO + 0 + + + C_S_DATA_HAS_TUSER + 0 + + + C_S_DATA_TDATA_WIDTH + 256 + + + C_S_DATA_TUSER_WIDTH + 1 + + + C_M_DATA_HAS_TREADY + 0 + + + C_M_DATA_HAS_TUSER + 0 + + + C_M_DATA_TDATA_WIDTH + 32 + + + C_M_DATA_TUSER_WIDTH + 1 + + + C_HAS_CONFIG_CHANNEL + 0 + + + C_CONFIG_SYNC_MODE + 0 + + + C_CONFIG_PACKET_SIZE + 0 + + + C_CONFIG_TDATA_WIDTH + 1 + + + C_RELOAD_TDATA_WIDTH + 1 + + + + + + choice_list_0dc4ca8f + Automatic + Custom + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_3f660234 + All + + + choice_list_5e9d103c + Signed + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_a63914d2 + Area + Speed + Custom + + + choice_list_dd381b21 + Automatic + Block + Distributed + + + choice_pairs_18e22ec6 + Full_Precision + Truncate_LSBs + Non_Symmetric_Rounding_Down + Non_Symmetric_Rounding_Up + Symmetric_Rounding_to_Zero + Symmetric_Rounding_to_Infinity + Convergent_Rounding_to_Even + Convergent_Rounding_to_Odd + + + choice_pairs_2074757d + None + All + Data_Path_Fanout + Pre-Adder_Pipeline + Coefficient_Fanout + Control_Path_Fanout + Control_Column_Fanout + Control_Broadcast_Fanout + Control_LUT_Pipeline + No_BRAM_Read_First_Mode + Optimal_Column_Lengths + Data_Path_Broadcast + Disable_Half_Band_Centre_Tap + No_SRL_Attributes + Other + + + choice_pairs_2b265cc8 + Frequency_Specification + Input_Sample_Period + Output_Sample_Period + + + choice_pairs_3ab545a3 + Not_Required + Chan_ID_Field + + + choice_pairs_480f8ce0 + Not_Required + Packet_Framing + + + choice_pairs_541959c1 + Inferred + Non_Symmetric + Symmetric + + + choice_pairs_74144f21 + COE_File + Vector + + + choice_pairs_789dfe7d + Single_Rate + Interpolation + Decimation + Hilbert + Interpolated + + + choice_pairs_8e2d2e35 + Not_Required + User_Field + + + choice_pairs_ab4ea833 + Systolic_Multiply_Accumulate + + + choice_pairs_b6c64168 + Single + By_Channel + + + choice_pairs_eb2746f0 + Integer + Fixed_Fractional + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + choice_pairs_fd92e388 + Integer_Coefficients + Quantize_Only + Maximize_Dynamic_Range + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + fir_compiler_0.vho + vhdlTemplate + + + fir_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_compiler_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + fir_compiler_v7_2_15 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/fir_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_compiler_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + ../fir.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Decimation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 1 + + + Decimation_Rate + 8 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Output_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Integer_Coefficients + + + Coefficient_Width + 16 + + + BestPrecision + false + + + Coefficient_Fractional_Bits + 0 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Zero + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 60 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/readout_top.v b/firmware/ip/axis_dyn_readout_v1/src/readout_top.v new file mode 100644 index 000000000..185b61b3e --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/readout_top.v @@ -0,0 +1,167 @@ +module readout_top + ( + // Reset and clock. + aresetn , + aclk , + + // Fifo interface. + fifo_wr_en , + fifo_full , + fifo_din , + + // S1_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + + // Registers. +// FREQ_REG , +// PHASE_REG , +// NSAMP_REG , +// OUTSEL_REG , +// MODE_REG , +// WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input fifo_wr_en; +output fifo_full; +input [87:0] fifo_din; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +//input [31:0] FREQ_REG; +//input [31:0] PHASE_REG; +//input [15:0] NSAMP_REG; +//input [1:0] OUTSEL_REG; +//input MODE_REG; +//input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +//wire we; +//reg we_r; + +wire fifo_wr_en; +wire [87:0] fifo_din; +wire fifo_rd_en; +wire [87:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// WE_REG sync. +//synchronizer_n +// WE_REG_resync_i +// ( +// .rstn (aresetn ), +// .clk (aclk ), +// .data_in (WE_REG ), +// .data_out (we ) +// ); + +// Down-conversion + Filter + Decimation. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .rstn (aresetn ), + .clk (aclk ), + + // S_AXIS for input. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M0_AXIS for output data (before filter and decimation). + .m0_axis_tready_i (m0_axis_tready ), + .m0_axis_tvalid_o (m0_axis_tvalid ), + .m0_axis_tdata_o (m0_axis_tdata ), + + // M1_AXIS for output data. + .m1_axis_tready_i (m1_axis_tready ), + .m1_axis_tvalid_o (m1_axis_tvalid ), + .m1_axis_tdata_o (m1_axis_tdata ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en ), + .fifo_empty_i (fifo_empty ), + .fifo_dout_i (fifo_dout ) + ); + +// Fifo for queuing waveforms. +fifo + #( + // Data width. + .B (88), + + // Fifo depth. + .N (8) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +//assign fifo_wr_en = we & ~we_r; +//assign fifo_din = {MODE_REG,OUTSEL_REG,NSAMP_REG,PHASE_REG,FREQ_REG}; + +//always @(posedge aclk) begin +// if (~aresetn) +// we_r <= 0; +// else +// we_r <= we; +//end + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv b/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv new file mode 100644 index 000000000..635fc27aa --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv @@ -0,0 +1,265 @@ +module tb(); + +localparam N = 8; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// s0_axis for pushing waveforms. +wire s0_axis_tready ; +reg s0_axis_tvalid ; +reg [87:0] s0_axis_tdata ; + +// s1_axis for input data (8 real samples per clock). +wire s1_axis_tready ; +reg s1_axis_tvalid ; +wire[N*16-1:0] s1_axis_tdata ; + +// m0_axis for output data (8 complex samples per clock). +reg m0_axis_tready ; +wire m0_axis_tvalid ; +wire[255:0] m0_axis_tdata ; + +// m1_axis for output data (1 complex sample per clock). +reg m1_axis_tready ; +wire m1_axis_tvalid ; +wire[31:0] m1_axis_tdata ; + +// Waveform parameters. +reg [31:0] freq_r ; +reg [31:0] phase_r ; +reg [15:0] nsamp_r ; +reg [1:0] outsel_r ; +reg mode_r ; +reg phrst_r ; +reg [3:0] zero_r ; + +// Input data. +reg [15:0] din_r [N] ; + +// Output full-speed data. +reg [31:0] dout_r_f [N] ; + +// Output data. +wire[15:0] dout_real ; +wire[15:0] dout_imag ; + +// Fast clock for parallel/serial conversion. +reg aclk_f ; +reg [15:0] din_r_f ; +reg [15:0] dout_real_f ; +reg [15:0] dout_imag_f ; + +// Test bench control. +reg tb_wave = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N; ii = ii + 1) begin : GEN_debug + assign s1_axis_tdata [ii*16 +: 16] = din_r[ii]; + assign dout_r_f[ii] = m0_axis_tdata[ii*32 +: 32]; +end +endgenerate + +assign dout_real = m1_axis_tdata[0 +: 16]; +assign dout_imag = m1_axis_tdata[16 +: 16]; + +assign s0_axis_tdata = {zero_r,phrst_r,mode_r,outsel_r,nsamp_r,phase_r,freq_r}; + +// DUT. +axis_dyn_readout_v1 + DUT + ( + // Reset and clock. + .aresetn , + .aclk , + + // s0_axis for pushing waveforms. + .s0_axis_tready , + .s0_axis_tvalid , + .s0_axis_tdata , + + // s1_axis for input data (8 real samples per clock). + .s1_axis_tready , + .s1_axis_tvalid , + .s1_axis_tdata , + + // m0_axis for output data (8 complex samples per clock). + .m0_axis_tready , + .m0_axis_tvalid , + .m0_axis_tdata , + + // m1_axis for output data (1 complex sample per clock). + .m1_axis_tready , + .m1_axis_tvalid , + .m1_axis_tdata + + ); + +initial begin + // Reset sequence. + aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + #500; + aresetn <= 1; + + #1000; + + tb_wave <= 1; + +end + +// Input data. +initial begin + int n; + real fs, f, pi, a; + + s1_axis_tvalid <= 1; + + for (int i=0; i + + QICK + QICK + axis_kidsim_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 256 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_kidsim_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 3f3c0a90 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_kidsim_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 3f3c0a90 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + 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"is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "address_spaces": { + "Master_AXI": { + "range": "4294967296", + "width": "32" + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_kidsim_v3/src/axi_slv.v b/firmware/ip/axis_kidsim_v3/src/axi_slv.v new file mode 100644 index 000000000..2d899c26e --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/axi_slv.v @@ -0,0 +1,1046 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [15:0] DDS_BVAL_REG , + output wire [15:0] DDS_SLOPE_REG , + output wire [15:0] DDS_STEPS_REG , + output wire [15:0] DDS_WAIT_REG , + output wire [15:0] DDS_FREQ_REG , + output wire [15:0] IIR_C0_REG , + output wire [15:0] IIR_C1_REG , + output wire [15:0] IIR_G_REG , + output wire [ 1:0] OUTSEL_REG , + output wire [15:0] PUNCT_ID_REG , + output wire [ 7:0] ADDR_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign DDS_BVAL_REG = slv_reg0 [15:0]; +assign DDS_SLOPE_REG = slv_reg1 [15:0]; +assign DDS_STEPS_REG = slv_reg2 [15:0]; +assign DDS_WAIT_REG = slv_reg3 [15:0]; +assign DDS_FREQ_REG = slv_reg4 [15:0]; +assign IIR_C0_REG = slv_reg5 [15:0]; +assign IIR_C1_REG = slv_reg6 [15:0]; +assign IIR_G_REG = slv_reg7 [15:0]; +assign OUTSEL_REG = slv_reg8 [ 1:0]; +assign PUNCT_ID_REG = slv_reg9 [15:0]; +assign ADDR_REG = slv_reg10 [ 7:0]; +assign WE_REG = slv_reg11 [ 0]; + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv b/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv new file mode 100644 index 000000000..45c779e7b --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv @@ -0,0 +1,192 @@ +module axis_kidsim_v3 + #( + // Number of lanes. + parameter L = 8 + ) + ( + // Modulation trigger. + input wire [L-1:0] trigger , + + // AXI Slave I/F for configuration. + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Reset and clock for axis_*. + input wire aresetn , + input wire aclk , + + // s_axis_* for input. + input wire s_axis_tvalid , + input wire [32*L-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // m_axis_* for output. + output wire m_axis_tvalid , + output wire [32*L-1:0] m_axis_tdata , + output wire m_axis_tlast + ); + +/********************/ +/* Internal signals */ +/********************/ + +// WE vector. +wire [L-1:0] enable_v ; +wire [L-1:0] WE_REG_v ; + +// Data input vector. +wire [31:0] din_v [L] ; + +// Data output vector. +wire [L-1:0] dout_valid ; +wire [31:0] dout_v [L] ; +wire [L-1:0] dout_last ; + +// Registers. +wire [15:0] DDS_BVAL_REG ; +wire [15:0] DDS_SLOPE_REG ; +wire [15:0] DDS_STEPS_REG ; +wire [15:0] DDS_WAIT_REG ; +wire [15:0] DDS_FREQ_REG ; +wire [15:0] IIR_C0_REG ; +wire [15:0] IIR_C1_REG ; +wire [15:0] IIR_G_REG ; +wire [ 1:0] OUTSEL_REG ; +wire [15:0] PUNCT_ID_REG ; +wire [ 7:0] ADDR_REG ; +wire WE_REG ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .DDS_BVAL_REG (DDS_BVAL_REG ), + .DDS_SLOPE_REG (DDS_SLOPE_REG ), + .DDS_STEPS_REG (DDS_STEPS_REG ), + .DDS_WAIT_REG (DDS_WAIT_REG ), + .DDS_FREQ_REG (DDS_FREQ_REG ), + .IIR_C0_REG (IIR_C0_REG ), + .IIR_C1_REG (IIR_C1_REG ), + .IIR_G_REG (IIR_G_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .PUNCT_ID_REG (PUNCT_ID_REG ), + .ADDR_REG (ADDR_REG ), + .WE_REG (WE_REG ) + ); + +genvar i; +generate + for (i=0; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_kidsim_v3/src/prod.sv b/firmware/ip/axis_kidsim_v3/src/prod.sv new file mode 100644 index 000000000..7de7b3229 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/prod.sv @@ -0,0 +1,141 @@ +module prod + #( + parameter CONJA = 0 , + parameter CONJB = 0 , + parameter B = 16 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire [2*B-1:0] dina , + input wire [2*B-1:0] dinb , + + // Output data. + output wire dout_valid , + output wire [2*B-1:0] dout + ); + +/*************/ +/* Internals */ +/*************/ +// Valid pipeline. +reg valid_r1; +reg valid_r2; +reg valid_r3; +reg valid_r4; + +// Input registers. +reg [2*B-1:0] dina_r; +reg [2*B-1:0] dinb_r; + +// Partial products. +wire signed [B-1:0] dina_real; +wire signed [B-1:0] dina_imag; +wire signed [B-1:0] dinb_real; +wire signed [B-1:0] dinb_imag; +wire signed [2*B-1:0] prod_real_a; +wire signed [2*B-1:0] prod_real_b; +wire signed [2*B-1:0] prod_imag_a; +wire signed [2*B-1:0] prod_imag_b; +reg signed [2*B-1:0] prod_real_a_r; +reg signed [2*B-1:0] prod_real_b_r; +reg signed [2*B-1:0] prod_imag_a_r; +reg signed [2*B-1:0] prod_imag_b_r; + +// Full product. +wire signed [2*B-1:0] prod_real; +wire signed [2*B-1:0] prod_imag; +reg signed [2*B-1:0] prod_real_r; +reg signed [2*B-1:0] prod_imag_r; + +// Rounding. +wire signed [B-1:0] prod_real_round; +wire signed [B-1:0] prod_imag_round; +wire [2*B-1:0] prod; +reg [2*B-1:0] prod_r; + +/****************/ +/* Architecture */ +/****************/ +// Partial products. +assign dina_real = dina_r[0 +: B]; +assign dina_imag = (CONJA == 1)? -dina_r[B +: B] : dina_r[B +: B]; +assign dinb_real = dinb_r[0 +: B]; +assign dinb_imag = (CONJB == 1)? -dinb_r[B +: B] : dinb_r[B +: B]; +assign prod_real_a = dina_real*dinb_real; +assign prod_real_b = dina_imag*dinb_imag; +assign prod_imag_a = dina_real*dinb_imag; +assign prod_imag_b = dina_imag*dinb_real; + +// Full product. +assign prod_real = prod_real_a_r - prod_real_b_r; +assign prod_imag = prod_imag_a_r + prod_imag_b_r; + +// Rounding. +assign prod_real_round = prod_real_r [2*B-2 -: B]; +assign prod_imag_round = prod_imag_r [2*B-2 -: B]; +assign prod = {prod_imag_round,prod_real_round}; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // Valid pipeline. + valid_r1 <= 0; + valid_r2 <= 0; + valid_r3 <= 0; + valid_r4 <= 0; + + // Input registers. + dina_r <= 0; + dinb_r <= 0; + + // Partial products. + prod_real_a_r <= 0; + prod_real_b_r <= 0; + prod_imag_a_r <= 0; + prod_imag_b_r <= 0; + + // Full product. + prod_real_r <= 0; + prod_imag_r <= 0; + + // Rounding. + prod_r <= 0; + end + else begin + // Valid pipeline. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + valid_r3 <= valid_r2; + valid_r4 <= valid_r3; + + // Input registers. + dina_r <= dina; + dinb_r <= dinb; + + // Partial products. + prod_real_a_r <= prod_real_a; + prod_real_b_r <= prod_real_b; + prod_imag_a_r <= prod_imag_a; + prod_imag_b_r <= prod_imag_b; + + // Full product. + prod_real_r <= prod_real; + prod_imag_r <= prod_imag; + + // Rounding. + prod_r <= prod; + + end +end + +// Assign outputs. +assign dout_valid = valid_r4; +assign dout = prod_r; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/punct.sv b/firmware/ip/axis_kidsim_v3/src/punct.sv new file mode 100644 index 000000000..d7d37ad9f --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/punct.sv @@ -0,0 +1,86 @@ +module punct + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire din_last , + + // Output data. + output wire dout_valid , + output wire dout_last , + output wire dout_en , + + // Registers. + input wire [15:0] ID_REG + ); + +/*************/ +/* Internals */ +/*************/; + +// Pipeline registers. +reg valid_r1 ; +reg valid_r2 ; +reg last_r1 ; +reg last_r2 ; + +// Counter. +reg [15:0] cnt ; + +// Flag. +wire flag ; + +// Registers. +reg [15:0] ID_REG_r ; + +/****************/ +/* Architecture */ +/****************/ + +// Flag. +assign flag = (ID_REG_r == cnt); + +always @(posedge clk) begin + if (~rstn) begin + // Pipeline registers. + valid_r1 <= 0; + valid_r2 <= 0; + last_r1 <= 0; + last_r2 <= 0; + + // Counter. + cnt <= 0; + + // Registers. + ID_REG_r <= 0; + end + else begin + // Pipeline registers. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + last_r1 <= din_last; + last_r2 <= last_r1; + + // Counter. + if ( valid_r2 == 1'b1 ) + if ( last_r2 == 1'b1 ) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + ID_REG_r <= ID_REG; + + end +end + +// Assign outputs. +assign dout_valid = valid_r2; +assign dout_last = last_r2; +assign dout_en = flag; + + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/tb/tb.sv b/firmware/ip/axis_kidsim_v3/src/tb/tb.sv new file mode 100644 index 000000000..6091fb18a --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/tb/tb.sv @@ -0,0 +1,416 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of lanes. +parameter L = 8; + +// Number of bits. +localparam B = 16; +localparam NLAST = 4; +//localparam PUNCT_ID = NLAST-1; +localparam PUNCT_ID = 0; + +// Modulation trigger. +reg [L-1:0] trigger ; + +// AXI Slave I/F for configuration. +reg s_axi_aclk ; +reg s_axi_aresetn ; + +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; + +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; + +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; + +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; + +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +// Reset and clock for axis_*. +reg aresetn ; +reg aclk ; + +reg s_axis_tvalid ; +wire [32*L-1:0] s_axis_tdata ; +reg s_axis_tlast ; + +// m_axis_* for output. +wire m_axis_tvalid ; +wire [32*L-1:0] m_axis_tdata ; +wire m_axis_tlast ; + +// Input/output data vectors. +reg [15:0] din_real_v [L] ; +reg [15:0] din_imag_v [L] ; +wire [15:0] dout_real_v [L] ; +wire [15:0] dout_imag_v [L] ; +wire [31:0] dout_v [L] ; + +// TDM. +reg tdm_sync ; +wire [32*NLAST-1:0] dout_tdm_demux_v [L] ; +wire [L-1:0] dout_valid_tdm_demux ; + +// TDM-demuxed data. +wire [31:0] dout_tdm_v [L][NLAST] ; +wire [15:0] dout_tdm_real_v [L][NLAST]; +wire [15:0] dout_tdm_imag_v [L][NLAST]; + +xil_axi_prot_t prot = 0; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_trigger = 0; + +genvar i,j; +generate + for (i=0; i NLAST, so none resonator will be used. + for (int i=0; i + + QICK + QICK + axis_pfb_readout_v2 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + 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/home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..491fd330c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + + m_axi_wdata + + + + + WID + + + m_axi_wid + + + + + WLAST + + + m_axi_wlast + + + + + WREADY + + + m_axi_wready + + + + + WSTRB + + + m_axi_wstrb + + + + + WUSER + + + m_axi_wuser + + + + + WVALID + + + m_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + simulation.tlm + + + + + PROTOCOL + AXI4LITE + + + simulation.tlm + + + + + FREQ_HZ + 100000000 + + + simulation.tlm + + + + + ID_WIDTH + 0 + + + simulation.tlm + + + + + ADDR_WIDTH + 32 + + + simulation.tlm + + + + + AWUSER_WIDTH + 0 + + + simulation.tlm + + + + + ARUSER_WIDTH + 0 + + + simulation.tlm + + + + + WUSER_WIDTH + 0 + + + simulation.tlm + + + + + RUSER_WIDTH + 0 + + + simulation.tlm + + + + + BUSER_WIDTH + 0 + + + simulation.tlm + + + + + READ_WRITE_MODE + READ_WRITE + + + simulation.tlm + + + + + HAS_BURST + 0 + + + simulation.tlm + + + + + HAS_LOCK + 0 + + + simulation.tlm + + + + + HAS_PROT + 1 + + + simulation.tlm + + + + + HAS_CACHE + 0 + + + simulation.tlm + + + + + HAS_QOS + 0 + + + simulation.tlm + + + + + HAS_REGION + 0 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xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd b/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd new file mode 100644 index 000000000..abafe4600 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + FREQ0_REG : out std_logic_vector (31 downto 0); + FREQ1_REG : out std_logic_vector (31 downto 0); + FREQ2_REG : out std_logic_vector (31 downto 0); + FREQ3_REG : out std_logic_vector (31 downto 0); + FREQ4_REG : out std_logic_vector (31 downto 0); + FREQ5_REG : out std_logic_vector (31 downto 0); + FREQ6_REG : out std_logic_vector (31 downto 0); + FREQ7_REG : out std_logic_vector (31 downto 0); + OUTSEL_REG : out std_logic_vector (1 downto 0); + CH0SEL_REG : out std_logic_vector (2 downto 0); + CH1SEL_REG : out std_logic_vector (2 downto 0); + CH2SEL_REG : out std_logic_vector (2 downto 0); + CH3SEL_REG : out std_logic_vector (2 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + FREQ0_REG <= slv_reg0; + FREQ1_REG <= slv_reg1; + FREQ2_REG <= slv_reg2; + FREQ3_REG <= slv_reg3; + FREQ4_REG <= slv_reg4; + FREQ5_REG <= slv_reg5; + FREQ6_REG <= slv_reg6; + FREQ7_REG <= slv_reg7; + OUTSEL_REG <= slv_reg8(1 downto 0); + CH0SEL_REG <= slv_reg9(2 downto 0); + CH1SEL_REG <= slv_reg10(2 downto 0); + CH2SEL_REG <= slv_reg11(2 downto 0); + CH3SEL_REG <= slv_reg12(2 downto 0); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v b/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v new file mode 100644 index 000000000..e7977bb57 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v @@ -0,0 +1,234 @@ +module axis_pfb_readout_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS for input samples + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // M_AXIS for CH0 output. + m0_axis_tvalid , + m0_axis_tdata , + + // M_AXIS for CH1 output. + m1_axis_tvalid , + m1_axis_tdata , + + // M_AXIS for CH2 output. + m2_axis_tvalid , + m2_axis_tdata , + + // M_AXIS for CH3 output. + m3_axis_tvalid , + m3_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) +parameter INTERLEAVED_INPUT = 1; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +input s_axis_tvalid; +output s_axis_tready; +input [4*32-1:0] s_axis_tdata; + +output m0_axis_tvalid; +output [31:0] m0_axis_tdata; + +output m1_axis_tvalid; +output [31:0] m1_axis_tdata; + +output m2_axis_tvalid; +output [31:0] m2_axis_tdata; + +output m3_axis_tvalid; +output [31:0] m3_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] FREQ0_REG; +wire [31:0] FREQ1_REG; +wire [31:0] FREQ2_REG; +wire [31:0] FREQ3_REG; +wire [31:0] FREQ4_REG; +wire [31:0] FREQ5_REG; +wire [31:0] FREQ6_REG; +wire [31:0] FREQ7_REG; +wire [1:0] OUTSEL_REG; +wire [2:0] CH0SEL_REG; +wire [2:0] CH1SEL_REG; +wire [2:0] CH2SEL_REG; +wire [2:0] CH3SEL_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .FREQ0_REG (FREQ0_REG ), + .FREQ1_REG (FREQ1_REG ), + .FREQ2_REG (FREQ2_REG ), + .FREQ3_REG (FREQ3_REG ), + .FREQ4_REG (FREQ4_REG ), + .FREQ5_REG (FREQ5_REG ), + .FREQ6_REG (FREQ6_REG ), + .FREQ7_REG (FREQ7_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .CH0SEL_REG (CH0SEL_REG ), + .CH1SEL_REG (CH1SEL_REG ), + .CH2SEL_REG (CH2SEL_REG ), + .CH3SEL_REG (CH3SEL_REG ) + ); + +// PFB with DDS product. +pfb_dds_mux + #( + .INTERLEAVED_INPUT(INTERLEAVED_INPUT) + ) + pfb_dds_mux_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .FREQ0_REG (FREQ0_REG ), + .FREQ1_REG (FREQ1_REG ), + .FREQ2_REG (FREQ2_REG ), + .FREQ3_REG (FREQ3_REG ), + .FREQ4_REG (FREQ4_REG ), + .FREQ5_REG (FREQ5_REG ), + .FREQ6_REG (FREQ6_REG ), + .FREQ7_REG (FREQ7_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .CH0SEL_REG (CH0SEL_REG ), + .CH1SEL_REG (CH1SEL_REG ), + .CH2SEL_REG (CH2SEL_REG ), + .CH3SEL_REG (CH3SEL_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo new file mode 100644 index 000000000..2aa6467de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [31 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_0.v when simulating +// the core, dds_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci new file mode 100644 index 000000000..f65db0d9d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 4 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 0 + 0 + 1 + 0 + 32 + 1 + 0 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Minimal + 0.06 + Coregen + false + false + false + false + 4 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Auto + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + None + false + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../project_1.gen/sources_1/ip/dds_0 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv new file mode 100644 index 000000000..985c391a6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv @@ -0,0 +1,183 @@ +module ddsprod + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata , + + // Registers. + FREQ_REG , + OUTSEL_REG + ); + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [31:0] s_axis_tdata; + +output m_axis_tvalid; +output [31:0] m_axis_tdata; + +input [31:0] FREQ_REG; +input [1:0] OUTSEL_REG; + +/********************/ +/* Internal signals */ +/********************/ +// Input valid. +reg tvalid_r1; +reg tvalid_r2; +reg tvalid_r3; + +// DDS valid input. +reg dds_valid_r; + +// Input data. +reg [31:0] di_r1; +reg [31:0] di_r2; +reg [31:0] di_r3; +wire signed [15:0] di_real; +wire signed [15:0] di_imag; + +// DDS output. +wire [31:0] dds_dout; +reg [31:0] dds_dout_r1; +reg [31:0] dds_dout_r2; +reg [31:0] dds_dout_r3; +wire signed [15:0] dds_real; +wire signed [15:0] dds_imag; + +// Partial products. +wire signed [31:0] do_real_a; +wire signed [31:0] do_real_b; +reg signed [31:0] do_real_a_r1; +reg signed [31:0] do_real_b_r1; +wire signed [31:0] do_imag_a; +wire signed [31:0] do_imag_b; +reg signed [31:0] do_imag_a_r1; +reg signed [31:0] do_imag_b_r1; + +// Full out. +wire signed [31:0] do_real; +reg signed [15:0] do_real_r1; +wire signed [31:0] do_imag; +reg signed [15:0] do_imag_r1; + +// Muxed output. +wire [31:0] do_mux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS instance. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(dds_valid_r ), + .s_axis_phase_tdata (FREQ_REG ), + .m_axis_data_tvalid ( ), + .m_axis_data_tdata (dds_dout ) + ); + +// Input data. +assign di_real = di_r1[15:0]; +assign di_imag = di_r1[31:16]; + +// DDS output. +assign dds_real = dds_dout_r1[15:0]; +assign dds_imag = dds_dout_r1[31:16]; + +// Partial products. +assign do_real_a = di_real*dds_real; +assign do_real_b = di_imag*dds_imag; +assign do_imag_a = di_real*dds_imag; +assign do_imag_b = di_imag*dds_real; + +// Full out. +assign do_real = do_real_a_r1 - do_real_b_r1; +assign do_imag = do_imag_a_r1 + do_imag_b_r1; + +// Muxed output. +assign do_mux = (OUTSEL_REG == 0)? {do_imag_r1,do_real_r1} : + (OUTSEL_REG == 1)? di_r3 : + (OUTSEL_REG == 2)? dds_dout_r3 : 32'h0000_0000; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // Input valid. + tvalid_r1 <= 0; + tvalid_r2 <= 0; + tvalid_r3 <= 0; + + // DDS valid input. + dds_valid_r <= 0; + + // Input data. + di_r1 <= 0; + di_r2 <= 0; + di_r3 <= 0; + + // DDS output. + dds_dout_r1 <= 0; + dds_dout_r2 <= 0; + dds_dout_r3 <= 0; + + // Partial products. + do_real_a_r1 <= 0; + do_real_b_r1 <= 0; + do_imag_a_r1 <= 0; + do_imag_b_r1 <= 0; + + // Full out. + do_real_r1 <= 0; + do_imag_r1 <= 0; + end + else begin + // Input valid. + tvalid_r1 <= s_axis_tvalid; + tvalid_r2 <= tvalid_r1; + tvalid_r3 <= tvalid_r2; + + // DDS valid input. + dds_valid_r <= 1; + + // Input data. + di_r1 <= s_axis_tdata; + di_r2 <= di_r1; + di_r3 <= di_r2; + + // DDS output. + dds_dout_r1 <= dds_dout; + dds_dout_r2 <= dds_dout_r1; + dds_dout_r3 <= dds_dout_r2; + + // Partial products. + do_real_a_r1 <= do_real_a; + do_real_b_r1 <= do_real_b; + do_imag_a_r1 <= do_imag_a; + do_imag_b_r1 <= do_imag_b; + + // Full out. + do_real_r1 <= do_real[30:15]; + do_imag_r1 <= do_imag[30:15]; + end +end + +// Assign outputs. +assign m_axis_tvalid = tvalid_r3; +assign m_axis_tdata = do_mux; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv new file mode 100644 index 000000000..64ba5e607 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv @@ -0,0 +1,116 @@ +module ddsprod_v + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata , + + // Registers. + FREQ0_REG , + FREQ1_REG , + FREQ2_REG , + FREQ3_REG , + FREQ4_REG , + FREQ5_REG , + FREQ6_REG , + FREQ7_REG , + OUTSEL_REG + ); + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [8*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output [8*32-1:0] m_axis_tdata; + +input [31:0] FREQ0_REG; +input [31:0] FREQ1_REG; +input [31:0] FREQ2_REG; +input [31:0] FREQ3_REG; +input [31:0] FREQ4_REG; +input [31:0] FREQ5_REG; +input [31:0] FREQ6_REG; +input [31:0] FREQ7_REG; +input [1:0] OUTSEL_REG; + +/********************/ +/* Internal signals */ +/********************/ +localparam L = 8; + +// Input data vector. +wire [31:0] din_v [0:L-1]; + +// Frequency registers. +wire [31:0] freq_reg_v [0:7]; + +// Output data vector. +wire [31:0] dout_v [0:L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Frequency registers. +assign freq_reg_v[0] = FREQ0_REG; +assign freq_reg_v[1] = FREQ1_REG; +assign freq_reg_v[2] = FREQ2_REG; +assign freq_reg_v[3] = FREQ3_REG; +assign freq_reg_v[4] = FREQ4_REG; +assign freq_reg_v[5] = FREQ5_REG; +assign freq_reg_v[6] = FREQ6_REG; +assign freq_reg_v[7] = FREQ7_REG; + +genvar i; +generate + for (i=0; i + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_0 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci new file mode 100644 index 000000000..1db52de13 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_1 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_1 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_1 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci new file mode 100644 index 000000000..0f0a644b8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_2 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_2 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_2 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci new file mode 100644 index 000000000..d0fd7e8ec --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_3 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_3 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci new file mode 100644 index 000000000..48cef3abb --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_4 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_4 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci new file mode 100644 index 000000000..be396b4ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_5 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_5 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci new file mode 100644 index 000000000..fb143ce18 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_6 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_6 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci new file mode 100644 index 000000000..bcf4c7433 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_7 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_7 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl b/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl new file mode 100755 index 000000000..deba046dc --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template new file mode 100644 index 000000000..0264c07c9 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template @@ -0,0 +1,26 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/v20.2/ip/axis_pfb_readout/src/fir/coef/.coe} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Coefficient_Structure {Non_Symmetric} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Number_Channels {1} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl new file mode 100644 index 000000000..e1a370512 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v2/src/firs.sv b/firmware/ip/axis_pfb_readout_v2/src/firs.sv new file mode 100644 index 000000000..c602e2b2c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/firs.sv @@ -0,0 +1,196 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of Lanes (Input). +parameter L = 4; + +// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) +parameter INTERLEAVED_INPUT = 1; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Input delay. +wire[31:0] data_v [0:L-1]; +reg [31:0] data_r1 [0:L-1]; +reg [31:0] data_r2 [0:L-1]; + +// Valid input. +reg valid_r; + +// FIR outputs. +wire[2*L-1:0] valid_v; +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + -- sel register. + sel <= (others => '0'); + + -- Pipeline registers. + din_r <= (others => '0'); + din_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + else + -- Signals combined after pm. + d_pm_r <= d_pm; + + -- sel register. + if (valid_r = '1') then + sel <= sel + 1; + end if; + + -- Pipeline registers. + din_r <= s_axis_tdata; + din_rr <= din_r; + valid_r <= s_axis_tvalid; + valid_rr <= valid_r; + end if; + end if; +end process; + +-- Slice input. +GEN_SLICE_IN: for I in 0 to N-1 generate + dv_i(I) <= signed(din_r ( (I+1)*B-1 downto I*B)); + dv_q(I) <= signed(din_r ( N*B+ (I+1)*B-1 downto N*B+ I*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to N/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to N-1 generate + d_pm ( (I+1)*B-1 downto I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ( N*B+ (I+1)*B-1 downto N*B+I*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +dout_mux <= din_rr when sel = to_unsigned(0,sel'length) else + d_pm_r; + + +-- Assign outputs. +m_axis_tdata <= dout_mux; +m_axis_tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd new file mode 100644 index 000000000..b8f1a8f5f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd new file mode 100644 index 000000000..26af1d6a7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd new file mode 100644 index 000000000..8ec9c8d10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd new file mode 100644 index 000000000..c943462db --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd new file mode 100644 index 000000000..18d605a54 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x8/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x8_scalar2vector; +architecture structural of ssr_8x8_scalar2vector is + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x8_vector_concat; +architecture structural of ssr_8x8_vector_concat is + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x8_vector_delay; +architecture structural of ssr_8x8_vector_delay is + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret; +architecture structural of ssr_8x8_vector_reinterpret is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret1; +architecture structural of ssr_8x8_vector_reinterpret1 is + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret2; +architecture structural of ssr_8x8_vector_reinterpret2 is + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret3; +architecture structural of ssr_8x8_vector_reinterpret3 is + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_slice_im; +architecture structural of ssr_8x8_vector_slice_im is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_slice_re; +architecture structural of ssr_8x8_vector_slice_re is + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x8_vector2scalar; +architecture structural of ssr_8x8_vector2scalar is + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_7ca5184bef + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 3-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 3-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_fft; +architecture structural of ssr_8x8_vector_fft is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 3-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_scale_net : std_logic_vector( 3-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x8_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x8_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x8_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x8_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x8_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x8_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x8_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x8_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x8_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x8_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 3 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 3, + N => 8, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_i_im; +architecture structural of ssr_8x8_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x8/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_i_re; +architecture structural of ssr_8x8_i_re is + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x8_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_struct is + port ( + i_scale : in std_logic_vector( 3-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 3-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_struct; +architecture structural of ssr_8x8_struct is + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_scale_net : std_logic_vector( 3-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x8_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x8_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x8_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_default_clock_driver is + port ( + ssr_8x8_sysclk : in std_logic; + ssr_8x8_sysce : in std_logic; + ssr_8x8_sysclr : in std_logic; + ssr_8x8_clk1 : out std_logic; + ssr_8x8_ce1 : out std_logic + ); +end ssr_8x8_default_clock_driver; +architecture structural of ssr_8x8_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x8_sysclk, + sysce => ssr_8x8_sysce, + sysclr => ssr_8x8_sysclr, + clk => ssr_8x8_clk1, + ce => ssr_8x8_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8 is + port ( + i_scale : in std_logic_vector( 3-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 3-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8; +architecture structural of ssr_8x8 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x8,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x8_default_clock_driver : entity xil_defaultlib.ssr_8x8_default_clock_driver + port map ( + ssr_8x8_sysclk => clk, + ssr_8x8_sysce => '1', + ssr_8x8_sysclr => '0', + ssr_8x8_clk1 => clk_1_net, + ssr_8x8_ce1 => ce_1_net + ); + ssr_8x8_struct : entity xil_defaultlib.ssr_8x8_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd new file mode 100644 index 000000000..3df02d622 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x8_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x8_xldelay; + +architecture behavior of ssr_8x8_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=AB + P:out SFIXED; -- O=AB + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=CAB + P:out SFIXED); -- O=CAB +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=AB + P:out SFIXED); -- O=AB +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 3; + N : integer := 8; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(2 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(2 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776; +architecture structural of WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(2 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(2 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 3; + N : integer := 8; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(2 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(2 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 3, + N => 8, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x8_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x8_xlslice; + +architecture behavior of ssr_8x8_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_965a32611a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_965a32611a; +architecture behavior of sysgen_concat_965a32611a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d1aaeed629 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d1aaeed629; +architecture behavior of sysgen_reinterpret_d1aaeed629 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_4035468568 is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_4035468568; +architecture behavior of sysgen_reinterpret_4035468568 +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_7ca5184bef is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_7ca5184bef; +architecture behavior of sysgen_concat_7ca5184bef +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd new file mode 100644 index 000000000..770ff703a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd new file mode 100644 index 000000000..5d837de43 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd new file mode 100644 index 000000000..34bfa2e8c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd new file mode 100644 index 000000000..92017d49a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd new file mode 100644 index 000000000..b78886923 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd @@ -0,0 +1,196 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x8 is + Generic + ( + NFFT : Integer := 8; + SSR : Integer := 8; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x8 is + +-- SSR FFT 8x8. +component ssr_8x8 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 3-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0); + o_scale : out std_logic_vector( 3-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input and output. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); +signal dout_i : std_logic_vector (SSR*B-1 downto 0); +signal dout_q : std_logic_vector (SSR*B-1 downto 0); + +-- FFT scale. +signal o_scale : std_logic_vector (2 downto 0); + +-- FFT output valid. +signal o_axis_tvalid : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (2 downto 0); +signal qout_reg_i : unsigned (2 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (2 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(2 downto 0)); + +-- Input/output data. +din_i <= s_axis_tdata (SSR*B-1 downto 0); +din_q <= s_axis_tdata (2*SSR*B-1 downto SSR*B); +o_axis_tdata(SSR*B-1 downto 0) <= dout_i; +o_axis_tdata(2*SSR*B-1 downto SSR*B) <= dout_q; + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= din_i((I+1)*B-1 downto I*B); + din_qv(I) <= din_q((I+1)*B-1 downto I*B); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + dout_i((I+1)*B-1 downto I*B) <= dout_iv(I); + dout_q((I+1)*B-1 downto I*B) <= dout_qv(I); +end generate GEN; + +-- SSR FFT 8x8. +ssr_8x8_i : ssr_8x8 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => s_axis_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd new file mode 100644 index 000000000..c2445f126 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd @@ -0,0 +1,224 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x8 is + Generic + ( + NFFT : Integer := 8; + SSR : Integer := 8; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 8; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0) := (others => '0'); +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0); +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ); + +begin + +-- DUT. +DUT : ssrfft_8x8 + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & + i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 300 ns; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 0 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv new file mode 100644 index 000000000..47777abd3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv @@ -0,0 +1,361 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire s_axis_tready; +reg s_axis_tvalid; +reg [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +reg [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +reg [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +reg [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +reg [31:0] m3_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v2 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // FREQ. + //for (int i=0; i<8; i = i+1) begin + // data_wr = freq_calc(100, i+10); + // axi_mst_0_agent.AXI4LITE_WRITE_BURST(i*4, prot, data_wr, resp); + // #10; + //end + + // FREQ0. + data_wr = freq_calc(100, 3.8); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // FREQ1. + data_wr = freq_calc(100, 92); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // FREQ2. + data_wr = freq_calc(100, 13.5); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + // FREQ3. + data_wr = freq_calc(100, 12.2); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); + #10; + + // FREQ4. + data_wr = freq_calc(100, 87); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // FREQ5. + data_wr = freq_calc(100, 95); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + #10; + + // FREQ6. + data_wr = freq_calc(100, 92); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, data_wr, resp); + #10; + + // FREQ7. + data_wr = freq_calc(100, 93); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, data_wr, resp); + #10; + + // OUTSEL. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, data_wr, resp); + #10; + + // CH0SEL. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, data_wr, resp); + #10; + + // CH1SEL. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, data_wr, resp); + #10; + + // CH2SEL. + data_wr = 4; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, data_wr, resp); + #10; + + // CH3SEL. + data_wr = 7; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(12*4, prot, data_wr, resp); + #10; + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + s_axis_tdata <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +// Function to compute frequency register. +function [31:0] freq_calc; + input int fclk; + input real f; + + // All input frequencies are in MHz. + real fs,temp; + fs = fclk; + temp = f/fs*2**30; + freq_calc = {int'(temp),2'b00}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl b/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl new file mode 100644 index 000000000..9eea8a80a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + ipgui::add_param $IPINST -name "INTERLEAVED_INPUT" + +} + +proc update_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to update INTERLEAVED_INPUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to validate INTERLEAVED_INPUT + return true +} + + +proc update_MODELPARAM_VALUE.INTERLEAVED_INPUT { MODELPARAM_VALUE.INTERLEAVED_INPUT PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INTERLEAVED_INPUT}] ${MODELPARAM_VALUE.INTERLEAVED_INPUT} +} + diff --git a/firmware/ip/axis_pfb_readout_v3/README b/firmware/ip/axis_pfb_readout_v3/README new file mode 100644 index 000000000..3d574edd1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/README @@ -0,0 +1,9 @@ +This block has 3 main components: +* Polyphse Filter Bank with 64 channels, 50 % overlap, x32 decimation. +* Channel selector to grab 4 channels from the PFB. +* Four phase-coherent DDSs with frequency/phase settings. + +The 4 outputs are independent from each other. The same PFB channels can +be routed multiple times to individual outputs, and apply a different +DDS down-conversion frequency. + diff --git a/firmware/ip/axis_pfb_readout_v3/component.xml b/firmware/ip/axis_pfb_readout_v3/component.xml new file mode 100644 index 000000000..25c016035 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/component.xml @@ -0,0 +1,1590 @@ + + + QICK + QICK + axis_pfb_readout_v3 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_pfb_readout_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9bf5fb0e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_pfb_readout_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9bf5fb0e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 64 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/pfb/fir/coef/fir_7.coe + coe + + + src/pfb/fir/coef/fir_6.coe + coe + + + src/pfb/fir/coef/fir_5.coe + coe + + + src/pfb/fir/coef/fir_4.coe + coe + + + src/pfb/fir/coef/fir_3.coe + coe + + + src/pfb/fir/coef/fir_2.coe + coe + + + src/pfb/fir/coef/fir_1.coe + coe + + + src/pfb/fir/coef/fir_0.coe + coe + + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_pfb_readout_i/ddsprod_v_i/GEN_ddsprod[0].ddsprod_i/dds_top_i/dds_i + + + src/pfb/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir7_i + + + src/pfb/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir6_i + + + src/pfb/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir5_i + + + src/pfb/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir4_i + + + src/pfb/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir3_i + + + src/pfb/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir2_i + + + src/pfb/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir1_i + + + src/pfb/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir0_i + + + src/dds/cmult_16x16.v + verilogSource + + + src/dds/cmult_sub.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/dds/mult_32x32.v + verilogSource + + + src/pfb_readout.v + verilogSource + + + src/pfb/pfb_switch.v + verilogSource + + + src/dds/dds_ctrl.sv + systemVerilogSource + + + src/dds/dds_top.sv + systemVerilogSource + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/pfb/firs.sv + systemVerilogSource + + + src/pfb/pfb.sv + systemVerilogSource + + + src/pfb/pfb_chsel.sv + systemVerilogSource + + + src/pfb/pfb_reorder.sv + systemVerilogSource + + + src/pfb/pfb_swap.sv + systemVerilogSource + + + src/pfb/pfb_top.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/pfb/fft/framing.vhd + vhdlSource + + + src/pfb/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb/pfb_cfg.vhd + vhdlSource + + + src/pfb/pfb_ctrl.vhd + vhdlSource + + + src/pfb/pfb_framing.vhd + vhdlSource + + + src/pfb/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/srl33e.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd + vhdlSource + + + src/pfb/fft/ssrfft_8x64_sync.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/tlast_gen.vhd + vhdlSource + + + src/pfb/zn_nb.vhd + vhdlSource + + + src/axis_pfb_readout_v3.v + verilogSource + CHECKSUM_dbf48f9f + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/pfb/fir/coef/fir_7.coe + coe + + + src/pfb/fir/coef/fir_6.coe + coe + + + src/pfb/fir/coef/fir_5.coe + coe + + + src/pfb/fir/coef/fir_4.coe + coe + + + src/pfb/fir/coef/fir_3.coe + coe + + + src/pfb/fir/coef/fir_2.coe + coe + + + src/pfb/fir/coef/fir_1.coe + coe + + + src/pfb/fir/coef/fir_0.coe + coe + + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_pfb_readout_i/ddsprod_v_i/GEN_ddsprod[0].ddsprod_i/dds_top_i/dds_i + + + src/pfb/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir7_i + + + src/pfb/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir6_i + + + src/pfb/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir5_i + + + src/pfb/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir4_i + + + src/pfb/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir3_i + + + src/pfb/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir2_i + + + src/pfb/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir1_i + + + src/pfb/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir0_i + + + src/dds/cmult_16x16.v + verilogSource + + + src/dds/cmult_sub.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/dds/mult_32x32.v + verilogSource + + + src/pfb_readout.v + verilogSource + + + src/pfb/pfb_switch.v + verilogSource + + + src/dds/dds_ctrl.sv + systemVerilogSource + + + src/dds/dds_top.sv + systemVerilogSource + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/pfb/firs.sv + systemVerilogSource + + + src/pfb/pfb.sv + systemVerilogSource + + + src/pfb/pfb_chsel.sv + systemVerilogSource + + + src/pfb/pfb_reorder.sv + systemVerilogSource + + + src/pfb/pfb_swap.sv + systemVerilogSource + + + src/pfb/pfb_top.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/pfb/fft/framing.vhd + vhdlSource + + + src/pfb/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb/pfb_cfg.vhd + vhdlSource + + + src/pfb/pfb_ctrl.vhd + vhdlSource + + + src/pfb/pfb_framing.vhd + vhdlSource + + + src/pfb/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/srl33e.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd + vhdlSource + + + src/pfb/fft/ssrfft_8x64_sync.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/tlast_gen.vhd + vhdlSource + + + src/pfb/zn_nb.vhd + vhdlSource + + + src/axis_pfb_readout_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfb_readout_v3_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS PFB Readout, 64 Channels, 4 outputs, V3. + + + N + N + 64 + + + Component_Name + axis_pfb_readout_v3_v1_0 + + + + + + zynquplus + + + /QICK/Readout + + AXIS PFB Readout V3 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2024-03-06T15:43:08Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..88ccced05 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": "../project_1/project_1.gen/sources_1/ip/axi_mst_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", 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] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "address_spaces": { + "Master_AXI": { + "range": "4294967296", + "width": "32" + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/axi_slv.vhd b/firmware/ip/axis_pfb_readout_v3/src/axi_slv.vhd new file mode 100644 index 000000000..fc0856d6a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axi_slv.vhd @@ -0,0 +1,532 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + ID0_REG : out std_logic_vector (15 downto 0); + ID1_REG : out std_logic_vector (15 downto 0); + ID2_REG : out std_logic_vector (15 downto 0); + ID3_REG : out std_logic_vector (15 downto 0); + PINC0_REG : out std_logic_vector (31 downto 0); + POFF0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + POFF1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + POFF2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + POFF3_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + ID0_REG <= slv_reg0 (15 downto 0); + ID1_REG <= slv_reg1 (15 downto 0); + ID2_REG <= slv_reg2 (15 downto 0); + ID3_REG <= slv_reg3 (15 downto 0); + PINC0_REG <= slv_reg4; + POFF0_REG <= slv_reg5; + PINC1_REG <= slv_reg6; + POFF1_REG <= slv_reg7; + PINC2_REG <= slv_reg8; + POFF2_REG <= slv_reg9; + PINC3_REG <= slv_reg10; + POFF3_REG <= slv_reg11; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v b/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v new file mode 100644 index 000000000..03dc29f44 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v @@ -0,0 +1,181 @@ +module axis_pfb_readout_v3 + #( + // Number of channels. + parameter N = 64 + ) + ( + // AXI Slave I/F for configuration. + input s_axi_aclk , + input s_axi_aresetn , + + input [5:0] s_axi_awaddr , + input [2:0] s_axi_awprot , + input s_axi_awvalid , + output s_axi_awready , + + input [31:0] s_axi_wdata , + input [3:0] s_axi_wstrb , + input s_axi_wvalid , + output s_axi_wready , + + output [1:0] s_axi_bresp , + output s_axi_bvalid , + input s_axi_bready , + + input [5:0] s_axi_araddr , + input [2:0] s_axi_arprot , + input s_axi_arvalid , + output s_axi_arready , + + output [31:0] s_axi_rdata , + output [1:0] s_axi_rresp , + output s_axi_rvalid , + input s_axi_rready , + + // s_* and m_* reset/clock. + input aresetn , + input aclk , + + // S_AXIS for input samples + input s_axis_tvalid , + input [4*32-1:0] s_axis_tdata , + + // M_AXIS for CH0 output. + output m0_axis_tvalid , + output [31:0] m0_axis_tdata , + + // M_AXIS for CH1 output. + output m1_axis_tvalid , + output [31:0] m1_axis_tdata , + + // M_AXIS for CH2 output. + output m2_axis_tvalid , + output [31:0] m2_axis_tdata , + + // M_AXIS for CH3 output. + output m3_axis_tvalid , + output [31:0] m3_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] ID0_REG ; +wire [15:0] ID1_REG ; +wire [15:0] ID2_REG ; +wire [15:0] ID3_REG ; +wire [31:0] PINC0_REG ; +wire [31:0] POFF0_REG ; +wire [31:0] PINC1_REG ; +wire [31:0] POFF1_REG ; +wire [31:0] PINC2_REG ; +wire [31:0] POFF2_REG ; +wire [31:0] PINC3_REG ; +wire [31:0] POFF3_REG ; + +// Internal valid. +wire valid_int ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +// PFB with DDS product. +pfb_readout + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(4) + ) + pfb_readout_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (valid_int ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +// Assign outputs. +assign m0_axis_tvalid = valid_int; +assign m1_axis_tvalid = valid_int; +assign m2_axis_tvalid = valid_int; +assign m3_axis_tvalid = valid_int; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v new file mode 100644 index 000000000..1c268a7f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v @@ -0,0 +1,46 @@ +module cmult_16x16 + ( + input wire clk , + input wire [15:0] din_i0 , + input wire [15:0] din_q0 , + input wire [15:0] din_i1 , + input wire [15:0] din_q1 , + output wire [31:0] dout_i , + output wire [31:0] dout_q + ); + +/****************/ +/* Architecture */ +/****************/ + +// Real part. +cmult_sub + #( + .op("sub") + ) + cmult_real_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_i1 ), + .c (din_q0 ), + .d (din_q1 ), + .x (dout_i ) + ); + +// Imaginary part. +cmult_sub + #( + .op("add") + ) + cmult_imag_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_q1 ), + .c (din_q0 ), + .d (din_i1 ), + .x (dout_q ) + ); + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v new file mode 100644 index 000000000..b0466a9a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v @@ -0,0 +1,82 @@ +module cmult_sub + #( + parameter op = "sub" + ) + ( + input wire clk , + input wire [15:0] a , + input wire [15:0] b , + input wire [15:0] c , + input wire [15:0] d , + output wire [31:0] x + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg signed [15:0] a_r1; +reg signed [15:0] b_r1; +reg signed [15:0] c_r1; +reg signed [15:0] c_r2; +reg signed [15:0] d_r1; +reg signed [15:0] d_r2; + +// Partial products. +wire signed [31:0] ab; +wire signed [31:0] cd; + +// Pipeline of partial products. +reg signed [31:0] ab_r1; +reg signed [31:0] ab_r2; +reg signed [31:0] cd_r1; + +// Combined result. +wire signed [31:0] res; + +// Pipelined result. +reg signed [31:0] res_r1; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign ab = a_r1*b_r1; +assign cd = c_r2*d_r2; + +// Combined result. +generate + if (op == "sub") begin + assign res = ab_r2 - cd_r1; + end + else if (op == "add") begin + assign res = ab_r2 + cd_r1; + end +endgenerate + +// Registers. +always @(posedge clk) begin + // Input pipeline. + a_r1 <= a; + b_r1 <= b; + c_r1 <= c; + c_r2 <= c_r1; + d_r1 <= d; + d_r2 <= d_r1; + + // Pipeline of partial products. + ab_r1 <= ab; + ab_r2 <= ab_r1; + cd_r1 <= cd; + + // Pipelined result. + res_r1 <= res; +end + +/***********/ +/* Outputs */ +/***********/ +assign x = res_r1; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci new file mode 100644 index 000000000..b6e5eac13 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci @@ -0,0 +1,476 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../project_1.gen/sources_1/ip/dds_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv new file mode 100644 index 000000000..c3c02b3bd --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv @@ -0,0 +1,110 @@ +/* + * DDS Control input: + * + * |----------|--------|----------|--------| + * | 71 .. 65 | 64 | 63 .. 32 | 31 .. 0| + * |----------|--------|----------|--------| + * | not used | resync | poff | pinc | + * |----------|--------|----------|--------| + * +*/ + +module dds_ctrl + ( + // Clock. + input wire aclk , + + // Enable input. + input wire en , + + // Output data. + output wire dout_valid , + output wire [71:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Time counter. +reg [31:0] cnt = 0; +reg [31:0] cnt_r1 = 0; + +// Registers. +reg [31:0] pinc_r1 = 0; +reg [31:0] pinc_r2 = 0; +reg [31:0] poff_r1 = 0; + +// Multiplier output (modulo arithmetic, keep lower bits). +wire [31:0] mult_int; + +// Final phase. +wire [31:0] poff_out; +reg [31:0] poff_out_r1; + +// Output control word. +wire [71:0] dds_ctrl_out; + +// latency for en. +wire en_la; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Final phase. +assign poff_out = poff_r1 + mult_int; + +// Output control word. +assign dds_ctrl_out = {7'b0000000,1'b1,poff_out_r1,pinc_r2}; + +// Multiplier: 32x32, unsigned, optimized for speed. +// Latency: 6. +(* keep_hierarchy = "true" *) mult_32x32 mult_i + ( + .clk (aclk ), + .din_a (pinc_r1 ), + .din_b (cnt_r1 ), + .dout (mult_int ) + ); + +// Latency for en (valid). +// Latency = 2 (cnt) + 6 (mult_32x32) + 1 (poff_out) = 9. +latency_reg + #( + .N(9), + .B(1) + ) + latency_reg_en_i + ( + .clk (aclk ), + .din (en ), + .dout (en_la ) + ); + + +// Registers. +always @(posedge aclk) begin + // Time counter. + if (en == 1'b1) + cnt <= cnt + 1; + cnt_r1 <= cnt; + + // Registers. + pinc_r1 <= PINC_REG; + pinc_r2 <= pinc_r1; + poff_r1 <= POFF_REG; + + // Final phase. + poff_out_r1 <= poff_out; +end + +// Assign outputs. +assign dout_valid = en_la ; +assign dout = dds_ctrl_out ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv new file mode 100644 index 000000000..e2a73654a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv @@ -0,0 +1,68 @@ +module dds_top + ( + // Clock. + input wire aclk , + + // Input valid. + input wire din_valid , + + // Output data. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +// DDS control. +wire ctrl_dout_valid ; +wire [71:0] ctrl_dout ; + +// DDS. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS control. +// Latency: 9. +dds_ctrl dds_ctrl_i + ( + // Clock. + .aclk (aclk ), + + // Enable input. + .en (din_valid ), + + // Output data. + .dout_valid (ctrl_dout_valid ), + .dout (ctrl_dout ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ) + ); + +// DDS instance. +// Latency: 10. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(ctrl_dout_valid ), + .s_axis_phase_tdata (ctrl_dout ), + .m_axis_data_tvalid (dds_dout_valid ), + .m_axis_data_tdata (dds_dout ) + ); + +// Assign outputs. +assign dout_valid = dds_dout_valid ; +assign dout = dds_dout ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v b/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v new file mode 100644 index 000000000..d7ac0d311 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v @@ -0,0 +1,57 @@ +/* + * This multiplier is optimized for 32x32 unsigned, so both of the + * operands are wider than the 27 (or 26 for unsigned) and then + * 4 DSPs are used. Pipeline is such that full-speed is achieved. + * + * Optimal pipeline: 6. + * + */ +module mult_32x32 + ( + input wire clk , + input wire [31:0] din_a , + input wire [31:0] din_b , + output wire [63:0] dout + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg [31:0] din_a_r1 ; +reg [31:0] din_b_r1 ; + +// Product. +wire [63:0] p ; + +// Output pipeline. +reg [63:0] p_r1 ; +reg [63:0] p_r2 ; +reg [63:0] p_r3 ; +reg [63:0] p_r4 ; +reg [63:0] p_r5 ; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign p = din_a_r1*din_b_r1; + +// Registers. +always @(posedge clk) begin + // Input pipeline. + din_a_r1 <= din_a ; + din_b_r1 <= din_b ; + + // Output pipeline. + p_r1 <= p ; + p_r2 <= p_r1 ; + p_r3 <= p_r2 ; + p_r4 <= p_r3 ; + p_r5 <= p_r4 ; +end + +assign dout = p_r5; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv new file mode 100644 index 000000000..fd39b3d0a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv @@ -0,0 +1,135 @@ +module ddsprod + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Data input latency. +wire [31:0] din_la ; + +// DDS output. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +// Real/Imaginary parts of product. +wire [15:0] din_real ; +wire [15:0] din_imag ; +wire [15:0] dds_real ; +wire [15:0] dds_imag ; + +// Full-precision product output. +wire [31:0] prod_real ; +wire [31:0] prod_imag ; + +// Quantized product. +wire [15:0] prod_real_q ; +wire [15:0] prod_imag_q ; +wire [31:0] prod ; +reg [31:0] prod_r1 ; + +// Latency for output valid. +wire valid_la ; + + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// DDS block. +// Latency: 19. +dds_top dds_top_i + ( + // Clock. + .aclk (aclk ), + + // Input valid. + .din_valid (s_axis_tvalid ), + + // Output data. + .dout_valid (dds_dout_valid ), + .dout (dds_dout ), + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// Latency for input data. +// Latency = 19 (dds top). +latency_reg + #( + .N(19), + .B(32) + ) + latency_reg_din_i + ( + .clk (aclk ), + .din (s_axis_tdata ), + .dout (din_la ) + ); + +// Real/Imaginary parts of product. +assign din_real = din_la [15:0] ; +assign din_imag = din_la [31:16] ; +assign dds_real = dds_dout [15:0] ; +assign dds_imag = dds_dout [31:16] ; + +// Full-speed, 16x16 complex product. +// Latency: 4. +cmult_16x16 cmult_i + ( + .clk (aclk ), + .din_i0 (din_real ), + .din_q0 (din_imag ), + .din_i1 (dds_real ), + .din_q1 (dds_imag ), + .dout_i (prod_real ), + .dout_q (prod_imag ) + ); + +// Quantized prodoct. +assign prod_real_q = prod_real [30 -: 16]; +assign prod_imag_q = prod_imag [30 -: 16]; +assign prod = {prod_imag_q, prod_real_q}; + +// Latency for output valid. +// Latency = 4 (cmult) + 1 (output register). +latency_reg + #( + .N(5), + .B(1) + ) + latency_reg_valid_i + ( + .clk (aclk ), + .din (dds_dout_valid ), + .dout (valid_la ) + ); + +// Registers. +always @(posedge aclk) begin + // Quantized product. + prod_r1 <= prod; +end + +// Assign outputs. +assign m_axis_tvalid = valid_la ; +assign m_axis_tdata = prod_r1 ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv new file mode 100644 index 000000000..6ca0d428b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv @@ -0,0 +1,129 @@ +/* + * This block instantiates 4 ddsprod blocks to apply + * the dds product to 4 independent inputs, with 4 + * independent DDS blocks. + */ +module ddsprod_v + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s0_axis_tdata , + input wire [31:0] s1_axis_tdata , + input wire [31:0] s2_axis_tdata , + input wire [31:0] s3_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + + // Registers. + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Number of inputs/outputs. +localparam N = 4; + +// Input valid. +reg vin_r ; + +// Output valid. +wire [N-1:0] vout_v ; +reg vout_r ; + +// Vectorized inputs. +wire [31:0] din_v [N] ; +reg [31:0] din_r [N] ; + +// Vectorized outputs. +wire [31:0] dout_v [N] ; +reg [31:0] dout_r [N] ; + +// Vectorized registers. +reg [31:0] pinc_v [N] ; +reg [31:0] poff_v [N] ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Vectorized inputs. +assign din_v [0] = s0_axis_tdata ; +assign din_v [1] = s1_axis_tdata ; +assign din_v [2] = s2_axis_tdata ; +assign din_v [3] = s3_axis_tdata ; + +// Vectorized registers. +assign pinc_v [0] = PINC0_REG ; +assign pinc_v [1] = PINC1_REG ; +assign pinc_v [2] = PINC2_REG ; +assign pinc_v [3] = PINC3_REG ; +assign poff_v [0] = POFF0_REG ; +assign poff_v [1] = POFF1_REG ; +assign poff_v [2] = POFF2_REG ; +assign poff_v [3] = POFF3_REG ; + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd similarity index 80% rename from firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd rename to firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd index eb83d1a5d..e1f76f7f7 100644 --- a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd @@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; use IEEE.NUMERIC_STD.ALL; -entity fifo_dc_axi is +entity fifo_axi is Generic ( -- Data width. @@ -14,12 +14,9 @@ entity fifo_dc_axi is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -32,12 +29,12 @@ entity fifo_dc_axi is full : out std_logic; empty : out std_logic ); -end fifo_dc_axi; +end fifo_axi; -architecture rtl of fifo_dc_axi is +architecture rtl of fifo_axi is --- Dual-clock FIFO. -component fifo_dc is +-- FIFO. +component fifo is Generic ( -- Data width. @@ -48,12 +45,9 @@ component fifo_dc is ); Port ( - wr_rstn : in std_logic; - wr_clk : in std_logic; + rstn : in std_logic; + clk : in std_logic; - rd_rstn : in std_logic; - rd_clk : in std_logic; - -- Write I/F. wr_en : in std_logic; din : in std_logic_vector (B-1 downto 0); @@ -98,8 +92,8 @@ signal empty_i : std_logic; begin --- Dual-clock FIFO. -fifo_i : fifo_dc +-- FIFO. +fifo_i : fifo Generic map ( -- Data width. @@ -110,12 +104,9 @@ fifo_i : fifo_dc ) Port map ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , + rstn => rstn , + clk => clk , - rd_rstn => rd_rstn , - rd_clk => rd_clk , - -- Write I/F. wr_en => wr_en , din => din , @@ -138,8 +129,8 @@ rd2axi_i : rd2axi ) Port map ( - rstn => rd_rstn , - clk => rd_clk , + rstn => rstn , + clk => clk , -- FIFO Read I/F. fifo_rd_en => rd_en_i , diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v b/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v new file mode 100644 index 000000000..b18c03930 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v @@ -0,0 +1,53 @@ +module latency_reg + ( + clk , + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +// Array initialization. +integer i; +initial begin + for (i=0; i '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd new file mode 100644 index 000000000..b8f1a8f5f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd new file mode 100644 index 000000000..26af1d6a7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd new file mode 100644 index 000000000..8ec9c8d10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd new file mode 100644 index 000000000..c943462db --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd new file mode 100644 index 000000000..32dae9491 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x64/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x64_scalar2vector; +architecture structural of ssr_8x64_scalar2vector is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_concat; +architecture structural of ssr_8x64_vector_concat is + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_delay; +architecture structural of ssr_8x64_vector_delay is + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret; +architecture structural of ssr_8x64_vector_reinterpret is + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret1; +architecture structural of ssr_8x64_vector_reinterpret1 is + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret2; +architecture structural of ssr_8x64_vector_reinterpret2 is + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret3; +architecture structural of ssr_8x64_vector_reinterpret3 is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_im; +architecture structural of ssr_8x64_vector_slice_im is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_re; +architecture structural of ssr_8x64_vector_slice_re is + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x64_vector2scalar; +architecture structural of ssr_8x64_vector2scalar is + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c0fcf025b9 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 6-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 6-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_fft; +architecture structural of ssr_8x64_vector_fft is + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 6-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x64_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x64_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x64_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x64_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x64_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x64_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x64_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x64_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x64_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x64_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 6 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_im; +architecture structural of ssr_8x64_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x64/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_re; +architecture structural of ssr_8x64_i_re is + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x64_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_struct is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_struct; +architecture structural of ssr_8x64_struct is + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x64_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x64_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x64_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_default_clock_driver is + port ( + ssr_8x64_sysclk : in std_logic; + ssr_8x64_sysce : in std_logic; + ssr_8x64_sysclr : in std_logic; + ssr_8x64_clk1 : out std_logic; + ssr_8x64_ce1 : out std_logic + ); +end ssr_8x64_default_clock_driver; +architecture structural of ssr_8x64_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x64_sysclk, + sysce => ssr_8x64_sysce, + sysclr => ssr_8x64_sysclr, + clk => ssr_8x64_clk1, + ce => ssr_8x64_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64 is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64; +architecture structural of ssr_8x64 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x64,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x64_default_clock_driver : entity xil_defaultlib.ssr_8x64_default_clock_driver + port map ( + ssr_8x64_sysclk => clk, + ssr_8x64_sysce => '1', + ssr_8x64_sysclr => '0', + ssr_8x64_clk1 => clk_1_net, + ssr_8x64_ce1 => ce_1_net + ); + ssr_8x64_struct : entity xil_defaultlib.ssr_8x64_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd new file mode 100644 index 000000000..0edbfe3e1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x64_xldelay; + +architecture behavior of ssr_8x64_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=AB + P:out SFIXED; -- O=AB + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=CAB + P:out SFIXED); -- O=CAB +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=AB + P:out SFIXED); -- O=AB +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61; +architecture structural of WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(5 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(5 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x64_xlslice; + +architecture behavior of ssr_8x64_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_384683215a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_384683215a; +architecture behavior of sysgen_concat_384683215a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_53c8e6f5a2 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_53c8e6f5a2; +architecture behavior of sysgen_reinterpret_53c8e6f5a2 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d7a483898b is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d7a483898b; +architecture behavior of sysgen_reinterpret_d7a483898b +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c0fcf025b9 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c0fcf025b9; +architecture behavior of sysgen_concat_c0fcf025b9 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd new file mode 100644 index 000000000..770ff703a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd new file mode 100644 index 000000000..5d837de43 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd new file mode 100644 index 000000000..34bfa2e8c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd new file mode 100644 index 000000000..92017d49a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd new file mode 100644 index 000000000..606006cf5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x64_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x64. +component ssr_8x64 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 6-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 6-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (5 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (5 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (5 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x1024. +ssr_8x64_i : ssr_8x64 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd new file mode 100644 index 000000000..1303dec75 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd @@ -0,0 +1,301 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 64; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x64_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_re_7 & i_im_6 & i_re_6 & i_im_5 & i_re_5 & i_im_4 & i_re_4 & i_im_3 & i_re_3 & i_im_2 & i_re_2 & i_im_1 & i_re_1 & i_im_0 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_im_0 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_1 <= m_axis_tdata (3*B-1 downto 2*B); +o_im_1 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_2 <= m_axis_tdata (5*B-1 downto 4*B); +o_im_2 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_3 <= m_axis_tdata (7*B-1 downto 6*B); +o_im_3 <= m_axis_tdata (8*B-1 downto 7*B); +o_re_4 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_4 <= m_axis_tdata (10*B-1 downto 9*B); +o_re_5 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_5 <= m_axis_tdata (12*B-1 downto 11*B); +o_re_6 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_6 <= m_axis_tdata (14*B-1 downto 13*B); +o_re_7 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + --wait for 110 ns; + --rd_start <= '0'; + --wait for 220 ns; + --rd_start <= '1'; + --wait for 490 ns; + --rd_start <= '0'; + --wait for 100 ns; + --rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + for K in 0 to 200 loop + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(10000,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + --for J in 0 to 2 loop + -- while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + -- end loop; + -- wait until rising_edge(aclk); + -- s_axis_tlast <= '0'; + -- s_axis_tvalid <= '1'; + -- i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + -- I := I + 1; + --end loop; + + --while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + --end loop; + --wait until rising_edge(aclk); + --s_axis_tlast <= '1'; + --s_axis_tvalid <= '1'; + --i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + --I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd new file mode 100644 index 000000000..c07cb2e44 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile new file mode 100644 index 000000000..df6451cd1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl new file mode 100644 index 000000000..9523c5de6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe new file mode 100644 index 000000000..90cedee5f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -409,-1113,14782,1965,1397,-401,0,-481,-393,12156,4247,1154,-459,0,-509,245,9446,6773,767,-499,0,-499,767,6773,9446,245,-509,0,-459,1154,4247,12156,-393,-481,0,-401,1397,1965,14782,-1113,-409,0,-331,1501,4,17203,-1868,-288,12,-259,1480,-1584,19303,-2600,-116,10 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe new file mode 100644 index 000000000..c69516550 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -190,1356,-2768,20978,-3243,101,2,-129,1154,-3547,22144,-3726,353,-14,-79,903,-3937,22742,-3979,627,-41,-41,627,-3979,22742,-3937,903,-79,-14,353,-3726,22144,-3547,1154,-129,2,101,-3243,20978,-2768,1356,-190,10,-116,-2600,19303,-1584,1480,-259,12,-288,-1868,17203,4,1501,-331 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe new file mode 100644 index 000000000..8a55eee10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -432,-928,14140,2508,1349,-417,0,-492,-225,11481,4859,1070,-471,0,-510,387,8770,7431,649,-504,0,-491,877,6123,10125,95,-506,0,-446,1228,3650,12825,-567,-468,0,-384,1435,1442,15411,-1301,-383,90,-313,1507,-430,17763,-2056,-249,12,-241,1458,-1918,19765,-2772,-66,9 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe new file mode 100644 index 000000000..a5989f588 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -174,1312,-3001,21320,-3381,161,-1,-116,1095,-3680,22349,-3813,421,-20,-68,835,-3979,22799,-3999,697,-49,-33,558,-3941,22648,-3874,969,-91,-9,288,-3624,21904,-3390,1211,-143,5,43,-3094,20604,-2511,1396,-206,11,-164,-2423,18814,-1224,1496,-277,12,-323,-1679,16624,461,1487,-349 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe new file mode 100644 index 000000000..5c3d7af8a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -451,-746,13487,3070,1293,-432,0,-500,-62,10804,5485,978,-482,0,-508,522,8098,8098,522,-508,0,-482,978,5485,10804,-62,-500,0,-432,1293,3070,13487,-746,-451,0,-367,1466,940,16026,-1490,-355,12,-295,1505,-839,18300,-2241,-208,12,-224,1430,-2227,20199,-2937,-13,7 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe new file mode 100644 index 000000000..f5b7af060 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -158,1263,-3208,21629,-3509,223,-5,-103,1033,-3789,22517,-3885,489,-26,-59,766,-3999,22818,-3999,766,-59,-26,489,-3885,22517,-3789,1033,-103,-5,223,-3509,21629,-3208,1263,-158,7,-13,-2937,20199,-2227,1430,-224,12,-208,-2241,18300,-839,1505,-295,12,-355,-1490,16026,940,1466,-367 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe new file mode 100644 index 000000000..5e0828d8f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -468,-567,12825,3650,1228,-446,0,-506,95,10125,6123,877,-491,0,-504,649,7431,8770,387,-510,0,-471,1070,4859,11481,-225,-492,0,-417,1349,2508,14140,-928,-432,0,-349,1487,461,16624,-1679,-323,12,-277,1496,-1224,18814,-2423,-164,11,-206,1396,-2511,20604,-3094,43,5 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe new file mode 100644 index 000000000..e67b9d3e7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -143,1211,-3390,21904,-3624,288,-9,-91,969,-3874,22648,-3941,558,-33,-49,697,-3999,22799,-3979,835,-68,-20,421,-3813,22349,-3680,1095,-116,-1,161,-3381,21320,-3001,1312,-174,9,-66,-2772,19765,-1918,1458,-241,12,-249,-2056,17763,-430,1507,-313,90,-383,-1301,15411,1442,1435,-384 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl new file mode 100644 index 000000000..df91aaf83 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo new file mode 100644 index 000000000..b9961ec8a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci new file mode 100644 index 000000000..6e7f4b1f3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci new file mode 100644 index 000000000..b475838b2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci new file mode 100644 index 000000000..3bc1fc617 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci new file mode 100644 index 000000000..f8e26b37e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci new file mode 100644 index 000000000..ee9dedca1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci new file mode 100644 index 000000000..a1288f46d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci new file mode 100644 index 000000000..c39cf3d16 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci new file mode 100644 index 000000000..3d7985f82 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl new file mode 100755 index 000000000..deba046dc --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template new file mode 100644 index 000000000..264e198ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl new file mode 100644 index 000000000..e1a370512 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv new file mode 100644 index 000000000..195dd2ae5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv @@ -0,0 +1,301 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r = 1'b0; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv new file mode 100644 index 000000000..ec89d1bc9 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv @@ -0,0 +1,108 @@ +// This block will extract 1 channel from the TDM-input. +// It uses ID_REG which is as follows: +// ID_REG [7:0] : packet. +// ID_REG [15:8] : index. +// +// Input packets are as follows: +// |-------| |-------| +// | | | | +// tlast --------------| |-------------| | +// +// |-----|-------|-------|-----|-------|-------| +// t | 0 | L | 2*L | 0 | L | 2*L | +// a | 1 | L+1 | 2*L+1 | 1 | L+1 | 2*L+1 | +// d | 2 | L+2 | 2*L+2 | 2 | L+2 | 2*L+2 | +// a | . | . | . | . | . | . | +// t | . | . | . | . | . | . | +// a | . | . | . | . | . | . | +// | L-1 | 2*L-1 | 3*L-1 | L-1 | 2*L-1 | 3*L-1 | +// |-----|-------|-------|-----|-------|-------| +// +// The internal counter counts packets relying on tlast and resets. +// Offset within a packet is given by index. +module pfb_chsel + #( + // Bits. + parameter B = 32, + + // Number of lanes. + parameter L = 8 + ) + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire [L*B-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [B-1:0] m_axis_tdata , + + // Registers. + input wire [15:0] ID_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Packet counter. +reg [7:0] cnt = 0; +wire wr_en; + +// Registers. +reg [7:0] packet_reg ; +reg [7:0] index_reg ; + +// Data registers. +reg [L*B-1:0] tdata_r ; +reg [B-1:0] data_mux_r ; + +// Muxed data. +wire [B-1:0] data_mux ; + +// tlast_pipeline (for tvalid). +reg tlast_r1 ; +reg tlast_r2 ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Packet counter. +assign wr_en = (cnt == packet_reg)? 1'b1 : 1'b0; + +// Muxed data. +assign data_mux = tdata_r [index_reg*B +: B]; + +// Registers. +always @(posedge aclk) begin + // Packet counter. + if (s_axis_tlast == 1'b1) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + packet_reg <= ID_REG [7:0]; + index_reg <= ID_REG [15:8]; + + // Data registers. + if (wr_en == 1'b1) + tdata_r <= s_axis_tdata; + + if (tlast_r1 == 1'b1) + data_mux_r <= data_mux; + + // tlast_pipeline (for tvalid). + tlast_r1 <= s_axis_tlast; + tlast_r2 <= tlast_r1; +end + +// Assign outputs. +assign m_axis_tvalid = tlast_r2; +assign m_axis_tdata = data_mux_r; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd new file mode 100644 index 000000000..24bd0a2c3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd new file mode 100644 index 000000000..db99fb3cf --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd new file mode 100644 index 000000000..5ff7e746f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv new file mode 100644 index 000000000..4b57dab4a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv @@ -0,0 +1,113 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1 = 0; +reg [2*L*B-1:0] data_r2 = 0; +reg [2*L*B-1:0] data_r3 = 0; +reg [2*L*B-1:0] data_r4 = 0; + +// Tlast registers. +reg last_r1 = 0; +reg last_r2 = 0; +reg last_r3 = 0; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd new file mode 100644 index 000000000..2add8e524 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v b/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v new file mode 100644 index 000000000..acba9e8d6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v @@ -0,0 +1,124 @@ +/* + * Top-leve block which instantiates the following: + * + * 1) PFB, 50 % Overlap, 64 Channels, 4 selectable outputs. + * 2) DDS, 4 channels, independent freq/phase, phase coherent. + */ +module pfb_readout + #( + // Number of channels. + parameter N = 32, + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [L*32-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + + // Registers. + input wire [15:0] ID0_REG , + input wire [15:0] ID1_REG , + input wire [15:0] ID2_REG , + input wire [15:0] ID3_REG , + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +wire tvalid_i; +wire [31:0] tdata0_i; +wire [31:0] tdata1_i; +wire [31:0] tdata2_i; +wire [31:0] tdata3_i; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// PFB. +pfb_top + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(L) + ) + pfb_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (tvalid_i ), + .m0_axis_tdata (tdata0_i ), + .m1_axis_tdata (tdata1_i ), + .m2_axis_tdata (tdata2_i ), + .m3_axis_tdata (tdata3_i ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ) + ); + +// DDS. +ddsprod_v ddsprod_v_i + ( + // Clock. + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (tvalid_i ), + .s0_axis_tdata (tdata0_i ), + .s1_axis_tdata (tdata1_i ), + .s2_axis_tdata (tdata2_i ), + .s3_axis_tdata (tdata3_i ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc new file mode 100644 index 000000000..d22e7ee64 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc @@ -0,0 +1,60 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wstrb[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wstrb[*]}] +set _xlnx_shared_i0 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_wready] +set_clock_groups -asynchronous -group [get_clocks s_axi_aclk] -group [get_clocks aclk] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc new file mode 100644 index 000000000..46515ba89 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports en] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports en] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc new file mode 100644 index 000000000..8e8a0a2c1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc new file mode 100644 index 000000000..5505ca00c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc @@ -0,0 +1,15 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {s_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {m_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {m_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] + +set_false_path -to [get_ports *m_axis*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv new file mode 100644 index 000000000..3665426e1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv @@ -0,0 +1,339 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of channels. +parameter N = 64; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; + +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +reg s_axis_tvalid; +wire [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +reg [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +reg [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +reg [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +reg [31:0] m3_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire [15:0] dout0_real; +wire [15:0] dout0_imag; +wire [15:0] dout1_real; +wire [15:0] dout1_imag; +wire [15:0] dout2_real; +wire [15:0] dout2_imag; +wire [15:0] dout3_real; +wire [15:0] dout3_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +assign dout0_real = m0_axis_tdata [15:0]; +assign dout0_imag = m0_axis_tdata [31:16]; +assign dout1_real = m1_axis_tdata [15:0]; +assign dout1_imag = m1_axis_tdata [31:16]; +assign dout2_real = m2_axis_tdata [15:0]; +assign dout2_imag = m2_axis_tdata [31:16]; +assign dout3_real = m3_axis_tdata [15:0]; +assign dout3_imag = m3_axis_tdata [31:16]; + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v3 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // ID0/1/2/3. + // ID [7:0]: packet + // ID [15:8]: id + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, (0 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, (1 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, (6 << 8) + 0, resp); + + // FREQ0/PHASE0. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, 0, resp); + + // FREQ1/PHASE1. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, freq(1,10), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, 0, resp); + + // FREQ2/PHASE2. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, freq(1, 33), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, 0, resp); + + // FREQ3/PHASE3. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, 0, resp); + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv new file mode 100644 index 000000000..d272783bf --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv @@ -0,0 +1,72 @@ +module tb(); + +// Reset and clock. +reg aclk ; + +// Enable input. +reg en ; + +// Output data. +wire dout_valid ; +wire [71:0] dout ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ + +/****************/ +/* Architecture */ +/****************/ + +// DUT. +dds_ctrl DUT + ( + // Reset and clock. + .aclk , + + // Enable input. + .en , + + // Output data. + .dout_valid , + .dout , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 1234; + POFF_REG <= 4567; + + #1000; +end + +// en. +initial begin + en <= 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + en <= 0; + end + @(posedge aclk); + en <= 1; + end +end + +always begin + aclk <= 0; + #8; + aclk <= 1; + #8; +end + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv new file mode 100644 index 000000000..554077ef6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv @@ -0,0 +1,77 @@ +module tb(); + +// Reset and clock. +reg aclk ; + +// Input valid. +reg din_valid ; + +// Output data. +wire dout_valid ; +wire [31:0] dout ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ +wire [15:0] dout_real ; +wire [15:0] dout_imag ; + +/****************/ +/* Architecture */ +/****************/ + +assign dout_real = dout[15:0]; +assign dout_imag = dout[31:16]; + +// DUT. +dds_top DUT + ( + // Reset and clock. + .aclk , + + // Input valid. + .din_valid , + + // Output data. + .dout_valid , + .dout , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 12345959; + POFF_REG <= 4567; + + #1000; +end + +// din_valid. +initial begin + din_valid <= 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + din_valid <= 0; + end + @(posedge aclk); + din_valid <= 1; + end +end + +always begin + aclk <= 0; + #8; + aclk <= 1; + #8; +end + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv new file mode 100644 index 000000000..86942bdf6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv @@ -0,0 +1,122 @@ +module tb(); + +// Clock. +reg aclk ; + +// S_AXIS for input data. +reg s_axis_tvalid ; +wire [31:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m_axis_tvalid ; +wire [31:0] m_axis_tdata ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ +reg [15:0] din_real ; +reg [15:0] din_imag ; +wire [15:0] dout_real ; +wire [15:0] dout_imag ; + +/****************/ +/* Architecture */ +/****************/ + +assign s_axis_tdata = {din_imag, din_real}; +assign dout_real = m_axis_tdata [15:0]; +assign dout_imag = m_axis_tdata [31:16]; + +// DUT. +ddsprod DUT + ( + // Clock. + .aclk , + + // S_AXIS for input data. + .s_axis_tvalid , + .s_axis_tdata , + + // M_AXIS for output data. + .m_axis_tvalid , + .m_axis_tdata , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 0; + POFF_REG <= 0; + + #1000; + + // Set dds frequency/phase. + PINC_REG <= freq(1, 500); + POFF_REG <= phase(90); +end + +// Input data. +initial begin + int n; + real a0, w0, f0, fs; + + s_axis_tvalid <= 0; + din_real <= 0; + din_imag <= 0; + + // Amplitude. + a0 = 0.5; + + // Frequency. + fs = 500; + f0 = 1; + w0 = f0/fs*2*3.14159; + + n = 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + s_axis_tvalid <= 0; + end + @(posedge aclk); + s_axis_tvalid <= 1; + din_real <= a0*2**15*$cos(w0*n); + din_imag <= a0*2**15*$sin(w0*n); + n = n+1; + end +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv new file mode 100644 index 000000000..2fa3c8820 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv @@ -0,0 +1,181 @@ +module tb(); + +// Number of channels. +parameter N = 64; + +// Number of Lanes (Input). +parameter L = 4; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// S_AXIS for input data. +reg s_axis_tvalid ; +wire [L*32-1:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m_axis_tvalid ; +wire m_axis_tlast ; +wire [2*L*32-1:0] m_axis_tdata ; + +// Registers. +reg [7:0] QOUT_REG ; + +/**************/ +/* Test Bench */ +/**************/ +localparam NCH = N/(2*L); +// x4 clock. +reg aclk_x4 ; +reg [15:0] din_real ; +reg [15:0] din_imag ; +reg [31:0] din [L] ; + +// x8 clock. +reg aclk_x8 ; + +// TDM Demux outputs. +reg tdm_sync ; +wire [NCH*32-1:0] tdm_dout [2*L] ; +wire [2*L-1:0] tdm_valid ; +wire signed [15:0] dout_real_ii [2*L][NCH] ; +wire signed [15:0] dout_imag_ii [2*L][NCH] ; + + +/****************/ +/* Architecture */ +/****************/ +genvar i,j; +generate + // Input data. + for (i=0; i parallel. +always @(posedge aclk) begin + for (int i=0; i parallel. +always @(posedge aclk) begin + for (int i=0; i + + QICK + QICK + axis_pfb_readout_v4 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + m4_axis + + + + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_pfb_readout_v4 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9ebcf76d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_pfb_readout_v4 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9ebcf76d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + 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xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfb_readout_v4_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS PFB Readout, 64 Channels, 8 outputs, V4. + + + N + N + 64 + + + Component_Name + axis_pfb_readout_v4_v1_0 + + + + + + zynquplus + + + /QICK/Readout + + AXIS PFB Readout V4 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2024-04-12T14:13:36Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v b/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v new file mode 100644 index 000000000..74f5f842f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v @@ -0,0 +1,1070 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [15:0] ID0_REG , + output wire [15:0] ID1_REG , + output wire [15:0] ID2_REG , + output wire [15:0] ID3_REG , + output wire [15:0] ID4_REG , + output wire [15:0] ID5_REG , + output wire [15:0] ID6_REG , + output wire [15:0] ID7_REG , + output wire [31:0] PINC0_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF7_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign ID0_REG = slv_reg0 [15:0] ; +assign ID1_REG = slv_reg1 [15:0] ; +assign ID2_REG = slv_reg2 [15:0] ; +assign ID3_REG = slv_reg3 [15:0] ; +assign ID4_REG = slv_reg4 [15:0] ; +assign ID5_REG = slv_reg5 [15:0] ; +assign ID6_REG = slv_reg6 [15:0] ; +assign ID7_REG = slv_reg7 [15:0] ; +assign PINC0_REG = slv_reg8 ; +assign POFF0_REG = slv_reg9 ; +assign PINC1_REG = slv_reg10 ; +assign POFF1_REG = slv_reg11 ; +assign PINC2_REG = slv_reg12 ; +assign POFF2_REG = slv_reg13 ; +assign PINC3_REG = slv_reg14 ; +assign POFF3_REG = slv_reg15 ; +assign PINC4_REG = slv_reg16 ; +assign POFF4_REG = slv_reg17 ; +assign PINC5_REG = slv_reg18 ; +assign POFF5_REG = slv_reg19 ; +assign PINC6_REG = slv_reg20 ; +assign POFF6_REG = slv_reg21 ; +assign PINC7_REG = slv_reg22 ; +assign POFF7_REG = slv_reg23 ; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v b/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v new file mode 100644 index 000000000..c272e0db9 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v @@ -0,0 +1,241 @@ +module axis_pfb_readout_v4 + #( + // Number of channels. + parameter N = 64 + ) + ( + // AXI Slave I/F for configuration. + input s_axi_aclk , + input s_axi_aresetn , + + input [7:0] s_axi_awaddr , + input [2:0] s_axi_awprot , + input s_axi_awvalid , + output s_axi_awready , + + input [31:0] s_axi_wdata , + input [3:0] s_axi_wstrb , + input s_axi_wvalid , + output s_axi_wready , + + output [1:0] s_axi_bresp , + output s_axi_bvalid , + input s_axi_bready , + + input [7:0] s_axi_araddr , + input [2:0] s_axi_arprot , + input s_axi_arvalid , + output s_axi_arready , + + output [31:0] s_axi_rdata , + output [1:0] s_axi_rresp , + output s_axi_rvalid , + input s_axi_rready , + + // s_* and m_* reset/clock. + input aresetn , + input aclk , + + // S_AXIS for input samples + input s_axis_tvalid , + input [4*32-1:0] s_axis_tdata , + + // M_AXIS for CH0 output. + output m0_axis_tvalid , + output [31:0] m0_axis_tdata , + + // M_AXIS for CH1 output. + output m1_axis_tvalid , + output [31:0] m1_axis_tdata , + + // M_AXIS for CH2 output. + output m2_axis_tvalid , + output [31:0] m2_axis_tdata , + + // M_AXIS for CH3 output. + output m3_axis_tvalid , + output [31:0] m3_axis_tdata , + + // M_AXIS for CH4 output. + output m4_axis_tvalid , + output [31:0] m4_axis_tdata , + + // M_AXIS for CH5 output. + output m5_axis_tvalid , + output [31:0] m5_axis_tdata , + + // M_AXIS for CH6 output. + output m6_axis_tvalid , + output [31:0] m6_axis_tdata , + + // M_AXIS for CH7 output. + output m7_axis_tvalid , + output [31:0] m7_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] ID0_REG ; +wire [15:0] ID1_REG ; +wire [15:0] ID2_REG ; +wire [15:0] ID3_REG ; +wire [15:0] ID4_REG ; +wire [15:0] ID5_REG ; +wire [15:0] ID6_REG ; +wire [15:0] ID7_REG ; +wire [31:0] PINC0_REG ; +wire [31:0] POFF0_REG ; +wire [31:0] PINC1_REG ; +wire [31:0] POFF1_REG ; +wire [31:0] PINC2_REG ; +wire [31:0] POFF2_REG ; +wire [31:0] PINC3_REG ; +wire [31:0] POFF3_REG ; +wire [31:0] PINC4_REG ; +wire [31:0] POFF4_REG ; +wire [31:0] PINC5_REG ; +wire [31:0] POFF5_REG ; +wire [31:0] PINC6_REG ; +wire [31:0] POFF6_REG ; +wire [31:0] PINC7_REG ; +wire [31:0] POFF7_REG ; + +// Internal valid. +wire valid_int ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +// PFB with DDS product. +pfb_readout + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(4) + ) + pfb_readout_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (valid_int ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + .m4_axis_tdata (m4_axis_tdata ), + .m5_axis_tdata (m5_axis_tdata ), + .m6_axis_tdata (m6_axis_tdata ), + .m7_axis_tdata (m7_axis_tdata ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +// Assign outputs. +assign m0_axis_tvalid = valid_int; +assign m1_axis_tvalid = valid_int; +assign m2_axis_tvalid = valid_int; +assign m3_axis_tvalid = valid_int; +assign m4_axis_tvalid = valid_int; +assign m5_axis_tvalid = valid_int; +assign m6_axis_tvalid = valid_int; +assign m7_axis_tvalid = valid_int; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v new file mode 100644 index 000000000..1c268a7f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v @@ -0,0 +1,46 @@ +module cmult_16x16 + ( + input wire clk , + input wire [15:0] din_i0 , + input wire [15:0] din_q0 , + input wire [15:0] din_i1 , + input wire [15:0] din_q1 , + output wire [31:0] dout_i , + output wire [31:0] dout_q + ); + +/****************/ +/* Architecture */ +/****************/ + +// Real part. +cmult_sub + #( + .op("sub") + ) + cmult_real_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_i1 ), + .c (din_q0 ), + .d (din_q1 ), + .x (dout_i ) + ); + +// Imaginary part. +cmult_sub + #( + .op("add") + ) + cmult_imag_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_q1 ), + .c (din_q0 ), + .d (din_i1 ), + .x (dout_q ) + ); + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v new file mode 100644 index 000000000..b0466a9a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v @@ -0,0 +1,82 @@ +module cmult_sub + #( + parameter op = "sub" + ) + ( + input wire clk , + input wire [15:0] a , + input wire [15:0] b , + input wire [15:0] c , + input wire [15:0] d , + output wire [31:0] x + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg signed [15:0] a_r1; +reg signed [15:0] b_r1; +reg signed [15:0] c_r1; +reg signed [15:0] c_r2; +reg signed [15:0] d_r1; +reg signed [15:0] d_r2; + +// Partial products. +wire signed [31:0] ab; +wire signed [31:0] cd; + +// Pipeline of partial products. +reg signed [31:0] ab_r1; +reg signed [31:0] ab_r2; +reg signed [31:0] cd_r1; + +// Combined result. +wire signed [31:0] res; + +// Pipelined result. +reg signed [31:0] res_r1; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign ab = a_r1*b_r1; +assign cd = c_r2*d_r2; + +// Combined result. +generate + if (op == "sub") begin + assign res = ab_r2 - cd_r1; + end + else if (op == "add") begin + assign res = ab_r2 + cd_r1; + end +endgenerate + +// Registers. +always @(posedge clk) begin + // Input pipeline. + a_r1 <= a; + b_r1 <= b; + c_r1 <= c; + c_r2 <= c_r1; + d_r1 <= d; + d_r2 <= d_r1; + + // Pipeline of partial products. + ab_r1 <= ab; + ab_r2 <= ab_r1; + cd_r1 <= cd; + + // Pipelined result. + res_r1 <= res; +end + +/***********/ +/* Outputs */ +/***********/ +assign x = res_r1; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci new file mode 100644 index 000000000..6ef4c7e10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci @@ -0,0 +1,476 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/dds_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv new file mode 100644 index 000000000..c3c02b3bd --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv @@ -0,0 +1,110 @@ +/* + * DDS Control input: + * + * |----------|--------|----------|--------| + * | 71 .. 65 | 64 | 63 .. 32 | 31 .. 0| + * |----------|--------|----------|--------| + * | not used | resync | poff | pinc | + * |----------|--------|----------|--------| + * +*/ + +module dds_ctrl + ( + // Clock. + input wire aclk , + + // Enable input. + input wire en , + + // Output data. + output wire dout_valid , + output wire [71:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Time counter. +reg [31:0] cnt = 0; +reg [31:0] cnt_r1 = 0; + +// Registers. +reg [31:0] pinc_r1 = 0; +reg [31:0] pinc_r2 = 0; +reg [31:0] poff_r1 = 0; + +// Multiplier output (modulo arithmetic, keep lower bits). +wire [31:0] mult_int; + +// Final phase. +wire [31:0] poff_out; +reg [31:0] poff_out_r1; + +// Output control word. +wire [71:0] dds_ctrl_out; + +// latency for en. +wire en_la; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Final phase. +assign poff_out = poff_r1 + mult_int; + +// Output control word. +assign dds_ctrl_out = {7'b0000000,1'b1,poff_out_r1,pinc_r2}; + +// Multiplier: 32x32, unsigned, optimized for speed. +// Latency: 6. +(* keep_hierarchy = "true" *) mult_32x32 mult_i + ( + .clk (aclk ), + .din_a (pinc_r1 ), + .din_b (cnt_r1 ), + .dout (mult_int ) + ); + +// Latency for en (valid). +// Latency = 2 (cnt) + 6 (mult_32x32) + 1 (poff_out) = 9. +latency_reg + #( + .N(9), + .B(1) + ) + latency_reg_en_i + ( + .clk (aclk ), + .din (en ), + .dout (en_la ) + ); + + +// Registers. +always @(posedge aclk) begin + // Time counter. + if (en == 1'b1) + cnt <= cnt + 1; + cnt_r1 <= cnt; + + // Registers. + pinc_r1 <= PINC_REG; + pinc_r2 <= pinc_r1; + poff_r1 <= POFF_REG; + + // Final phase. + poff_out_r1 <= poff_out; +end + +// Assign outputs. +assign dout_valid = en_la ; +assign dout = dds_ctrl_out ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv new file mode 100644 index 000000000..e2a73654a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv @@ -0,0 +1,68 @@ +module dds_top + ( + // Clock. + input wire aclk , + + // Input valid. + input wire din_valid , + + // Output data. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +// DDS control. +wire ctrl_dout_valid ; +wire [71:0] ctrl_dout ; + +// DDS. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS control. +// Latency: 9. +dds_ctrl dds_ctrl_i + ( + // Clock. + .aclk (aclk ), + + // Enable input. + .en (din_valid ), + + // Output data. + .dout_valid (ctrl_dout_valid ), + .dout (ctrl_dout ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ) + ); + +// DDS instance. +// Latency: 10. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(ctrl_dout_valid ), + .s_axis_phase_tdata (ctrl_dout ), + .m_axis_data_tvalid (dds_dout_valid ), + .m_axis_data_tdata (dds_dout ) + ); + +// Assign outputs. +assign dout_valid = dds_dout_valid ; +assign dout = dds_dout ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v b/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v new file mode 100644 index 000000000..d7ac0d311 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v @@ -0,0 +1,57 @@ +/* + * This multiplier is optimized for 32x32 unsigned, so both of the + * operands are wider than the 27 (or 26 for unsigned) and then + * 4 DSPs are used. Pipeline is such that full-speed is achieved. + * + * Optimal pipeline: 6. + * + */ +module mult_32x32 + ( + input wire clk , + input wire [31:0] din_a , + input wire [31:0] din_b , + output wire [63:0] dout + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg [31:0] din_a_r1 ; +reg [31:0] din_b_r1 ; + +// Product. +wire [63:0] p ; + +// Output pipeline. +reg [63:0] p_r1 ; +reg [63:0] p_r2 ; +reg [63:0] p_r3 ; +reg [63:0] p_r4 ; +reg [63:0] p_r5 ; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign p = din_a_r1*din_b_r1; + +// Registers. +always @(posedge clk) begin + // Input pipeline. + din_a_r1 <= din_a ; + din_b_r1 <= din_b ; + + // Output pipeline. + p_r1 <= p ; + p_r2 <= p_r1 ; + p_r3 <= p_r2 ; + p_r4 <= p_r3 ; + p_r5 <= p_r4 ; +end + +assign dout = p_r5; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv new file mode 100644 index 000000000..fd39b3d0a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv @@ -0,0 +1,135 @@ +module ddsprod + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Data input latency. +wire [31:0] din_la ; + +// DDS output. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +// Real/Imaginary parts of product. +wire [15:0] din_real ; +wire [15:0] din_imag ; +wire [15:0] dds_real ; +wire [15:0] dds_imag ; + +// Full-precision product output. +wire [31:0] prod_real ; +wire [31:0] prod_imag ; + +// Quantized product. +wire [15:0] prod_real_q ; +wire [15:0] prod_imag_q ; +wire [31:0] prod ; +reg [31:0] prod_r1 ; + +// Latency for output valid. +wire valid_la ; + + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// DDS block. +// Latency: 19. +dds_top dds_top_i + ( + // Clock. + .aclk (aclk ), + + // Input valid. + .din_valid (s_axis_tvalid ), + + // Output data. + .dout_valid (dds_dout_valid ), + .dout (dds_dout ), + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// Latency for input data. +// Latency = 19 (dds top). +latency_reg + #( + .N(19), + .B(32) + ) + latency_reg_din_i + ( + .clk (aclk ), + .din (s_axis_tdata ), + .dout (din_la ) + ); + +// Real/Imaginary parts of product. +assign din_real = din_la [15:0] ; +assign din_imag = din_la [31:16] ; +assign dds_real = dds_dout [15:0] ; +assign dds_imag = dds_dout [31:16] ; + +// Full-speed, 16x16 complex product. +// Latency: 4. +cmult_16x16 cmult_i + ( + .clk (aclk ), + .din_i0 (din_real ), + .din_q0 (din_imag ), + .din_i1 (dds_real ), + .din_q1 (dds_imag ), + .dout_i (prod_real ), + .dout_q (prod_imag ) + ); + +// Quantized prodoct. +assign prod_real_q = prod_real [30 -: 16]; +assign prod_imag_q = prod_imag [30 -: 16]; +assign prod = {prod_imag_q, prod_real_q}; + +// Latency for output valid. +// Latency = 4 (cmult) + 1 (output register). +latency_reg + #( + .N(5), + .B(1) + ) + latency_reg_valid_i + ( + .clk (aclk ), + .din (dds_dout_valid ), + .dout (valid_la ) + ); + +// Registers. +always @(posedge aclk) begin + // Quantized product. + prod_r1 <= prod; +end + +// Assign outputs. +assign m_axis_tvalid = valid_la ; +assign m_axis_tdata = prod_r1 ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv new file mode 100644 index 000000000..134eab891 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv @@ -0,0 +1,161 @@ +/* + * This block instantiates 4 ddsprod blocks to apply + * the dds product to 4 independent inputs, with 4 + * independent DDS blocks. + */ +module ddsprod_v + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s0_axis_tdata , + input wire [31:0] s1_axis_tdata , + input wire [31:0] s2_axis_tdata , + input wire [31:0] s3_axis_tdata , + input wire [31:0] s4_axis_tdata , + input wire [31:0] s5_axis_tdata , + input wire [31:0] s6_axis_tdata , + input wire [31:0] s7_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + output wire [31:0] m4_axis_tdata , + output wire [31:0] m5_axis_tdata , + output wire [31:0] m6_axis_tdata , + output wire [31:0] m7_axis_tdata , + + // Registers. + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG , + input wire [31:0] PINC4_REG , + input wire [31:0] POFF4_REG , + input wire [31:0] PINC5_REG , + input wire [31:0] POFF5_REG , + input wire [31:0] PINC6_REG , + input wire [31:0] POFF6_REG , + input wire [31:0] PINC7_REG , + input wire [31:0] POFF7_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Number of inputs/outputs. +localparam N = 8; + +// Input valid. +reg vin_r ; + +// Output valid. +wire [N-1:0] vout_v ; +reg vout_r ; + +// Vectorized inputs. +wire [31:0] din_v [N] ; +reg [31:0] din_r [N] ; + +// Vectorized outputs. +wire [31:0] dout_v [N] ; +reg [31:0] dout_r [N] ; + +// Vectorized registers. +reg [31:0] pinc_v [N] ; +reg [31:0] poff_v [N] ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Vectorized inputs. +assign din_v [0] = s0_axis_tdata ; +assign din_v [1] = s1_axis_tdata ; +assign din_v [2] = s2_axis_tdata ; +assign din_v [3] = s3_axis_tdata ; +assign din_v [4] = s4_axis_tdata ; +assign din_v [5] = s5_axis_tdata ; +assign din_v [6] = s6_axis_tdata ; +assign din_v [7] = s7_axis_tdata ; + +// Vectorized registers. +assign pinc_v [0] = PINC0_REG ; +assign pinc_v [1] = PINC1_REG ; +assign pinc_v [2] = PINC2_REG ; +assign pinc_v [3] = PINC3_REG ; +assign pinc_v [4] = PINC4_REG ; +assign pinc_v [5] = PINC5_REG ; +assign pinc_v [6] = PINC6_REG ; +assign pinc_v [7] = PINC7_REG ; +assign poff_v [0] = POFF0_REG ; +assign poff_v [1] = POFF1_REG ; +assign poff_v [2] = POFF2_REG ; +assign poff_v [3] = POFF3_REG ; +assign poff_v [4] = POFF4_REG ; +assign poff_v [5] = POFF5_REG ; +assign poff_v [6] = POFF6_REG ; +assign poff_v [7] = POFF7_REG ; + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v b/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v new file mode 100644 index 000000000..b18c03930 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v @@ -0,0 +1,53 @@ +module latency_reg + ( + clk , + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +// Array initialization. +integer i; +initial begin + for (i=0; i '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd new file mode 100644 index 000000000..b8f1a8f5f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd new file mode 100644 index 000000000..26af1d6a7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd new file mode 100644 index 000000000..8ec9c8d10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd new file mode 100644 index 000000000..c943462db --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd new file mode 100644 index 000000000..32dae9491 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x64/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x64_scalar2vector; +architecture structural of ssr_8x64_scalar2vector is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_concat; +architecture structural of ssr_8x64_vector_concat is + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_delay; +architecture structural of ssr_8x64_vector_delay is + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret; +architecture structural of ssr_8x64_vector_reinterpret is + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret1; +architecture structural of ssr_8x64_vector_reinterpret1 is + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret2; +architecture structural of ssr_8x64_vector_reinterpret2 is + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret3; +architecture structural of ssr_8x64_vector_reinterpret3 is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_im; +architecture structural of ssr_8x64_vector_slice_im is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_re; +architecture structural of ssr_8x64_vector_slice_re is + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x64_vector2scalar; +architecture structural of ssr_8x64_vector2scalar is + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c0fcf025b9 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 6-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 6-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_fft; +architecture structural of ssr_8x64_vector_fft is + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 6-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x64_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x64_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x64_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x64_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x64_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x64_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x64_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x64_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x64_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x64_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 6 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_im; +architecture structural of ssr_8x64_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x64/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_re; +architecture structural of ssr_8x64_i_re is + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x64_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_struct is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_struct; +architecture structural of ssr_8x64_struct is + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x64_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x64_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x64_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_default_clock_driver is + port ( + ssr_8x64_sysclk : in std_logic; + ssr_8x64_sysce : in std_logic; + ssr_8x64_sysclr : in std_logic; + ssr_8x64_clk1 : out std_logic; + ssr_8x64_ce1 : out std_logic + ); +end ssr_8x64_default_clock_driver; +architecture structural of ssr_8x64_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x64_sysclk, + sysce => ssr_8x64_sysce, + sysclr => ssr_8x64_sysclr, + clk => ssr_8x64_clk1, + ce => ssr_8x64_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64 is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64; +architecture structural of ssr_8x64 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x64,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x64_default_clock_driver : entity xil_defaultlib.ssr_8x64_default_clock_driver + port map ( + ssr_8x64_sysclk => clk, + ssr_8x64_sysce => '1', + ssr_8x64_sysclr => '0', + ssr_8x64_clk1 => clk_1_net, + ssr_8x64_ce1 => ce_1_net + ); + ssr_8x64_struct : entity xil_defaultlib.ssr_8x64_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd new file mode 100644 index 000000000..0edbfe3e1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x64_xldelay; + +architecture behavior of ssr_8x64_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=AB + P:out SFIXED; -- O=AB + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=CAB + P:out SFIXED); -- O=CAB +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=AB + P:out SFIXED); -- O=AB +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61; +architecture structural of WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(5 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(5 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x64_xlslice; + +architecture behavior of ssr_8x64_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_384683215a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_384683215a; +architecture behavior of sysgen_concat_384683215a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_53c8e6f5a2 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_53c8e6f5a2; +architecture behavior of sysgen_reinterpret_53c8e6f5a2 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d7a483898b is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d7a483898b; +architecture behavior of sysgen_reinterpret_d7a483898b +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c0fcf025b9 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c0fcf025b9; +architecture behavior of sysgen_concat_c0fcf025b9 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd new file mode 100644 index 000000000..770ff703a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd new file mode 100644 index 000000000..5d837de43 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd new file mode 100644 index 000000000..34bfa2e8c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd new file mode 100644 index 000000000..92017d49a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd new file mode 100644 index 000000000..606006cf5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x64_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x64. +component ssr_8x64 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 6-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 6-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (5 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (5 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (5 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x1024. +ssr_8x64_i : ssr_8x64 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd new file mode 100644 index 000000000..1303dec75 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd @@ -0,0 +1,301 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 64; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x64_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_re_7 & i_im_6 & i_re_6 & i_im_5 & i_re_5 & i_im_4 & i_re_4 & i_im_3 & i_re_3 & i_im_2 & i_re_2 & i_im_1 & i_re_1 & i_im_0 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_im_0 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_1 <= m_axis_tdata (3*B-1 downto 2*B); +o_im_1 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_2 <= m_axis_tdata (5*B-1 downto 4*B); +o_im_2 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_3 <= m_axis_tdata (7*B-1 downto 6*B); +o_im_3 <= m_axis_tdata (8*B-1 downto 7*B); +o_re_4 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_4 <= m_axis_tdata (10*B-1 downto 9*B); +o_re_5 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_5 <= m_axis_tdata (12*B-1 downto 11*B); +o_re_6 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_6 <= m_axis_tdata (14*B-1 downto 13*B); +o_re_7 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + --wait for 110 ns; + --rd_start <= '0'; + --wait for 220 ns; + --rd_start <= '1'; + --wait for 490 ns; + --rd_start <= '0'; + --wait for 100 ns; + --rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + for K in 0 to 200 loop + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(10000,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + --for J in 0 to 2 loop + -- while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + -- end loop; + -- wait until rising_edge(aclk); + -- s_axis_tlast <= '0'; + -- s_axis_tvalid <= '1'; + -- i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + -- I := I + 1; + --end loop; + + --while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + --end loop; + --wait until rising_edge(aclk); + --s_axis_tlast <= '1'; + --s_axis_tvalid <= '1'; + --i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + --I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd new file mode 100644 index 000000000..c07cb2e44 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile new file mode 100644 index 000000000..df6451cd1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl new file mode 100644 index 000000000..9523c5de6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe new file mode 100644 index 000000000..90cedee5f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -409,-1113,14782,1965,1397,-401,0,-481,-393,12156,4247,1154,-459,0,-509,245,9446,6773,767,-499,0,-499,767,6773,9446,245,-509,0,-459,1154,4247,12156,-393,-481,0,-401,1397,1965,14782,-1113,-409,0,-331,1501,4,17203,-1868,-288,12,-259,1480,-1584,19303,-2600,-116,10 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe new file mode 100644 index 000000000..c69516550 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -190,1356,-2768,20978,-3243,101,2,-129,1154,-3547,22144,-3726,353,-14,-79,903,-3937,22742,-3979,627,-41,-41,627,-3979,22742,-3937,903,-79,-14,353,-3726,22144,-3547,1154,-129,2,101,-3243,20978,-2768,1356,-190,10,-116,-2600,19303,-1584,1480,-259,12,-288,-1868,17203,4,1501,-331 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe new file mode 100644 index 000000000..8a55eee10 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -432,-928,14140,2508,1349,-417,0,-492,-225,11481,4859,1070,-471,0,-510,387,8770,7431,649,-504,0,-491,877,6123,10125,95,-506,0,-446,1228,3650,12825,-567,-468,0,-384,1435,1442,15411,-1301,-383,90,-313,1507,-430,17763,-2056,-249,12,-241,1458,-1918,19765,-2772,-66,9 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe new file mode 100644 index 000000000..a5989f588 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -174,1312,-3001,21320,-3381,161,-1,-116,1095,-3680,22349,-3813,421,-20,-68,835,-3979,22799,-3999,697,-49,-33,558,-3941,22648,-3874,969,-91,-9,288,-3624,21904,-3390,1211,-143,5,43,-3094,20604,-2511,1396,-206,11,-164,-2423,18814,-1224,1496,-277,12,-323,-1679,16624,461,1487,-349 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe new file mode 100644 index 000000000..5c3d7af8a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -451,-746,13487,3070,1293,-432,0,-500,-62,10804,5485,978,-482,0,-508,522,8098,8098,522,-508,0,-482,978,5485,10804,-62,-500,0,-432,1293,3070,13487,-746,-451,0,-367,1466,940,16026,-1490,-355,12,-295,1505,-839,18300,-2241,-208,12,-224,1430,-2227,20199,-2937,-13,7 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe new file mode 100644 index 000000000..f5b7af060 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -158,1263,-3208,21629,-3509,223,-5,-103,1033,-3789,22517,-3885,489,-26,-59,766,-3999,22818,-3999,766,-59,-26,489,-3885,22517,-3789,1033,-103,-5,223,-3509,21629,-3208,1263,-158,7,-13,-2937,20199,-2227,1430,-224,12,-208,-2241,18300,-839,1505,-295,12,-355,-1490,16026,940,1466,-367 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe new file mode 100644 index 000000000..5e0828d8f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -468,-567,12825,3650,1228,-446,0,-506,95,10125,6123,877,-491,0,-504,649,7431,8770,387,-510,0,-471,1070,4859,11481,-225,-492,0,-417,1349,2508,14140,-928,-432,0,-349,1487,461,16624,-1679,-323,12,-277,1496,-1224,18814,-2423,-164,11,-206,1396,-2511,20604,-3094,43,5 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe new file mode 100644 index 000000000..e67b9d3e7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -143,1211,-3390,21904,-3624,288,-9,-91,969,-3874,22648,-3941,558,-33,-49,697,-3999,22799,-3979,835,-68,-20,421,-3813,22349,-3680,1095,-116,-1,161,-3381,21320,-3001,1312,-174,9,-66,-2772,19765,-1918,1458,-241,12,-249,-2056,17763,-430,1507,-313,90,-383,-1301,15411,1442,1435,-384 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl new file mode 100644 index 000000000..df91aaf83 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo new file mode 100644 index 000000000..b9961ec8a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci new file mode 100644 index 000000000..d3704deda --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci new file mode 100644 index 000000000..09d60320e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 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Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci new file mode 100644 index 000000000..6c6b57bf4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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+ false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci new file mode 100644 index 000000000..578e4d745 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci new file mode 100644 index 000000000..a711e889a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 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ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci new file mode 100644 index 000000000..7a66fd719 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci new file mode 100644 index 000000000..c5d236249 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci new file mode 100644 index 000000000..f3d90963c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl new file mode 100755 index 000000000..deba046dc --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template new file mode 100644 index 000000000..264e198ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl new file mode 100644 index 000000000..e1a370512 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv new file mode 100644 index 000000000..195dd2ae5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv @@ -0,0 +1,301 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r = 1'b0; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv new file mode 100644 index 000000000..ec89d1bc9 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv @@ -0,0 +1,108 @@ +// This block will extract 1 channel from the TDM-input. +// It uses ID_REG which is as follows: +// ID_REG [7:0] : packet. +// ID_REG [15:8] : index. +// +// Input packets are as follows: +// |-------| |-------| +// | | | | +// tlast --------------| |-------------| | +// +// |-----|-------|-------|-----|-------|-------| +// t | 0 | L | 2*L | 0 | L | 2*L | +// a | 1 | L+1 | 2*L+1 | 1 | L+1 | 2*L+1 | +// d | 2 | L+2 | 2*L+2 | 2 | L+2 | 2*L+2 | +// a | . | . | . | . | . | . | +// t | . | . | . | . | . | . | +// a | . | . | . | . | . | . | +// | L-1 | 2*L-1 | 3*L-1 | L-1 | 2*L-1 | 3*L-1 | +// |-----|-------|-------|-----|-------|-------| +// +// The internal counter counts packets relying on tlast and resets. +// Offset within a packet is given by index. +module pfb_chsel + #( + // Bits. + parameter B = 32, + + // Number of lanes. + parameter L = 8 + ) + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire [L*B-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [B-1:0] m_axis_tdata , + + // Registers. + input wire [15:0] ID_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Packet counter. +reg [7:0] cnt = 0; +wire wr_en; + +// Registers. +reg [7:0] packet_reg ; +reg [7:0] index_reg ; + +// Data registers. +reg [L*B-1:0] tdata_r ; +reg [B-1:0] data_mux_r ; + +// Muxed data. +wire [B-1:0] data_mux ; + +// tlast_pipeline (for tvalid). +reg tlast_r1 ; +reg tlast_r2 ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Packet counter. +assign wr_en = (cnt == packet_reg)? 1'b1 : 1'b0; + +// Muxed data. +assign data_mux = tdata_r [index_reg*B +: B]; + +// Registers. +always @(posedge aclk) begin + // Packet counter. + if (s_axis_tlast == 1'b1) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + packet_reg <= ID_REG [7:0]; + index_reg <= ID_REG [15:8]; + + // Data registers. + if (wr_en == 1'b1) + tdata_r <= s_axis_tdata; + + if (tlast_r1 == 1'b1) + data_mux_r <= data_mux; + + // tlast_pipeline (for tvalid). + tlast_r1 <= s_axis_tlast; + tlast_r2 <= tlast_r1; +end + +// Assign outputs. +assign m_axis_tvalid = tlast_r2; +assign m_axis_tdata = data_mux_r; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd new file mode 100644 index 000000000..24bd0a2c3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd new file mode 100644 index 000000000..db99fb3cf --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd new file mode 100644 index 000000000..5ff7e746f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv new file mode 100644 index 000000000..4b57dab4a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv @@ -0,0 +1,113 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1 = 0; +reg [2*L*B-1:0] data_r2 = 0; +reg [2*L*B-1:0] data_r3 = 0; +reg [2*L*B-1:0] data_r4 = 0; + +// Tlast registers. +reg last_r1 = 0; +reg last_r2 = 0; +reg last_r3 = 0; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd new file mode 100644 index 000000000..2add8e524 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v b/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v new file mode 100644 index 000000000..56d4be8e0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v @@ -0,0 +1,168 @@ +/* + * Top-leve block which instantiates the following: + * + * 1) PFB, 50 % Overlap, 64 Channels, 8 selectable outputs. + * 2) DDS, 8 channels, independent freq/phase, phase coherent. + */ +module pfb_readout + #( + // Number of channels. + parameter N = 32, + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [L*32-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + output wire [31:0] m4_axis_tdata , + output wire [31:0] m5_axis_tdata , + output wire [31:0] m6_axis_tdata , + output wire [31:0] m7_axis_tdata , + + // Registers. + input wire [15:0] ID0_REG , + input wire [15:0] ID1_REG , + input wire [15:0] ID2_REG , + input wire [15:0] ID3_REG , + input wire [15:0] ID4_REG , + input wire [15:0] ID5_REG , + input wire [15:0] ID6_REG , + input wire [15:0] ID7_REG , + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG , + input wire [31:0] PINC4_REG , + input wire [31:0] POFF4_REG , + input wire [31:0] PINC5_REG , + input wire [31:0] POFF5_REG , + input wire [31:0] PINC6_REG , + input wire [31:0] POFF6_REG , + input wire [31:0] PINC7_REG , + input wire [31:0] POFF7_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +wire tvalid_i; +wire [31:0] tdata0_i; +wire [31:0] tdata1_i; +wire [31:0] tdata2_i; +wire [31:0] tdata3_i; +wire [31:0] tdata4_i; +wire [31:0] tdata5_i; +wire [31:0] tdata6_i; +wire [31:0] tdata7_i; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// PFB. +pfb_top + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(L) + ) + pfb_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (tvalid_i ), + .m0_axis_tdata (tdata0_i ), + .m1_axis_tdata (tdata1_i ), + .m2_axis_tdata (tdata2_i ), + .m3_axis_tdata (tdata3_i ), + .m4_axis_tdata (tdata4_i ), + .m5_axis_tdata (tdata5_i ), + .m6_axis_tdata (tdata6_i ), + .m7_axis_tdata (tdata7_i ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ) + ); + +// DDS. +ddsprod_v ddsprod_v_i + ( + // Clock. + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (tvalid_i ), + .s0_axis_tdata (tdata0_i ), + .s1_axis_tdata (tdata1_i ), + .s2_axis_tdata (tdata2_i ), + .s3_axis_tdata (tdata3_i ), + .s4_axis_tdata (tdata4_i ), + .s5_axis_tdata (tdata5_i ), + .s6_axis_tdata (tdata6_i ), + .s7_axis_tdata (tdata7_i ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + .m4_axis_tdata (m4_axis_tdata ), + .m5_axis_tdata (m5_axis_tdata ), + .m6_axis_tdata (m6_axis_tdata ), + .m7_axis_tdata (m7_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc new file mode 100644 index 000000000..d22e7ee64 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc @@ -0,0 +1,60 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wstrb[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wstrb[*]}] +set _xlnx_shared_i0 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_wready] +set_clock_groups -asynchronous -group [get_clocks s_axi_aclk] -group [get_clocks aclk] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc new file mode 100644 index 000000000..46515ba89 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports en] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports en] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc new file mode 100644 index 000000000..8e8a0a2c1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc new file mode 100644 index 000000000..5505ca00c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc @@ -0,0 +1,15 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {s_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {m_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {m_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] + +set_false_path -to [get_ports *m_axis*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv new file mode 100644 index 000000000..86da2a51b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv @@ -0,0 +1,426 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of channels. +parameter N = 64; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; + +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +reg s_axis_tvalid; +wire [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +wire [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +wire [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +wire [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +wire [31:0] m3_axis_tdata; +wire m4_axis_tvalid; +wire [31:0] m4_axis_tdata; +wire m5_axis_tvalid; +wire [31:0] m5_axis_tdata; +wire m6_axis_tvalid; +wire [31:0] m6_axis_tdata; +wire m7_axis_tvalid; +wire [31:0] m7_axis_tdata; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire [15:0] dout0_real; +wire [15:0] dout0_imag; +wire [15:0] dout1_real; +wire [15:0] dout1_imag; +wire [15:0] dout2_real; +wire [15:0] dout2_imag; +wire [15:0] dout3_real; +wire [15:0] dout3_imag; +wire [15:0] dout4_real; +wire [15:0] dout4_imag; +wire [15:0] dout5_real; +wire [15:0] dout5_imag; +wire [15:0] dout6_real; +wire [15:0] dout6_imag; +wire [15:0] dout7_real; +wire [15:0] dout7_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +assign dout0_real = m0_axis_tdata [15:0]; +assign dout0_imag = m0_axis_tdata [31:16]; +assign dout1_real = m1_axis_tdata [15:0]; +assign dout1_imag = m1_axis_tdata [31:16]; +assign dout2_real = m2_axis_tdata [15:0]; +assign dout2_imag = m2_axis_tdata [31:16]; +assign dout3_real = m3_axis_tdata [15:0]; +assign dout3_imag = m3_axis_tdata [31:16]; +assign dout4_real = m4_axis_tdata [15:0]; +assign dout4_imag = m4_axis_tdata [31:16]; +assign dout5_real = m5_axis_tdata [15:0]; +assign dout5_imag = m5_axis_tdata [31:16]; +assign dout6_real = m6_axis_tdata [15:0]; +assign dout6_imag = m6_axis_tdata [31:16]; +assign dout7_real = m7_axis_tdata [15:0]; +assign dout7_imag = m7_axis_tdata [31:16]; + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v4 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + // M_AXIS for CH4 output. + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + // M_AXIS for CH5 output. + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + // M_AXIS for CH6 output. + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + // M_AXIS for CH7 output. + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // ID0/1/2/3/4/5/6/7. + // ID [7:0]: packet + // ID [15:8]: id + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, (0 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, (1 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, (6 << 8) + 0, resp); + + // FREQ0/PHASE0. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, 0, resp); + + // FREQ1/PHASE1. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, freq(1,10), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, 0, resp); + + // FREQ2/PHASE2. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(12*4, prot, freq(1, 33), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(13*4, prot, 0, resp); + + // FREQ3/PHASE3. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(14*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(15*4, prot, 0, resp); + + // FREQ4/PHASE4. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(16*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(17*4, prot, 0, resp); + + // FREQ5/PHASE5. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(18*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(19*4, prot, 0, resp); + + // FREQ6/PHASE6. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(20*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(21*4, prot, 0, resp); + + // FREQ7/PHASE7. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(22*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(23*4, prot, 0, resp); + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3, fd4, fd5, fd6, fd7; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + shortint real_d4, imag_d4; + shortint real_d5, imag_d5; + shortint real_d6, imag_d6; + shortint real_d7, imag_d7; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + fd4 = $fopen("../../../../../tb/dout_4.csv","w"); + fd5 = $fopen("../../../../../tb/dout_5.csv","w"); + fd6 = $fopen("../../../../../tb/dout_6.csv","w"); + fd7 = $fopen("../../../../../tb/dout_7.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + $fdisplay(fd4, "valid, real, imag"); + $fdisplay(fd5, "valid, real, imag"); + $fdisplay(fd6, "valid, real, imag"); + $fdisplay(fd7, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + real_d4 = m4_axis_tdata[15:0]; + imag_d4 = m4_axis_tdata[31:16]; + real_d5 = m5_axis_tdata[15:0]; + imag_d5 = m5_axis_tdata[31:16]; + real_d6 = m6_axis_tdata[15:0]; + imag_d6 = m6_axis_tdata[31:16]; + real_d7 = m7_axis_tdata[15:0]; + imag_d7 = m7_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + $fdisplay(fd4,"%d,%d,%d",m4_axis_tvalid,real_d4,imag_d4); + $fdisplay(fd5,"%d,%d,%d",m5_axis_tvalid,real_d5,imag_d5); + $fdisplay(fd6,"%d,%d,%d",m6_axis_tvalid,real_d6,imag_d6); + $fdisplay(fd7,"%d,%d,%d",m7_axis_tvalid,real_d7,imag_d7); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); + $fclose(fd4); + $fclose(fd5); + $fclose(fd6); + $fclose(fd7); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl b/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl new file mode 100644 index 000000000..716ad7e7c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/README b/firmware/ip/axis_pfba_pr_4x256_v1/README new file mode 100644 index 000000000..6d9b83f21 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/README @@ -0,0 +1 @@ +This IP is a PFB for Analysis and Perfect Reconstruction (cascaded). diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/component.xml b/firmware/ip/axis_pfba_pr_4x256_v1/component.xml new file mode 100644 index 000000000..9cc40b5f4 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/component.xml @@ -0,0 +1,1346 @@ + + + QICK + QICK + axis_pfba_pr_4x256_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_pfba_pr_4x256_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 0960c124 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_pfba_pr_4x256_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 0960c124 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 256 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfba_pr_4x256_v1.sv + systemVerilogSource + CHECKSUM_b87cf49d + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfba_pr_4x256_v1.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfba_pr_4x256_v1_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS PFB 4 lanes, 256 Channels, 50 % Overlap, Perfect Reconstruction, V1. + + + Component_Name + axis_pfba_pr_4x256_v1_v1_0 + + + N + N + 256 + + + + + + zynquplus + + + /QICK + + AXIS PFBA PR 4x256 V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 7 + 2023-04-26T18:18:48Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..0fecc6e85 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + 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Wed Feb 02 19:13:41 UTC 2022 + + + outputProductCRC + 9:b40c5c85 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + axi_vip_v1_1_8_top + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Wed Feb 02 19:13:41 UTC 2022 + + + outputProductCRC + 9:b40c5c85 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed Feb 02 19:14:59 UTC 2022 + + + outputProductCRC + 9:b40c5c85 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + axi_vip_v1_1_8_top + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Tue Apr 05 16:46:58 UTC 2022 + + + outputProductCRC + 9:a9f86b20 + + + + + xilinx_systemcsimulation + SystemC Simulation + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd new file mode 100644 index 000000000..6d4348a6a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd @@ -0,0 +1,510 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + QOUT_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + QOUT_REG <= slv_reg0; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv new file mode 100644 index 000000000..5db508ff6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv @@ -0,0 +1,169 @@ +// Polyphase Filter Bank, 4 lanes, 256 channels, 50 % overlap. +// This block has FIR coefficients that are good for cascading +// with the Synthesis PFB only. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +module axis_pfba_pr_4x256_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aresetn , + aclk , + + // S_AXIS for data input. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for data output. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +parameter N = 256; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [4*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [8*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] QOUT_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +// PFB Block. +pfb + #( + .N (256), + .L (4 ) + ) + pfb_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tdata (m_axis_tdata ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README new file mode 100644 index 000000000..a8858c0dc --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README @@ -0,0 +1,9 @@ +This block integrates Xilinx's SSR FFT, generated with Syetem Generator. + +The top level also includes the framing block, which aligns the data with +the input TLAST to ensure data is properly aligned. + +NOTE: This implementation does not use pkt_align block, which allows to +buffer packets in the case tvalid drops in the middle of a frame. This +simplified implementation will just discard samples and re-sync again. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd new file mode 100644 index 000000000..42f60869b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end framing; + +architecture rtl of framing is + +constant NWAIT : Integer := 256; +constant NWAIT_LOG2 : Integer := Integer(ceil(log2(real(NWAIT)))); +constant CYCLES : Integer := NFFT/SSR; +constant CYCLES_LOG2 : Integer := Integer(ceil(log2(real(CYCLES)))); + +-- FSM. +type fsm_type is ( INIT_ST , + RST_ST , + S0_ST , + S1_ST , + S2_ST ); +signal current_state, next_state : fsm_type; + +signal rst_state : std_logic; + +signal data_r : std_logic_vector (s_axis_tdata'length-1 downto 0); +signal data_rr : std_logic_vector (s_axis_tdata'length-1 downto 0); + +signal valid_i : std_logic; +signal valid_r : std_logic; +signal valid_rr : std_logic; + +signal cnt_nwait : unsigned (NWAIT_LOG2-1 downto 0); +signal cnt : unsigned (CYCLES_LOG2-1 downto 0); + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Pipeline registers. + data_r <= (others => '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd new file mode 100644 index 000000000..b8f1a8f5f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd new file mode 100644 index 000000000..26af1d6a7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd new file mode 100644 index 000000000..8ec9c8d10 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd new file mode 100644 index 000000000..c943462db --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd new file mode 100644 index 000000000..fabdcdb31 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x256/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x256_scalar2vector; +architecture structural of ssr_8x256_scalar2vector is + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_concat; +architecture structural of ssr_8x256_vector_concat is + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_delay; +architecture structural of ssr_8x256_vector_delay is + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret; +architecture structural of ssr_8x256_vector_reinterpret is + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret1; +architecture structural of ssr_8x256_vector_reinterpret1 is + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret2; +architecture structural of ssr_8x256_vector_reinterpret2 is + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret3; +architecture structural of ssr_8x256_vector_reinterpret3 is + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_im; +architecture structural of ssr_8x256_vector_slice_im is + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_re; +architecture structural of ssr_8x256_vector_slice_re is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x256_vector2scalar; +architecture structural of ssr_8x256_vector2scalar is + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c6ccfb3c89 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 8-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 8-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_fft; +architecture structural of ssr_8x256_vector_fft is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal clk_net : std_logic; + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 8-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x256_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x256_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x256_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x256_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x256_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x256_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x256_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x256_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x256_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x256_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 8 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_im; +architecture structural of ssr_8x256_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x256/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_re; +architecture structural of ssr_8x256_i_re is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x256_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_struct is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_struct; +architecture structural of ssr_8x256_struct is + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal ce_net : std_logic; + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x256_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x256_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x256_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_default_clock_driver is + port ( + ssr_8x256_sysclk : in std_logic; + ssr_8x256_sysce : in std_logic; + ssr_8x256_sysclr : in std_logic; + ssr_8x256_clk1 : out std_logic; + ssr_8x256_ce1 : out std_logic + ); +end ssr_8x256_default_clock_driver; +architecture structural of ssr_8x256_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x256_sysclk, + sysce => ssr_8x256_sysce, + sysclr => ssr_8x256_sysclr, + clk => ssr_8x256_clk1, + ce => ssr_8x256_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256 is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256; +architecture structural of ssr_8x256 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x256,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal clk_1_net : std_logic; + signal ce_1_net : std_logic; +begin + ssr_8x256_default_clock_driver : entity xil_defaultlib.ssr_8x256_default_clock_driver + port map ( + ssr_8x256_sysclk => clk, + ssr_8x256_sysce => '1', + ssr_8x256_sysclr => '0', + ssr_8x256_clk1 => clk_1_net, + ssr_8x256_ce1 => ce_1_net + ); + ssr_8x256_struct : entity xil_defaultlib.ssr_8x256_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd new file mode 100644 index 000000000..f338faa5d --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x256_xldelay; + +architecture behavior of ssr_8x256_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=AB + P:out SFIXED; -- O=AB + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=CAB + P:out SFIXED); -- O=CAB +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=AB + P:out SFIXED); -- O=AB +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e; +architecture structural of WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(7 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(7 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x256_xlslice; + +architecture behavior of ssr_8x256_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_6128f842cc is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_6128f842cc; +architecture behavior of sysgen_concat_6128f842cc +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_3bad6996c0 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_3bad6996c0; +architecture behavior of sysgen_reinterpret_3bad6996c0 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_9cd5a6908e is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_9cd5a6908e; +architecture behavior of sysgen_reinterpret_9cd5a6908e +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c6ccfb3c89 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c6ccfb3c89; +architecture behavior of sysgen_concat_c6ccfb3c89 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd new file mode 100644 index 000000000..770ff703a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd new file mode 100644 index 000000000..5d837de43 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd new file mode 100644 index 000000000..34bfa2e8c --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd new file mode 100644 index 000000000..92017d49a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd new file mode 100644 index 000000000..30f2d1e4a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x256_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x256_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x256. +component ssr_8x256 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 8-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 8-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (7 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (7 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (7 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x256. +ssr_8x256_i : ssr_8x256 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd new file mode 100644 index 000000000..ef0ef0372 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd @@ -0,0 +1,251 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x32_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 32; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x32_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 2 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd new file mode 100644 index 000000000..c07cb2e44 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile new file mode 100644 index 000000000..df6451cd1 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl new file mode 100644 index 000000000..9523c5de6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe new file mode 100644 index 000000000..e8a9cad9b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -2,12,-50,16384,51,-12,2,0,-8,57,-245,16372,260,-61,9,0,-14,100,-430,16346,478,-112,17,0,-20,141,-606,16305,705,-165,26,-1,-25,179,-772,16249,941,-220,35,-1,-30,215,-929,16178,1186,-278,44,-1,-34,248,-1076,16092,1439,-337,54,-2,-38,279,-1214,15992,1701,-399,65,-2,-41,308,-1343,15878,1971,-462,76,-3,-44,334,-1462,15750,2248,-526,87,-3,-46,358,-1571,15607,2534,-592,99,-4,-48,379,-1672,15452,2826,-660,112,-5,-50,399,-1763,15283,3126,-728,125,-6,-51,416,-1846,15101,3432,-798,138,-6,-52,431,-1920,14906,3745,-868,152,-7,-53,443,-1985,14699,4063,-939,166,-8,-53,454,-2042,14480,4387,-1011,180,-10,-53,463,-2090,14250,4715,-1082,195,-11,-53,469,-2131,14009,5049,-1154,210,-12,-53,474,-2164,13757,5386,-1226,225,-13,-52,477,-2189,13495,5727,-1297,240,-15,-51,479,-2207,13224,6072,-1368,255,-16,-50,479,-2218,12943,6419,-1438,270,-18,-49,477,-2222,12654,6768,-1506,286,-19,-48,474,-2220,12356,7119,-1573,301,-21,-47,469,-2212,12051,7471,-1639,316,-23,-45,463,-2198,11739,7824,-1702,331,-24,-43,456,-2178,11420,8177,-1763,346,-26,-42,448,-2152,11096,8529,-1822,360,-28,-40,439,-2122,10766,8880,-1878,374,-30,-38,429,-2087,10431,9229,-1931,387,-32,-36,418,-2047,10092,9576,-1980,400,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe new file mode 100644 index 000000000..7aecf7590 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -34,406,-2004,9749,9921,-2026,412,-35,-33,393,-1956,9403,10262,-2068,423,-37,-31,380,-1905,9055,10599,-2105,434,-39,-29,367,-1850,8704,10931,-2138,444,-41,-27,353,-1793,8353,11259,-2166,452,-43,-25,338,-1733,8000,11580,-2188,460,-44,-23,324,-1671,7647,11896,-2205,466,-46,-22,309,-1606,7295,12205,-2217,472,-47,-20,293,-1540,6944,12506,-2222,475,-49,-18,278,-1472,6593,12799,-2221,478,-50,-17,263,-1403,6245,13085,-2213,479,-51,-15,247,-1333,5899,13361,-2199,478,-52,-14,232,-1262,5556,13628,-2177,476,-53,-13,217,-1190,5217,13884,-2148,472,-53,-11,202,-1118,4881,14131,-2111,466,-53,-10,187,-1047,4550,14367,-2067,458,-53,-9,173,-975,4224,14591,-2014,449,-53,-8,159,-904,3903,14804,-1953,437,-53,-7,145,-833,3588,15005,-1884,423,-52,-6,131,-763,3278,15193,-1806,407,-51,-5,118,-694,2975,15369,-1719,389,-49,-4,105,-626,2679,15531,-1623,369,-47,-4,93,-559,2390,15680,-1518,346,-45,-3,81,-494,2109,15815,-1403,321,-42,-3,70,-430,1835,15937,-1280,294,-39,-2,59,-368,1569,16044,-1147,264,-36,-2,49,-307,1311,16137,-1004,232,-32,-1,39,-249,1062,16215,-852,197,-28,-1,30,-193,822,16279,-690,160,-23,-1,21,-138,590,16327,-519,121,-17,0,13,-86,367,16361,-339,79,-11,0,5,-36,154,16380,-149,35,-5 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe new file mode 100644 index 000000000..96cdeb004 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -3,23,-100,16382,102,-24,4,0,-10,68,-292,16367,313,-73,11,0,-16,110,-475,16337,534,-125,19,0,-21,151,-649,16292,763,-179,28,-1,-26,188,-813,16232,1001,-235,37,-1,-31,223,-967,16158,1248,-293,47,-1,-35,256,-1112,16069,1504,-352,57,-2,-39,287,-1247,15965,1768,-414,67,-2,-42,315,-1373,15847,2039,-478,79,-3,-44,340,-1490,15715,2319,-542,90,-4,-47,363,-1597,15570,2606,-609,102,-4,-49,384,-1695,15411,2901,-677,115,-5,-50,403,-1785,15238,3202,-745,128,-6,-52,420,-1865,15053,3510,-815,141,-7,-52,434,-1937,14855,3824,-886,155,-8,-53,446,-2000,14646,4143,-957,169,-9,-53,456,-2054,14424,4468,-1029,184,-10,-53,464,-2101,14191,4798,-1100,198,-11,-53,471,-2140,13947,5133,-1172,213,-12,-53,475,-2171,13693,5471,-1244,228,-14,-52,478,-2194,13428,5813,-1315,244,-15,-51,479,-2211,13154,6158,-1385,259,-17,-50,478,-2220,12872,6506,-1455,274,-18,-49,476,-2223,12580,6856,-1523,290,-20,-48,473,-2219,12281,7207,-1590,305,-21,-46,468,-2209,11974,7559,-1655,320,-23,-45,462,-2193,11660,7912,-1718,335,-25,-43,454,-2172,11340,8265,-1778,349,-27,-41,446,-2145,11014,8617,-1836,363,-28,-40,436,-2114,10682,8967,-1892,377,-30,-38,426,-2077,10346,9316,-1943,390,-32,-36,415,-2037,10006,9663,-1992,403,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe new file mode 100644 index 000000000..6a67668c1 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -34,403,-1992,9663,10006,-2037,415,-36,-32,390,-1943,9316,10346,-2077,426,-38,-30,377,-1892,8967,10682,-2114,436,-40,-28,363,-1836,8617,11014,-2145,446,-41,-27,349,-1778,8265,11340,-2172,454,-43,-25,335,-1718,7912,11660,-2193,462,-45,-23,320,-1655,7559,11974,-2209,468,-46,-21,305,-1590,7207,12281,-2219,473,-48,-20,290,-1523,6856,12580,-2223,476,-49,-18,274,-1455,6506,12872,-2220,478,-50,-17,259,-1385,6158,13154,-2211,479,-51,-15,244,-1315,5813,13428,-2194,478,-52,-14,228,-1244,5471,13693,-2171,475,-53,-12,213,-1172,5133,13947,-2140,471,-53,-11,198,-1100,4798,14191,-2101,464,-53,-10,184,-1029,4468,14424,-2054,456,-53,-9,169,-957,4143,14646,-2000,446,-53,-8,155,-886,3824,14855,-1937,434,-52,-7,141,-815,3510,15053,-1865,420,-52,-6,128,-745,3202,15238,-1785,403,-50,-5,115,-677,2901,15411,-1695,384,-49,-4,102,-609,2606,15570,-1597,363,-47,-4,90,-542,2319,15715,-1490,340,-44,-3,79,-478,2039,15847,-1373,315,-42,-2,67,-414,1768,15965,-1247,287,-39,-2,57,-352,1504,16069,-1112,256,-35,-1,47,-293,1248,16158,-967,223,-31,-1,37,-235,1001,16232,-813,188,-26,-1,28,-179,763,16292,-649,151,-21,0,19,-125,534,16337,-475,110,-16,0,11,-73,313,16367,-292,68,-10,0,4,-24,102,16382,-100,23,-3 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe new file mode 100644 index 000000000..369ba04de --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -5,35,-149,16380,154,-36,5,0,-11,79,-339,16361,367,-86,13,0,-17,121,-519,16327,590,-138,21,-1,-23,160,-690,16279,822,-193,30,-1,-28,197,-852,16215,1062,-249,39,-1,-32,232,-1004,16137,1311,-307,49,-2,-36,264,-1147,16044,1569,-368,59,-2,-39,294,-1280,15937,1835,-430,70,-3,-42,321,-1403,15815,2109,-494,81,-3,-45,346,-1518,15680,2390,-559,93,-4,-47,369,-1623,15531,2679,-626,105,-4,-49,389,-1719,15369,2975,-694,118,-5,-51,407,-1806,15193,3278,-763,131,-6,-52,423,-1884,15005,3588,-833,145,-7,-53,437,-1953,14804,3903,-904,159,-8,-53,449,-2014,14591,4224,-975,173,-9,-53,458,-2067,14367,4550,-1047,187,-10,-53,466,-2111,14131,4881,-1118,202,-11,-53,472,-2148,13884,5217,-1190,217,-13,-53,476,-2177,13628,5556,-1262,232,-14,-52,478,-2199,13361,5899,-1333,247,-15,-51,479,-2213,13085,6245,-1403,263,-17,-50,478,-2221,12799,6593,-1472,278,-18,-49,475,-2222,12506,6944,-1540,293,-20,-47,472,-2217,12205,7295,-1606,309,-22,-46,466,-2205,11896,7647,-1671,324,-23,-44,460,-2188,11580,8000,-1733,338,-25,-43,452,-2166,11259,8353,-1793,353,-27,-41,444,-2138,10931,8704,-1850,367,-29,-39,434,-2105,10599,9055,-1905,380,-31,-37,423,-2068,10262,9403,-1956,393,-33,-35,412,-2026,9921,9749,-2004,406,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe new file mode 100644 index 000000000..2fc62d09b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -34,400,-1980,9576,10092,-2047,418,-36,-32,387,-1931,9229,10431,-2087,429,-38,-30,374,-1878,8880,10766,-2122,439,-40,-28,360,-1822,8529,11096,-2152,448,-42,-26,346,-1763,8177,11420,-2178,456,-43,-24,331,-1702,7824,11739,-2198,463,-45,-23,316,-1639,7471,12051,-2212,469,-47,-21,301,-1573,7119,12356,-2220,474,-48,-19,286,-1506,6768,12654,-2222,477,-49,-18,270,-1438,6419,12943,-2218,479,-50,-16,255,-1368,6072,13224,-2207,479,-51,-15,240,-1297,5727,13495,-2189,477,-52,-13,225,-1226,5386,13757,-2164,474,-53,-12,210,-1154,5049,14009,-2131,469,-53,-11,195,-1082,4715,14250,-2090,463,-53,-10,180,-1011,4387,14480,-2042,454,-53,-8,166,-939,4063,14699,-1985,443,-53,-7,152,-868,3745,14906,-1920,431,-52,-6,138,-798,3432,15101,-1846,416,-51,-6,125,-728,3126,15283,-1763,399,-50,-5,112,-660,2826,15452,-1672,379,-48,-4,99,-592,2534,15607,-1571,358,-46,-3,87,-526,2248,15750,-1462,334,-44,-3,76,-462,1971,15878,-1343,308,-41,-2,65,-399,1701,15992,-1214,279,-38,-2,54,-337,1439,16092,-1076,248,-34,-1,44,-278,1186,16178,-929,215,-30,-1,35,-220,941,16249,-772,179,-25,-1,26,-165,705,16305,-606,141,-20,0,17,-112,478,16346,-430,100,-14,0,9,-61,260,16372,-245,57,-8,0,2,-12,51,16384,-50,12,-2 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe new file mode 100644 index 000000000..ac9e2a2d7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -7,46,-197,16376,206,-48,7,0,-13,90,-385,16354,422,-99,15,0,-19,131,-563,16316,647,-152,23,-1,-24,170,-732,16264,881,-206,32,-1,-29,206,-891,16197,1124,-263,42,-1,-33,240,-1041,16115,1375,-322,52,-2,-37,272,-1181,16019,1635,-383,62,-2,-40,301,-1311,15908,1902,-446,73,-3,-43,328,-1433,15783,2178,-510,84,-3,-46,352,-1545,15644,2462,-575,96,-4,-48,374,-1647,15492,2753,-643,109,-5,-50,394,-1741,15326,3050,-711,121,-5,-51,412,-1826,15147,3355,-780,135,-6,-52,427,-1902,14956,3666,-850,148,-7,-53,440,-1969,14752,3983,-921,162,-8,-53,451,-2028,14536,4305,-993,176,-9,-53,461,-2079,14309,4633,-1065,191,-10,-53,468,-2121,14070,4965,-1136,206,-12,-53,473,-2156,13821,5302,-1208,221,-13,-52,477,-2183,13562,5642,-1279,236,-14,-52,479,-2203,13293,5985,-1350,251,-16,-51,479,-2216,13014,6332,-1420,267,-17,-50,477,-2222,12727,6681,-1489,282,-19,-48,475,-2221,12431,7031,-1557,297,-21,-47,470,-2215,12128,7383,-1622,312,-22,-45,465,-2202,11818,7736,-1686,327,-24,-44,458,-2183,11501,8088,-1748,342,-26,-42,450,-2159,11177,8441,-1808,356,-28,-40,441,-2130,10849,8792,-1864,370,-29,-39,431,-2096,10515,9142,-1918,384,-31,-37,420,-2058,10177,9490,-1968,397,-33,-35,409,-2015,9835,9835,-2015,409,-35 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe new file mode 100644 index 000000000..e73253085 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -33,397,-1968,9490,10177,-2058,420,-37,-31,384,-1918,9142,10515,-2096,431,-39,-29,370,-1864,8792,10849,-2130,441,-40,-28,356,-1808,8441,11177,-2159,450,-42,-26,342,-1748,8088,11501,-2183,458,-44,-24,327,-1686,7736,11818,-2202,465,-45,-22,312,-1622,7383,12128,-2215,470,-47,-21,297,-1557,7031,12431,-2221,475,-48,-19,282,-1489,6681,12727,-2222,477,-50,-17,267,-1420,6332,13014,-2216,479,-51,-16,251,-1350,5985,13293,-2203,479,-52,-14,236,-1279,5642,13562,-2183,477,-52,-13,221,-1208,5302,13821,-2156,473,-53,-12,206,-1136,4965,14070,-2121,468,-53,-10,191,-1065,4633,14309,-2079,461,-53,-9,176,-993,4305,14536,-2028,451,-53,-8,162,-921,3983,14752,-1969,440,-53,-7,148,-850,3666,14956,-1902,427,-52,-6,135,-780,3355,15147,-1826,412,-51,-5,121,-711,3050,15326,-1741,394,-50,-5,109,-643,2753,15492,-1647,374,-48,-4,96,-575,2462,15644,-1545,352,-46,-3,84,-510,2178,15783,-1433,328,-43,-3,73,-446,1902,15908,-1311,301,-40,-2,62,-383,1635,16019,-1181,272,-37,-2,52,-322,1375,16115,-1041,240,-33,-1,42,-263,1124,16197,-891,206,-29,-1,32,-206,881,16264,-732,170,-24,-1,23,-152,647,16316,-563,131,-19,0,15,-99,422,16354,-385,90,-13,0,7,-48,206,16376,-197,46,-7,0,0,0,0,16384,0,0,0 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl new file mode 100644 index 000000000..7d82aaf54 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo new file mode 100644 index 000000000..b2d1d6ff4 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci new file mode 100644 index 000000000..db459c217 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci new file mode 100644 index 000000000..c9d7b7df6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci new file mode 100644 index 000000000..eccedac45 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci new file mode 100644 index 000000000..c14a39bba --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci new file mode 100644 index 000000000..b084bdf70 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci new file mode 100644 index 000000000..d8f3747f3 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci new file mode 100644 index 000000000..b2c12a751 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci new file mode 100644 index 000000000..37996fc1e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl new file mode 100755 index 000000000..deba046dc --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template new file mode 100644 index 000000000..c35fdf97a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl new file mode 100644 index 000000000..e1a370512 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv new file mode 100644 index 000000000..c7f296cf6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv @@ -0,0 +1,312 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd new file mode 100644 index 000000000..24bd0a2c3 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd new file mode 100644 index 000000000..db99fb3cf --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd new file mode 100644 index 000000000..5ff7e746f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv new file mode 100644 index 000000000..2541b1132 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv @@ -0,0 +1,132 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1; +reg [2*L*B-1:0] data_r2; +reg [2*L*B-1:0] data_r3; +reg [2*L*B-1:0] data_r4; + +// Tlast registers. +reg last_r1; +reg last_r2; +reg last_r3; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv new file mode 100644 index 000000000..d762ef5e9 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv @@ -0,0 +1,254 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +parameter L = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire s_axis_tready; +reg s_axis_tvalid; +reg [4*32-1:0] s_axis_tdata; + +wire m_axis_tvalid; +wire m_axis_tlast; +reg [8*32-1:0] m_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire[31:0] dout_ii [0:2*L-1]; +wire[15:0] dout_real_ii [0:2*L-1]; +wire[15:0] dout_imag_ii [0:2*L-1]; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + +generate +genvar ii; +for (ii = 0; ii < L; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; + assign dout_ii[ii+L] = m_axis_tdata[32*(ii+L) +: 32]; + assign dout_real_ii[ii] = m_axis_tdata[32*ii +: 16]; + assign dout_real_ii[ii+L] = m_axis_tdata[32*(ii+L) +: 16]; + assign dout_imag_ii[ii] = m_axis_tdata[32*ii+16 +: 16]; + assign dout_imag_ii[ii+L] = m_axis_tdata[32*(ii+L)+16 +: 16]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfba_pr_4x256_v1 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk , + .s_axi_aresetn , + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arready , + .s_axi_arvalid , + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awready , + .s_axi_awvalid , + .s_axi_bready , + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_rdata , + .s_axi_rready , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_wdata , + .s_axi_wready , + .s_axi_wstrb , + .s_axi_wvalid , + + // s_* and m_* reset/clock. + .aresetn , + .aclk , + + // S_AXIS for data input. + .s_axis_tvalid , + .s_axis_tready , + .s_axis_tdata , + + // M_AXIS for data output. + .m_axis_tvalid , + .m_axis_tlast , + .m_axis_tdata + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + // QOUT_REG + data_wr = 8; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // Wait until FIR framing is done. + #48000; + + // Start data. + tb_data <= 1; + #3500; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 1; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == L) begin + i = 0; + @(posedge aclk); + //s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + //s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, last, real, imag"); + + wait (tb_write_out); + wait (m_axis_tlast); + wait (!m_axis_tlast); + + while (tb_write_out) begin + @(posedge aclk); + for (int i=0; i<2*L; i = i+1) begin + real_d = m_axis_tdata[32*i +: 16]; + imag_d = m_axis_tdata[32*i+16 +: 16]; + $fdisplay(fd,"%d,%d,%d,%d",m_axis_tvalid,m_axis_tlast,real_d,imag_d); + end + end + + $display("Closing file, t = %0t", $time); + $fclose(fd); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd new file mode 100644 index 000000000..784638551 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Shift registers. + shift_reg_tdata <= (others => (others => '0')); + else + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl new file mode 100644 index 000000000..716ad7e7c --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/README b/firmware/ip/axis_pfbs_pr_4x256_v1/README new file mode 100644 index 000000000..eb014451b --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/README @@ -0,0 +1 @@ +This IP is a PFB for Synthesis and Perfect Reconstruction (cascaded). diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml b/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml new file mode 100644 index 000000000..61f0ecb72 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml @@ -0,0 +1,1357 @@ + + + QICK + QICK + axis_pfbs_pr_4x256_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_pfbs_pr_4x256_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e141cd30 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_pfbs_pr_4x256_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e141cd30 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 256 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_conjugate.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfbs_pr_4x256_v1.sv + systemVerilogSource + CHECKSUM_50266a58 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_conjugate.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfbs_pr_4x256_v1.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS PFB 4 lanes, 256 Channels, 50 % Overlap, Perfect Reconstruction, V1. + + + Component_Name + axis_pfbs_pr_4x256_v1_v1_0 + + + N + N + 256 + + + + + + zynquplus + + + /QICK + + AXIS PFBS PR 4x256 V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 4 + 2023-04-26T18:26:06Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..8a5353a86 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + + m_axi_wdata + + + + + WID + + + m_axi_wid + + + + + WLAST + + + m_axi_wlast + + + + + WREADY + + + m_axi_wready + + + + + WSTRB + + + m_axi_wstrb + + + + + WUSER + + + m_axi_wuser + + + + + WVALID + + + m_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + simulation.tlm + + + + + PROTOCOL + AXI4LITE + + + simulation.tlm + + + + + FREQ_HZ + 100000000 + + + simulation.tlm + + + + + ID_WIDTH + 0 + + + simulation.tlm + + + + + ADDR_WIDTH + 32 + + + simulation.tlm + + + + + AWUSER_WIDTH + 0 + + + simulation.tlm + + + + + ARUSER_WIDTH + 0 + + + simulation.tlm + + + + + WUSER_WIDTH + 0 + + + simulation.tlm + + + + + RUSER_WIDTH + 0 + + + simulation.tlm + + + + + BUSER_WIDTH + 0 + + + simulation.tlm + + + + + READ_WRITE_MODE + READ_WRITE + + + simulation.tlm + + + + + HAS_BURST + 0 + + + simulation.tlm + + + + + HAS_LOCK + 0 + + + simulation.tlm + + + + + HAS_PROT + 1 + + + simulation.tlm + + + + + HAS_CACHE + 0 + + + simulation.tlm + + + + + HAS_QOS + 0 + + + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd new file mode 100644 index 000000000..6d4348a6a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd @@ -0,0 +1,510 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + QOUT_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + QOUT_REG <= slv_reg0; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv new file mode 100644 index 000000000..1e76952f6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv @@ -0,0 +1,127 @@ +// Synthesis Polyphase Filter Bank, 4 lanes, 256 channels, 50 % overlap. +// This IP is good for cascading with the Analysis PFB only. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +module axis_pfbs_pr_4x256_v1 + ( + // AXI Slave I/F for configuration. + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [5:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // s_* and m_* reset/clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for data input. + input wire [8*32-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + output wire s_axis_tready , + + // M_AXIS for data output. + output wire [4*32-1:0] m_axis_tdata , + output wire m_axis_tvalid + ); + +parameter N = 256; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] QOUT_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +// PFB Block. +pfb + #( + .N (256), + .L (4 ) + ) + pfb_i + ( + // Reset and clock. + .aresetn , + .aclk , + + // S_AXIS for input data. + .s_axis_tdata , + .s_axis_tlast , + .s_axis_tvalid , + .s_axis_tready , + + // M_AXIS for output data. + .m_axis_tdata , + .m_axis_tvalid , + + // Registers. + .QOUT_REG + ); + +endmodule + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README new file mode 100644 index 000000000..a8858c0dc --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README @@ -0,0 +1,9 @@ +This block integrates Xilinx's SSR FFT, generated with Syetem Generator. + +The top level also includes the framing block, which aligns the data with +the input TLAST to ensure data is properly aligned. + +NOTE: This implementation does not use pkt_align block, which allows to +buffer packets in the case tvalid drops in the middle of a frame. This +simplified implementation will just discard samples and re-sync again. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd new file mode 100644 index 000000000..42f60869b --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end framing; + +architecture rtl of framing is + +constant NWAIT : Integer := 256; +constant NWAIT_LOG2 : Integer := Integer(ceil(log2(real(NWAIT)))); +constant CYCLES : Integer := NFFT/SSR; +constant CYCLES_LOG2 : Integer := Integer(ceil(log2(real(CYCLES)))); + +-- FSM. +type fsm_type is ( INIT_ST , + RST_ST , + S0_ST , + S1_ST , + S2_ST ); +signal current_state, next_state : fsm_type; + +signal rst_state : std_logic; + +signal data_r : std_logic_vector (s_axis_tdata'length-1 downto 0); +signal data_rr : std_logic_vector (s_axis_tdata'length-1 downto 0); + +signal valid_i : std_logic; +signal valid_r : std_logic; +signal valid_rr : std_logic; + +signal cnt_nwait : unsigned (NWAIT_LOG2-1 downto 0); +signal cnt : unsigned (CYCLES_LOG2-1 downto 0); + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Pipeline registers. + data_r <= (others => '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd new file mode 100644 index 000000000..b8f1a8f5f --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd new file mode 100644 index 000000000..26af1d6a7 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd new file mode 100644 index 000000000..8ec9c8d10 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd new file mode 100644 index 000000000..c943462db --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd new file mode 100644 index 000000000..fabdcdb31 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x256/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x256_scalar2vector; +architecture structural of ssr_8x256_scalar2vector is + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_concat; +architecture structural of ssr_8x256_vector_concat is + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_delay; +architecture structural of ssr_8x256_vector_delay is + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret; +architecture structural of ssr_8x256_vector_reinterpret is + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret1; +architecture structural of ssr_8x256_vector_reinterpret1 is + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret2; +architecture structural of ssr_8x256_vector_reinterpret2 is + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret3; +architecture structural of ssr_8x256_vector_reinterpret3 is + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_im; +architecture structural of ssr_8x256_vector_slice_im is + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_re; +architecture structural of ssr_8x256_vector_slice_re is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x256_vector2scalar; +architecture structural of ssr_8x256_vector2scalar is + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c6ccfb3c89 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 8-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 8-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_fft; +architecture structural of ssr_8x256_vector_fft is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal clk_net : std_logic; + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 8-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x256_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x256_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x256_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x256_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x256_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x256_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x256_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x256_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x256_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x256_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 8 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_im; +architecture structural of ssr_8x256_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x256/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_re; +architecture structural of ssr_8x256_i_re is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x256_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_struct is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_struct; +architecture structural of ssr_8x256_struct is + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal ce_net : std_logic; + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x256_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x256_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x256_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_default_clock_driver is + port ( + ssr_8x256_sysclk : in std_logic; + ssr_8x256_sysce : in std_logic; + ssr_8x256_sysclr : in std_logic; + ssr_8x256_clk1 : out std_logic; + ssr_8x256_ce1 : out std_logic + ); +end ssr_8x256_default_clock_driver; +architecture structural of ssr_8x256_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x256_sysclk, + sysce => ssr_8x256_sysce, + sysclr => ssr_8x256_sysclr, + clk => ssr_8x256_clk1, + ce => ssr_8x256_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256 is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256; +architecture structural of ssr_8x256 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x256,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal clk_1_net : std_logic; + signal ce_1_net : std_logic; +begin + ssr_8x256_default_clock_driver : entity xil_defaultlib.ssr_8x256_default_clock_driver + port map ( + ssr_8x256_sysclk => clk, + ssr_8x256_sysce => '1', + ssr_8x256_sysclr => '0', + ssr_8x256_clk1 => clk_1_net, + ssr_8x256_ce1 => ce_1_net + ); + ssr_8x256_struct : entity xil_defaultlib.ssr_8x256_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd new file mode 100644 index 000000000..f338faa5d --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x256_xldelay; + +architecture behavior of ssr_8x256_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=AB + P:out SFIXED; -- O=AB + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=CAB + P:out SFIXED); -- O=CAB +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=AB + P:out SFIXED); -- O=AB +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e; +architecture structural of WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(7 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(7 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x256_xlslice; + +architecture behavior of ssr_8x256_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_6128f842cc is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_6128f842cc; +architecture behavior of sysgen_concat_6128f842cc +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_3bad6996c0 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_3bad6996c0; +architecture behavior of sysgen_reinterpret_3bad6996c0 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_9cd5a6908e is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_9cd5a6908e; +architecture behavior of sysgen_reinterpret_9cd5a6908e +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c6ccfb3c89 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c6ccfb3c89; +architecture behavior of sysgen_concat_c6ccfb3c89 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd new file mode 100644 index 000000000..770ff703a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd new file mode 100644 index 000000000..5d837de43 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd new file mode 100644 index 000000000..34bfa2e8c --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd new file mode 100644 index 000000000..92017d49a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd new file mode 100644 index 000000000..30f2d1e4a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x256_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x256_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x256. +component ssr_8x256 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 8-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 8-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (7 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (7 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (7 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x256. +ssr_8x256_i : ssr_8x256 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd new file mode 100644 index 000000000..ef0ef0372 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd @@ -0,0 +1,251 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x32_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 32; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x32_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 2 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd new file mode 100644 index 000000000..c07cb2e44 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile new file mode 100644 index 000000000..df6451cd1 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl new file mode 100644 index 000000000..9523c5de6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe new file mode 100644 index 000000000..63207d0a8 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 0,-293,-611,-893,31761,-893,-611,-293,-28,-331,-750,-1340,31712,-455,-471,-254,-30,-367,-886,-1793,31565,-31,-332,-215,-31,-401,-1019,-2247,31322,378,-195,-175,-32,-433,-1147,-2699,30983,768,-60,-135,-32,-463,-1269,-3145,30551,1136,70,-95,-32,-489,-1383,-3580,30028,1481,196,-56,-31,-511,-1488,-4000,29417,1798,316,-18,-29,-530,-1582,-4401,28722,2088,428,19,-27,-544,-1665,-4778,27945,2349,533,54,-24,-554,-1735,-5126,27093,2578,630,87,-20,-559,-1792,-5442,26168,2776,717,119,-15,-560,-1833,-5721,25178,2941,795,148,-10,-554,-1859,-5958,24126,3074,863,174,-3,-544,-1868,-6151,23020,3175,922,199,4,-528,-1861,-6294,21864,3243,969,221,13,-506,-1835,-6385,20666,3279,1007,240,22,-479,-1791,-6420,19431,3284,1034,256,32,-446,-1729,-6396,18166,3260,1050,270,43,-407,-1649,-6310,16878,3206,1057,281,55,-364,-1551,-6160,15574,3125,1054,290,67,-315,-1434,-5944,14261,3019,1041,296,81,-261,-1301,-5659,12944,2889,1020,300,95,-203,-1150,-5306,11631,2738,990,301,109,-140,-984,-4882,10328,2566,952,300,124,-74,-802,-4388,9042,2378,907,297,139,-4,-607,-3824,7778,2174,856,292,155,68,-400,-3190,6543,1957,798,285,170,143,-181,-2486,5342,1730,736,276,186,219,46,-1716,4180,1495,669,267,201,296,281,-880,3062,1254,599,255,215,373,521,19,1993,1010,525,242 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe new file mode 100644 index 000000000..e24661a01 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 230,450,765,978,978,765,450,230,242,525,1010,1993,19,521,373,215,255,599,1254,3062,-880,281,296,201,267,669,1495,4180,-1716,46,219,186,276,736,1730,5342,-2486,-181,143,170,285,798,1957,6543,-3190,-400,68,155,292,856,2174,7778,-3824,-607,-4,139,297,907,2378,9042,-4388,-802,-74,124,300,952,2566,10328,-4882,-984,-140,109,301,990,2738,11631,-5306,-1150,-203,95,300,1020,2889,12944,-5659,-1301,-261,81,296,1041,3019,14261,-5944,-1434,-315,67,290,1054,3125,15574,-6160,-1551,-364,55,281,1057,3206,16878,-6310,-1649,-407,43,270,1050,3260,18166,-6396,-1729,-446,32,256,1034,3284,19431,-6420,-1791,-479,22,240,1007,3279,20666,-6385,-1835,-506,13,221,969,3243,21864,-6294,-1861,-528,4,199,922,3175,23020,-6151,-1868,-544,-3,174,863,3074,24126,-5958,-1859,-554,-10,148,795,2941,25178,-5721,-1833,-560,-15,119,717,2776,26168,-5442,-1792,-559,-20,87,630,2578,27093,-5126,-1735,-554,-24,54,533,2349,27945,-4778,-1665,-544,-27,19,428,2088,28722,-4401,-1582,-530,-29,-18,316,1798,29417,-4000,-1488,-511,-31,-56,196,1481,30028,-3580,-1383,-489,-32,-95,70,1136,30551,-3145,-1269,-463,-32,-135,-60,768,30983,-2699,-1147,-433,-32,-175,-195,378,31322,-2247,-1019,-401,-31,-215,-332,-31,31565,-1793,-886,-367,-30,-254,-471,-455,31712,-1340,-750,-331,-28 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe new file mode 100644 index 000000000..ab437e3b4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -688,-303,-646,-1004,31758,-783,-576,-284,-28,-340,-784,-1453,31684,-348,-437,-244,-30,-376,-920,-1906,31514,73,-298,-205,-31,-410,-1052,-2360,31246,478,-161,-165,-32,-441,-1178,-2811,30884,862,-27,-125,-32,-469,-1298,-3255,30429,1225,102,-85,-32,-495,-1410,-3687,29884,1563,226,-46,-31,-516,-1512,-4102,29251,1874,344,-9,-29,-534,-1604,-4497,28535,2156,455,28,-26,-547,-1684,-4867,27739,2409,558,62,-23,-556,-1751,-5208,26868,2631,652,95,-19,-560,-1804,-5515,25927,2820,738,126,-14,-559,-1841,-5784,24920,2978,813,155,-8,-552,-1863,-6011,23855,3103,879,181,-1,-540,-1868,-6191,22735,3195,934,205,6,-523,-1856,-6322,21568,3255,980,226,15,-500,-1826,-6399,20360,3283,1014,244,24,-471,-1777,-6420,19117,3281,1039,260,35,-437,-1711,-6380,17846,3249,1053,273,46,-397,-1626,-6279,16554,3188,1057,284,58,-352,-1523,-6112,15247,3101,1052,292,71,-302,-1402,-5879,13931,2989,1037,297,84,-247,-1264,-5578,12615,2853,1013,300,98,-187,-1110,-5207,11304,2697,981,301,113,-124,-940,-4765,10005,2521,942,299,128,-56,-755,-4254,8724,2328,895,296,143,14,-556,-3672,7466,2121,842,290,159,87,-346,-3020,6239,1901,783,283,174,162,-125,-2300,5047,1672,720,274,189,238,104,-1513,3896,1435,652,264,204,315,341,-661,2790,1193,581,252,219,393,582,253,1734,949,507,239 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe new file mode 100644 index 000000000..58e870415 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 233,469,826,1226,732,704,431,226,245,544,1071,2256,-212,461,354,212,258,616,1315,3337,-1095,222,277,197,269,686,1554,4466,-1915,-12,200,182,279,752,1788,5638,-2669,-237,124,166,287,813,2012,6849,-3355,-453,50,151,293,869,2226,8092,-3971,-657,-22,136,298,919,2426,9362,-4518,-849,-91,120,301,963,2611,10653,-4995,-1027,-156,106,301,998,2778,11959,-5401,-1189,-218,91,299,1026,2924,13273,-5737,-1336,-275,77,295,1045,3048,14590,-6004,-1465,-327,64,288,1056,3148,15901,-6204,-1577,-375,52,279,1056,3222,17202,-6338,-1671,-418,40,267,1047,3268,18485,-6408,-1747,-455,29,253,1028,3286,19742,-6417,-1804,-486,19,235,998,3273,20969,-6368,-1843,-512,10,215,958,3229,22157,-6263,-1864,-532,2,193,908,3153,23301,-6107,-1868,-547,-5,168,847,3044,24395,-5903,-1854,-556,-11,141,777,2903,25431,-5655,-1824,-560,-17,111,696,2729,26406,-5366,-1779,-559,-21,79,606,2524,27313,-5042,-1719,-552,-25,45,508,2286,28147,-4686,-1645,-541,-28,10,401,2019,28903,-4303,-1559,-526,-30,-27,286,1722,29578,-3897,-1462,-506,-31,-66,165,1397,30167,-3473,-1355,-482,-32,-105,38,1047,30668,-3034,-1239,-456,-32,-145,-94,673,31077,-2587,-1116,-426,-31,-185,-229,278,31392,-2133,-986,-393,-31,-225,-367,-135,31611,-1679,-852,-358,-29,-264,-506,-564,31733,-1228,-715,-322,-27 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe new file mode 100644 index 000000000..915b71ebc --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -27,-312,-681,-1116,31749,-673,-541,-274,-29,-349,-818,-1566,31651,-241,-402,-235,-30,-384,-953,-2020,31456,176,-263,-195,-31,-418,-1084,-2474,31165,576,-127,-155,-32,-448,-1209,-2923,30779,955,6,-115,-32,-476,-1327,-3364,30301,1312,134,-75,-31,-500,-1436,-3792,29734,1643,257,-37,-30,-521,-1536,-4203,29080,1947,373,1,-28,-538,-1625,-4592,28343,2222,482,37,-26,-550,-1702,-4956,27528,2467,582,71,-22,-557,-1765,-5288,26639,2681,675,103,-18,-560,-1814,-5586,25681,2863,757,133,-13,-558,-1848,-5845,24659,3012,831,161,-7,-550,-1866,-6060,23580,3129,894,187,0,-537,-1867,-6229,22448,3213,947,210,8,-518,-1850,-6346,21270,3265,989,231,17,-493,-1815,-6410,20052,3285,1021,248,27,-463,-1763,-6416,18802,3276,1043,264,37,-427,-1691,-6361,17525,3236,1055,276,49,-386,-1602,-6243,16228,3169,1057,286,61,-340,-1495,-6060,14918,3075,1049,293,74,-288,-1370,-5810,13602,2957,1032,298,88,-232,-1227,-5491,12287,2816,1006,301,102,-172,-1069,-5103,10978,2654,972,301,117,-107,-895,-4644,9683,2474,931,299,132,-39,-706,-4115,8407,2278,882,295,147,32,-505,-3515,7157,2067,828,289,163,105,-292,-2847,5938,1845,768,281,178,181,-69,-2110,4755,1613,703,272,193,258,163,-1306,3615,1375,634,261,208,335,401,-438,2521,1132,562,250,223,412,643,491,1479,888,488,236 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe new file mode 100644 index 000000000..dca0ad408 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 236,488,888,1479,491,643,412,223,250,562,1132,2521,-438,401,335,208,261,634,1375,3615,-1306,163,258,193,272,703,1613,4755,-2110,-69,181,178,281,768,1845,5938,-2847,-292,105,163,289,828,2067,7157,-3515,-505,32,147,295,882,2278,8407,-4115,-706,-39,132,299,931,2474,9683,-4644,-895,-107,117,301,972,2654,10978,-5103,-1069,-172,102,301,1006,2816,12287,-5491,-1227,-232,88,298,1032,2957,13602,-5810,-1370,-288,74,293,1049,3075,14918,-6060,-1495,-340,61,286,1057,3169,16228,-6243,-1602,-386,49,276,1055,3236,17525,-6361,-1691,-427,37,264,1043,3276,18802,-6416,-1763,-463,27,248,1021,3285,20052,-6410,-1815,-493,17,231,989,3265,21270,-6346,-1850,-518,8,210,947,3213,22448,-6229,-1867,-537,0,187,894,3129,23580,-6060,-1866,-550,-7,161,831,3012,24659,-5845,-1848,-558,-13,133,757,2863,25681,-5586,-1814,-560,-18,103,675,2681,26639,-5288,-1765,-557,-22,71,582,2467,27528,-4956,-1702,-550,-26,37,482,2222,28343,-4592,-1625,-538,-28,1,373,1947,29080,-4203,-1536,-521,-30,-37,257,1643,29734,-3792,-1436,-500,-31,-75,134,1312,30301,-3364,-1327,-476,-32,-115,6,955,30779,-2923,-1209,-448,-32,-155,-127,576,31165,-2474,-1084,-418,-31,-195,-263,176,31456,-2020,-953,-384,-30,-235,-402,-241,31651,-1566,-818,-349,-29,-274,-541,-673,31749,-1116,-681,-312,-27 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe new file mode 100644 index 000000000..5a7d377e1 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -27,-322,-715,-1228,31733,-564,-506,-264,-29,-358,-852,-1679,31611,-135,-367,-225,-31,-393,-986,-2133,31392,278,-229,-185,-31,-426,-1116,-2587,31077,673,-94,-145,-32,-456,-1239,-3034,30668,1047,38,-105,-32,-482,-1355,-3473,30167,1397,165,-66,-31,-506,-1462,-3897,29578,1722,286,-27,-30,-526,-1559,-4303,28903,2019,401,10,-28,-541,-1645,-4686,28147,2286,508,45,-25,-552,-1719,-5042,27313,2524,606,79,-21,-559,-1779,-5366,26406,2729,696,111,-17,-560,-1824,-5655,25431,2903,777,141,-11,-556,-1854,-5903,24395,3044,847,168,-5,-547,-1868,-6107,23301,3153,908,193,2,-532,-1864,-6263,22157,3229,958,215,10,-512,-1843,-6368,20969,3273,998,235,19,-486,-1804,-6417,19742,3286,1028,253,29,-455,-1747,-6408,18485,3268,1047,267,40,-418,-1671,-6338,17202,3222,1056,279,52,-375,-1577,-6204,15901,3148,1056,288,64,-327,-1465,-6004,14590,3048,1045,295,77,-275,-1336,-5737,13273,2924,1026,299,91,-218,-1189,-5401,11959,2778,998,301,106,-156,-1027,-4995,10653,2611,963,301,120,-91,-849,-4518,9362,2426,919,298,136,-22,-657,-3971,8092,2226,869,293,151,50,-453,-3355,6849,2012,813,287,166,124,-237,-2669,5638,1788,752,279,182,200,-12,-1915,4466,1554,686,269,197,277,222,-1095,3337,1315,616,258,212,354,461,-212,2256,1071,544,245,226,431,704,732,1226,826,469,233 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe new file mode 100644 index 000000000..af874178f --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 239,507,949,1734,253,582,393,219,252,581,1193,2790,-661,341,315,204,264,652,1435,3896,-1513,104,238,189,274,720,1672,5047,-2300,-125,162,174,283,783,1901,6239,-3020,-346,87,159,290,842,2121,7466,-3672,-556,14,143,296,895,2328,8724,-4254,-755,-56,128,299,942,2521,10005,-4765,-940,-124,113,301,981,2697,11304,-5207,-1110,-187,98,300,1013,2853,12615,-5578,-1264,-247,84,297,1037,2989,13931,-5879,-1402,-302,71,292,1052,3101,15247,-6112,-1523,-352,58,284,1057,3188,16554,-6279,-1626,-397,46,273,1053,3249,17846,-6380,-1711,-437,35,260,1039,3281,19117,-6420,-1777,-471,24,244,1014,3283,20360,-6399,-1826,-500,15,226,980,3255,21568,-6322,-1856,-523,6,205,934,3195,22735,-6191,-1868,-540,-1,181,879,3103,23855,-6011,-1863,-552,-8,155,813,2978,24920,-5784,-1841,-559,-14,126,738,2820,25927,-5515,-1804,-560,-19,95,652,2631,26868,-5208,-1751,-556,-23,62,558,2409,27739,-4867,-1684,-547,-26,28,455,2156,28535,-4497,-1604,-534,-29,-9,344,1874,29251,-4102,-1512,-516,-31,-46,226,1563,29884,-3687,-1410,-495,-32,-85,102,1225,30429,-3255,-1298,-469,-32,-125,-27,862,30884,-2811,-1178,-441,-32,-165,-161,478,31246,-2360,-1052,-410,-31,-205,-298,73,31514,-1906,-920,-376,-30,-244,-437,-348,31684,-1453,-784,-340,-28,-284,-576,-783,31758,-1004,-646,-303,-688 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl new file mode 100644 index 000000000..83d67e016 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl @@ -0,0 +1,264 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo new file mode 100644 index 000000000..b2d1d6ff4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci new file mode 100644 index 000000000..a73c782d2 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_0.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci new file mode 100644 index 000000000..81ced9d7c --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_1.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci new file mode 100644 index 000000000..f1fbb7ab4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_2.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci new file mode 100644 index 000000000..652cf8e61 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_3.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci new file mode 100644 index 000000000..42ef53298 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_4.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci new file mode 100644 index 000000000..15e1f9a2e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_5.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci new file mode 100644 index 000000000..00552f8a8 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_6.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci new file mode 100644 index 000000000..c5b4328e4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_7.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl new file mode 100755 index 000000000..deba046dc --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template new file mode 100644 index 000000000..510b2d316 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template @@ -0,0 +1,33 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl new file mode 100644 index 000000000..e1a370512 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv new file mode 100644 index 000000000..fb45002ac --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv @@ -0,0 +1,300 @@ +module firs + #( + // Number of channels. + parameter N = 32 , + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire [2*L*32-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // M_AXIS for output data. + output wire [L*32-1:0] m_axis_tdata , + output wire m_axis_tvalid + ); + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire [7:0] config_tdata; + +// Framing. +wire tvalid_fr; +wire fr_sync; + +// Input data. +wire [31:0] data_v [2*L]; + +// FIR outputs. +wire signed [31:0] dout_v [2*L]; + +// Delayed FIR outputs. +wire signed [31:0] dout_v_d [L]; + +// Addition of FIR outputs. +wire signed [15:0] sum_real_v [L]; +wire signed [15:0] sum_imag_v [L]; +wire [31:0] sum_v [L]; +wire [L*32-1:0] sum; +reg [L*32-1:0] sum_r1; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv new file mode 100644 index 000000000..87944f33a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv @@ -0,0 +1,108 @@ +// This block computes the complex conjugate of the data. +module pfb_conjugate + #( + // Number of bits of real/imaginary part. + parameter B = 16 , + + // Number of lanes. + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire [2*B*L-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // M_AXIS for output data. + output wire [2*B*L-1:0] m_axis_tdata , + output wire m_axis_tlast , + output wire m_axis_tvalid + ); + +/********************/ +/* Internal signals */ +/********************/ +// Input data registers. +reg [2*B*L-1:0] din_r1; + +// I/Q parts. +wire signed [B-1:0] din_i_v[L]; +wire signed [B-1:0] din_q_v[L]; + +// Complex conjugate. +wire signed [B-1:0] din_i_conj_v[L]; +wire signed [B-1:0] din_q_conj_v[L]; + +// Output data. +wire [2*B*L-1:0] dout; + +// Output data registers. +reg [2*B*L-1:0] dout_r1; + +// tlast/tvalid registers. +reg tlast_r1; +reg tlast_r2; +reg tvalid_r1; +reg tvalid_r2; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tvalid => tvalid , + fr_sync => fr_sync + ); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd new file mode 100644 index 000000000..db99fb3cf --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd new file mode 100644 index 000000000..9aa0bae1b --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd @@ -0,0 +1,114 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tvalid : out std_logic; + fr_sync : in std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Wait value. +constant WAIT_C : Integer := 2*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +signal tvalid_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +wait_cnt_en <= '0'; +tvalid_i <= '1'; + case current_state is + when INIT_ST => + + when SHIFT_ST => + tvalid_i <= '0'; + + when WAIT_ST => + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +tvalid <= tvalid_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv new file mode 100644 index 000000000..1297219d8 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv @@ -0,0 +1,133 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Data registers. +reg [2*L*B-1:0] data_r1; +reg [2*L*B-1:0] data_r2; +reg [2*L*B-1:0] data_r3; +reg [2*L*B-1:0] data_r4; + +// Tlast registers. +reg last_r1; +reg last_r2; +reg last_r3; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +// Sorted output data. +wire [2*L*B-1:0] dmux_sort; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv new file mode 100644 index 000000000..81b2da376 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv @@ -0,0 +1,331 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +`timescale 1ns/1ps + +parameter N = 256; +parameter L = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire [8*32-1:0] s_axis_tdata; +reg s_axis_tlast; +reg s_axis_tvalid; +wire s_axis_tready; + +wire [4*32-1:0] m_axis_tdata; +wire m_axis_tvalid; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +wire[31:0] din_ii [2*L]; +reg signed [15:0] din_real_ii [2*L]; +reg signed [15:0] din_imag_ii [2*L]; + +// Output data. +wire[31:0] dout_ii [L]; +wire[15:0] dout_real_ii[L]; +wire[15:0] dout_imag_ii[L]; + +// Debug. +reg faclk; +reg [31:0] debug_v; +reg [15:0] debug_v_real; +reg [15:0] debug_v_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + +generate +genvar ii; +for (ii = 0; ii < L; ii = ii + 1) begin + // Input data. + assign din_ii [ii] = {din_imag_ii[ii] , din_real_ii[ii]}; + assign din_ii [ii+L] = {din_imag_ii[ii+L], din_real_ii[ii+L]}; + + assign s_axis_tdata [32*ii +: 32] = din_ii[ii]; + assign s_axis_tdata [32*(ii+L) +: 32] = din_ii[ii+L]; + + assign dout_ii [ii] = m_axis_tdata[32*ii +: 32]; + assign dout_real_ii [ii] = dout_ii[ii][15:0]; + assign dout_imag_ii [ii] = dout_ii[ii][31:16]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfbsynth_4x256_v1 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk , + .s_axi_aresetn , + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arready , + .s_axi_arvalid , + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awready , + .s_axi_awvalid , + .s_axi_bready , + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_rdata , + .s_axi_rready , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_wdata , + .s_axi_wready , + .s_axi_wstrb , + .s_axi_wvalid , + + // s_* and m_* reset/clock. + .aresetn , + .aclk , + + // S_AXIS for data input. + .s_axis_tdata , + .s_axis_tlast , + .s_axis_tvalid , + .s_axis_tready , + + // M_AXIS for data output. + .m_axis_tdata , + .m_axis_tvalid + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + // QOUT_REG + data_wr = 4; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // Start data. + tb_data <= 1; + #10000; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; +end + +// Input data. +initial begin + real pi; + real w; + real a; + int n; + + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + wait(tb_data); + @(posedge aclk); + + n = 0; + pi = 3.1415; + w = 0.07; + a = 0.9; + for (int k=0; k<500; k=k+1) begin + for (int i=0; i (others => '0')); + else + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl new file mode 100644 index 000000000..716ad7e7c --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_readout_v1/component.xml b/firmware/ip/axis_readout_v1/component.xml index 1fe28566c..9a190cbbb 100644 --- a/firmware/ip/axis_readout_v1/component.xml +++ b/firmware/ip/axis_readout_v1/component.xml @@ -1,7 +1,7 @@ - user.org - user + QICK + QICK axis_readout_v1 1.0 @@ -432,6 +432,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -1078,6 +1092,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS Readout V1 block with digital down-conversion, filtering and 8x decimation. @@ -1092,10 +1113,12 @@ zynquplus - /UserIP + /QICK/Readout AXIS Readout V1 package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ 9 2021-07-09T15:22:25Z diff --git a/firmware/ip/axis_readout_v2/component.xml b/firmware/ip/axis_readout_v2/component.xml index e519817f6..438b36ee0 100644 --- a/firmware/ip/axis_readout_v2/component.xml +++ b/firmware/ip/axis_readout_v2/component.xml @@ -1,7 +1,7 @@ - user.org - user + QICK + QICK axis_readout_v2 1.0 @@ -36,6 +36,13 @@ + + + + true + + + m1_axis @@ -392,7 +399,7 @@ viewChecksum - 722f5916 + 2443c52b @@ -414,7 +421,7 @@ viewChecksum - 722f5916 + 2443c52b @@ -428,7 +435,21 @@ viewChecksum - f92e9879 + f835ce2d + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 @@ -955,10 +976,16 @@ src/fir_compiler_0/fir_compiler_0.xci xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i/fir_compiler_0 src/dds_compiler_0/dds_compiler_0.xci xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir.coe + coe src/down_conversion.v @@ -992,10 +1019,6 @@ src/synchronizer_n.vhd vhdlSource - - src/fir.coe - coe - src/axis_readout_v2.v verilogSource @@ -1027,10 +1050,16 @@ src/fir_compiler_0/fir_compiler_0.xci xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i/fir_compiler_0 src/dds_compiler_0/dds_compiler_0.xci xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir.coe + coe src/down_conversion.v @@ -1064,10 +1093,6 @@ src/synchronizer_n.vhd vhdlSource - - src/fir.coe - coe - src/axis_readout_v2.v verilogSource @@ -1098,10 +1123,18 @@ xgui/axis_readout_v2_v1_0.tcl tclSource - CHECKSUM_f92e9879 + CHECKSUM_f835ce2d XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + AXIS Readout V2 block with digital down-conversion (32-bit, phase coherent), filtering and 8x decimation. @@ -1109,6 +1142,11 @@ Component_Name axis_readout_v2_v1_0 + + FULLSPEED_OUTPUT + Fullspeed Output + true + @@ -1116,12 +1154,14 @@ zynquplus - /UserIP + /QICK/Readout AXIS Readout V2 package_project - 4 - 2021-09-01T20:58:34Z + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 9 + 2025-09-11T22:24:47Z /home/lstefana/qsystem_2/ip/axis_readout_v2 /home/lstefana/qsystem_2/ip/axis_readout_v2 @@ -1168,15 +1208,61 @@ /home/lstefana/qsystem_2/ip/axis_readout_v2 /home/lstefana/qsystem_2/ip/axis_readout_v2 /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - 2019.1 - + 2023.1 + - + - + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo index 5f3313504..7cfbd51b5 100644 --- a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo @@ -1,4 +1,4 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 +// IP Revision: 8 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho index 5c4d9a9f7..a53be60f7 100644 --- a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho @@ -1,4 +1,4 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 +-- IP Revision: 8 -- The following code must appear in the VHDL architecture header. diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci index 34f0b1287..ac9cf042c 100644 --- a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci @@ -12,6 +12,7 @@ ACTIVE_LOW 100000000 + 0 0 0.000 32 @@ -128,26 +129,26 @@ 0 0 0 - virtex7 - + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 - xc7vx485t - ffg1157 + xczu49dr + ffvf1760 VERILOG MIXED - -1 + -2 - + E TRUE TRUE IP_Flow - 5 + 8 TRUE . . - 2019.1 + 2020.2 OUT_OF_CONTEXT @@ -180,6 +181,18 @@ + + + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml index 51a5f3350..4b49cfec7 100644 --- a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml @@ -1419,6 +1419,15 @@ FREQ_HZ 100000000 + + FREQ_TOLERANCE_HZ + 0 + + + none + + + PHASE 0.000 @@ -1543,11 +1552,11 @@ GENtimestamp - Thu Dec 17 22:05:33 UTC 2020 + Fri Feb 18 19:55:05 UTC 2022 outputProductCRC - 9:564fbf77 + 9:b40c5c85 @@ -1556,7 +1565,7 @@ Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog - axi_vip_v1_1_5_top + axi_vip_v1_1_8_top xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset @@ -1566,11 +1575,11 @@ GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:564fbf77 + 9:b40c5c85 @@ -1584,11 +1593,11 @@ GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:564fbf77 + 9:b40c5c85 @@ -1604,48 +1613,11 @@ GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_5_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Thu Dec 17 22:06:13 UTC 2020 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:564fbf77 + 9:b40c5c85 @@ -1654,7 +1626,7 @@ Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog - axi_vip_v1_1_5_top + axi_vip_v1_1_8_top xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset @@ -1664,11 +1636,11 @@ GENtimestamp - Wed Sep 01 18:47:47 UTC 2021 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:eaaf4dfa + 9:a9f86b20 @@ -1684,11 +1656,11 @@ GENtimestamp - Wed Sep 01 18:47:47 UTC 2021 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:6d8e49fa + 9:81fdbefd sim_type @@ -1712,11 +1684,11 @@ GENtimestamp - Wed Sep 01 18:47:47 UTC 2021 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:eaaf4dfa + 9:a9f86b20 @@ -1732,11 +1704,11 @@ GENtimestamp - Wed Sep 01 18:47:47 UTC 2021 + Fri Feb 18 19:59:09 UTC 2022 outputProductCRC - 9:6d8e49fa + 9:81fdbefd sim_type @@ -1744,6 +1716,43 @@ + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + axi_vip_v1_1_8_top + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Fri Feb 18 19:59:09 UTC 2022 + + + outputProductCRC + 9:b40c5c85 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Fri Feb 18 20:00:27 UTC 2022 + + + outputProductCRC + 9:b40c5c85 + + + @@ -4296,7 +4305,7 @@ hdl/axi_vip_v1_1_vlsyn_rfs.sv systemVerilogSource - axi_vip_v1_1_5 + axi_vip_v1_1_8 @@ -4317,50 +4326,6 @@ xil_defaultlib - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset @@ -4394,7 +4359,7 @@ hdl/axi_vip_v1_1_vl_rfs.sv systemVerilogSource USED_IN_ipstatic - axi_vip_v1_1_5 + axi_vip_v1_1_8 @@ -4402,13 +4367,13 @@ sysc/axi_vip.cpp systemCSource - axi_vip_v1_1_5 + axi_vip_v1_1_8 sysc/axi_vip.h systemCSource true - axi_vip_v1_1_5 + axi_vip_v1_1_8 @@ -4444,6 +4409,50 @@ systemVerilogSource + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + The AXI Verification IP. @@ -4470,7 +4479,7 @@ ADDR_WIDTH ADDRESS WIDTH - 32 + 32 DATA_WIDTH @@ -4706,7 +4715,7 @@ xtlm - 5 + 8 true @@ -4738,14 +4747,14 @@ - 2019.1 + 2020.2 - + - + diff --git a/firmware/ip/axis_readout_v2/src/ctrl.sv b/firmware/ip/axis_readout_v2/src/ctrl.sv index 0df88e71c..a6932cfbb 100644 --- a/firmware/ip/axis_readout_v2/src/ctrl.sv +++ b/firmware/ip/axis_readout_v2/src/ctrl.sv @@ -57,16 +57,24 @@ reg [31:0] cnt_n_reg; // Pinc/phase. wire [31:0] pinc_int; reg [31:0] pinc_r1; +reg [31:0] pinc_r2; wire [31:0] pinc_N; reg [31:0] pinc_N_r1; reg [31:0] pinc_N_r2; reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; wire [31:0] pinc_Nm; reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; wire [31:0] phase_int; reg [31:0] phase_r1; reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; wire [31:0] phase_0; reg [31:0] phase_0_r1; @@ -74,16 +82,11 @@ reg [31:0] phase_0_r1; wire [31:0] phase_v0 [0:N_DDS-1]; reg [31:0] phase_v0_r1 [0:N_DDS-1]; reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; wire [31:0] phase_v1 [0:N_DDS-1]; reg [31:0] phase_v1_r1 [0:N_DDS-1]; -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; - // Number of samples. wire [15:0] nsamp_int; @@ -93,18 +96,26 @@ reg [1:0] outsel_r1; reg [1:0] outsel_r2; reg [1:0] outsel_r3; reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; // Mode. wire mode_int; // Load enable flag. wire load_int; -reg load_r; +reg load_r1; +reg load_r2; +reg load_r3; +reg load_r4; +reg load_r5; +reg load_r6; +reg load_r7; +reg load_r8; // Fifo Read Enable. reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; // Counter. reg [15:0] cnt; @@ -124,33 +135,41 @@ always @(posedge clk) begin // Pinc/phase/sync. pinc_r1 <= 0; + pinc_r2 <= 0; pinc_N_r1 <= 0; pinc_N_r2 <= 0; pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; phase_r1 <= 0; phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; phase_0_r1 <= 0; - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - // Output selection. outsel_r1 <= 0; outsel_r2 <= 0; outsel_r3 <= 0; outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; + load_r1 <= 0; + load_r2 <= 0; + load_r3 <= 0; + load_r4 <= 0; + load_r5 <= 0; + load_r6 <= 0; + load_r7 <= 0; + load_r8 <= 0; // Counter. cnt <= 0; @@ -167,43 +186,51 @@ always @(posedge clk) begin endcase // Fifo dout register. - if (load_r) + if (load_r1) fifo_dout_r <= fifo_dout_i; // Non-stop counter for time calculation. cnt_n <= cnt_n + N_DDS; - if (sync_reg) + if (load_r2) cnt_n_reg <= cnt_n; // Pinc/phase/sync. pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; pinc_N_r1 <= pinc_N; pinc_N_r2 <= pinc_N_r1; pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; phase_r1 <= phase_int; phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; phase_0_r1 <= phase_0; - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - // Output selection. outsel_r1 <= outsel_int; outsel_r2 <= outsel_r1; outsel_r3 <= outsel_r2; outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; + load_r1 <= load_int; + load_r2 <= load_r1; + load_r3 <= load_r2; + load_r4 <= load_r3; + load_r5 <= load_r4; + load_r6 <= load_r5; + load_r7 <= load_r6; + load_r8 <= load_r7; // Counter. if (rd_en_int) @@ -235,11 +262,11 @@ assign outsel_int = fifo_dout_r[81:80]; assign mode_int = fifo_dout_r[82]; // Frequency calculation. -assign pinc_N = pinc_r1*N_DDS; +assign pinc_N = pinc_r2*N_DDS; // Phase calculation. -assign pinc_Nm = pinc_r1*cnt_n_reg; -assign phase_0 = pinc_Nm_r1 + phase_r2; +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; // Phase vectors. generate @@ -251,6 +278,8 @@ genvar i; // v0. phase_v0_r1[i] <= 0; phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; // v1. phase_v1_r1[i] <= 0; @@ -259,6 +288,8 @@ genvar i; // v0. phase_v0_r1[i] <= phase_v0[i]; phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; // v1. phase_v1_r1[i] <= phase_v1[i]; @@ -266,13 +297,13 @@ genvar i; end // v0. - assign phase_v0[i] = pinc_r1*i; + assign phase_v0[i] = pinc_r2*i; // v1. - assign phase_v1[i] = phase_v0_r2[i] + phase_0_r1; + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; // dds_ctrl_o output. - assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r4,phase_v1_r1[i],pinc_N_r3}; + assign dds_ctrl_o[i*72 +: 72] = {7'h00,load_r8,phase_v1_r1[i],pinc_N_r5}; end endgenerate @@ -281,7 +312,7 @@ assign load_int = rd_en_int & ~fifo_empty_i; // Assign outputs. assign fifo_rd_en_o = rd_en_int; -assign outsel_o = outsel_r4; +assign outsel_o = outsel_r7; endmodule diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo index 894ecd665..7bf3bc5ed 100644 --- a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo @@ -1,4 +1,4 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 +// IP Revision: 20 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho index e65044c1b..8bdeb4aa1 100644 --- a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho @@ -1,4 +1,4 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 +-- IP Revision: 20 -- The following code must appear in the VHDL architecture header. diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci index 50c4a4b9b..5435361c9 100644 --- a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -1,306 +1,358 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 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"xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_phase_in_invalid_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_phase_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_phase_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_phase_chanid_incorrect_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "S_AXIS_PHASE": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "s_axis_phase_tdata" } ], + "TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ] + } + }, + "aclk_intf": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml index 5620a65aa..57bba34ce 100644 --- a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml @@ -461,6 +461,15 @@ aclk 100000000 + + FREQ_TOLERANCE_HZ + 0 + + + none + + + PHASE 0.000 @@ -539,12 +548,7 @@ POLARITY - ACTIVE_LOW - - - none - - + ACTIVE_HIGH @@ -1079,86 +1083,11 @@ GENtimestamp - Wed Sep 01 20:39:32 UTC 2021 - - - outputProductCRC - 9:c041be49 - - - - - xilinx_vhdlsynthesis - VHDL Synthesis - vhdlSource:vivado.xilinx.com:synthesis - vhdl - dds_compiler_v6_0_18 - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_view_fileset - - - - GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 - - - outputProductCRC - 9:c041be49 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:c041be49 - - - - - xilinx_vhdlsynthesiswrapper - VHDL Synthesis Wrapper - vhdlSource:vivado.xilinx.com:synthesis.wrapper - vhdl - dds_compiler_0 - - xilinx_vhdlsynthesiswrapper_view_fileset - - - - GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 + Fri Feb 18 20:02:32 UTC 2022 outputProductCRC - 9:c041be49 + 9:2f182b5a @@ -1167,7 +1096,7 @@ VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl - dds_compiler_v6_0_18 + dds_compiler_v6_0_20 xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset @@ -1198,11 +1127,11 @@ GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 + Fri Feb 18 20:02:41 UTC 2022 outputProductCRC - 9:0147f840 + 9:2d00cc37 @@ -1218,68 +1147,11 @@ GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 - - - outputProductCRC - 9:0147f840 - - - - - xilinx_cmodelsimulation - C Simulation - cSource:vivado.xilinx.com:simulation.cmodel - c - - xilinx_cmodelsimulation_view_fileset - - - - GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 + Fri Feb 18 20:02:41 UTC 2022 outputProductCRC - 9:c041be49 - - - - - xilinx_vhdltestbench - VHDL Test Bench - vhdlSource:vivado.xilinx.com:simulation.testbench - vhdl - testbench - - xilinx_vhdltestbench_view_fileset - - - - GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 - - - outputProductCRC - 9:c041be49 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Wed Sep 01 20:39:47 UTC 2021 - - - outputProductCRC - 9:c041be49 + 9:2d00cc37 @@ -1292,7 +1164,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1308,7 +1179,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1331,7 +1201,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1354,7 +1223,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1377,7 +1245,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1404,7 +1271,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1427,7 +1293,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1454,7 +1319,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1477,7 +1341,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1500,7 +1363,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1527,7 +1389,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1550,7 +1411,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1573,7 +1433,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1596,7 +1455,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1623,7 +1481,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1646,7 +1503,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1673,7 +1529,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1696,7 +1551,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1719,7 +1573,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1746,7 +1599,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1769,7 +1621,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1796,7 +1647,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1819,7 +1669,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1842,7 +1691,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1865,7 +1713,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1888,7 +1735,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1911,7 +1757,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1934,7 +1779,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1957,7 +1801,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1980,7 +1823,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -2342,142 +2184,6 @@ verilogTemplate - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - mult_gen_v12_0_15 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - dds_compiler_v6_0_18 - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset @@ -2488,7 +2194,7 @@ - + @@ -2548,11 +2254,11 @@ hdl/mult_gen_v12_0_vh_rfs.vhd vhdlSource USED_IN_ipstatic - mult_gen_v12_0_15 + mult_gen_v12_0_16 - + @@ -2612,7 +2318,7 @@ hdl/dds_compiler_v6_0_vh_rfs.vhd vhdlSource USED_IN_ipstatic - dds_compiler_v6_0_18 + dds_compiler_v6_0_20 @@ -2623,31 +2329,6 @@ xil_defaultlib - - xilinx_cmodelsimulation_view_fileset - - cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip - zip - - - cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. @@ -3101,7 +2782,7 @@ DDS Compiler - 18 + 20 @@ -3154,9 +2835,9 @@ - 2019.1 - - + 2020.2 + + diff --git a/firmware/ip/axis_readout_v2/src/down_conversion.v b/firmware/ip/axis_readout_v2/src/down_conversion.v index 7bc6c02e1..ae8bd04d0 100644 --- a/firmware/ip/axis_readout_v2/src/down_conversion.v +++ b/firmware/ip/axis_readout_v2/src/down_conversion.v @@ -55,7 +55,7 @@ wire [N_DDS*72-1:0] dds_ctrl_int; reg [N_DDS*72-1:0] dds_ctrl_int_r; // Output selection. -wire outsel_int; +wire [1:0] outsel_int; // DDS output. wire [31:0] dds_dout [0:N_DDS-1]; diff --git a/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd index 2fbb69667..ff87e9d21 100644 --- a/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd +++ b/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd @@ -29,6 +29,9 @@ architecture rtl of synchronizer_vect is type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); signal data_int_reg : reg_t; +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo index 2b70a4acf..e66a3e880 100644 --- a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo @@ -1,4 +1,4 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 12 +// IP Revision: 15 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho index 0f516af6d..a87716732 100644 --- a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho @@ -1,4 +1,4 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and @@ -47,7 +47,7 @@ -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 12 +-- IP Revision: 15 -- The following code must appear in the VHDL architecture header. diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci index af887176b..40ecae593 100644 --- a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci @@ -1,296 +1,352 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_compiler_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 32 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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml index 8c64b46c5..8dedd2636 100644 --- a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml @@ -422,6 +422,15 @@ aclk 100000000 + + FREQ_TOLERANCE_HZ + 0 + + + none + + + PHASE 0.000 @@ -500,12 +509,7 @@ POLARITY - ACTIVE_LOW - - - none - - + ACTIVE_HIGH @@ -1026,68 +1030,11 @@ GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 + Fri Feb 18 19:53:54 UTC 2022 outputProductCRC - 9:070cedb5 - - - - - xilinx_vhdlsynthesis - VHDL Synthesis - vhdlSource:vivado.xilinx.com:synthesis - vhdl - fir_compiler_v7_2_12 - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - - xilinx_vhdlsynthesis_view_fileset - - - - GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 - - - outputProductCRC - 9:070cedb5 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:070cedb5 - - - - - xilinx_vhdlsynthesiswrapper - VHDL Synthesis Wrapper - vhdlSource:vivado.xilinx.com:synthesis.wrapper - vhdl - fir_compiler_0 - - xilinx_vhdlsynthesiswrapper_view_fileset - - - - GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 - - - outputProductCRC - 9:070cedb5 + 9:8f264088 @@ -1096,7 +1043,7 @@ VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl - fir_compiler_v7_2_12 + fir_compiler_v7_2_15 xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset @@ -1109,11 +1056,11 @@ GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 + Fri Feb 18 19:59:07 UTC 2022 outputProductCRC - 9:90f6d50b + 9:970eb771 @@ -1129,79 +1076,11 @@ GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 - - - outputProductCRC - 9:90f6d50b - - - - - xilinx_cmodelsimulation - C Simulation - cSource:vivado.xilinx.com:simulation.cmodel - c - - xilinx_cmodelsimulation_view_fileset - - - - GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 - - - outputProductCRC - 9:070cedb5 - - - - - xilinx_vhdltestbench - VHDL Test Bench - vhdlSource:vivado.xilinx.com:simulation.testbench - vhdl - testbench - - xilinx_vhdltestbench_view_fileset - - - - GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 - - - outputProductCRC - 9:070cedb5 - - - - - xilinx_project_archive - Miscellaneous - :vivado.xilinx.com:misc.files - - - outputProductCRC - 9:070cedb5 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Wed Sep 01 20:57:50 UTC 2021 + Fri Feb 18 19:59:07 UTC 2022 outputProductCRC - 9:070cedb5 + 9:970eb771 @@ -1214,7 +1093,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1237,7 +1115,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1250,7 +1127,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1273,7 +1149,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1289,7 +1164,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1305,7 +1179,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1332,7 +1205,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1359,7 +1231,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1375,7 +1246,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1398,7 +1268,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1421,7 +1290,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1448,7 +1316,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1471,7 +1338,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1494,7 +1360,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1517,7 +1382,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1544,7 +1408,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1567,7 +1430,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1583,7 +1445,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1606,7 +1467,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1633,7 +1493,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1660,7 +1519,6 @@ std_logic_vector - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1676,7 +1534,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1699,7 +1556,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1722,7 +1578,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1745,7 +1600,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1768,7 +1622,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1791,7 +1644,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1814,7 +1666,6 @@ std_logic - xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -1850,7 +1701,7 @@ C_COEF_FILE_LINES - 120 + 60 C_FILTER_TYPE @@ -1870,7 +1721,7 @@ C_SYMMETRY - 0 + 1 C_NUM_FILTS @@ -1910,7 +1761,7 @@ C_COL_CONFIG - 120 + 60 C_OPTIMIZATION @@ -1990,7 +1841,7 @@ C_NUM_MADDS - 120 + 60 C_OPT_MADDS @@ -2030,7 +1881,7 @@ C_MEM_ARRANGEMENT - 2 + 1 C_DATA_MEM_PACKING @@ -2046,7 +1897,7 @@ C_LATENCY - 126 + 67 C_HAS_ARESETn @@ -2190,16 +2041,17 @@ Not_Required Chan_ID_Field - - choice_pairs_433eb1cb - Inferred - Non_Symmetric - choice_pairs_480f8ce0 Not_Required Packet_Framing + + choice_pairs_541959c1 + Inferred + Non_Symmetric + Symmetric + choice_pairs_74144f21 COE_File @@ -2256,61 +2108,6 @@ verilogTemplate - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - constraints/fir_compiler_v7_2.xdc - xdc - fir_compiler_v7_2_12 - - - fir_compiler_0.mif - mif - - - hdl/fir_compiler_v7_2_vh_rfs.vhd - vhdlSource - fir_compiler_v7_2_12 - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/fir_compiler_0.vhd - vhdlSource - xil_defaultlib - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset @@ -2321,7 +2118,7 @@ - + @@ -2348,7 +2145,7 @@ constraints/fir_compiler_v7_2.xdc xdc - fir_compiler_v7_2_12 + fir_compiler_v7_2_15 fir_compiler_0.mif @@ -2358,7 +2155,7 @@ hdl/fir_compiler_v7_2_vh_rfs.vhd vhdlSource USED_IN_ipstatic - fir_compiler_v7_2_12 + fir_compiler_v7_2_15 @@ -2369,39 +2166,6 @@ xil_defaultlib - - xilinx_cmodelsimulation_view_fileset - - cmodel/fir_compiler_0.h - cSource - - - cmodel/tb_fir_compiler_0.c - cSource - - - cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip - zip - - - cmodel/fir_compiler_v7_2_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_fir_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/fir_compiler_v7_2_changelog.txt - text - - The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. @@ -2515,7 +2279,7 @@ Coefficient_Structure - Inferred + Inferred Data_Sign @@ -2549,6 +2313,58 @@ Optimization_Selection None + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + Optimization_List None @@ -2583,7 +2399,7 @@ ColumnConfig - 120 + 60 DATA_Has_TLAST @@ -2681,7 +2497,7 @@ FIR Compiler - 12 + 15 @@ -2737,12 +2553,12 @@ - 2019.1 - - + 2020.2 + + - - + + diff --git a/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd b/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd index 925425de9..a29bd9be1 100644 --- a/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd +++ b/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd @@ -22,6 +22,9 @@ architecture rtl of synchronizer_n is -- Internal register. signal data_int_reg : std_logic_vector (N-1 downto 0); +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_readout_v2/src/tb/dout.csv b/firmware/ip/axis_readout_v2/src/tb/dout.csv index 7b3f24fd1..bddb23dc0 100644 --- a/firmware/ip/axis_readout_v2/src/tb/dout.csv +++ b/firmware/ip/axis_readout_v2/src/tb/dout.csv @@ -114,3621 +114,2673 @@ valid, real, imag 1, 0, 0 1, 0, 0 1, 0, 0 -1, 32766, -6 -1, 32766, 6 -1, 32766, 6 -1, 32766, 6 -1, 32766, 6 -1, 32766, 6 -1, 32766, 6 -1, 32766, -6 -1, 32766, 6 -1, 32766, -6 -1, 32766, -6 -1, 32766, -6 -1, 32766, 6 -1, -31165, -10117 -1, -26515, -19250 -1, -19260, -26508 -1, -10117, -31165 -1, -6, -32766 -1, 10117, -31165 -1, 19260, -26508 -1, 26515, -19250 -1, 31165, -10117 -1, 32766, 6 -1, 31161, 10129 -1, 26515, 19250 -1, 19250, 26515 -1, 10129, 31161 -1, -6, 32766 -1, -10117, 31165 -1, -19271, 26500 -1, -26515, 19250 -1, -31161, 10129 -1, -32766, 6 -1, -31161, -10129 -1, -26515, -19250 -1, -19250, -26515 -1, -10129, -31161 -1, 6, -32766 -1, 10117, -31165 -1, 19250, -26515 -1, 26500, -19271 -1, 31161, -10129 -1, 32766, -6 -1, 31165, 10117 -1, 26508, 19260 -1, 19250, 26515 -1, 10117, 31165 -1, 6, 32766 -1, -10129, 31161 -1, -19260, 26508 -1, -26508, 19260 -1, -31165, 10117 -1, -32766, 6 -1, -31161, -10129 -1, -26515, -19250 -1, -19260, -26508 -1, -10129, -31161 -1, -6, -32766 -1, 10117, -31165 -1, 19260, -26508 -1, 26515, -19250 -1, 31161, -10129 -1, 32766, -6 -1, 31165, 10117 -1, 26508, 19260 -1, 19271, 26500 -1, 10141, 31157 -1, 6, 32766 -1, -10117, 31165 -1, -19260, 26508 -1, -26515, 19250 -1, -31161, 10129 -1, -32766, -6 -1, -31161, -10129 -1, -26515, -19250 -1, -19250, -26515 -1, -10129, -31161 -1, 6, -32766 -1, 10117, -31165 -1, 19260, -26508 -1, 26500, -19271 -1, 31165, -10117 -1, 32766, -6 -1, 31165, 10117 -1, 26500, 19271 -1, 19250, 26515 -1, 10129, 31161 -1, 6, 32766 -1, -10117, 31165 -1, -19271, 26500 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, 6 -1, -31165, -10117 -1, -26508, -19260 -1, -19250, -26515 -1, -10117, -31165 -1, 6, -32766 -1, 10129, -31161 -1, 19271, -26500 -1, 26508, -19260 -1, 31165, -10117 -1, 32766, -19 -1, 31165, 10117 -1, 26508, 19260 -1, 19250, 26515 -1, 10117, 31165 -1, -6, 32766 -1, -10129, 31161 -1, -19260, 26508 -1, -26500, 19271 -1, -31161, 10129 -1, -32766, -6 -1, -31165, -10117 -1, -26500, -19271 -1, -19250, -26515 -1, -10141, -31157 -1, 6, -32766 -1, 10117, -31165 -1, 19250, -26515 -1, 26508, -19260 -1, 31165, -10117 -1, 32766, -6 -1, 31161, 10129 -1, 26515, 19250 -1, 19260, 26508 -1, 10129, 31161 -1, 6, 32766 -1, -10129, 31161 -1, -19271, 26500 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, 6 -1, -31161, -10129 -1, -26515, -19250 -1, -19260, -26508 -1, -10117, -31165 -1, 6, -32766 -1, 10129, -31161 -1, 19250, -26515 -1, 26500, -19271 -1, 31161, -10129 -1, 32766, 6 -1, 31165, 10117 -1, 26515, 19250 -1, 19250, 26515 -1, 10117, 31165 -1, -6, 32766 -1, -10141, 31157 -1, -19271, 26500 -1, -26515, 19250 -1, -31161, 10129 -1, -32766, 6 -1, -31161, -10129 -1, -26515, -19250 -1, -19250, -26515 -1, -10117, -31165 -1, 6, -32766 -1, 10117, -31165 -1, 19260, -26508 -1, 26508, -19260 -1, 31161, -10129 -1, 32766, 6 -1, 31161, 10129 -1, 26515, 19250 -1, 19260, 26508 -1, 10117, 31165 -1, 6, 32766 -1, -10129, 31161 -1, -19250, 26515 -1, -26508, 19260 -1, -31165, 10117 -1, -32766, 6 -1, -31161, -10129 -1, -26508, -19260 -1, -19260, -26508 -1, -10129, -31161 -1, -6, -32766 -1, 10129, -31161 -1, 19271, -26500 -1, 26500, -19271 -1, 31161, -10129 -1, 32766, -6 -1, 31161, 10129 -1, 26508, 19260 -1, 19271, 26500 -1, 10117, 31165 -1, 6, 32766 -1, -10129, 31161 -1, -19260, 26508 -1, -26500, 19271 -1, -31165, 10117 -1, -32766, 6 -1, -31165, -10117 -1, -26515, -19250 -1, -19260, -26508 -1, -10117, -31165 -1, 6, -32766 -1, 10129, -31161 -1, 19250, -26515 -1, 26508, -19260 -1, 31161, -10129 -1, 32766, 6 -1, 31161, 10129 -1, 26508, 19260 -1, 19260, 26508 -1, 10141, 31157 -1, -6, 32766 -1, -10129, 31161 -1, -19250, 26515 -1, -26515, 19250 -1, -31165, 10117 -1, -32766, -6 -1, -31161, -10129 -1, -26508, -19260 -1, -19250, -26515 -1, -10117, -31165 -1, -6, -32766 -1, 10129, -31161 -1, 19250, -26515 -1, 26515, -19250 -1, 31157, -10141 -1, 32766, -6 -1, 31161, 10129 -1, 26508, 19260 -1, 19271, 26500 -1, 10129, 31161 -1, 6, 32766 -1, -10129, 31161 -1, -19250, 26515 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, -6 -1, -31165, -10117 -1, -26515, -19250 -1, -19250, -26515 -1, -10129, -31161 -1, 6, -32766 -1, 10117, -31165 -1, 19271, -26500 -1, 26508, -19260 -1, 31161, -10129 -1, 32766, -6 -1, 31161, 10129 -1, 26515, 19250 -1, 19250, 26515 -1, 10129, 31161 -1, 6, 32766 -1, -10141, 31157 -1, -19271, 26500 -1, -26500, 19271 -1, -31161, 10129 -1, -32766, -6 -1, -31161, -10129 -1, -26515, -19250 -1, -19260, -26508 -1, -10129, -31161 -1, -6, -32766 -1, 10129, -31161 -1, 19250, -26515 -1, 26515, -19250 -1, 31161, -10129 -1, 32766, -6 -1, 31157, 10141 -1, 26508, 19260 -1, 19260, 26508 -1, 10117, 31165 -1, -6, 32766 -1, -10129, 31161 -1, -19260, 26508 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, 6 -1, -31165, -10117 -1, -26515, -19250 -1, -19260, -26508 -1, -10141, -31157 -1, -6, -32766 -1, 10117, -31165 -1, 19250, -26515 -1, 26515, -19250 -1, 31161, -10129 -1, 32766, 6 -1, 31165, 10117 -1, 26500, 19271 -1, 19250, 26515 -1, 10129, 31161 -1, 6, 32766 -1, -10129, 31161 -1, -19271, 26500 -1, -26500, 19271 -1, -31161, 10129 -1, -32766, -6 -1, -31157, -10141 -1, -26508, -19260 -1, -19271, -26500 -1, -10129, -31161 -1, 6, -32766 -1, 10141, -31157 -1, 19260, -26508 -1, 26515, -19250 -1, 31165, -10117 -1, 32766, 6 -1, 31161, 10129 -1, 26508, 19260 -1, 19250, 26515 -1, 10141, 31157 -1, -6, 32766 -1, -10117, 31165 -1, -19260, 26508 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, 6 -1, -31165, -10117 -1, -26515, -19250 -1, -19271, -26500 -1, -10129, -31161 -1, -6, -32766 -1, 10129, -31161 -1, 19271, -26500 -1, 26508, -19260 -1, 31157, -10141 -1, 32766, 6 -1, 31165, 10117 -1, 26508, 19260 -1, 19260, 26508 -1, 10129, 31161 -1, 6, 32766 -1, -10129, 31161 -1, -19260, 26508 -1, -26508, 19260 -1, -31161, 10129 -1, -32766, 6 -1, -31165, -10117 -1, -26515, -19250 -1, -19260, -26508 -1, -10129, -31161 -1, -6, -32766 -1, 10117, -31165 -1, 19271, -26500 -1, 26508, -19260 -1, 31161, -10129 -1, 32766, 6 -1, 31161, 10129 -1, 26500, 19271 -1, 19260, 26508 -1, 10129, 31161 -1, -6, 32766 -1, -10117, 31165 -1, -19250, 26515 -1, -26508, 19260 -1, -31165, 10117 -1, -32766, 6 -1, -31161, -10129 -1, -26508, -19260 -1, -19260, -26508 -1, -10117, -31165 -1, -6, -32766 -1, 10141, -31157 -1, 19250, -26515 -1, 26508, -19260 -1, 31161, -10129 -1, 32766, -6 -1, 31165, 10117 -1, 26508, 19260 -1, 19260, 26508 -1, 10129, 31161 -1, 6, 32766 -1, -10129, 31161 -1, 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1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 +1, 1172, 0 diff --git a/firmware/ip/axis_readout_v2/src/tb/dout_fs.csv b/firmware/ip/axis_readout_v2/src/tb/dout_fs.csv index 2ad933c12..13ac77a79 100644 --- a/firmware/ip/axis_readout_v2/src/tb/dout_fs.csv +++ b/firmware/ip/axis_readout_v2/src/tb/dout_fs.csv @@ -919,28947 +919,21363 @@ valid, idx, real, imag 1, 5, 0, 0 1, 6, 0, 0 1, 7, 0, 0 -1, 0, 32766, -6 -1, 1, 32766, -6 -1, 2, 32766, -6 -1, 3, 32766, -6 -1, 4, 32766, -6 -1, 5, 32766, -6 -1, 6, 32766, -6 -1, 7, 32766, -6 -1, 0, 32766, 6 -1, 1, 32766, 6 -1, 2, 32766, 6 -1, 3, 32766, 6 -1, 4, 32766, 6 -1, 5, 32766, 6 -1, 6, 32766, 6 -1, 7, 32766, 6 -1, 0, 32766, 6 -1, 1, 32766, 6 -1, 2, 32766, 6 -1, 3, 32766, 6 -1, 4, 32766, 6 -1, 5, 32766, 6 -1, 6, 32766, 6 -1, 7, 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a/firmware/ip/axis_readout_v2/src/tb/tb.sv b/firmware/ip/axis_readout_v2/src/tb/tb.sv index ef17adc08..55c62be45 100644 --- a/firmware/ip/axis_readout_v2/src/tb/tb.sv +++ b/firmware/ip/axis_readout_v2/src/tb/tb.sv @@ -200,7 +200,7 @@ initial begin #10; // OUTSEL : 0 (product), 1 (dds), 2 (input). - data_wr = 1; + data_wr = 2; axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); #10; @@ -223,34 +223,34 @@ initial begin #10000; - // FREQ. - data_wr = freq_calc(100, N_DDS, 17); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; + //// FREQ. + //data_wr = freq_calc(100, N_DDS, 17); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + //#10; - // WE. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; + //// WE. + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; - #100; + //#100; - // WE. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; + //// WE. + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; - #8484; + //#8484; - // FREQ. - data_wr = freq_calc(100, N_DDS, 5); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; + //// FREQ. + //data_wr = freq_calc(100, N_DDS, 5); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + //#10; - // WE. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; + //// WE. + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; #100; diff --git a/firmware/ip/axis_readout_v2/xgui/axis_readout_v2_v1_0.tcl b/firmware/ip/axis_readout_v2/xgui/axis_readout_v2_v1_0.tcl index 0db18e9a9..da416ed40 100644 --- a/firmware/ip/axis_readout_v2/xgui/axis_readout_v2_v1_0.tcl +++ b/firmware/ip/axis_readout_v2/xgui/axis_readout_v2_v1_0.tcl @@ -4,7 +4,18 @@ proc init_gui { IPINST } { #Adding Page ipgui::add_page $IPINST -name "Page 0" + set FULLSPEED_OUTPUT [ipgui::add_param $IPINST -name "FULLSPEED_OUTPUT"] + set_property tooltip {Enable additional output port for non-decimated data} ${FULLSPEED_OUTPUT} } +proc update_PARAM_VALUE.FULLSPEED_OUTPUT { PARAM_VALUE.FULLSPEED_OUTPUT } { + # Procedure called to update FULLSPEED_OUTPUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FULLSPEED_OUTPUT { PARAM_VALUE.FULLSPEED_OUTPUT } { + # Procedure called to validate FULLSPEED_OUTPUT + return true +} + diff --git a/firmware/ip/axis_readout_v3/component.xml b/firmware/ip/axis_readout_v3/component.xml new file mode 100644 index 000000000..fbfb259ae --- /dev/null +++ b/firmware/ip/axis_readout_v3/component.xml @@ -0,0 +1,615 @@ + + + QICK + QICK + axis_readout_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s0_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_readout_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 81f6c76e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_readout_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 81f6c76e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir_0/fir.coe + coe + + + src/fir_0/fir_0/fir_0.xci + xci + CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 + + + src/dds_0/dds_0/dds_0.xci + xci + CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 + + + src/latency_reg.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/down_conversion.sv + systemVerilogSource + + + src/down_conversion_fir.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_readout_v3.v + verilogSource + CHECKSUM_ff9d9536 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir.coe + coe + + + src/fir_0/fir_0/fir_0.xci + xci + CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 + + + src/dds_0/dds_0/dds_0.xci + xci + CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 + + + src/latency_reg.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/down_conversion.sv + systemVerilogSource + + + src/down_conversion_fir.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_readout_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_readout_v3_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS Readout V3 block with DDC (32-bit, phase coherent), filtering and 4x decimation, tProc controlled. + + + Component_Name + axis_readout_v3_v1_0 + + + + + + zynquplus + + + /QICK/Readout + + AXIS Readout V3 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 5 + 2025-09-11T22:22:07Z + + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + + + + 2023.1 + + + + + + + diff --git a/firmware/ip/axis_readout_v3/src/axis_readout_v3.v b/firmware/ip/axis_readout_v3/src/axis_readout_v3.v new file mode 100644 index 000000000..0f8f84a05 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/axis_readout_v3.v @@ -0,0 +1,98 @@ +module axis_readout_v3 + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // s0_axis for pushing waveforms. + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [87:0] s0_axis_tdata , + + // s1_axis for input data (4 real samples per clock). + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [4*16-1:0] s1_axis_tdata , + + // m_axis for output data (1 complex sample per clock). + input wire m_axis_tready , + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata + ); + +/********************/ +/* Internal Signals */ +/********************/ + +// Fifo. +wire fifo_wr_en ; +wire [87:0] fifo_din ; +wire fifo_rd_en ; +wire [87:0] fifo_dout ; +wire fifo_full ; +wire fifo_empty ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Fifo for queuing waveforms. +fifo + #( + // Data width. + .B (88), + + // Fifo depth. + .N (8) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +assign fifo_wr_en = s0_axis_tvalid; +assign fifo_din = s0_axis_tdata; + +// Down-conversion + Decimation FIR. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en ), + .fifo_empty (fifo_empty ), + .fifo_dout (fifo_dout ), + + // s_axis for input data (N samples per clock). + .s_axis_tready (s1_axis_tready ), + .s_axis_tvalid (s1_axis_tvalid ), + .s_axis_tdata (s1_axis_tdata ), + + // m_axis for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// Assign outputs. +assign s0_axis_tready = ~fifo_full; + +endmodule + diff --git a/firmware/ip/axis_readout_v3/src/ctrl.sv b/firmware/ip/axis_readout_v3/src/ctrl.sv new file mode 100644 index 000000000..7bc071432 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/ctrl.sv @@ -0,0 +1,377 @@ +//Format of waveform interface: +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// phrst : 1 bit +module ctrl + #( + parameter N = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // Fifo interface. + output wire fifo_rd_en , + input wire fifo_empty , + input wire [87:0] fifo_dout , + + // dds control. + output wire [N*72-1:0] dds_ctrl , + + // Output source selection. + output wire [1:0] outsel , + + // Output enable. + output wire en + ); + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [87:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [N]; +reg [31:0] phase_v0_r1 [N]; +reg [31:0] phase_v0_r2 [N]; +reg [31:0] phase_v0_r3 [N]; +reg [31:0] phase_v0_r4 [N]; +wire [31:0] phase_v1 [N]; +reg [31:0] phase_v1_r1 [N]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign phrst_int = fifo_dout_r[83]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge aclk) begin + if (~aresetn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty; + +// Assign outputs. +assign fifo_rd_en = rd_en_int; +assign outsel = outsel_r7; +assign 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+ output wire m_axis_tvalid , + output wire [N*32-1:0] m_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Input data. +reg [15:0] din_real_r1 [N] ; +wire [15:0] din_real_la [N] ; +wire [15:0] din_la_mux [N] ; + +// DDS input control. +reg dds_tvalid_r ; +wire [N*72-1:0] dds_ctrl_int ; +reg [N*72-1:0] dds_ctrl_int_r ; + +// DDS output. +wire [31:0] dds_dout [N] ; +reg [31:0] dds_dout_r1 [N] ; +wire [31:0] dds_dout_la [N] ; +wire [31:0] dds_la_mux [N] ; + +// Product. +wire signed [15:0] prod_a_real [N] ; +wire signed [15:0] prod_b_real [N] ; +wire signed [15:0] prod_b_imag [N] ; +wire signed [31:0] prod_y_real [N] ; +wire signed [31:0] prod_y_imag [N] ; +wire signed [15:0] prod_y_real_round [N] ; +wire signed [15:0] prod_y_imag_round [N] ; +wire [31:0] prod_y [N] ; +reg [31:0] prod_y_r1 [N] ; +reg [31:0] prod_y_r2 [N] ; + +// Muxed output. +wire [31:0] dout_mux [N] ; +reg [31:0] dout_mux_r1 [N] ; + +// Output source selection. +wire [1:0] outsel_int ; +wire [1:0] outsel_la ; + +// Output enable. +wire en_int ; +wire en_la ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N(N) + ) + ctrl_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en ), + .fifo_empty (fifo_empty ), + .fifo_dout (fifo_dout ), + + // dds control. + .dds_ctrl (dds_ctrl_int ), + + // Output source selection. + .outsel (outsel_int ), + + // Output enable. + .en (en_int ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd b/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir.coe b/firmware/ip/axis_readout_v3/src/fir_0/fir.coe new file mode 100644 index 000000000..26bffb37f --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -19,178,379,653,910,1053,997,719,273,-208,-558,-646,-438,-19,424,684,623,247,-287,-726,-844,-547,58,700,1059,922,301,-547,-1218,-1351,-811,213,1262,1803,1492,367,-1114,-2244,-2387,-1307,651,2636,3623,2887,414,-2944,-5678,-6144,-3225,3142,11784,20585,27137,29559,27137,20585,11784,3142,-3225,-6144,-5678,-2944,414,2887,3623,2636,651,-1307,-2387,-2244,-1114,367,1492,1803,1262,213,-811,-1351,-1218,-547,301,922,1059,700,58,-547,-844,-726,-287,247,623,684,424,-19,-438,-646,-558,-208,273,719,997,1053,910,653,379,178,-19 \ No newline at end of file diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v new file mode 100644 index 000000000..9c50b5e04 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v @@ -0,0 +1,13 @@ +module fir_0 + ( + input wire aclk , + input wire s_axis_data_tvalid , + output wire s_axis_data_tready , + input wire [127:0] s_axis_data_tdata , + output wire m_axis_data_tvalid , + output wire [31:0] m_axis_data_tdata + ); + +assign s_axis_data_tready = 1'b1; +assign m_axis_data_tvalid = 1'b1; +assign m_axis_data_tdata = s_axis_data_tdata[0 +: 16]; diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo new file mode 100644 index 000000000..00695f692 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [127 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci b/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci new file mode 100644 index 000000000..e3b5f8361 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci @@ -0,0 +1,352 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "fir_0", + "cell_name": "down_conversion_fir_i/fir_0_i/fir_0", + "component_reference": "xilinx.com:ip:fir_compiler:7.2", + "ip_revision": "19", + "gen_directory": "../../../../../projects/qick_tprocv2_216_demo/top/top.tmp/axis_readout_v3_v1_0_project/axis_readout_v3_v1_0_project.gen/sources_1/ip/fir_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "fir_0", "resolve_type": "user", "usage": "all" } ], + "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ], + "CoefficientSource": [ { "value": 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"parameters": { + "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_readout_v3/src/latency_reg.v b/firmware/ip/axis_readout_v3/src/latency_reg.v new file mode 100644 index 000000000..687a9f3fb --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i + + QICK + QICK + axis_register_slice_nb + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_register_slice_nb + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 71ea944a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_register_slice_nb + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 71ea944a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + B + B + 16 + + + N + N + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_register_slice_nb.vhd + vhdlSource + CHECKSUM_71ea944a + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_register_slice_nb.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_register_slice_nb_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Register Slice Non-Blocking. + + + B + B + 16 + + + N + N + 4 + + + Component_Name + axis_register_slice_nb_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /QICK/AXI_Peripheral + + AXIS Register Slice Non-Blocking + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + 2022-04-11T15:56:34Z + + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd b/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd new file mode 100644 index 000000000..14fdb50a2 --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity axis_register_slice_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + -- Reset and clock. + aclk : in std_logic; + aresetn : in std_logic; + + -- AXIS Slave I/F. + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + -- AXIS Master I/F. + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end axis_register_slice_nb; + +architecture rtl of axis_register_slice_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Shift registers. + shift_reg_tdata <= (others => (others => '0')); + else + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +s_axis_tready <= '1'; + +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= '1'; + +end rtl; + diff --git a/firmware/ip/axis_register_slice_nb/src/tb.vhd b/firmware/ip/axis_register_slice_nb/src/tb.vhd new file mode 100644 index 000000000..cd3763fe7 --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/src/tb.vhd @@ -0,0 +1,142 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +constant B : Integer := 8; +constant N : Integer := 3; + +-- DUT. +component axis_register_slice_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + -- Reset and clock. + aclk : in std_logic; + aresetn : in std_logic; + + -- AXIS Slave I/F. + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + -- AXIS Master I/F. + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end component; + +-- Reset and clock. +signal aclk : std_logic; +signal aresetn : std_logic; + +-- AXIS Slave I/F. +signal s_axis_tdata : std_logic_vector(B-1 downto 0); +signal s_axis_tvalid : std_logic; +signal s_axis_tready : std_logic; + +-- AXIS Master I/F. +signal m_axis_tdata : std_logic_vector(B-1 downto 0); +signal m_axis_tvalid : std_logic; +signal m_axis_tready : std_logic; + +begin + +-- DUT. +DUT: axis_register_slice_nb + Generic map + ( + -- Number of bits. + B => B , + + -- Delay. + N => N + ) + Port map + ( + -- Reset and clock. + aclk => aclk , + aresetn => aresetn , + + -- AXIS Slave I/F. + s_axis_tdata => s_axis_tdata , + s_axis_tvalid => s_axis_tvalid , + s_axis_tready => s_axis_tready , + + -- AXIS Master I/F. + m_axis_tdata => m_axis_tdata , + m_axis_tvalid => m_axis_tvalid , + m_axis_tready => m_axis_tready + ); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 300 ns; + aresetn <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(54,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); + s_axis_tvalid <= '0'; + + wait until rising_edge(aclk); + wait until rising_edge(aclk); + wait until rising_edge(aclk); + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(38,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); + s_axis_tvalid <= '1'; +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + + +end rtl; + diff --git a/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl b/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl new file mode 100644 index 000000000..1717489f3 --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_reorder_iq_v1/component.xml b/firmware/ip/axis_reorder_iq_v1/component.xml new file mode 100644 index 000000000..f01e9af70 --- /dev/null +++ b/firmware/ip/axis_reorder_iq_v1/component.xml @@ -0,0 +1,432 @@ + + + QICK + QICK + axis_reorder_iq_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_reorder_iq_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c6b7ae6a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_reorder_iq_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c6b7ae6a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 38cf361c + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + B + B + 16 + + + L + L + 4 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_reorder_iq_v1.sv + systemVerilogSource + CHECKSUM_c6b7ae6a + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_reorder_iq_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_reorder_iq_v1_v1_0.tcl + tclSource + CHECKSUM_38cf361c + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Reorder IQ, output interleaved, V1. + + + B + B + 16 + + + L + L + 4 + + + Component_Name + axis_reorder_iq_v1_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /QICK/AXI_Peripheral + + AXIS Reorder IQ V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2023-02-27T15:39:16Z + + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv b/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv new file mode 100644 index 000000000..5b9ec3595 --- /dev/null +++ b/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv @@ -0,0 +1,70 @@ +// This block reorders the data to format it for PFB. +// Input is formatted as follows: +// +// Q[L-1] ... Q[2] Q[1] Q[0] I[L-1] .. I[2] I[1] I[0] +// +// where Q[k],I[k] are B bits. Output is reordered to +// interleave the values as follows: +// +// Q[L-1] I[L-1] .. Q[2] I[2] Q[1] I[1] Q[0] I[0] +// +module axis_reorder_iq_v1 + #( + // Number of bits. + parameter B = 16 , + + // Number of lanes. + parameter L = 4 + ) + ( + // s_* and m_* reset/clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for data input. + input wire [2*B*L-1:0] s_axis_tdata , + input wire s_axis_tvalid , + output wire s_axis_tready , + + // M_AXIS for data output. + output wire [2*B*L-1:0] m_axis_tdata , + output wire m_axis_tvalid , + input wire m_axis_tready + ); + +/********************/ +/* Internal signals */ +/********************/ +// I/Q sections. +wire [B*L-1:0] data_i; +wire [B*L-1:0] data_q; + +// I/Q vectors. +wire [B-1:0] data_iv [L]; +wire [B-1:0] data_qv [L]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// I/Q sectiions. +assign data_i = s_axis_tdata[0 +: B*L]; +assign data_q = s_axis_tdata[B*L +: B*L]; + +genvar i; +generate + for (i=0; i + + QICK + QICK + axis_resampler_2x1_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_resampler_2x1_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2f191ebf + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_resampler_2x1_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 2f191ebf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + B + B + 16 + + + N + N + 8 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_resampler_2x1_v1.sv + systemVerilogSource + CHECKSUM_2f191ebf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_resampler_2x1_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_resampler_2x1_v1_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Resampler 2x1 V1 + + + B + B + 16 + + + N + N + 8 + + + Component_Name + axis_resampler_2x1_v1_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /QICK/Miscellaneous + + AXIS Resampler 2x1 V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2022-09-30T20:20:16Z + + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv b/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv new file mode 100644 index 000000000..82a6aa442 --- /dev/null +++ b/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv @@ -0,0 +1,103 @@ +// This block resamples input data to reduce the number of lanes by 2. +// It is extremely important to be sure input data is valid only +// every other clock. Faster input data rate will make the block fail. +module axis_resampler_2x1_v1 + #( + // Number of bits. + parameter B = 16 , + + // Number of lanes (input). + parameter N = 8 + ) + ( + // Reset and clock. + input wire aclk , + input wire aresetn , + + // s_axis_* for input data. + output wire s_axis_tready , + input wire s_axis_tvalid , + input wire [N*B-1:0] s_axis_tdata , + + // m_axis_* for output data. + input wire m_axis_tready , + output wire m_axis_tvalid , + output wire [N/2*B-1:0] m_axis_tdata + ); + +/*************/ +/* Internals */ +/*************/ + +// Data registers. +reg [N*B-1:0] din_r1 ; +reg [N*B-1:0] din_r2 ; + +// Low/high part. +wire [N/2*B-1:0] din_low ; +wire [N/2*B-1:0] din_high ; + +// Muxed output. +wire [N/2*B-1:0] d_mux ; +reg [N/2*B-1:0] d_mux_r1 ; + +// Valid. +reg valid_r1 ; +reg valid_r2 ; +reg valid_r3 ; +reg valid_r4 ; +wire valid_i ; + +/****************/ +/* Architecture */ +/****************/ + +// Low/high part. +assign din_low = din_r2 [0 +: N/2*B]; +assign din_high = din_r2 [N/2*B +: N/2*B]; + +// Muxed output. +assign d_mux = (valid_r2)? din_low : din_high; + +// Valid. +assign valid_i = valid_r3 || valid_r4; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // Data registers. + din_r1 <= 0; + din_r2 <= 0; + + d_mux_r1 <= 0; + + // Valid. + valid_r1 <= 0; + valid_r2 <= 0; + valid_r3 <= 0; + valid_r4 <= 0; + end + else begin + // Data registers. + din_r1 <= s_axis_tdata; + if (valid_r1) + din_r2 <= din_r1; + + // Muxed output. + d_mux_r1 <= d_mux; + + // Valid. + valid_r1 <= s_axis_tvalid; + valid_r2 <= valid_r1; + valid_r3 <= valid_r2; + valid_r4 <= valid_r3; + end +end + +// Assign outputs. +assign s_axis_tready = 1'b1 ; +assign m_axis_tvalid = valid_i ; +assign m_axis_tdata = d_mux_r1 ; + +endmodule + diff --git a/firmware/ip/axis_resampler_2x1_v1/src/tb.sv b/firmware/ip/axis_resampler_2x1_v1/src/tb.sv new file mode 100644 index 000000000..bcbbdf27f --- /dev/null +++ b/firmware/ip/axis_resampler_2x1_v1/src/tb.sv @@ -0,0 +1,84 @@ +module tb(); + +// Number of bits. +parameter B = 8; + +// Number of lanes (input). +parameter N = 4; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// s_axis_* for input data. +wire s_axis_tready ; +reg s_axis_tvalid ; +reg [N*B-1:0] s_axis_tdata ; + +// m_axis_* for output data. +reg m_axis_tready ; +wire m_axis_tvalid ; +wire [N/2*B-1:0] m_axis_tdata ; + +/**************/ +/* Test Bench */ +/**************/ + +// DUT. +axis_resampler_2x1_v1 + #( + // Number of bits. + .B(B), + + // Number of lanes (input). + .N(N) + ) + DUT + ( + // Reset and clock. + .aclk , + .aresetn , + + // s_axis_* for input data. + .s_axis_tready , + .s_axis_tvalid , + .s_axis_tdata , + + // m_axis_* for output data. + .m_axis_tready , + .m_axis_tvalid , + .m_axis_tdata + ); + +initial begin + // Reset sequence. + aresetn <= 0; + s_axis_tvalid <= 0; + m_axis_tready <= 1; + #500; + aresetn <= 1; + + #1000; + + for (int i=0; i<200; i=i+1) begin + @(posedge aclk); + s_axis_tvalid <= 0; + @(posedge aclk); + @(posedge aclk); + @(posedge aclk); + s_axis_tvalid <= 1; + for (int j=0; j - user.org - user + QICK + QICK axis_set_reg 1.0 @@ -150,6 +150,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -318,6 +332,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS Set Register Block. @@ -358,10 +379,12 @@ kintexu - /UserIP + /QICK/AXI_Peripheral AXIS Set Register package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ 3 2020-12-15T18:32:58Z diff --git a/firmware/ip/axis_sg_int4_v1/component.xml b/firmware/ip/axis_sg_int4_v1/component.xml new file mode 100644 index 000000000..f3de71b99 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/component.xml @@ -0,0 +1,1328 @@ + + + QICK + QICK + axis_sg_int4_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_int4_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 95568600 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_int4_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 95568600 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9465d594 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 87 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 12 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i/fir_0 + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v1.v + verilogSource + CHECKSUM_c287fed2 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i/fir_0 + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_int4_v1_v1_0.tcl + tclSource + CHECKSUM_9465d594 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Signal Generator with x4 Interpolated Envelope + + + N + N + 12 + + + Component_Name + axis_sg_int4_v1_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG x4 Interpolation + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 6 + 2022-04-07T20:07:10Z + + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + 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/home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..7be1f507d --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + + m_axi_wdata + + + + + WID + + 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out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arlock + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arregion + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd b/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd new file mode 100644 index 000000000..c60ea98f2 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v b/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v new file mode 100644 index 000000000..f913b85c6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v @@ -0,0 +1,197 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_sg_int4_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +localparam [31:0] N_DDS = 4; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [87:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [4*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/bram.v b/firmware/ip/axis_sg_int4_v1/src/bram.v new file mode 100644 index 000000000..018317e0f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/ctrl.sv b/firmware/ip/axis_sg_int4_v1/src/ctrl.sv new file mode 100644 index 000000000..0cfd01a65 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/ctrl.sv @@ -0,0 +1,499 @@ +//Format of waveform interface: +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 48 | 47 .. 32 | 31 .. 16 | 15 .. 0 | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | phrst | stdysel | mode | outsel | nsamp | gain | addr | phase | freq | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// freq : 16 bits +// phase : 16 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +// +// Total : 85. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [84:0] fifo_dout_i; +output [N_DDS*40-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [84:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [15:0] cnt_n; +reg [15:0] cnt_n_reg; + +// Pinc/phase. +wire [15:0] pinc_int; +reg [15:0] pinc_r1; +reg [15:0] pinc_r2; +wire [15:0] pinc_N; +reg [15:0] pinc_N_r1; +reg [15:0] pinc_N_r2; +reg [15:0] pinc_N_r3; +reg [15:0] pinc_N_r4; +reg [15:0] pinc_N_r5; +wire [15:0] pinc_Nm; +reg [15:0] pinc_Nm_r1; +reg [15:0] pinc_Nm_r2; +reg [15:0] pinc_Nm_r3; + +wire [15:0] phase_int; +reg [15:0] phase_r1; +reg [15:0] phase_r2; +reg [15:0] phase_r3; +reg [15:0] phase_r4; +reg [15:0] phase_r5; +wire [15:0] phase_0; +reg [15:0] phase_0_r1; + +// Phase vectors. +wire [15:0] phase_v0 [0:N_DDS-1]; +reg [15:0] phase_v0_r1 [0:N_DDS-1]; +reg [15:0] phase_v0_r2 [0:N_DDS-1]; +reg [15:0] phase_v0_r3 [0:N_DDS-1]; +reg [15:0] phase_v0_r4 [0:N_DDS-1]; +wire [15:0] phase_v1 [0:N_DDS-1]; +reg [15:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[15:0]; +assign phase_int = fifo_dout_r[31:16]; +assign addr_int = fifo_dout_r[47:32]; +assign gain_int = fifo_dout_r[63:48]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign stdysel_int = fifo_dout_r[83]; +assign phrst_int = fifo_dout_r[84]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*40 +: 40] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd b/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd new file mode 100644 index 000000000..8fa76e3ec --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Memory size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory address space. +signal mem_addr_full : unsigned (N-1 downto 0); +signal mem_addr_full_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_full_r <= (others => '0'); + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_full_r <= mem_addr_full; + + end if; + end if; +end process; + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= '1'; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_full_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..c3dea2989 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..4db3fc682 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..562a7638f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 5 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 40 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 3906.25 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 000000000..251c3925f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,3237 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + + + + + INTERRUPT + + + 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xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + dds_compiler_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + dds_compiler_v6_0_20 + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:4d9beb0f + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + dds_compiler_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:4d9beb0f + + + + + xilinx_cmodelsimulation + C Simulation + cSource:vivado.xilinx.com:simulation.cmodel + c + + xilinx_cmodelsimulation_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_vhdltestbench + VHDL Test Bench + vhdlSource:vivado.xilinx.com:simulation.testbench + vhdl + testbench + + xilinx_vhdltestbench_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Thu Feb 10 21:24:16 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Thu Feb 10 21:25:49 UTC 2022 + + + outputProductCRC + 9:5ef6fa43 + + + + + + + aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + aclken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + s_axis_phase_tvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axis_phase_tready + + out + + + std_logic + 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C_HAS_M_PHASE + 0 + + + C_M_PHASE_TDATA_WIDTH + 1 + + + C_M_PHASE_HAS_TUSER + 0 + + + C_M_PHASE_TUSER_WIDTH + 1 + + + C_DEBUG_INTERFACE + 0 + + + C_CHAN_WIDTH + 1 + + + + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_230272f2 + None + Fixed + Programmable + Streaming + + + choice_list_45db86b7 + Auto + Configurable + + + choice_list_4721e082 + Minimal + Maximal + + + choice_list_950bd3bd + Auto + Area + Speed + + + choice_list_ba6ede68 + Standard + Rasterized + + + choice_list_cd7e1d82 + Coregen + Sysgen + + + choice_list_de3e80a0 + Fixed + Programmable + Streaming + + + choice_list_faa329ca + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + + + choice_pairs_0079eeec + Twos_Complement + Sign_and_Magnitude + + + choice_pairs_27d1d409 + Auto + Distributed_ROM + Block_ROM + + + choice_pairs_65a5252d + Full_Range + Unit_Circle + + + choice_pairs_6bdc34ae + System_Parameters + Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + dds_compiler_v6_0_20 + + + + xilinx_synthesisconstraints_view_fileset + + dds_compiler_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe new file mode 100644 index 000000000..fd9c44577 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 0.004708,0.005461,0.000000,-0.013987,-0.029332,-0.030123,0.000000,0.065216,0.149630,0.221652,0.250000,0.221652,0.149630,0.065216,0.000000,-0.030123,-0.029332,-0.013987,0.000000,0.005461,0.004708 \ No newline at end of file diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo new file mode 100644 index 000000000..44cd8475f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [127 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho new file mode 100644 index 000000000..be451e165 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_0 + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_0.vhd when simulating +-- the core, fir_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci new file mode 100644 index 000000000..e6289ddc3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci @@ -0,0 +1,321 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 16 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31,31,31,31,31,31,31 + 31,31,31,31,31,31,31,31 + fixed + fir_0.mif + 24 + 2 + 0 + 0,0,0,0,0,0,0,0 + 0,0,2,2,4,4,6,6 + 16,16,16,16,16,16,16,16 + 0 + 16 + 6 + 1 + 4 + fir_0 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + -0;-1;-0;-1;-0;-1;-0;-1 + 0,0,0,0,0,0,0,0 + 0,1,0,1,0,1,0,1 + 16,16,16,16,16,16,16,16 + 16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 12 + 2 + 0 + 0 + 128 + 1 + 1 + 1 + 6 + 1 + 21 + 0 + 0 + none;none;none;none + -0;-1;-0;-1;-0;-1;-0;-1 + 16,16,16,16,16,16,16,16 + 1 + 16 + 1 + 0,1,2,3,4,5,6,7 + 1 + 3 + 0 + 0 + 0 + 32 + 1 + zynquplus + 1 + true + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + fir_0.coe + 16 + false + 1 + Signed + Inferred + 16 + 6 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 4 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Infinity + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Quantize_Only + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml new file mode 100644 index 000000000..57879e21d --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml @@ -0,0 +1,2875 @@ + + + xilinx.com + customized_ip + fir_0 + 1.0 + + + event_s_data_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_data_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + S_AXIS_RELOAD + S_AXIS_RELOAD + + + + + + + TDATA + + + s_axis_reload_tdata + + + + + TLAST + + + s_axis_reload_tlast + + + + + TREADY + + + s_axis_reload_tready + + + + + TVALID + + + s_axis_reload_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + aclk_intf + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD + + + ASSOCIATED_RESET + aresetn + + + ASSOCIATED_CLKEN + aclken + + + FREQ_HZ + aclk + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aresetn_intf + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aclken_intf + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_HIGH + + + + + S_AXIS_DATA + S_AXIS_DATA + + + + + + + TDATA + + + s_axis_data_tdata + + + + + TLAST + + + s_axis_data_tlast + + + + + TREADY + + + s_axis_data_tready + + + + + TUSER + + + s_axis_data_tuser + + + + + TVALID + + + s_axis_data_tvalid + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M_AXIS_DATA + M_AXIS_DATA + + + + + + + TDATA + + + m_axis_data_tdata + + + + + TLAST + + + m_axis_data_tlast + + + + + TREADY + + + m_axis_data_tready + + + + + TUSER + + + m_axis_data_tuser + + + + + TVALID + + + m_axis_data_tvalid + + + + + + TDATA_NUM_BYTES + 16 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS_CONFIG + S_AXIS_CONFIG + + + + + + + TDATA + + + s_axis_config_tdata + + + + + TLAST + + + s_axis_config_tlast + + + + + TREADY + + + s_axis_config_tready + + + + + TVALID + + + s_axis_config_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:39 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + fir_compiler_v7_2_15 + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:39 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:39 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + fir_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:39 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_cmodelsimulation + C Simulation + cSource:vivado.xilinx.com:simulation.cmodel + c + + xilinx_cmodelsimulation_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:39 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_vhdltestbench + VHDL Test Bench + vhdlSource:vivado.xilinx.com:simulation.testbench + vhdl + testbench + + xilinx_vhdltestbench_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:40 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_project_archive + Miscellaneous + :vivado.xilinx.com:misc.files + + + outputProductCRC + 9:ab919098 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Wed Feb 02 16:51:40 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed Feb 02 16:53:29 UTC 2022 + + + outputProductCRC + 9:ab919098 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + fir_compiler_v7_2_15 + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Thu Feb 10 19:39:33 UTC 2022 + + + outputProductCRC + 9:9729a5c6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + fir_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Thu Feb 10 19:39:33 UTC 2022 + + + outputProductCRC + 9:9729a5c6 + + + + + + + aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + aclken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + s_axis_data_tvalid + + in + + + std_logic + xilinx_vhdlsynthesis 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C_COEF_RELOAD + 0 + + + C_NUM_RELOAD_SLOTS + 1 + + + C_COL_MODE + 1 + + + C_COL_PIPE_LEN + 4 + + + C_COL_CONFIG + 6 + + + C_OPTIMIZATION + 0 + + + C_DATA_PATH_WIDTHS + 16,16,16,16,16,16,16,16 + + + C_DATA_IP_PATH_WIDTHS + 16,16 + + + C_DATA_PX_PATH_WIDTHS + 16,16 + + + C_DATA_WIDTH + 16 + + + C_COEF_PATH_WIDTHS + 16,16,16,16,16,16,16,16 + + + C_COEF_WIDTH + 16 + + + C_DATA_PATH_SRC + 0,1,0,1,0,1,0,1 + + + C_COEF_PATH_SRC + 0,0,2,2,4,4,6,6 + + + C_PX_PATH_SRC + 0,1,2,3,4,5,6,7 + + + C_DATA_PATH_SIGN + 0,0,0,0,0,0,0,0 + + + C_COEF_PATH_SIGN + 0,0,0,0,0,0,0,0 + + + C_ACCUM_PATH_WIDTHS + 31,31,31,31,31,31,31,31 + + + C_OUTPUT_WIDTH + 16 + + + C_OUTPUT_PATH_WIDTHS + 16,16,16,16,16,16,16,16 + + + C_ACCUM_OP_PATH_WIDTHS + 31,31,31,31,31,31,31,31 + + + C_EXT_MULT_CNFG + none + + + C_DATA_PATH_PSAMP_SRC + -0;-1;-0;-1;-0;-1;-0;-1 + + + C_OP_PATH_PSAMP_SRC + -0;-1;-0;-1;-0;-1;-0;-1 + + + C_NUM_MADDS + 6 + + + C_OPT_MADDS + none;none;none;none + + + C_OVERSAMPLING_RATE + 1 + + + C_INPUT_RATE + 1 + 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+ Area + Speed + Custom + + + choice_list_dd381b21 + Automatic + Block + Distributed + + + choice_pairs_18e22ec6 + Full_Precision + Truncate_LSBs + Non_Symmetric_Rounding_Down + Non_Symmetric_Rounding_Up + Symmetric_Rounding_to_Zero + Symmetric_Rounding_to_Infinity + Convergent_Rounding_to_Even + Convergent_Rounding_to_Odd + + + choice_pairs_2074757d + None + All + Data_Path_Fanout + Pre-Adder_Pipeline + Coefficient_Fanout + Control_Path_Fanout + Control_Column_Fanout + Control_Broadcast_Fanout + Control_LUT_Pipeline + No_BRAM_Read_First_Mode + Optimal_Column_Lengths + Data_Path_Broadcast + Disable_Half_Band_Centre_Tap + No_SRL_Attributes + Other + + + choice_pairs_2b265cc8 + Frequency_Specification + Input_Sample_Period + Output_Sample_Period + + + choice_pairs_33abc840 + Quantize_Only + Maximize_Dynamic_Range + Normalize_to_Centre_Coefficient + + + choice_pairs_3ab545a3 + Not_Required + Chan_ID_Field + + + choice_pairs_433eb1cb + Inferred + Non_Symmetric + + + choice_pairs_480f8ce0 + Not_Required + Packet_Framing + + + choice_pairs_74144f21 + COE_File + Vector + + + choice_pairs_789dfe7d + Single_Rate + Interpolation + Decimation + Hilbert + Interpolated + + + choice_pairs_8e2d2e35 + Not_Required + User_Field + + + choice_pairs_ab4ea833 + Systolic_Multiply_Accumulate + + + choice_pairs_b6c64168 + Single + By_Channel + + + choice_pairs_eb2746f0 + Integer + Fixed_Fractional + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + fir_0.vho + vhdlTemplate + + + fir_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + fir_compiler_v7_2_15 + + + + xilinx_synthesisconstraints_view_fileset + + fir_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/fir_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/fir_0.h + cSource + + + cmodel/tb_fir_0.c + cSource + + + cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip + zip + + + cmodel/fir_compiler_v7_2_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_fir_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/fir_compiler_v7_2_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + fir_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + fir_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + fir_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + fir_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + fir_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + fir_compiler_v7_2_15 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/fir_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + fir_0.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Interpolation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 4 + + + Decimation_Rate + 1 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Input_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Quantize_Only + + + Coefficient_Width + 16 + + + BestPrecision + true + + + Coefficient_Fractional_Bits + 16 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Infinity + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 6 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/latency_reg.v b/firmware/ip/axis_sg_int4_v1/src/latency_reg.v new file mode 100644 index 000000000..687a9f3fb --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py b/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py new file mode 100755 index 000000000..ea72942bf --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py @@ -0,0 +1,18 @@ +import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=32000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yi = gauss(mu=300, si=120, length=600) +yq = np.zeros(len(yi)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + diff --git a/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv b/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv new file mode 100644 index 000000000..5f4db0f02 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv @@ -0,0 +1,495 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// Dummy clock for debugging. +reg aclk4; + +// s1_axis interfase. +reg [87:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [15:0] freq_r; +reg [15:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; +reg [31:0] dout_f; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_int4_v1 + # + ( + .N(N) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,gain_r,addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // Load Table. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load data into memroy. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../tb/gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + +end + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + + /************/ + /* Flat Top */ + /************/ + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 15); + addr_r <= 0; + gain_r <= 22000; + nsamp_r <= 300; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + addr_r <= 300; + gain_r <= 11000; + nsamp_r <= 200; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 1; // 0: nsamp, 1: periodic + + @(posedge aclk); + s1_axis_tvalid <= 0; + + #15000; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + addr_r <= 300; + gain_r <= 22000; + nsamp_r <= 300; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 1; + + /*****************/ + /* Latency Check */ + /*****************/ + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 19); + //phase_r <= 100; + //addr_r <= 10; + //gain_r <= 30000; + //nsamp_r <= 17; + //outsel_r <= 0; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 1); + //phase_r <= 245; + //addr_r <= 300; + //gain_r <= 30000; + //nsamp_r <= 5; + //outsel_r <= 0; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 22); + //phase_r <= 7689; + //addr_r <= 0; + //gain_r <= 30000; + //nsamp_r <= 70/N_DDS; + //outsel_r <= 2; // 0: prod, 1: dds, 2: mem + //mode_r <= 1; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_sg_int4_v2 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + 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+ + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_int4_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 70772e45 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_int4_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 70772e45 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9465d594 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 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xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 159 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 12 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v2.v + verilogSource + CHECKSUM_fcc81491 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v2.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_int4_v2_v1_0.tcl + tclSource + CHECKSUM_9465d594 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS Signal Generator with x4 Interpolated Envelope, 32-bit phase+frequency + + + N + N + 12 + + + Component_Name + axis_sg_int4_v2_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG x4 Interpolation, V2 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 10 + 2025-09-11T22:17:54Z + + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd b/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd new file mode 100644 index 000000000..c60ea98f2 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v b/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v new file mode 100644 index 000000000..fa1ffc34d --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v @@ -0,0 +1,197 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_sg_int4_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +localparam [31:0] N_DDS = 4; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [4*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/bram.v b/firmware/ip/axis_sg_int4_v2/src/bram.v new file mode 100644 index 000000000..018317e0f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/ctrl.sv b/firmware/ip/axis_sg_int4_v2/src/ctrl.sv new file mode 100644 index 000000000..76767e5a9 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/ctrl.sv @@ -0,0 +1,497 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; +assign phrst_int = fifo_dout_r[148]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd b/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd new file mode 100644 index 000000000..8fa76e3ec --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Memory size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory address space. +signal mem_addr_full : unsigned (N-1 downto 0); +signal mem_addr_full_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_full_r <= (others => '0'); + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_full_r <= mem_addr_full; + + end if; + end if; +end process; + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= '1'; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_full_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..24559beb4 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,358 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "dds_compiler_0", + "cell_name": "signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i", + "component_reference": "xilinx.com:ip:dds_compiler:6.0", + "ip_revision": "22", + "gen_directory": "../../../../projects/qick_tprocv2_216_demo/top/top.tmp/axis_sg_int4_v2_v1_0_project/axis_sg_int4_v2_v1_0_project.gen/sources_1/ip/dds_compiler_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "dds_compiler_0", "resolve_type": "user", "usage": "all" } ], + "PartsPresent": [ { "value": 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true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer 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data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl b/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl new file mode 100644 index 000000000..96e9e447a --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_sg_mixmux8_v1/component.xml b/firmware/ip/axis_sg_mixmux8_v1/component.xml new file mode 100644 index 000000000..325b24c47 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/component.xml @@ -0,0 +1,1094 @@ + + + QICK + QICK + axis_sg_mixmux8_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mixmux8_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 3c107a09 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mixmux8_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 3c107a09 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 4813f2bb + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mixmux8_v1.v + verilogSource + CHECKSUM_fbb8f9e5 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mixmux8_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mixmux8_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS SG Mux8, IQ Output, V1. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mixmux8_v1_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG Mixer-Mux8, V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 6 + 2025-09-11T21:57:07Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v b/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v new file mode 100644 index 000000000..a7089bb72 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v @@ -0,0 +1,1072 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [31:0] PINC0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] POFF7_REG , + output wire [31:0] GAIN0_REG , + output wire [31:0] GAIN1_REG , + output wire [31:0] GAIN2_REG , + output wire [31:0] GAIN3_REG , + output wire [31:0] GAIN4_REG , + output wire [31:0] GAIN5_REG , + output wire [31:0] GAIN6_REG , + output wire [31:0] GAIN7_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign PINC0_REG = slv_reg0 ; +assign PINC1_REG = slv_reg1 ; +assign PINC2_REG = slv_reg2 ; +assign PINC3_REG = slv_reg3 ; +assign PINC4_REG = slv_reg4 ; +assign PINC5_REG = slv_reg5 ; +assign PINC6_REG = slv_reg6 ; +assign PINC7_REG = slv_reg7 ; +assign POFF0_REG = slv_reg8 ; +assign POFF1_REG = slv_reg9 ; +assign POFF2_REG = slv_reg10 ; +assign POFF3_REG = slv_reg11 ; +assign POFF4_REG = slv_reg12 ; +assign POFF5_REG = slv_reg13 ; +assign POFF6_REG = slv_reg14 ; +assign POFF7_REG = slv_reg15 ; +assign GAIN0_REG = slv_reg16 ; +assign GAIN1_REG = slv_reg17 ; +assign GAIN2_REG = slv_reg18 ; +assign GAIN3_REG = slv_reg19 ; +assign GAIN4_REG = slv_reg20 ; +assign GAIN5_REG = slv_reg21 ; +assign GAIN6_REG = slv_reg22 ; +assign GAIN7_REG = slv_reg23 ; +assign WE_REG = slv_reg24[0] ; + +endmodule diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v b/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v new file mode 100644 index 000000000..94bb1a876 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v @@ -0,0 +1,238 @@ +module axis_sg_mixmux8_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [7:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [7:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [31:0] PINC4_REG; +wire [31:0] PINC5_REG; +wire [31:0] PINC6_REG; +wire [31:0] PINC7_REG; +wire [31:0] POFF0_REG; +wire [31:0] POFF1_REG; +wire [31:0] POFF2_REG; +wire [31:0] POFF3_REG; +wire [31:0] POFF4_REG; +wire [31:0] POFF5_REG; +wire [31:0] POFF6_REG; +wire [31:0] POFF7_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire [15:0] GAIN4_REG; +wire [15:0] GAIN5_REG; +wire [15:0] GAIN6_REG; +wire [15:0] GAIN7_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux8 + #( + .N_DDS (N_DDS ) + ) + sg_mux8_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv b/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv new file mode 100644 index 000000000..e4d78b03e --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv @@ -0,0 +1,183 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT0_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT0_ST; + + CNT0_ST: + state <= CNT_ST; + + CNT_ST: + if ( cnt == nsamp_int ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT0_ST: + rd_en_int = 0; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mixmux8_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 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[N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [15:0] prod_a_imag [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +wire signed [31:0] prod_imag [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +reg [31:0] prod_imag_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod_imag_q [0:N_DDS-1]; +wire [31:0] prod [0:N_DDS-1]; +reg [31:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v b/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v new file mode 100644 index 000000000..4150ef68a --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv b/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv new file mode 100644 index 000000000..8ee720c7a --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv @@ -0,0 +1,359 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [32:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mixmux8_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // Register mapping: + // 0-7 : PINC. + // 8-15 : POFF. + // 16-23: GAIN. + // 24 : WE. + + for (int i=0; i<8; i=i+1) begin + // PINCx_REG + data_wr = freq_calc(100, N_DDS, 10+i); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*i, prot, data_wr, resp); + + // POFFx_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+8), prot, data_wr, resp); + + // GAINx_REG + data_wr = 20000+1000*i; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+16), prot, data_wr, resp); + + end + + //// PINC0/1/2. + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + + //// POFF0/1/2. + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+8), prot, data_wr, resp); + + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+8), prot, data_wr, resp); + + //data_wr = phase_calc(180); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+8), prot, data_wr, resp); + + //// GAIN0/1/2. + //data_wr = 30000; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+16), prot, data_wr, resp); + + //// 0 gain just for quantization... + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(7+16), prot, 0, resp); + + // WE. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 1, resp); + #10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 0, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #50000; + #50000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 550; + //mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 3500; + mask_r <= 8'b1111_1111; + + // Phase-coherency test. + // 1 sine wave first. + // 2 sine waves, same phase, same frequency. + // 2 sine waves, 180 out of phase, same frequency. + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b1000_0001; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0011; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0101; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_sg_mux4_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8e4f9196 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8e4f9196 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + CHECKSUM_d597a72a + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Signal Generator with 4 muxed outputs. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v1_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG mux 4 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2022-02-22T20:24:54Z + + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..f5a8b151f --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 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xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd new file mode 100644 index 000000000..bcce17082 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd @@ -0,0 +1,525 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (15 downto 0); + PINC1_REG : out std_logic_vector (15 downto 0); + PINC2_REG : out std_logic_vector (15 downto 0); + PINC3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 16-bit. Frequency of output 0. + -- 1 : PINC1_REG : 16-bit. Frequency of output 1. + -- 2 : PINC2_REG : 16-bit. Frequency of output 2. + -- 3 : PINC3_REG : 16-bit. Frequency of output 3. + -- 4 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(15 downto 0); + PINC1_REG <= slv_reg1(15 downto 0); + PINC2_REG <= slv_reg2(15 downto 0); + PINC3_REG <= slv_reg3(15 downto 0); + WE_REG <= slv_reg4(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v b/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v new file mode 100644 index 000000000..5b555524d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v @@ -0,0 +1,182 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] PINC0_REG; +wire [15:0] PINC1_REG; +wire [15:0] PINC2_REG; +wire [15:0] PINC3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv new file mode 100644 index 000000000..e1ccea93d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..c3dea2989 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..4db3fc682 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..274be99b6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 5 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 40 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 3906.25 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../test_axis_sg_int4_v1/top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 000000000..251c3925f --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,3237 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + 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Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + dds_compiler_v6_0_20 + + + + xilinx_synthesisconstraints_view_fileset + + dds_compiler_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_top.v b/firmware/ip/axis_sg_mux4_v1/src/dds_top.v new file mode 100644 index 000000000..587b63d28 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_top.v @@ -0,0 +1,120 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*32-1:0] dds_dout_o; + +input [15:0] PINC_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*40-1:0] dds_ctrl_int; +reg [N_DDS*40-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v new file mode 100644 index 000000000..687a9f3fb --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv b/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv new file mode 100644 index 000000000..1a8273e25 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv @@ -0,0 +1,3685 @@ +valid, idx, real, imag +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 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axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 2; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_sg_mux4_v2 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5ea64aa6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5ea64aa6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + CHECKSUM_0b7ef357 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v2_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Signal Generator with 4 muxed outputs, 32-bit DDS and individual Gain. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v1_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG mux 4 V2 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + 2022-05-12T19:42:38Z + + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..c2c515642 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + 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axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd new file mode 100644 index 000000000..c92dcb176 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd @@ -0,0 +1,537 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + GAIN0_REG : out std_logic_vector (15 downto 0); + GAIN1_REG : out std_logic_vector (15 downto 0); + GAIN2_REG : out std_logic_vector (15 downto 0); + GAIN3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 32-bit. Frequency of output 0. + -- 1 : PINC1_REG : 32-bit. Frequency of output 1. + -- 2 : PINC2_REG : 32-bit. Frequency of output 2. + -- 3 : PINC3_REG : 32-bit. Frequency of output 3. + -- 4 : GAIN0_REG : 16-bit. Frequency of output 0. + -- 5 : GAIN1_REG : 16-bit. Frequency of output 1. + -- 6 : GAIN2_REG : 16-bit. Frequency of output 2. + -- 7 : GAIN3_REG : 16-bit. Frequency of output 3. + -- 8 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(31 downto 0); + PINC1_REG <= slv_reg1(31 downto 0); + PINC2_REG <= slv_reg2(31 downto 0); + PINC3_REG <= slv_reg3(31 downto 0); + GAIN0_REG <= slv_reg4(15 downto 0); + GAIN1_REG <= slv_reg5(15 downto 0); + GAIN2_REG <= slv_reg6(15 downto 0); + GAIN3_REG <= slv_reg7(15 downto 0); + WE_REG <= slv_reg8(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v b/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v new file mode 100644 index 000000000..b28a74845 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v @@ -0,0 +1,194 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv new file mode 100644 index 000000000..e1ccea93d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..c3dea2989 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..4db3fc682 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..6ae4d1670 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.08 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../test_axis_sg_int4_v1/top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 000000000..251c3925f --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,3237 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + 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xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_top.v b/firmware/ip/axis_sg_mux4_v2/src/dds_top.v new file mode 100644 index 000000000..c940d2623 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_top.v @@ -0,0 +1,163 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*32-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [15:0] prod_a_imag [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +wire signed [31:0] prod_imag [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +reg [31:0] prod_imag_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod_imag_q [0:N_DDS-1]; +wire [31:0] prod [0:N_DDS-1]; +reg [31:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v new file mode 100644 index 000000000..687a9f3fb --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv b/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv new file mode 100644 index 000000000..5dce62b29 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv @@ -0,0 +1,340 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 2; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // GAIN0_REG + data_wr = 32000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // GAIN1_REG + data_wr = 25000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + #10; + + // GAIN2_REG + data_wr = 10000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*6, prot, data_wr, resp); + #10; + + // GAIN3_REG + data_wr = 1000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*7, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_sg_mux4_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + a303c385 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a303c385 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4_v3.v + verilogSource + CHECKSUM_e34aa402 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v3_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS SG Mux4, Real Output, V3. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v3_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG Mux4, V3 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + 2024-01-25T16:25:58Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix b/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix new file mode 100644 index 000000000..212338d3a Binary files /dev/null and b/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix differ diff --git a/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd new file mode 100644 index 000000000..c92dcb176 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd @@ -0,0 +1,537 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + GAIN0_REG : out std_logic_vector (15 downto 0); + GAIN1_REG : out std_logic_vector (15 downto 0); + GAIN2_REG : out std_logic_vector (15 downto 0); + GAIN3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 32-bit. Frequency of output 0. + -- 1 : PINC1_REG : 32-bit. Frequency of output 1. + -- 2 : PINC2_REG : 32-bit. Frequency of output 2. + -- 3 : PINC3_REG : 32-bit. Frequency of output 3. + -- 4 : GAIN0_REG : 16-bit. Frequency of output 0. + -- 5 : GAIN1_REG : 16-bit. Frequency of output 1. + -- 6 : GAIN2_REG : 16-bit. Frequency of output 2. + -- 7 : GAIN3_REG : 16-bit. Frequency of output 3. + -- 8 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(31 downto 0); + PINC1_REG <= slv_reg1(31 downto 0); + PINC2_REG <= slv_reg2(31 downto 0); + PINC3_REG <= slv_reg3(31 downto 0); + GAIN0_REG <= slv_reg4(15 downto 0); + GAIN1_REG <= slv_reg5(15 downto 0); + GAIN2_REG <= slv_reg6(15 downto 0); + GAIN3_REG <= slv_reg7(15 downto 0); + WE_REG <= slv_reg8(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v b/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v new file mode 100644 index 000000000..c537317bd --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v @@ -0,0 +1,194 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v3 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv new file mode 100644 index 000000000..e1ccea93d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..3d3cffbbd --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,477 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 2 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 16 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.08 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../project_1/project_1.gen/sources_1/ip/dds_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v3/src/dds_top.v b/firmware/ip/axis_sg_mux4_v3/src/dds_top.v new file mode 100644 index 000000000..635b09b1a --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/dds_top.v @@ -0,0 +1,138 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*16-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [15:0] dds_dout [0:N_DDS-1]; +wire [15:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod [0:N_DDS-1]; +reg [15:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v new file mode 100644 index 000000000..4150ef68a --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv b/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv new file mode 100644 index 000000000..f729a46fe --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv @@ -0,0 +1,339 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v3 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // GAIN0_REG + data_wr = 32000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // GAIN1_REG + data_wr = 25000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + #10; + + // GAIN2_REG + data_wr = 10000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*6, prot, data_wr, resp); + #10; + + // GAIN3_REG + data_wr = 1000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*7, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_sg_mux8_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux8_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f849e027 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux8_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f849e027 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux8_v1.v + verilogSource + CHECKSUM_93286a60 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux8_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux8_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS SG Mux8, Real Output, V1. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux8_v1_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS SG Mux8, V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 2 + 2025-09-11T21:44:12Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix b/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix new file mode 100644 index 000000000..f737726e6 Binary files /dev/null and b/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix differ diff --git a/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v b/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v new file mode 100644 index 000000000..a7089bb72 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v @@ -0,0 +1,1072 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [31:0] PINC0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] POFF7_REG , + output wire [31:0] GAIN0_REG , + output wire [31:0] GAIN1_REG , + output wire [31:0] GAIN2_REG , + output wire [31:0] GAIN3_REG , + output wire [31:0] GAIN4_REG , + output wire [31:0] GAIN5_REG , + output wire [31:0] GAIN6_REG , + output wire [31:0] GAIN7_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign PINC0_REG = slv_reg0 ; +assign PINC1_REG = slv_reg1 ; +assign PINC2_REG = slv_reg2 ; +assign PINC3_REG = slv_reg3 ; +assign PINC4_REG = slv_reg4 ; +assign PINC5_REG = slv_reg5 ; +assign PINC6_REG = slv_reg6 ; +assign PINC7_REG = slv_reg7 ; +assign POFF0_REG = slv_reg8 ; +assign POFF1_REG = slv_reg9 ; +assign POFF2_REG = slv_reg10 ; +assign POFF3_REG = slv_reg11 ; +assign POFF4_REG = slv_reg12 ; +assign POFF5_REG = slv_reg13 ; +assign POFF6_REG = slv_reg14 ; +assign POFF7_REG = slv_reg15 ; +assign GAIN0_REG = slv_reg16 ; +assign GAIN1_REG = slv_reg17 ; +assign GAIN2_REG = slv_reg18 ; +assign GAIN3_REG = slv_reg19 ; +assign GAIN4_REG = slv_reg20 ; +assign GAIN5_REG = slv_reg21 ; +assign GAIN6_REG = slv_reg22 ; +assign GAIN7_REG = slv_reg23 ; +assign WE_REG = slv_reg24[0] ; + +endmodule diff --git a/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v b/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v new file mode 100644 index 000000000..c5ff09ed4 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v @@ -0,0 +1,238 @@ +module axis_sg_mux8_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [7:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [7:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [31:0] PINC4_REG; +wire [31:0] PINC5_REG; +wire [31:0] PINC6_REG; +wire [31:0] PINC7_REG; +wire [31:0] POFF0_REG; +wire [31:0] POFF1_REG; +wire [31:0] POFF2_REG; +wire [31:0] POFF3_REG; +wire [31:0] POFF4_REG; +wire [31:0] POFF5_REG; +wire [31:0] POFF6_REG; +wire [31:0] POFF7_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire [15:0] GAIN4_REG; +wire [15:0] GAIN5_REG; +wire [15:0] GAIN6_REG; +wire [15:0] GAIN7_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux8 + #( + .N_DDS (N_DDS ) + ) + sg_mux8_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv b/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv new file mode 100644 index 000000000..e4d78b03e --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv @@ -0,0 +1,183 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT0_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT0_ST; + + CNT0_ST: + state <= CNT_ST; + + CNT_ST: + if ( cnt == nsamp_int ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT0_ST: + rd_en_int = 0; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux8_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux8_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..de507f8f0 --- /dev/null +++ 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} + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_sg_mux8_v1/src/dds_top.v b/firmware/ip/axis_sg_mux8_v1/src/dds_top.v new file mode 100644 index 000000000..aa93fc7a4 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/dds_top.v @@ -0,0 +1,141 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + POFF_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*16-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [31:0] POFF_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [15:0] dds_dout [0:N_DDS-1]; +wire [15:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod [0:N_DDS-1]; +reg [15:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v b/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v new file mode 100644 index 000000000..4150ef68a --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc b/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc new file mode 100644 index 000000000..f6cc48a86 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc @@ -0,0 +1,66 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {s_axis_tdata_i[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {s_axis_tdata_i[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports WE_REG] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports WE_REG] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports s_axis_tvalid_i] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports s_axis_tvalid_i] +set _xlnx_shared_i0 [get_ports {m_axis_tdata_o[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 $_xlnx_shared_i0 +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 $_xlnx_shared_i0 +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 [get_ports m_axis_tvalid_o] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid_o] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 [get_ports s_axis_tready_o] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports s_axis_tready_o] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv b/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv new file mode 100644 index 000000000..f879613db --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv @@ -0,0 +1,359 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux8_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // Register mapping: + // 0-7 : PINC. + // 8-15 : POFF. + // 16-23: GAIN. + // 24 : WE. + + for (int i=0; i<8; i=i+1) begin + // PINCx_REG + data_wr = freq_calc(100, N_DDS, 10+i); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*i, prot, data_wr, resp); + + // POFFx_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+8), prot, data_wr, resp); + + // GAINx_REG + data_wr = 20000+1000*i; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+16), prot, data_wr, resp); + + end + + //// PINC0/1/2. + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + + //// POFF0/1/2. + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+8), prot, data_wr, resp); + + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+8), prot, data_wr, resp); + + //data_wr = phase_calc(180); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+8), prot, data_wr, resp); + + //// GAIN0/1/2. + //data_wr = 30000; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+16), prot, data_wr, resp); + + //// 0 gain just for quantization... + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(7+16), prot, 0, resp); + + // WE. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 1, resp); + #10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 0, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #50000; + #50000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 550; + //mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 3500; + mask_r <= 8'b1111_1111; + + // Phase-coherency test. + // 1 sine wave first. + // 2 sine waves, same phase, same frequency. + // 2 sine waves, 180 out of phase, same frequency. + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b1000_0001; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0011; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0101; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i - user.org - user + QICK + QICK axis_signal_gen_v4 1.0 @@ -474,6 +474,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -1154,6 +1168,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS Signal Generator V4 with 32-bit resolution, IQ envelope and dithering. @@ -1178,10 +1199,12 @@ zynquplus - /UserIP + /QICK/Signal_Generator AXIS Signal Generator V4 package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ 14 2021-07-21T20:01:35Z diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd index 2fbb69667..ff87e9d21 100644 --- a/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd @@ -29,6 +29,9 @@ architecture rtl of synchronizer_vect is type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); signal data_int_reg : reg_t; +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_signal_gen_v4/src/synchronizer_n.vhd b/firmware/ip/axis_signal_gen_v4/src/synchronizer_n.vhd index 925425de9..a29bd9be1 100644 --- a/firmware/ip/axis_signal_gen_v4/src/synchronizer_n.vhd +++ b/firmware/ip/axis_signal_gen_v4/src/synchronizer_n.vhd @@ -22,6 +22,9 @@ architecture rtl of synchronizer_n is -- Internal register. signal data_int_reg : std_logic_vector (N-1 downto 0); +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_signal_gen_v5/README b/firmware/ip/axis_signal_gen_v5/README new file mode 100644 index 000000000..bd12955f4 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/README @@ -0,0 +1,6 @@ +Signal Generator Block: +* 32-bit for phase/frequency of DDS. +* Simplified output computation: only keeps real part of result. +* Un-used imaginary part logic removed. + + diff --git a/firmware/ip/axis_signal_gen_v5/component.xml b/firmware/ip/axis_signal_gen_v5/component.xml new file mode 100644 index 000000000..8448a4ba1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/component.xml @@ -0,0 +1,1292 @@ + + + QICK + QICK + axis_signal_gen_v5 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_signal_gen_v5 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6b2d8ce5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_signal_gen_v5 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6b2d8ce5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e51fb623 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + 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src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_signal_gen_v5.v + verilogSource + CHECKSUM_1e94d0d3 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_signal_gen_v5.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_signal_gen_v5_v1_0.tcl + tclSource + CHECKSUM_e51fb623 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS Signal Generator V5, imaginary part output logic removed. + + + N + N + 12 + + + N_DDS + N Dds + 16 + + + Component_Name + axis_signal_gen_v5_v1_0 + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS Signal Generator V5 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 6 + 2022-02-14T20:44:43Z + + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + 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/home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..7cfbd51b5 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..a53be60f7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..ac9cf042c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..fa530b1d6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + + m_axi_wdata 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xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd b/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd new file mode 100644 index 000000000..c60ea98f2 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v b/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v new file mode 100644 index 000000000..240bff672 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v @@ -0,0 +1,198 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_signal_gen_v5 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/bram.v b/firmware/ip/axis_signal_gen_v5/src/bram.v new file mode 100644 index 000000000..018317e0f --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/ctrl.sv b/firmware/ip/axis_signal_gen_v5/src/ctrl.sv new file mode 100644 index 000000000..7cc6a0941 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/ctrl.sv @@ -0,0 +1,466 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [15:0] cnt_n; +reg [15:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + cnt_n <= cnt_n + N_DDS; + if (sync_reg) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r3; + stdysel_r6 <= stdysel_r3; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; + +// Frequency calculation. +assign pinc_N = pinc_r1*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r1*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r4; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r1*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r6,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r5; +assign gain_o = gain_r6; +assign src_o = outsel_r6; +assign stdy_o = stdysel_r6; +assign en_o = en_reg_r7; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd b/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd new file mode 100644 index 000000000..cbf19127f --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd @@ -0,0 +1,226 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of tables. + NT : Integer := 16; + -- Address map of each table. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. +constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory Enable. +signal mem_en_i : std_logic_vector (NT-1 downto 0); +signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. +signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); +signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); +signal mem_addr_high : unsigned (N-1 downto 0); +signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +-- Enable logic generation. +GEN: for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else + '0'; + +end generate GEN; + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; +end process; + +-- Address computation. +mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); +mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= mem_en_r; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_high_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..894ecd665 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..e65044c1b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..825c3173c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../top/top.tmp/axis_signal_gen_v5_v1_0_project/axis_signal_gen_v5_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + 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vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_18 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 2 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/latency_reg.v b/firmware/ip/axis_signal_gen_v5/src/latency_reg.v new file mode 100644 index 000000000..687a9f3fb --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv b/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv new file mode 100644 index 000000000..0ecffa5de --- /dev/null +++ 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a/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv b/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv new file mode 100644 index 000000000..929571db6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv @@ -0,0 +1,427 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// s1_axis interfase. +reg [159:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +// AXI VIP master address. +xil_axi_ulong addr_start_addr = 32'h40000000; // 0 +xil_axi_ulong addr_we = 32'h40000004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_signal_gen_v5 + # + ( + .N (N ), + .N_DDS (N_DDS ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + // Load Table. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + #1000; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load data into memroy. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../tb/gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + +end + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 123; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 13); + phase_r <= 0; + addr_r <= 0; + gain_r <= 30000; + nsamp_r <= 512/N_DDS; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 22); + //phase_r <= 7689; + //addr_r <= 0; + //gain_r <= 30000; + //nsamp_r <= 70/N_DDS; + //outsel_r <= 2; // 0: prod, 1: dds, 2: mem + //mode_r <= 1; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + QICK + QICK + axis_signal_gen_v6 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_signal_gen_v6 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bcdbbbf8 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_signal_gen_v6 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c1c90b5c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + d9c2185d + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 51e2e134 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + 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out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + 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+ Gen Dds + TRUE + + + ENVELOPE_TYPE + Envelope Type + COMPLEX + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_de9e6111 + COMPLEX + REAL + + + choice_list_e7c484ae + TRUE + FALSE + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/signal_gen_ooc.xdc + xdc + USED_IN_out_of_context + + + src/signal_gen_v6.xdc + xdc + + processing_order + late + + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].genblk1.dds_i + + + src/signal_gen_top.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/ctrl_sg_v6.sv + systemVerilogSource + + + src/axi_slv_sg_v6.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + CHECKSUM_d9a7f3d8 + + + ../../hdl/bram_dp_xpm.sv + systemVerilogSource + + + ../../hdl/fifo_xpm.sv + systemVerilogSource + + + src/axis_signal_gen_v6.v + verilogSource + CHECKSUM_fc4e8a0c + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].genblk1.dds_i + + + src/signal_gen_top.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/ctrl_sg_v6.sv + systemVerilogSource + + + src/axi_slv_sg_v6.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + ../../hdl/bram_dp_xpm.sv + systemVerilogSource + + + ../../hdl/fifo_xpm.sv + systemVerilogSource + + + src/axis_signal_gen_v6.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_signal_gen_v6_v1_0.tcl + tclSource + CHECKSUM_d9c2185d + XGUI_VERSION_2 + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + + + src/tb/axi_mst_0/axi_mst_0.xci + xci + + + src/tb/tb_behav_waves.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + src/tb/gauss.txt + txt + USED_IN_testbench + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS Signal Generator V6, Phase coherent with Phase reset. + + + N + N + 12 + + + N_DDS + N Dds + 16 + + + Component_Name + axis_signal_gen_v6_v1_0 + + + GEN_DDS + Gen Dds + TRUE + + + ENVELOPE_TYPE + Envelope Type + COMPLEX + + + + + + zynquplus + + + /QICK/Signal_Generator + + AXIS Signal Generator V6 + package_project + + XPM_FIFO + XPM_MEMORY + + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 8 + 2025-09-11T21:24:42Z + + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/axi_slv_sg_v6.vhd b/firmware/ip/axis_signal_gen_v6/src/axi_slv_sg_v6.vhd new file mode 100644 index 000000000..87e81a333 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/axi_slv_sg_v6.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_sg_v6 is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv_sg_v6; + +architecture rtl of axi_slv_sg_v6 is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v b/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v new file mode 100644 index 000000000..e23379fe9 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v @@ -0,0 +1,211 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_signal_gen_v6 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Envelope Table Memory Size (in 2**N words) +parameter N = 12; + +// Number of parallel DDS blocks. +parameter N_DDS = 16; + +// True: Generate DDS for Envelope Upconversion. False: Remove DDS for Baseband Envelope only +parameter GEN_DDS = "TRUE"; +//parameter GEN_DDS = "FALSE"; + +// COMPLEX: Allow Complex Envelope generation. REAL: Allow only Real envelope generation +//parameter ENVELOPE_TYPE = "REAL"; +parameter ENVELOPE_TYPE = "COMPLEX"; + + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// `uselib lib=lib_axis_signal_gen_v6 +// AXI Slave. +axi_slv_sg_v6 axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ), + .GEN_DDS (GEN_DDS ), + .ENVELOPE_TYPE (ENVELOPE_TYPE ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/ctrl_sg_v6.sv b/firmware/ip/axis_signal_gen_v6/src/ctrl_sg_v6.sv new file mode 100644 index 000000000..f5e02bbaa --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/ctrl_sg_v6.sv @@ -0,0 +1,545 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl_sg_v6 ( + // Reset and clock. + rstn, + clk, + + // Fifo interface. + fifo_rd_en_o, + fifo_empty_i, + fifo_dout_i, + + // dds control. + dds_ctrl_o, + + // memory control. + mem_addr_o, + + // gain. + gain_o, + + // Output source selection. + src_o, + + // Steady value selection. + stdy_o, + + // Output enable. + en_o +); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; + +// wire [31:0] pinc_Nm; +// reg [31:0] pinc_Nm_r1; +// reg [31:0] pinc_Nm_r2; +// reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [15:0] cnt_nsamp_r; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt_nsamp_r <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt_nsamp_r == 2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt_nsamp_r <= fifo_dout_i[143:128]; + else + cnt_nsamp_r <= cnt_nsamp_r - 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; +assign phrst_int = fifo_dout_r[148]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +// Original code - 48bits multiplier and mod32 operation +// doesn't map to DSPs and doesn't meet timing + +// assign pinc_Nm = pinc_r2 * cnt_n_reg; + +// pinc_Nm Registers +// always @(posedge clk) begin +// if (~rstn) begin +// pinc_Nm_r1 <= 0; +// pinc_Nm_r2 <= 0; +// pinc_Nm_r3 <= 0; +// end +// else begin +// pinc_Nm_r1 <= pinc_Nm; +// pinc_Nm_r2 <= pinc_Nm_r1; +// pinc_Nm_r3 <= pinc_Nm_r2; +// end +// end + +// Phase calculation. +// Alternate Implementation - split multiplier and mod32 in more operations +// maps to DSPs and improves timing +localparam WL = 17; localparam WH = 32-WL; +logic [WL:0] pinc_r2_lo_r, cnt_n_reg_lo_r; +logic [WH:0] pinc_r2_hi_r, cnt_n_reg_hi_r; +assign pinc_r2_lo_r = $signed({1'b0,pinc_r2[WL-1:0]}); +assign pinc_r2_hi_r = $signed({1'b0,pinc_r2[31:WL]}); +assign cnt_n_reg_lo_r = $signed({1'b0,cnt_n_reg[WL-1:0]}); +assign cnt_n_reg_hi_r = $signed({1'b0,cnt_n_reg[31:WL]}); + +logic signed [2*(WL+1)-1:0] pinc_Nm_dsp_p0_r1_3; +logic signed [2*(WL+1)-1:0] pinc_Nm_dsp_p0_r2_3; +logic signed [2*(WH+1)-1:0] pinc_Nm_dsp_p1_r1_3; +logic signed [2*(WH+1)-1:0] pinc_Nm_dsp_p1_r2_3; +logic signed [2*(WH+1)-1:0] pinc_Nm_dsp_p2_r1_3; +logic signed [2*(WH+1)-1:0] pinc_Nm_dsp_p2_r2_3; + +logic signed [31:0] pinc_Nm_dsp_r3_3; + +always @(posedge clk) begin + pinc_Nm_dsp_p0_r1_3 <= pinc_r2_lo_r * cnt_n_reg_lo_r; // WL x WL : MREG + pinc_Nm_dsp_p1_r1_3 <= pinc_r2_hi_r * cnt_n_reg_lo_r; // WH x WL : MREG + pinc_Nm_dsp_p2_r1_3 <= pinc_r2_lo_r * cnt_n_reg_hi_r; // WL x WH : MREG + + pinc_Nm_dsp_p0_r2_3 <= pinc_Nm_dsp_p0_r1_3; + pinc_Nm_dsp_p1_r2_3 <= pinc_Nm_dsp_p1_r1_3 << 17; + pinc_Nm_dsp_p2_r2_3 <= pinc_Nm_dsp_p2_r1_3 << 17; + pinc_Nm_dsp_r3_3 <= pinc_Nm_dsp_p0_r2_3[31:0] + pinc_Nm_dsp_p1_r2_3 + pinc_Nm_dsp_p2_r2_3; +end + +assign phase_0 = pinc_Nm_dsp_r3_3 + phase_r5; + + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd b/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd new file mode 100644 index 000000000..e38b1c466 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd @@ -0,0 +1,226 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of tables. + NT : Integer := 16; + -- Address map of each table. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. +constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory Enable. +signal mem_en_i : std_logic_vector (NT-1 downto 0); +signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. +signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); +signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); +signal mem_addr_high : unsigned (N-1 downto 0); +signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +-- Enable logic generation. +GEN: for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else + '0'; + +end generate GEN; + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; +end process; + +-- Address computation. +mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); +mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= mem_en_r; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_high_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 000000000..894ecd665 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 000000000..e65044c1b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 000000000..f9b7d57de --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,357 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "dds_compiler_0", + "component_reference": "xilinx.com:ip:dds_compiler:6.0", + "ip_revision": "22", + "gen_directory": "../../../../projects/qick_tprocv2_4x2_standard/top/top.tmp/axis_signal_gen_v6_v1_0_project/axis_signal_gen_v6_v1_0_project.gen/sources_1/ip/dds_compiler_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "dds_compiler_0", "resolve_type": "user", "usage": "all" } ], + "PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "DDS_Clock_Rate": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ], + "Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Parameter_Entry": [ { "value": "System_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Spurious_Free_Dynamic_Range": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "Frequency_Resolution": [ { "value": "0.06", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "Noise_Shaping": [ { "value": "Auto", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Resync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Phase_offset": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ], + "Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ], + "Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ], + "Optimization_Goal": [ { "value": "Speed", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "DSP48_Use": [ { "value": "Maximal", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Has_TREADY": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ], + "S_CONFIG_Sync_Mode": [ { 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Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + mult_gen_v12_0_15 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + dds_compiler_v6_0_18 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_15 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_18 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 2 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/latency_reg.v b/firmware/ip/axis_signal_gen_v6/src/latency_reg.v new file mode 100644 index 000000000..169060ecf --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i> 1; // divide by 2 to match product path scaling + assign dds_la_mux[i][15:0] = (2**15)-1; + end + + // Muxed output. + assign dout_mux[i] = (src_la == 0)? prod_y_mux[i] : + (src_la == 1)? dds_la_mux[i] : + (src_la == 2)? mem_la_mux[i] : + 16'h0000; + // Product with Gain. + assign prodg_a_real[i] = dout_mux_la[i]; + assign prodg_y_full_real[i] = prodg_a_real[i] * gain_la; + + // Rounding. + assign round[i] = prodg_y_full_real_r2[i][30 -: 16]; + + /***********/ + /* Outputs */ + /***********/ + assign m_axis_tdata_o[i*16 +: 16] = (en_la_r == 1'b1)? round[i] : + (stdy_la == 1'b0)? last_r[i] : + 16'h0000; + end +endgenerate + +// Latency for source selection. +latency_reg + #( + .N(16), + .B(2) + ) + src_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (src_int ), + .dout (src_la ) + ); + +// Latency for gain. +latency_reg + #( + .N(18), + .B(16) + ) + gain_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (gain_int ), + .dout (gain_la ) + ); + +// Latency for steady value selection. +latency_reg + #( + .N(20), + .B(1) + ) + stdy_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (stdy_int ), + .dout (stdy_la ) + ); + +// Latency for output enable. +latency_reg + #( + .N(19), + .B(1) + ) + en_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_int ), + .dout (en_la ) + ); + +// Registers. +generate +if (GEN_DDS == "TRUE") begin + always @(posedge clk) begin + if (~rstn) begin + // DDS intput control. + dds_tvalid_r <= 0; + dds_ctrl_int_r <= 0; + end + else begin + // DDS intput control. + dds_tvalid_r <= 1; + dds_ctrl_int_r <= dds_ctrl_int; + end + end +end +endgenerate +always @(posedge clk) begin + if (~rstn) begin + // Memory address. + mem_addr_int_r <= 0; + // Output enable. + en_la_r <= 0; + end + else begin + // Memory address. + mem_addr_int_r <= mem_addr_int; + // Output enable. + en_la_r <= en_la; + end +end + +// Outputs. +assign mem_addr_o = mem_addr_int_r; +assign m_axis_tvalid_o = en_la_r; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/signal_gen_ooc.xdc b/firmware/ip/axis_signal_gen_v6/src/signal_gen_ooc.xdc new file mode 100644 index 000000000..fd3a744e7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/signal_gen_ooc.xdc @@ -0,0 +1,3 @@ +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +create_clock -period 4.000 -name s0_axis_aclk -waveform {0.000 2.000} [get_ports s0_axis_aclk] +create_clock -period 1.600 -name aclk -waveform {0.000 0.800} [get_ports aclk] diff --git a/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v b/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v new file mode 100644 index 000000000..ce930404e --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v @@ -0,0 +1,257 @@ +module signal_gen_top + ( + // Reset and clock. + aresetn , + aclk , + + // AXIS Slave to load memory samples. + s0_axis_aresetn , + s0_axis_aclk , + s0_axis_tdata_i , + s0_axis_tvalid_i , + s0_axis_tready_o , + + // AXIS Slave to queue waveforms. + s1_axis_tdata_i , + s1_axis_tvalid_i , + s1_axis_tready_o , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Registers. + START_ADDR_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 16; + +// True: Generate DDS for Envelope Upconversion. False: Remove DDS for Baseband Envelope only +parameter GEN_DDS = "TRUE"; + +// COMPLEX: Allow Complex Envelope generation. REAL: Allow only Real envelope generation +parameter ENVELOPE_TYPE = "COMPLEX"; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s0_axis_aresetn; +input s0_axis_aclk; +input [31:0] s0_axis_tdata_i; +input s0_axis_tvalid_i; +output s0_axis_tready_o; + +input [159:0] s1_axis_tdata_i; +input s1_axis_tvalid_i; +output s1_axis_tready_o; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*16-1:0] m_axis_tdata_o; + +input [31:0] START_ADDR_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// Fifo. +wire fifo_wr_en; +wire [159:0] fifo_din; +wire fifo_rd_en; +wire [159:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +// Memory. +wire [N_DDS-1:0] mem_ena; +wire mem_wea; +wire [N-1:0] mem_addra; +wire [31:0] mem_dia; +wire [N-1:0] mem_addrb; +wire [N_DDS*16-1:0] mem_dob_real; +wire [N_DDS*16-1:0] mem_dob_imag; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Fifo. +fifo_xpm + #( + // Data width. + .B (160), + + // Fifo depth. + .N (16) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +assign fifo_wr_en = s1_axis_tvalid_i; +assign fifo_din = s1_axis_tdata_i; + +// Data writer. +data_writer + #( + // Number of tables. + .NT (N_DDS ), + // Address map of memory. + .N (N ), + // Data width. + .B (32 ) + ) + data_writer_i + ( + .rstn (s0_axis_aresetn ), + .clk (s0_axis_aclk ), + + // AXI Stream I/F. + .s_axis_tready (s0_axis_tready_o ), + .s_axis_tdata (s0_axis_tdata_i ), + .s_axis_tvalid (s0_axis_tvalid_i ), + + // Memory I/F. + .mem_en (mem_ena ), + .mem_we (mem_wea ), + .mem_addr (mem_addra ), + .mem_di (mem_dia ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +generate + genvar i; + for (i=0; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..5653a7928 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..4ca178885 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. 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xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc new file mode 100644 index 000000000..bb1ff41ee --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name aclk [get_ports aclk] + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt b/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt new file mode 100644 index 000000000..68d926581 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt @@ -0,0 +1,512 @@ +57,0 +60,0 +62,0 +65,0 +68,0 +71,0 +74,0 +77,0 +80,0 +83,0 +87,0 +90,0 +94,0 +98,0 +102,0 +106,0 +110,0 +115,0 +119,0 +124,0 +129,0 +134,0 +140,0 +145,0 +151,0 +157,0 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+1865,0 +1814,0 +1764,0 +1715,0 +1667,0 +1620,0 +1574,0 +1530,0 +1486,0 +1444,0 +1403,0 +1362,0 diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py b/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py new file mode 100644 index 000000000..89bb7b796 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py @@ -0,0 +1,22 @@ +import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=30000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yq = gauss(mu=300, si=120, length=512) +yi = np.zeros(len(yq)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + +# plt.figure() +# plt.plot(yq) +# plt.show() + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv b/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv new file mode 100644 index 000000000..96979772c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv @@ -0,0 +1,531 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// Dummy clock for debugging. +reg aclk4; + +// s1_axis interfase. +reg [159:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; +reg [15:0] dout_f; + +// AXI VIP master address. +xil_axi_ulong addr_start_addr = 32'h40000000; // 0 +xil_axi_ulong addr_we = 32'h40000004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_signal_gen_v6 + # + ( + .N (N ), + .N_DDS (N_DDS ), + .GEN_DDS ("FALSE" ), + .ENVELOPE_TYPE ("REAL" ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + // Load Envelope Table Memory. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + #1000; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #10us; + + // Stop writing output data. + tb_write_out <= 0; + + #5us; + + $finish(); + +end + +// Load pulse data into memory. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + // File must be in the same directory from where the simulation is run + fd = $fopen("./gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", vali,valq) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; +end + + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. +// phase_r <= 0; +// addr_r <= 22; +// gain_r <= 12000; +// nsamp_r <= 80; +// outsel_r <= 1; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 0; // 0: last, 1: zero. +// phrst_r <= 0; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 2; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. +// phase_r <= 0; +// addr_r <= 22; +// gain_r <= 12000; +// nsamp_r <= 123; +// outsel_r <= 1; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 0; // 0: last, 1: zero. +// phrst_r <= 1; + +// @(posedge aclk); +// s1_axis_tvalid <= 0; + +// #5us; + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 13); +// phase_r <= 0; +// addr_r <= 0; +// gain_r <= 30000; +// nsamp_r <= 400/N_DDS; +// outsel_r <= 0; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 1; // 0: last, 1: zero. +// phrst_r <= 0; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 22); +// phase_r <= 7689; +// addr_r <= 0; +// gain_r <= 30000; +// nsamp_r <= 70/N_DDS; +// outsel_r <= 2; // 0: prod, 1: dds, 2: mem +// mode_r <= 1; // 0: nsamp, 1: periodic +// stdysel_r <= 1; // 0: last, 1: zero. + +// @(posedge aclk); +// s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("./dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LOAD_MEMORY + label + + tb_load_mem + tb_load_mem + + + s0_axis_tready + s0_axis_tready + + + s0_axis_tvalid + s0_axis_tvalid + + + s0_axis_tdata[31:0] + s0_axis_tdata[31:0] + + + New Virtual Bus 13 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + New Virtual Bus 12 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + + tb_load_mem_done + tb_load_mem_done + + + + LOAD_WAVEFORM + label + + + tb_load_wave + tb_load_wave + + + freq_r[31:0] + freq_r[31:0] + UNSIGNEDDECRADIX + + + phase_r[31:0] + phase_r[31:0] + UNSIGNEDDECRADIX + + + addr_r[15:0] + addr_r[15:0] + UNSIGNEDDECRADIX + + + gain_r[15:0] + gain_r[15:0] + UNSIGNEDDECRADIX + + + nsamp_r[15:0] + nsamp_r[15:0] + UNSIGNEDDECRADIX + + + outsel_r[1:0] + outsel_r[1:0] + UNSIGNEDDECRADIX + + + mode_r + mode_r + + + stdysel_r + stdysel_r + + + phrst_r + phrst_r + + + s1_axis_tready + s1_axis_tready + + + s1_axis_tvalid + s1_axis_tvalid + + + s1_axis_tdata[159:0] + s1_axis_tdata[159:0] + + + tb_load_wave_done + tb_load_wave_done + + + + tb_write_out + tb_write_out + + + SG_DATA_WRITER + label + + rstn + rstn + + + clk + clk + + + state + state + + + + SG_FIFO_IN + label + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[159:0] + din[159:0] + + + full + full + + + rd_en + rd_en + + + dout[159:0] + dout[159:0] + + + empty + empty + + + + DDSs_COMPILER + label + + DDS_0 + label + + + dds_0_imag + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + + dds_0_real + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + + + DDS_1 + label + + + DDS_2 + label + + + DDS_3 + label + + + + CTRL + label + + fifo_rd_en_o + fifo_rd_en_o + + + fifo_empty_i + fifo_empty_i + + + fifo_dout_i[159:0] + fifo_dout_i[159:0] + + + cnt_n[31:0] + cnt_n[31:0] + UNSIGNEDDECRADIX + + + cnt_n_reg[31:0] + cnt_n_reg[31:0] + UNSIGNEDDECRADIX + + + state[31:0] + state[31:0] + + + mem_addr_o[9:0] + mem_addr_o[9:0] + + + gain_o[15:0] + gain_o[15:0] + UNSIGNEDDECRADIX + + + src_o[1:0] + src_o[1:0] + + + stdy_o + stdy_o + + + en_o + en_o + + + + SIGNAL_PATH + label + + + [0][15:0] + [0][15:0] + SIGNEDDECRADIX + STYLE_ANALOG + 100 + ANALOG_YRANGETYPE_AUTO + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + + [0][15:0] + [0][15:0] + SIGNEDDECRADIX + STYLE_ANALOG + 100 + ANALOG_YRANGETYPE_AUTO + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + + + M_AXIS_OUT + label + + m_axis_tready_i + m_axis_tready_i + + + m_axis_tvalid_o + m_axis_tvalid_o + + + m_axis_tdata_o[63:0] + m_axis_tdata_o[63:0] + + + dout_ii[0:3][15:0] + dout_ii[0:3][15:0] + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv b/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv new file mode 100644 index 000000000..b49ac5afd --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv @@ -0,0 +1,188 @@ +module tb(); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 2; + +// Ports. +reg rstn; +reg clk; + +wire fifo_rd_en_o; +reg fifo_empty_i; +wire[159:0] fifo_dout_i; +wire[N_DDS*72-1:0] dds_ctrl_o; +wire[N-1:0] mem_addr_o; +wire[15:0] gain_o; +wire[1:0] src_o; +wire stdy_o; +wire en_o; + +// Fifo signals. +reg fifo_wr_en; +wire[159:0] fifo_din; +wire fifo_full; + +// Fifo Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of DDSs for debugging. +wire [71:0] dds_ctrl_ii [0:N_DDS-1]; + +integer i; + +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dds_ctrl_ii[ii] = dds_ctrl_o[72*ii +: 72]; +end +endgenerate + +// Fifo. +fifo_xpm + #( + // Data width. + .B (160), + + // Fifo depth. + .N (16) + ) + fifo_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en_o ), + .dout (fifo_dout_i ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty_i ) + ); + +// DUT. +ctrl_sg_v6 + #( + .N (N ), + .N_DDS (N_DDS ) + ) + DUT + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en_o ), + .fifo_empty_i (fifo_empty_i ), + .fifo_dout_i (fifo_dout_i ), + + // dds control. + .dds_ctrl_o (dds_ctrl_o ), + + // memory control. + .mem_addr_o (mem_addr_o ), + + // gain. + .gain_o (gain_o ), + + // Output source selection. + .src_o (src_o ), + + // Steady value selection. + .stdy_o (stdy_o ), + + // Output enable. + .en_o (en_o ) + ); + +assign fifo_din = { {11{1'b0}} , + phrst_r , + stdysel_r , + mode_r , + outsel_r , + nsamp_r , + {16{1'b0}} , + gain_r , + {16{1'b0}} , + addr_r , + phase_r , + freq_r }; + +initial begin + rstn <= 0; + fifo_wr_en <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + #200; + rstn <= 1; + + #200; + + @(posedge clk); + fifo_wr_en <= 1; + freq_r <= 100; + phase_r <= 0; + addr_r <= 50; + gain_r <= 40; + nsamp_r <= 10; + outsel_r <= 2; + mode_r <= 1; + stdysel_r <= 0; + phrst_r <= 1; + + @(posedge clk); + fifo_wr_en <= 0; + + #1000; + + @(posedge clk); + fifo_wr_en <= 1; + freq_r <= 3516; + phase_r <= 2345; + addr_r <= 5; + gain_r <= 4; + nsamp_r <= 5; + outsel_r <= 2; + mode_r <= 0; + stdysel_r <= 1; + phrst_r <= 0; + + @(posedge clk); + fifo_wr_en <= 0; + + #10000; + +end + +always begin + clk <= 0; + #10; + clk <= 1; + #10; +end + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/timing.xdc b/firmware/ip/axis_signal_gen_v6/src/timing.xdc new file mode 100644 index 000000000..49ab49cd6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/timing.xdc @@ -0,0 +1,10 @@ +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +create_clock -period 2.000 -name aclk -waveform {0.000 1.000} [get_ports aclk] +create_clock -period 10.000 -name s0_axis_aclk -waveform {0.000 5.000} [get_ports s0_axis_aclk] + +set_clock_groups -asynchronous -group [get_clocks aclk] -group [get_clocks s0_axis_aclk] -group [get_clocks s_axi_aclk] + + + +set _xlnx_shared_i0 [get_ports s1_axis_t*] +set_false_path -from $_xlnx_shared_i0 diff --git a/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl b/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl new file mode 100644 index 000000000..ce6168da6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl @@ -0,0 +1,71 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set N [ipgui::add_param $IPINST -name "N" -parent ${Page_0}] + set_property tooltip {Envelope Memory Size in 2^N Words} ${N} + ipgui::add_param $IPINST -name "N_DDS" -parent ${Page_0} + ipgui::add_param $IPINST -name "GEN_DDS" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "ENVELOPE_TYPE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.ENVELOPE_TYPE { PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to update ENVELOPE_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENVELOPE_TYPE { PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to validate ENVELOPE_TYPE + return true +} + +proc update_PARAM_VALUE.GEN_DDS { PARAM_VALUE.GEN_DDS } { + # Procedure called to update GEN_DDS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.GEN_DDS { PARAM_VALUE.GEN_DDS } { + # Procedure called to validate GEN_DDS + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.N_DDS { PARAM_VALUE.N_DDS } { + # Procedure called to update N_DDS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_DDS { PARAM_VALUE.N_DDS } { + # Procedure called to validate N_DDS + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.N_DDS { MODELPARAM_VALUE.N_DDS PARAM_VALUE.N_DDS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_DDS}] ${MODELPARAM_VALUE.N_DDS} +} + +proc update_MODELPARAM_VALUE.GEN_DDS { MODELPARAM_VALUE.GEN_DDS PARAM_VALUE.GEN_DDS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.GEN_DDS}] ${MODELPARAM_VALUE.GEN_DDS} +} + +proc update_MODELPARAM_VALUE.ENVELOPE_TYPE { MODELPARAM_VALUE.ENVELOPE_TYPE PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENVELOPE_TYPE}] ${MODELPARAM_VALUE.ENVELOPE_TYPE} +} + diff --git a/firmware/ip/axis_terminator/component.xml b/firmware/ip/axis_terminator/component.xml index b75874eca..65823237f 100644 --- a/firmware/ip/axis_terminator/component.xml +++ b/firmware/ip/axis_terminator/component.xml @@ -1,7 +1,7 @@ - user.org - user + QICK + QICK axis_terminator 1.0 @@ -150,6 +150,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -301,6 +315,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS Terminator block. @@ -340,10 +361,12 @@ kintexu - /UserIP + /QICK/AXI_Peripheral AXIS Terminator package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ 2 2019-08-16T18:41:23Z diff --git a/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix b/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix new file mode 100644 index 000000000..2bd23d6b9 Binary files /dev/null and b/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix differ diff --git a/firmware/ip/axis_tmux_v1/component.xml b/firmware/ip/axis_tmux_v1/component.xml new file mode 100644 index 000000000..f17d8c10c --- /dev/null +++ b/firmware/ip/axis_tmux_v1/component.xml @@ -0,0 +1,820 @@ + + + QICK + QICK + axis_tmux_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + + true + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + + false + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + + false + + + + + + m4_axis + + + + true + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + + + false + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + + + false + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + + + false + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + + + false + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_tmux_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 49caebd3 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_tmux_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 49caebd3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5752b26c + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m0_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m4_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m5_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m5_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m6_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m6_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m7_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m7_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 2 + + + B + B + 16 + + + + + + choice_list_2a885f8d + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/tmux.sv + systemVerilogSource + + + src/axis_tmux_v1.sv + systemVerilogSource + CHECKSUM_625dc80f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/tmux.sv + systemVerilogSource + + + src/axis_tmux_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_tmux_v1_v1_0.tcl + tclSource + CHECKSUM_5752b26c + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + AXIS tMux for tProcessor, V1. + + + N + N + 2 + + + B + B + 16 + + + Component_Name + axis_tmux_v1_v1_0 + + + + + + zynquplus + + + /QICK/Miscellaneous + + AXIS tMux V1 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + 2024-08-05T21:30:41Z + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv b/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv new file mode 100644 index 000000000..0ee228b95 --- /dev/null +++ b/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv @@ -0,0 +1,94 @@ +module axis_tmux_v1 + #( + // Number of outputs. + parameter N = 8, + + // Number of data bits. + parameter B = 16 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + output wire s_axis_tready , + input wire s_axis_tvalid , + input wire [B-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata + ); + +/**********************/ +/* Begin Architecture */ +/**********************/ +tmux + #( + // Number of outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + tmux_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ) + ); + +endmodule + diff --git a/firmware/ip/axis_tmux_v1/src/tb.sv b/firmware/ip/axis_tmux_v1/src/tb.sv new file mode 100644 index 000000000..e07aa64b5 --- /dev/null +++ b/firmware/ip/axis_tmux_v1/src/tb.sv @@ -0,0 +1,150 @@ +module tb; + +// Number of outputs. +parameter N = 8 ; + +// Number of data bits. +parameter B = 32 ; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// S_AXIS for input data. +wire s_axis_tready ; +reg s_axis_tvalid ; +wire [B-1:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m0_axis_tvalid ; +wire [B-1:0] m0_axis_tdata ; + +wire m1_axis_tvalid ; +wire [B-1:0] m1_axis_tdata ; + +wire m2_axis_tvalid ; +wire [B-1:0] m2_axis_tdata ; + +wire m3_axis_tvalid ; +wire [B-1:0] m3_axis_tdata ; + +wire m4_axis_tvalid ; +wire [B-1:0] m4_axis_tdata ; + +wire m5_axis_tvalid ; +wire [B-1:0] m5_axis_tdata ; + +wire m6_axis_tvalid ; +wire [B-1:0] m6_axis_tdata ; + +wire m7_axis_tvalid ; +wire [B-1:0] m7_axis_tdata ; + +// Sel/data. +reg [7:0] sel_r ; +reg [23:0] data_r ; + +// Input sel/data. +assign s_axis_tdata = {sel_r, data_r}; + +// DUT. +axis_tmux_v1 + #( + // Number of outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + DUT + ( + // Reset and clock. + .aresetn , + .aclk , + + // S_AXIS for input data. + .s_axis_tready , + .s_axis_tvalid , + .s_axis_tdata , + + // M_AXIS for output data. + .m0_axis_tvalid , + .m0_axis_tdata , + + .m1_axis_tvalid , + .m1_axis_tdata , + + .m2_axis_tvalid , + .m2_axis_tdata , + + .m3_axis_tvalid , + .m3_axis_tdata , + + .m4_axis_tvalid , + .m4_axis_tdata , + + .m5_axis_tvalid , + .m5_axis_tdata , + + .m6_axis_tvalid , + .m6_axis_tdata , + + .m7_axis_tvalid , + .m7_axis_tdata + ); + +// Main TB. +initial begin + aresetn <= 0; + s_axis_tvalid <= 0; + sel_r <= 0; + data_r <= 0; + #300; + aresetn <= 1; + + #1000; + + for (int i=0; i - user.org - user + QICK + QICK axis_tproc64x32_x8 1.0 @@ -850,7 +850,7 @@ viewChecksum - eac17fa8 + 2cddc9c3 @@ -866,7 +866,7 @@ viewChecksum - eac17fa8 + 2cddc9c3 @@ -884,6 +884,20 @@ + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + @@ -2248,6 +2262,13 @@ XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + AXIS tProcessor, 64-bit Instructions, 32-bit registers, 4 input channels, 8 output channels. @@ -2268,37 +2289,16 @@ - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - /UserIP + /QICK/Timed_Processor AXIS tProcessor 64x32, 8 channels V1. + level_2 package_project - 3 - 2021-06-11T18:17:59Z + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 4 + 2023-08-08T16:38:04Z /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 @@ -2326,10 +2326,10 @@ - 2019.1 + 2022.1 - + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd index 2fbb69667..ff87e9d21 100644 --- a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd @@ -29,6 +29,9 @@ architecture rtl of synchronizer_vect is type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); signal data_int_reg : reg_t; +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl old mode 100644 new mode 100755 diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd index 925425de9..a29bd9be1 100644 --- a/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd @@ -22,6 +22,9 @@ architecture rtl of synchronizer_n is -- Internal register. signal data_int_reg : std_logic_vector (N-1 downto 0); +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + begin process(clk) diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v b/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v index d6a338a51..b99bc986f 100644 --- a/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v @@ -166,6 +166,7 @@ localparam FW = 5*B + TW + 8; // Synced regs. wire START_SRC_REG_resync; wire START_REG_resync; +wire start_input_resync; // Muxed start. wire start_i; @@ -322,6 +323,19 @@ synchronizer_n .data_out (START_REG_resync ) ); +// start_input_resync +synchronizer_n + #( + .N(2) + ) + start_input_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (start ), + .data_out (start_input_resync ) + ); + // Control block. ctrl ctrl_i @@ -382,7 +396,7 @@ ctrl ); // Muxed start. -assign start_i = (START_SRC_REG_resync == 1)? start : START_REG_resync; +assign start_i = (START_SRC_REG_resync == 1)? start_input_resync : START_REG_resync; // Instruction fields. assign opcode_i = ir_r[63:56]; diff --git a/firmware/ip/axis_weighted_buffer/component.xml b/firmware/ip/axis_weighted_buffer/component.xml new file mode 100644 index 000000000..dc4760892 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/component.xml @@ -0,0 +1,1558 @@ + + + QICK + QICK + axis_weighted_buffer + 1.3 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TLAST + + + m0_axis_tlast + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TLAST + + + m1_axis_tlast + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi:s1_axis_weights + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + FREQ_HZ + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_RESET + m_axis_aresetn + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis + + + FREQ_HZ + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + s1_axis_weights + + + + + + + TVALID + + + s1_axis_tvalid + + + + + TDATA + + + s1_axis_tdata + + + + + TREADY + + + s1_axis_tready + + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_weighted_buffer + + xilinx_anylanguagesynthesis_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b446663c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_weighted_buffer + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b446663c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 62c01b7a + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + 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+ in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m2_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_AVG + N Avg + 14 + + + N_BUF + N Buf + 14 + + + B + B + 16 + + + N_WGT + N Wgt + 14 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dsp_macro_0/dsp_macro_0.xci + xci + CELL_NAME_avg_buffer_i/matchfilt_i/matched_filter_mult_ac + + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + ../../hdl/fifo_dc_axi_xpm.sv + systemVerilogSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + CHECKSUM_34e13cff + + + src/matched_filter.vhd + vhdlSource + CHECKSUM_f6218d31 + + + src/axis_weighted_buffer.v + verilogSource + CHECKSUM_b6b3033f + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dsp_macro_0/dsp_macro_0.xci + xci + CELL_NAME_avg_buffer_i/matchfilt_i/matched_filter_mult_ac + + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + ../../hdl/fifo_dc_axi_xpm.sv + systemVerilogSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/matched_filter.vhd + vhdlSource + + + src/axis_weighted_buffer.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_weighted_buffer_v1_3.tcl + tclSource + CHECKSUM_62c01b7a + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + AXIS Weighted Integrator + Buffer block with external trigger and edge-counting mode. + + + N_AVG + N Avg + 14 + + + N_BUF + N Buf + 14 + + + B + B + 16 + + + Component_Name + axis_weighted_buffer_v1_0 + + + N_WGT + N Weights + 14 + + + + + + /QICK/Miscellaneous + + AXIS Weighted Integrator + Buffer + level_2 + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 3 + + QICK:QICK:axis_matchfilt_buffer:1.0 + QICK:QICK:axis_matchfilt_buffer:1.1 + QICK:QICK:axis_matchfilt_buffer:1.2 + QICK:QICK:axis_weighted_buffer:1.2 + + 2025-09-11T22:26:52Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_weighted_buffer/src/avg.sv b/firmware/ip/axis_weighted_buffer/src/avg.sv new file mode 100644 index 000000000..64932e043 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg.sv @@ -0,0 +1,274 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG , + PHOTON_MODE_REG, + H_THRSH_REG , + L_THRSH_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + output mem_we_o; + output [N-1:0] mem_addr_o; + output [4*B-1:0] mem_di_o; + + + input START_REG; + input [N-1:0] ADDR_REG; + input [31:0] LEN_REG; + input PHOTON_MODE_REG; + input [B-1:0] H_THRSH_REG; + input [B-1:0] L_THRSH_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + // States. + typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + AVG_ST , + QOUT_ST , + WRITE_MEM_ST , + WAIT_TRIGGER_ST + } state_t; + + // State register. + (* fsm_encoding = "one_hot" *) state_t state; + + reg start_state; + reg trigger_state; + reg avg_state; + reg qout_state; + reg write_mem_state; + + // Edge counter states. + reg high_state; + reg high_state_reg; + + // Counter. + reg [31:0] cnt; + + // Registers. + reg [N-1:0] addr_r; + reg [31:0] len_r; + reg photon_mode_r; + reg signed [B-1:0] h_thrsh_r; + reg signed [B-1:0] l_thrsh_r; + + + // Input data. + wire signed [B-1:0] din_ii, din_qq; + + // Accumulators. + reg signed [2*B-1:0] acc_i, acc_q; + reg [4*B-1:0] acc_photon; + + // Quantized outputs. + reg [4*B-1:0] out_result_r; + + + ////////////////// + // Architecture // + ////////////////// + assign din_ii = din_i[B-1:0]; + assign din_qq = din_i[2*B-1:B]; + + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + photon_mode_r <= 1'b0; + h_thrsh_r <= 0; + l_thrsh_r <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; + + // Accumulators. + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + + // Quantized outputs. + out_result_r <= 0; + + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= AVG_ST; + + AVG_ST: + if ( cnt == len_r && din_valid_i == 1'b1 ) + state <= QOUT_ST; + + QOUT_ST: + state <= WRITE_MEM_ST; + + WRITE_MEM_ST: + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( avg_state == 1'b1 ) begin + if ( din_valid_i == 1'b1) begin + cnt <= cnt + 1; + end + end + else begin + cnt <= 0; + end + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG - 1; + photon_mode_r <= PHOTON_MODE_REG; + h_thrsh_r <= H_THRSH_REG; + l_thrsh_r <= L_THRSH_REG; + end + else if ( write_mem_state == 1'b1 ) begin + addr_r <= addr_r + 1; + end + + // Accumulators. + if ( trigger_state == 1'b1 ) begin + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; + end + else if ( avg_state == 1'b1 && din_valid_i == 1'b1 ) begin + // Accumulator counter. + if ( photon_mode_r == 1'b0 ) begin + acc_i <= acc_i + din_ii; + acc_q <= acc_q + din_qq; + end + // Rising edge counter. + else if ( high_state == 1'b1 && high_state_reg == 1'b0) + acc_photon <= acc_photon + 1; + end + + // Edge counter detect. + high_state_reg <= high_state; + if ( din_ii > h_thrsh_r ) + high_state <= 1'b1; + else if ( din_ii < l_thrsh_r ) + high_state <= 1'b0; + + // Quantized outputs. + // if ( qout_state == 1'b1 ) begin + if ( photon_mode_r == 1'b0 ) + out_result_r <= {acc_q,acc_i}; + else + out_result_r <= acc_photon; + // end + end + end + + // FSM outputs. + always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + avg_state = 0; + qout_state = 0; + write_mem_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + AVG_ST: + avg_state = 1'b1; + + QOUT_ST: + qout_state = 1'b1; + + WRITE_MEM_ST: + write_mem_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase + end + + // Assign outputs. + + // BRAM for result storage + assign mem_we_o = write_mem_state; + assign mem_addr_o = addr_r; + assign mem_di_o = out_result_r; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/avg_buffer.v b/firmware/ip/axis_weighted_buffer/src/avg_buffer.v new file mode 100644 index 000000000..7cf49595d --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg_buffer.v @@ -0,0 +1,277 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg_buffer ( + // Reset and clock for readout data path + s_axis_aclk , + s_axis_aresetn , + + // Reset and clock for writing weights + s_axi_aclk , + s_axi_aresetn , + + // Trigger input. + trigger , + + // AXIS Slave for memory programming + s1_axis_tvalid, + s1_axis_tdata, + s1_axis_tready, + + // AXIS Slave for input data. + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0, m1 and m2. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG , + AVG_DR_START_REG , + AVG_DR_ADDR_REG , + AVG_DR_LEN_REG , + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + BUF_DR_START_REG , + BUF_DR_ADDR_REG , + BUF_DR_LEN_REG, + WGT_DW_ADDR_REG, + WGT_DW_START_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N_AVG = 14; + parameter N_BUF = 14; + parameter N_WGT = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input s_axis_aclk; + input s_axis_aresetn; + + input s_axi_aclk; + input s_axi_aresetn; + + input trigger; + + input s_axis_tvalid; + output s_axis_tready; + input [2*B-1:0] s_axis_tdata; + + input s1_axis_tvalid; + input [2*B-1:0] s1_axis_tdata; + output s1_axis_tready; + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [2*B-1:0] m1_axis_tdata; + output m1_axis_tlast; + + output m2_axis_tvalid; + input m2_axis_tready; + output [4*B-1:0] m2_axis_tdata; + + input AVG_START_REG; + input [N_AVG-1:0] AVG_ADDR_REG; + input [31:0] AVG_LEN_REG; + input AVG_PHOTON_MODE_REG; + input [B-1:0] AVG_H_THRSH_REG; + input [B-1:0] AVG_L_THRSH_REG; + input AVG_DR_START_REG; + input [N_AVG-1:0] AVG_DR_ADDR_REG; + input [N_AVG-1:0] AVG_DR_LEN_REG; + input BUF_START_REG; + input [N_BUF-1:0] BUF_ADDR_REG; + input [N_BUF-1:0] BUF_LEN_REG; + input BUF_DR_START_REG; + input [N_BUF-1:0] BUF_DR_ADDR_REG; + input [N_BUF-1:0] BUF_DR_LEN_REG; + + input [N_WGT-1:0] WGT_DW_ADDR_REG; + input WGT_DW_START_REG; + + + ////////////////////// + // Internal signals // + ////////////////////// + + wire trigger_resync; + + wire [2*B-1 : 0] s_axis_filtered_tdata; + wire s_axis_filtered_tvalid; + + + ////////////////// + // Architecture // + ////////////////// + + // trigger_resync + synchronizer_n + #( + .N (2) + ) + trigger_resync_i ( + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + + matched_filter + #( + .N (N_WGT), + .B (B) + ) + matchfilt_i + ( + .clk (s_axis_aclk), + + .write_rstn (s_axi_aresetn), + .write_clk (s_axi_aclk), + + .trigger_i (trigger_resync), + .trigger_o (trigger_dsp_latency_compensated), + + .s_axis_tready(s1_axis_tready), + .s_axis_tvalid(s1_axis_tvalid), + .s_axis_tdata(s1_axis_tdata), + + .din_valid_i (s_axis_tvalid), + .din_i (s_axis_tdata), + + .dout_valid_o (s_axis_filtered_tvalid), + .dout_o (s_axis_filtered_tdata), + + .DW_ADDR_REG(WGT_DW_ADDR_REG), + .WE_REG(WGT_DW_START_REG), + .LEN_REG(AVG_LEN_REG) + ); + + + // Average block. + avg_top + #( + .N (N_AVG ), + .B (B ) + ) + avg_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_dsp_latency_compensated ), + + // Data input. + .din_valid_i (s_axis_filtered_tvalid ), + .din_i (s_axis_filtered_tdata ), + + // Reset and clock for M_AXIS_* + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for register output. + .m1_axis_tvalid (m2_axis_tvalid ), + .m1_axis_tready (m2_axis_tready ), + .m1_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .DR_START_REG (AVG_DR_START_REG ), + .DR_ADDR_REG (AVG_DR_ADDR_REG ), + .DR_LEN_REG (AVG_DR_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ) + ); + + // Buffer block. + buffer_top + #( + .N (N_BUF ), + .B (B ) + ) + buffer_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_dsp_latency_compensated ), + + // Data input. + .din_valid_i (s_axis_filtered_tvalid ), + .din_i (s_axis_filtered_tdata ), + + // AXIS Master for output. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_tvalid (m1_axis_tvalid ), + .m_axis_tready (m1_axis_tready ), + .m_axis_tdata (m1_axis_tdata ), + .m_axis_tlast (m1_axis_tlast ), + + // Registers. + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .DR_START_REG (BUF_DR_START_REG ), + .DR_ADDR_REG (BUF_DR_ADDR_REG ), + .DR_LEN_REG (BUF_DR_LEN_REG ) + ); + + // Assign outputs. + assign s_axis_tready = 1'b1; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/avg_top.v b/firmware/ip/axis_weighted_buffer/src/avg_top.v new file mode 100644 index 000000000..e33028872 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg_top.v @@ -0,0 +1,248 @@ +module avg_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Reset and clock for M_AXIS_* + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for register output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [4*B-1:0] m1_axis_tdata; + + input AVG_START_REG; + input [N-1:0] AVG_ADDR_REG; + input [31:0] AVG_LEN_REG; + input DR_START_REG; + input [N-1:0] DR_ADDR_REG; + input [N-1:0] DR_LEN_REG; + input AVG_PHOTON_MODE_REG; + input [B-1:0] AVG_H_THRSH_REG; + input [B-1:0] AVG_L_THRSH_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + + wire mem_envelope_wea; + wire [N-1:0] mem_envelope_addra, mem_envelope_addrb; + wire [4*B-1:0] mem_envelope_dia, mem_envelope_dob; + + wire mem_we_int; + wire [N-1:0] mem_addra_int, mem_addrb_int; + wire [4*B-1:0] mem_di_int, mem_do_int; + + wire AVG_START_REG_resync; + wire DR_START_REG_resync; + + wire fifo_empty; + + ////////////////// + // Architecture // + ////////////////// + + // AVG_START_REG_resync + synchronizer_n + #( + .N (2) + ) + AVG_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (AVG_START_REG ), + .data_out (AVG_START_REG_resync ) + ); + + // DR_START_REG_resync + synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + + // Average block. + avg + #( + .N (N), + .B (B) + ) + avg_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_valid_i (din_valid_i ), + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (AVG_START_REG_resync ), + .ADDR_REG (AVG_ADDR_REG ), + .LEN_REG (AVG_LEN_REG ), + .PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .H_THRSH_REG (AVG_H_THRSH_REG ), + .L_THRSH_REG (AVG_L_THRSH_REG ) + ); + + + // Dual port BRAM. + bram_dp + #( + .N (N ), + .B (4*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + + // Data reader. + data_reader + #( + .N (N ), + .B (4*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m0_axis_tdata ), + .dready (m0_axis_tready ), + .dvalid (m0_axis_tvalid ), + .dlast (m0_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + + // Output data register (dc fifo to cross domain). + fifo_dc_axi_xpm + #( + // Data width. + .B (4*B ), + + // Fifo depth. + .N (16 ) + ) + fifo_i + ( + .wr_rstn (rstn ), + .wr_clk (clk ), + + .rd_rstn (m_axis_aresetn ), + .rd_clk (m_axis_aclk ), + + // Write I/F. + .wr_en (mem_we_int ), + .din (mem_di_int ), + + // Read I/F. + .rd_en (m1_axis_tready ), + .dout (m1_axis_tdata ), + + // Flags. + .full ( ), + .empty (fifo_empty ) + ); + + // Assign outputs. + assign m1_axis_tvalid = ~fifo_empty; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..5653a7928 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..4ca178885 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..b7ba98a42 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", 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axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc new file mode 100644 index 000000000..bb1ff41ee --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name aclk [get_ports aclk] + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt new file mode 100755 index 000000000..967c3dc43 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt @@ -0,0 +1,198 @@ +2023.1: + * Version 1.1 (Rev. 14) + * Revision change in one or more subcores + +2022.2.2: + * Version 1.1 (Rev. 13) + * No changes + +2022.2.1: + * Version 1.1 (Rev. 13) + * No changes + +2022.2: + * Version 1.1 (Rev. 13) + * Revision change in one or more subcores + +2022.1.2: + * Version 1.1 (Rev. 12) + * No changes + +2022.1.1: + * Version 1.1 (Rev. 12) + * No changes + +2022.1: + * Version 1.1 (Rev. 12) + * General: bug fix, + * Revision change in one or more subcores + +2021.2.2: + * Version 1.1 (Rev. 11) + * No changes + +2021.2.1: + * Version 1.1 (Rev. 11) + * No changes + +2021.2: + * Version 1.1 (Rev. 11) + * General: Run time enhancements, fix + * General: Fixed systemC model, unbound aresetn port - fix + * Revision change in one or more subcores + +2021.1.1: + * Version 1.1 (Rev. 10) + * No changes + +2021.1: + * Version 1.1 (Rev. 10) + * General: added external process traffic generation support using XTLM IPC for SystemC Models + * Revision change in one or more subcores + +2020.3: + * Version 1.1 (Rev. 9) + * Revision change in one or more subcores + +2020.2.2: + * Version 1.1 (Rev. 8) + * No changes + +2020.2.1: + * Version 1.1 (Rev. 8) + * No changes + +2020.2: + * Version 1.1 (Rev. 8) + * General: added new feature + * Revision change in one or more subcores + +2020.1.1: + * Version 1.1 (Rev. 7) + * No changes + +2020.1: + * Version 1.1 (Rev. 7) + * General: added new feature + * Revision change in one or more subcores + +2019.2.2: + * Version 1.1 (Rev. 6) + * No changes + +2019.2.1: + * Version 1.1 (Rev. 6) + * No changes + +2019.2: + * Version 1.1 (Rev. 6) + * General: update example design for portable + * Revision change in one or more subcores + +2019.1.3: + * Version 1.1 (Rev. 5) + * No changes + +2019.1.2: + * Version 1.1 (Rev. 5) + * No changes + +2019.1.1: + * Version 1.1 (Rev. 5) + * No changes + +2019.1: + * Version 1.1 (Rev. 5) + * General: update to have has_size + * Revision change in one or more subcores + +2018.3.1: + * Version 1.1 (Rev. 4) + * No changes + +2018.3: + * Version 1.1 (Rev. 4) + * General: update QOS in user interface tcl to match AXI meta-data in IPI + * Revision change in one or more subcores + +2018.2: + * Version 1.1 (Rev. 3) + * General: fixed typo in example design stimulus + * Revision change in one or more subcores + +2018.1: + * Version 1.1 (Rev. 2) + * General: updated coreinfo.yml,fix + * Revision change in one or more subcores + +2017.4: + * Version 1.1 (Rev. 1) + * General: updated example design + * General: added slv_rd_driver verbosity + * General: modified interface assertion + * Revision change in one or more subcores + +2017.3: + * Version 1.1 + * versionless of package, interface and PC + * Revision change in one or more subcores + +2017.2: + * Version 1.0 (Rev. 2) + * Sub core IP clk_wiz version changed to 5.4 + * Revision change in one or more subcores + +2017.1: + * Version 1.0 (Rev. 1) + * production release + * Revision change in one or more subcores + +2016.4: + * Version 1.0 + * Initial Release + +(c) Copyright 2016 - 2023 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh new file mode 100755 index 000000000..d3d4a0eae --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh @@ -0,0 +1,138 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Generic Functions used by AXI Infrastructure Modules +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// Global Parameters: +// +// Functions: +// +// Tasks: +//-------------------------------------------------------------------------- +/////////////////////////////////////////////////////////////////////////////// +// BEGIN Global Parameters +/////////////////////////////////////////////////////////////////////////////// +localparam G_AXI_AWADDR_INDEX = 0; +localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH; +localparam G_AXI_AWPROT_WIDTH = 3; +localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH; +localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH; +localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH; +localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH; +localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH; +localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH; +localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH; +localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH; +localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH; +localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH; +localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH; +localparam G_AXI_ARADDR_INDEX = 0; +localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH; +localparam G_AXI_ARPROT_WIDTH = 3; +localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH; +localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH; +localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH; +localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH; +localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH; +localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH; +localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH; +localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH; +localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH; +localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH; +localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH; +// Write channel widths +localparam G_AXI_WDATA_INDEX = 0; +localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH; +localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8; +localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH; +localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH; +localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH; +localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH; +localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH; +// Write Response channel Widths +localparam G_AXI_BRESP_INDEX = 0; +localparam G_AXI_BRESP_WIDTH = 2; +localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH; +localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH; +localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH; +localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH; +// Read channel widths +localparam G_AXI_RDATA_INDEX = 0; +localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH; +localparam G_AXI_RRESP_WIDTH = 2; +localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH; +localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH; +localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH; +localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH; +localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v new file mode 100755 index 000000000..d6ec7f819 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v @@ -0,0 +1,670 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axis to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axi2vector # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + + // payloads + output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, + output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, + input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, + output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, + input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; +assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; + +assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; +assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; + +assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; + +assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; +assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; + +assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; +assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; + assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; + assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; + assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; + assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; + assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; + assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; + + assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; + end + else begin : gen_no_axi3_wid_packing + end + + assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; + + assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; + assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; + assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; + assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; + assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; + assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; + assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; + + assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; + assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; + assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; + end + else begin : gen_no_region_signals + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; + assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; + assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; + assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; + assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; + end + else begin : gen_no_user_signals + assign s_axi_buser = 'b0; + assign s_axi_ruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign s_axi_bid = 'b0; + assign s_axi_buser = 'b0; + + assign s_axi_rlast = 1'b1; + assign s_axi_rid = 'b0; + assign s_axi_ruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + +// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Description: SRL based FIFO for AXIS/AXI Channels. +//-------------------------------------------------------------------------- + + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axic_srl_fifo #( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter C_FAMILY = "virtex7", + parameter integer C_PAYLOAD_WIDTH = 1, + parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + input wire aclk, // Clock + input wire aresetn, // Reset + input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data + input wire s_valid, // Input data valid + output reg s_ready, // Input data ready + output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data + output reg m_valid, // Output data valid + input wire m_ready // Output data ready +); +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +// ceiling logb2 +function integer f_clogb2 (input integer size); + integer s; + begin + s = size; + s = s - 1; + for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) + s = s >> 1; + end +endfunction // clogb2 + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// +localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// +reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; +wire [4-1:0] fifo_addr; +wire push; +wire pop ; +reg areset_r1; + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +always @(posedge aclk) begin + areset_r1 <= ~aresetn; +end + +always @(posedge aclk) begin + if (~aresetn) begin + fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; + end + else begin + fifo_index <= push & ~pop ? fifo_index + 1'b1 : + ~push & pop ? fifo_index - 1'b1 : + fifo_index; + end +end + +assign push = s_valid & s_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + s_ready <= 1'b0; + end + else begin + s_ready <= areset_r1 ? 1'b1 : + push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : + ~push & pop ? 1'b1 : + s_ready; + end +end + +assign pop = m_valid & m_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + m_valid <= 1'b0; + end + else begin + m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : + push & ~pop ? 1'b1 : + m_valid; + end +end + +generate + if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr + assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; + end + else begin : gen_fifo_addr + assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + end +endgenerate + + +generate + genvar i; + for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit + SRL16E + u_srl_fifo( + .Q ( m_payload[i] ) , + .A0 ( fifo_addr[0] ) , + .A1 ( fifo_addr[1] ) , + .A2 ( fifo_addr[2] ) , + .A3 ( fifo_addr[3] ) , + .CE ( push ) , + .CLK ( aclk ) , + .D ( s_payload[i] ) + ); + end +endgenerate + +endmodule + +`default_nettype wire + + +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axi to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_vector2axi # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + + // Slave Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + + // Slave Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + + // Slave Interface Read Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + + // Slave Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + + // payloads + input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, + input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, + output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, + input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, + output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; +assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; + +assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; +assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; + +assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; + +assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; +assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; + +assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; +assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; + assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; + assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; + assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; + assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; + assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; + assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; + + assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; + end + else begin : gen_no_axi3_wid_packing + assign m_axi_wid = 1'b0; + end + + assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; + + assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; + assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; + assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; + assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; + assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; + assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; + assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; + + assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; + assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; + assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; + end + else begin : gen_no_region_signals + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; + assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; + assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; + assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; + assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; + end + else begin : gen_no_user_signals + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_awburst = 'b0; + assign m_axi_awcache = 'b0; + assign m_axi_awlen = 'b0; + assign m_axi_awlock = 'b0; + assign m_axi_awid = 'b0; + assign m_axi_awqos = 'b0; + + assign m_axi_wlast = 1'b1; + assign m_axi_wid = 'b0; + + + assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_arburst = 'b0; + assign m_axi_arcache = 'b0; + assign m_axi_arlen = 'b0; + assign m_axi_arlock = 'b0; + assign m_axi_arid = 'b0; + assign m_axi_arqos = 'b0; + + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv new file mode 100755 index 000000000..589cf878f --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv @@ -0,0 +1,633 @@ +// (c) Copyright 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// AXI VIP wrapper +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// axi_vip +// +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_vip_v1_1_14_top # + ( + parameter C_AXI_PROTOCOL = 0, + parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_WDATA_WIDTH = 32, + parameter integer C_AXI_RDATA_WIDTH = 32, + parameter integer C_AXI_WID_WIDTH = 0, + parameter integer C_AXI_RID_WIDTH = 0, + parameter integer C_AXI_AWUSER_WIDTH = 0, + parameter integer C_AXI_ARUSER_WIDTH = 0, + parameter integer C_AXI_WUSER_WIDTH = 0, + parameter integer C_AXI_RUSER_WIDTH = 0, + parameter integer C_AXI_BUSER_WIDTH = 0, + parameter integer C_AXI_SUPPORTS_NARROW = 1, + parameter integer C_AXI_HAS_BURST = 1, + parameter integer C_AXI_HAS_LOCK = 1, + parameter integer C_AXI_HAS_CACHE = 1, + parameter integer C_AXI_HAS_REGION = 1, + parameter integer C_AXI_HAS_PROT = 1, + parameter integer C_AXI_HAS_QOS = 1, + parameter integer C_AXI_HAS_WSTRB = 1, + parameter integer C_AXI_HAS_BRESP = 1, + parameter integer C_AXI_HAS_RRESP = 1, + parameter integer C_AXI_HAS_ARESETN = 1 + ) + ( + //NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE + //Please refer xgui tcl and coreinfo.yml + + // System Signals + input wire aclk, + input wire aclken, + input wire aresetn, + + // Slave Interface Write Address Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Slave Interface Write Data Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Slave Interface Write Response Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Slave Interface Read Address Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Slave Interface Read Data Ports + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // Master Interface Write Address Port + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Master Interface Write Data Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Master Interface Write Response Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Master Interface Read Address Port + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid, + output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Master Interface Read Data Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready + ); + + /********************************************************************************************** + * NOTE: + * C_AXI_INTERFACE_MODE =0 -- MASTER MODE, + * C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE + * C_AXI_INTERFACE_MODE =2 -- SLAVE MODE + * Please refer xgui tcl and coreinfo.yml + * User can change PASS_THROUGH VIP to run time master mode or run time slave mode during + * the simulation + *********************************************************************************************/ + + /********************************************************************************************** + * Master_mode means that either the dut is statically being configured to be in master mode + * or it statically being configured to be pass-through mode and switched to be in master mode + * in run time. + + * Slave mode means that either the dut is statically being configured to be in slave mode + * or it statically being configured to be pass-through mode and switched to be in slave mode + * in run time. + + * Pass-through mode means that either the dut is statically being configured to be in + * pass-through mode or it statically being configured to be pass-through mode and switched + * to be in master/slave mode and then switch back to be in pass-through mode in run time + *********************************************************************************************/ + + logic runtime_master =0; + logic runtime_slave =0; + + wire run_slave_mode; + wire run_master_mode; + wire run_passth_mode; + wire compile_master_mode; + wire compile_slave_mode; + wire master_mode; + wire slave_mode; + + assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0); + assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0; + assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0); + + assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ; + assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ; + + assign master_mode = compile_master_mode || run_master_mode; + assign slave_mode = compile_slave_mode || run_slave_mode; + + // Slave Interface Write Address Ports Internal + assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}}; + assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}}; + assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}}; + assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}}; + assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}}; + assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}}; + assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}}; + assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}}; + assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz}; + assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0}; + + // Slave Interface Write Data Ports + assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}}; + assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}}; + assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz}; + assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}}; + assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz}; + assign s_axi_wready = slave_mode? IF.WREADY : {1'b0}; + + // Slave Interface Write Response Ports + assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}}; + assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}}; + assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}}; + assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}}; + + // Slave Interface Read Address Ports + assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ; + assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}}; + assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}}; + assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}}; + assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}}; + assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ; + assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}}; + assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}}; + assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz}; + assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0}; + + //Slave Interface Read Data Ports + assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}}; + assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}}; + assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}}; + assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}}; + assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}}; + assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}}; + + // Master Interface Write Address Port + assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}}; + assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}}; + assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}}; + assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}}; + assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}}; + assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}}; + assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}}; + assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0}; + assign IF.AWREADY = master_mode? m_axi_awready :{1'bz}; + + // Master Interface Write Data Ports Internal + assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}}; + assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}}; + assign m_axi_wlast = master_mode? IF.WLAST : {1'b0}; + assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}}; + assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0}; + assign IF.WREADY = master_mode? m_axi_wready : {1'bz}; + + // Master Interface Write Response Ports Internal + assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}}; + assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}}; + assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz; + assign m_axi_bready = master_mode? IF.BREADY : 1'b0; + + // Master Interface Read Address Port Internal + assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}}; + assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}}; + assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}}; + assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}}; + assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}}; + assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}}; + assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}}; + assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0}; + assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}}; + + // Master Interface Read Data Ports Internal + assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}}; + assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}}; + assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}}; + assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}}; + assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}}; + assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}}; + + axi_vip_if #( + .C_AXI_PROTOCOL(C_AXI_PROTOCOL), + .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ), + .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ), + .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ), + .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ), + .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), + .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), + .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ), + .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ), + .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ), + .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ), + .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW), + .C_AXI_HAS_BURST(C_AXI_HAS_BURST), + .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK), + .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE), + .C_AXI_HAS_REGION(C_AXI_HAS_REGION), + .C_AXI_HAS_PROT(C_AXI_HAS_PROT), + .C_AXI_HAS_QOS(C_AXI_HAS_QOS), + .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB), + .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP), + .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP), + .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN) + ) IF ( + .ACLK(aclk), + .ARESET_N(aresetn), + .ACLKEN(aclken) + ); + + + //synthesis translate_off + initial begin + $display("XilinxAXIVIP: Found at Path: %m"); + end + + //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode + generate + initial begin + if(C_AXI_INTERFACE_MODE ==0) begin + IF.set_intf_master; + end else if(C_AXI_INTERFACE_MODE ==2) begin + IF.set_intf_slave; + end else if(C_AXI_INTERFACE_MODE ==1) begin + $display("This AXI VIP is in passthrough mode"); + end else begin + $fatal(0,"This AXI VIP's mode is out of range"); + end + end + endgenerate + + /* + Function: set_passthrough_mode + Sets AXI VIP passthrough into run time passthrough mode + */ + function void set_passthrough_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 0; + IF.set_intf_monitor(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction: set_passthrough_mode + + /* + Function: set_master_mode + Sets AXI VIP passthrough into run time master mode + */ + function void set_master_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 1; + runtime_slave = 0; + IF.set_intf_master(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP "); + end + endfunction : set_master_mode + + /* + Function: set_slave_mode + Sets AXI VIP passthrough into run time slave mode + */ + function void set_slave_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 1; + IF.set_intf_slave(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction : set_slave_mode + + /* + Function: set_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 1 + */ + function void set_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 1; + endfunction + + /* + Function: clr_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 0 + */ + function void clr_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 0; + endfunction + + /* + Function: set_max_aw_wait_cycles (not available in VIVADO Simulator) + Sets max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_aw_wait_cycles(input integer unsigned new_num); + IF.PC.max_aw_wait_cycles = new_num; + endfunction : set_max_aw_wait_cycles + + /* + Function: set_max_ar_wait_cycles (not available in VIVADO Simulator) + Sets max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_ar_wait_cycles(input integer unsigned new_num); + IF.PC.max_ar_wait_cycles = new_num; + endfunction : set_max_ar_wait_cycles + + /* + Function: set_max_r_wait_cycles (not available in VIVADO Simulator) + Sets max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_r_wait_cycles(input integer unsigned new_num); + IF.PC.max_r_wait_cycles = new_num; + endfunction : set_max_r_wait_cycles + + /* + Function: set_max_b_wait_cycles (not available in VIVADO Simulator) + Sets max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_b_wait_cycles(input integer unsigned new_num); + IF.PC.max_b_wait_cycles = new_num; + endfunction : set_max_b_wait_cycles + + /* + Function: set_max_w_wait_cycles (not available in VIVADO Simulator) + Sets max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_w_wait_cycles(input integer unsigned new_num); + IF.PC.max_w_wait_cycles = new_num; + endfunction : set_max_w_wait_cycles + + /* + Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator) + Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlast_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlast_to_awvalid_wait_cycles = new_num; + endfunction : set_max_wlast_wait_cycles + + /* + Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_rtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_rtransfers_wait_cycles = new_num; + endfunction : set_max_rtransfers_wait_cycles + + /* + Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_wtransfers_wait_cycles = new_num; + endfunction : set_max_wtransfers_wait_cycles + + /* + Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlcmd_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlcmd_wait_cycles = new_num; + endfunction : set_max_wlcmd_wait_cycles + + /* + Function: get_max_aw_wait_cycles (not available in VIVADO Simulator) + Returns max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_aw_wait_cycles(); + return(IF.PC.max_aw_wait_cycles); + endfunction : get_max_aw_wait_cycles + + /* + Function: get_max_ar_wait_cycles (not available in VIVADO Simulator) + Returns max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_ar_wait_cycles(); + return(IF.PC.max_ar_wait_cycles); + endfunction : get_max_ar_wait_cycles + + /* + Function: get_max_r_wait_cycles (not available in VIVADO Simulator) + Returns max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_r_wait_cycles(); + return(IF.PC.max_r_wait_cycles); + endfunction : get_max_r_wait_cycles + + /* + Function: get_max_b_wait_cycles (not available in VIVADO Simulator) + Returns max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_b_wait_cycles(); + return(IF.PC.max_b_wait_cycles); + endfunction : get_max_b_wait_cycles + + /* + Function: get_max_w_wait_cycles (not available in VIVADO Simulator) + Returns max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_w_wait_cycles(); + return(IF.PC.max_w_wait_cycles); + endfunction :get_max_w_wait_cycles + + /* + Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator) + Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlast_wait_cycles(); + return(IF.PC.max_wlast_to_awvalid_wait_cycles); + endfunction :get_max_wlast_wait_cycles + + /* + Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_rtransfers_wait_cycles(); + return(IF.PC.max_rtransfers_wait_cycles); + endfunction :get_max_rtransfers_wait_cycles + + /* + Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wtransfers_wait_cycles(); + return(IF.PC.max_wtransfers_wait_cycles); + endfunction :get_max_wtransfers_wait_cycles + + /* + Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlcmd_wait_cycles(); + return(IF.PC.max_wlcmd_wait_cycles); + endfunction :get_max_wlcmd_wait_cycles + + /* + Function: set_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1 + */ + function void set_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 1; + endfunction : set_fatal_to_warnings + + /* + Function: clr_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0 + */ + function void clr_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 0; + endfunction : clr_fatal_to_warnings + //synthesis translate_on + +endmodule // axi_vip_v1_1_14_top + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv new file mode 100755 index 000000000..3aebc6b1f --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv @@ -0,0 +1,257 @@ +// (c) Copyright 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// AXI VIP wrapper +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// axi_vip +// +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_vip_v1_1_14_top # + ( + parameter C_AXI_PROTOCOL = 0, + parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_WDATA_WIDTH = 32, + parameter integer C_AXI_RDATA_WIDTH = 32, + parameter integer C_AXI_WID_WIDTH = 0, + parameter integer C_AXI_RID_WIDTH = 0, + parameter integer C_AXI_AWUSER_WIDTH = 0, + parameter integer C_AXI_ARUSER_WIDTH = 0, + parameter integer C_AXI_WUSER_WIDTH = 0, + parameter integer C_AXI_RUSER_WIDTH = 0, + parameter integer C_AXI_BUSER_WIDTH = 0, + parameter integer C_AXI_SUPPORTS_NARROW = 1, + parameter integer C_AXI_HAS_BURST = 1, + parameter integer C_AXI_HAS_LOCK = 1, + parameter integer C_AXI_HAS_CACHE = 1, + parameter integer C_AXI_HAS_REGION = 1, + parameter integer C_AXI_HAS_PROT = 1, + parameter integer C_AXI_HAS_QOS = 1, + parameter integer C_AXI_HAS_WSTRB = 1, + parameter integer C_AXI_HAS_BRESP = 1, + parameter integer C_AXI_HAS_RRESP = 1, + parameter integer C_AXI_HAS_ARESETN = 1 + ) + ( + //NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE + //Please refer xgui tcl and coreinfo.yml + + // System Signals + input wire aclk, + input wire aclken, + input wire aresetn, + + // Slave Interface Write Address Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Slave Interface Write Data Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Slave Interface Write Response Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Slave Interface Read Address Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Slave Interface Read Data Ports + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // Master Interface Write Address Port + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Master Interface Write Data Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Master Interface Write Response Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Master Interface Read Address Port + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Master Interface Read Data Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready + ); + + assign s_axi_awready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_awready ; + assign s_axi_wready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_wready; + assign s_axi_bid = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}}:m_axi_bid; + assign s_axi_bresp = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_bresp; + assign s_axi_buser = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH {1'b0}} :m_axi_buser; + assign s_axi_bvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_bvalid; + assign s_axi_arready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_arready; + assign s_axi_rid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}}:m_axi_rid; + assign s_axi_rdata = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RDATA_WIDTH==0?1:C_AXI_RDATA_WIDTH {1'b0}} :m_axi_rdata; + assign s_axi_rresp = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rresp; + assign s_axi_rlast = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rlast ; + assign s_axi_ruser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH {1'b0}} :m_axi_ruser; + assign s_axi_rvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rvalid ; + + assign m_axi_awid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}} :s_axi_awid; + assign m_axi_awaddr = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_ADDR_WIDTH==0?1:C_AXI_ADDR_WIDTH {1'b0}} :s_axi_awaddr ; + assign m_axi_awlen = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 4 : 8) {1'b0}} :s_axi_awlen; + assign m_axi_awsize = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_awsize; + assign m_axi_awburst = (C_AXI_INTERFACE_MODE != 1) ? 2'b0 :s_axi_awburst; + assign m_axi_awlock = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 2 : 1) {1'b0}} :s_axi_awlock; + assign m_axi_awcache = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awcache; + assign m_axi_awprot = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_awprot; + assign m_axi_awregion = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awregion; + assign m_axi_awqos = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awqos ; + assign m_axi_awuser = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH {1'b0}} :s_axi_awuser; + assign m_axi_awvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_awvalid; + assign m_axi_wid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}} :s_axi_wid ; + assign m_axi_wdata = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WDATA_WIDTH==0?1:C_AXI_WDATA_WIDTH {1'b0}} :s_axi_wdata; + assign m_axi_wstrb = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WDATA_WIDTH==0?1:C_AXI_WDATA_WIDTH/8 {1'b0}} :s_axi_wstrb; + assign m_axi_wlast = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_wlast; + assign m_axi_wuser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH {1'b0}} :s_axi_wuser; + assign m_axi_wvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_wvalid; + assign m_axi_bready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_bready ; + assign m_axi_arid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH {1'b0}} :s_axi_arid; + assign m_axi_araddr = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_ADDR_WIDTH==0?1:C_AXI_ADDR_WIDTH {1'b0}} :s_axi_araddr; + assign m_axi_arlen = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 4 : 8) {1'b0}} :s_axi_arlen; + assign m_axi_arsize = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_arsize; + assign m_axi_arburst = (C_AXI_INTERFACE_MODE != 1) ? 2'b0 :s_axi_arburst; + assign m_axi_arlock = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 1 : 1) {1'b0}} :s_axi_arlock; + assign m_axi_arcache = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arcache; + assign m_axi_arprot = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_arprot; + assign m_axi_arregion = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arregion; + assign m_axi_arqos = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arqos; + assign m_axi_aruser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH {1'b0}} : s_axi_aruser; + assign m_axi_arvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_arvalid ; + assign m_axi_rready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_rready; + + +endmodule // axi_vip_v1_1_14_top + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp new file mode 100644 index 000000000..411b87541 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp @@ -0,0 +1,582 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#include "axi_mst_0_sc.h" + +#include "axi_mst_0.h" + +#include "axi_vip.h" + +#include +#include + + + + + +#ifdef XILINX_SIMULATOR +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // Instantiate Socket Stubs + + // configure M_AXI_transactor + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // initialize transactors stubs + M_AXI_transactor_initiator_wr_socket_stub = nullptr; + M_AXI_transactor_initiator_rd_socket_stub = nullptr; + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + + } + else + { + M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0); + M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket)); + M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0); + M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_M_AXI_transactor->disable_transactor(); + } + +} + +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // Instantiate Socket Stubs + + // configure M_AXI_transactor + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // initialize transactors stubs + M_AXI_transactor_initiator_wr_socket_stub = nullptr; + M_AXI_transactor_initiator_rd_socket_stub = nullptr; + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + + } + else + { + M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0); + M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket)); + M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0); + M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_M_AXI_transactor->disable_transactor(); + } + +} + +#endif // MTI_SYSTEMC + + + + +axi_mst_0::~axi_mst_0() +{ + delete mp_M_AXI_transactor; + +} + +#ifdef MTI_SYSTEMC +SC_MODULE_EXPORT(axi_mst_0); +#endif + +#ifdef XM_SYSTEMC +XMSC_MODULE_EXPORT(axi_mst_0); +#endif + +#ifdef RIVIERA +SC_MODULE_EXPORT(axi_mst_0); +#endif + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h new file mode 100644 index 000000000..f3001bf79 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h @@ -0,0 +1,330 @@ +#ifndef IP_AXI_MST_0_H_ +#define IP_AXI_MST_0_H_ + +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "axi_mst_0_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +#include "utils/xtlm_aximm_initiator_stub.h" + +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + + // Transactor stubs + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub; + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub; + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +#include "utils/xtlm_aximm_initiator_stub.h" + +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + + // Transactor stubs + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub; + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub; + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_AXI_MST_0_H_ diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv new file mode 100644 index 000000000..7a6cbf044 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv @@ -0,0 +1,246 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axi_mst_0 ( + aclk, + aresetn, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [31 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [3 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [31 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B\ +ITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(2), + .C_AXI_INTERFACE_MODE(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_WDATA_WIDTH(32), + .C_AXI_RDATA_WIDTH(32), + .C_AXI_WID_WIDTH(0), + .C_AXI_RID_WIDTH(0), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(0), + .C_AXI_HAS_BURST(0), + .C_AXI_HAS_LOCK(0), + .C_AXI_HAS_CACHE(0), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(0), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) inst ( + .aclk(aclk), + .aclken(1'B1), + .aresetn(aresetn), + .s_axi_awid(1'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B1), + .s_axi_awlock(1'B0), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'B0), + .s_axi_awready(), + .s_axi_wid(1'B0), + .s_axi_wdata(32'B0), + .s_axi_wstrb(4'HF), + .s_axi_wlast(1'B0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'B0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'B0), + .s_axi_arid(1'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B1), + .s_axi_arlock(1'B0), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arregion(4'B0), + .s_axi_arqos(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'B0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'B0), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(1'B0), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'B0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(1'B0), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(1'B0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv new file mode 100644 index 000000000..33345d8b4 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv @@ -0,0 +1,69 @@ +/////////////////////////////////////////////////////////////////////////// +//NOTE: This file has been automatically generated by Vivado. +/////////////////////////////////////////////////////////////////////////// +`timescale 1ps/1ps +package axi_mst_0_pkg; +import axi_vip_pkg::*; +/////////////////////////////////////////////////////////////////////////// +// These parameters are named after the component for use in your verification +// environment. +/////////////////////////////////////////////////////////////////////////// + parameter axi_mst_0_VIP_PROTOCOL = 2; + parameter axi_mst_0_VIP_READ_WRITE_MODE = "READ_WRITE"; + parameter axi_mst_0_VIP_INTERFACE_MODE = 0; + parameter axi_mst_0_VIP_ADDR_WIDTH = 32; + parameter axi_mst_0_VIP_DATA_WIDTH = 32; + parameter axi_mst_0_VIP_ID_WIDTH = 0; + parameter axi_mst_0_VIP_AWUSER_WIDTH = 0; + parameter axi_mst_0_VIP_ARUSER_WIDTH = 0; + parameter axi_mst_0_VIP_RUSER_WIDTH = 0; + parameter axi_mst_0_VIP_WUSER_WIDTH = 0; + parameter axi_mst_0_VIP_BUSER_WIDTH = 0; + parameter axi_mst_0_VIP_SUPPORTS_NARROW = 0; + parameter axi_mst_0_VIP_HAS_BURST = 0; + parameter axi_mst_0_VIP_HAS_LOCK = 0; + parameter axi_mst_0_VIP_HAS_CACHE = 0; + parameter axi_mst_0_VIP_HAS_REGION = 0; + parameter axi_mst_0_VIP_HAS_QOS = 0; + parameter axi_mst_0_VIP_HAS_PROT = 1; + parameter axi_mst_0_VIP_HAS_WSTRB = 1; + parameter axi_mst_0_VIP_HAS_BRESP = 1; + parameter axi_mst_0_VIP_HAS_RRESP = 1; + parameter axi_mst_0_VIP_HAS_ACLKEN = 0; + parameter axi_mst_0_VIP_HAS_ARESETN = 1; +/////////////////////////////////////////////////////////////////////////// +typedef axi_mst_agent #(axi_mst_0_VIP_PROTOCOL, + axi_mst_0_VIP_ADDR_WIDTH, + axi_mst_0_VIP_DATA_WIDTH, + axi_mst_0_VIP_DATA_WIDTH, + axi_mst_0_VIP_ID_WIDTH, + axi_mst_0_VIP_ID_WIDTH, + axi_mst_0_VIP_AWUSER_WIDTH, + axi_mst_0_VIP_WUSER_WIDTH, + axi_mst_0_VIP_BUSER_WIDTH, + axi_mst_0_VIP_ARUSER_WIDTH, + axi_mst_0_VIP_RUSER_WIDTH, + axi_mst_0_VIP_SUPPORTS_NARROW, + axi_mst_0_VIP_HAS_BURST, + axi_mst_0_VIP_HAS_LOCK, + axi_mst_0_VIP_HAS_CACHE, + axi_mst_0_VIP_HAS_REGION, + axi_mst_0_VIP_HAS_PROT, + axi_mst_0_VIP_HAS_QOS, + axi_mst_0_VIP_HAS_WSTRB, + axi_mst_0_VIP_HAS_BRESP, + axi_mst_0_VIP_HAS_RRESP, + axi_mst_0_VIP_HAS_ARESETN) axi_mst_0_mst_t; + +/////////////////////////////////////////////////////////////////////////// +// How to start the verification component +/////////////////////////////////////////////////////////////////////////// +// axi_mst_0_mst_t axi_mst_0_mst; +// initial begin : START_axi_mst_0_MASTER +// axi_mst_0_mst = new("axi_mst_0_mst", `axi_mst_0_PATH_TO_INTERFACE); +// axi_mst_0_mst.start_master(); +// end + + + +endpackage : axi_mst_0_pkg diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp new file mode 100644 index 000000000..7c931c666 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp @@ -0,0 +1,102 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#include "axi_mst_0_sc.h" + +#include "axi_vip.h" + +#include +#include + +axi_mst_0_sc::axi_mst_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL) +{ + // configure connectivity manager + xsc::utils::xsc_sim_manager::addInstance("axi_mst_0", this); + + // initialize module + xsc::common_cpp::properties model_param_props; + model_param_props.addLong("C_AXI_PROTOCOL", "2"); + model_param_props.addLong("C_AXI_INTERFACE_MODE", "0"); + model_param_props.addLong("C_AXI_ADDR_WIDTH", "32"); + model_param_props.addLong("C_AXI_WDATA_WIDTH", "32"); + model_param_props.addLong("C_AXI_RDATA_WIDTH", "32"); + model_param_props.addLong("C_AXI_WID_WIDTH", "0"); + model_param_props.addLong("C_AXI_RID_WIDTH", "0"); + model_param_props.addLong("C_AXI_AWUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_ARUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_WUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_RUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_BUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_SUPPORTS_NARROW", "0"); + model_param_props.addLong("C_AXI_HAS_BURST", "0"); + model_param_props.addLong("C_AXI_HAS_LOCK", "0"); + model_param_props.addLong("C_AXI_HAS_CACHE", "0"); + model_param_props.addLong("C_AXI_HAS_REGION", "0"); + model_param_props.addLong("C_AXI_HAS_PROT", "1"); + model_param_props.addLong("C_AXI_HAS_QOS", "0"); + model_param_props.addLong("C_AXI_HAS_WSTRB", "1"); + model_param_props.addLong("C_AXI_HAS_BRESP", "1"); + model_param_props.addLong("C_AXI_HAS_RRESP", "1"); + model_param_props.addLong("C_AXI_HAS_ARESETN", "1"); + model_param_props.addString("COMPONENT_NAME", "axi_mst_0"); + + mp_impl = new axi_vip("inst", model_param_props); + + // initialize AXI sockets + M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket; + M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket; +} + +axi_mst_0_sc::~axi_mst_0_sc() +{ + xsc::utils::xsc_sim_manager::clean(); + + delete mp_impl; +} + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h new file mode 100644 index 000000000..5820d4b74 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h @@ -0,0 +1,96 @@ +#ifndef IP_AXI_MST_0_SC_H_ +#define IP_AXI_MST_0_SC_H_ + +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class axi_vip; + +class DllExport axi_mst_0_sc : public sc_core::sc_module +{ +public: + + axi_mst_0_sc(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0_sc(); + + // module socket-to-socket AXI TLM interfaces + + xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket; + xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket; + + // module socket-to-socket TLM interfaces + + +protected: + + axi_vip* mp_impl; + +private: + + axi_mst_0_sc(const axi_mst_0_sc&); + const axi_mst_0_sc& operator=(const axi_mst_0_sc&); + +}; + +#endif // IP_AXI_MST_0_SC_H_ diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv new file mode 100644 index 000000000..ba8eb44b8 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv @@ -0,0 +1,121 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +//------------------------------------------------------------------------------------ +// Filename: axi_mst_0_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// +//------------------------------------------------------------------------------------ +`timescale 1ps/1ps + +`ifdef XILINX_SIMULATOR + +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module axi_mst_0 ( + input bit_as_bool aclk, + input bit_as_bool aresetn, + output bit [31 : 0] m_axi_awaddr, + output bit [2 : 0] m_axi_awprot, + output bit_as_bool m_axi_awvalid, + input bit_as_bool m_axi_awready, + output bit [31 : 0] m_axi_wdata, + output bit [3 : 0] m_axi_wstrb, + output bit_as_bool m_axi_wvalid, + input bit_as_bool m_axi_wready, + input bit [1 : 0] m_axi_bresp, + input bit_as_bool m_axi_bvalid, + output bit_as_bool m_axi_bready, + output bit [31 : 0] m_axi_araddr, + output bit [2 : 0] m_axi_arprot, + output bit_as_bool m_axi_arvalid, + input bit_as_bool m_axi_arready, + input bit [31 : 0] m_axi_rdata, + input bit [1 : 0] m_axi_rresp, + input bit_as_bool m_axi_rvalid, + output bit_as_bool m_axi_rready +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module axi_mst_0 (aclk,aresetn,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready) +(* integer foreign = "SystemC"; +*); + input bit aclk; + input bit aresetn; + output wire [31 : 0] m_axi_awaddr; + output wire [2 : 0] m_axi_awprot; + output wire m_axi_awvalid; + input bit m_axi_awready; + output wire [31 : 0] m_axi_wdata; + output wire [3 : 0] m_axi_wstrb; + output wire m_axi_wvalid; + input bit m_axi_wready; + input bit [1 : 0] m_axi_bresp; + input bit m_axi_bvalid; + output wire m_axi_bready; + output wire [31 : 0] m_axi_araddr; + output wire [2 : 0] m_axi_arprot; + output wire m_axi_arvalid; + input bit m_axi_arready; + input bit [31 : 0] m_axi_rdata; + input bit [1 : 0] m_axi_rresp; + input bit m_axi_rvalid; + output wire m_axi_rready; +endmodule +`endif diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv new file mode 100644 index 000000000..e238f2d35 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv @@ -0,0 +1,248 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +(* X_CORE_INFO = "axi_vip_v1_1_14_top,Vivado 2023.1" *) +(* CHECK_LICENSE_TYPE = "axi_mst_0,axi_vip_v1_1_14_top,{}" *) +(* CORE_GENERATION_INFO = "axi_mst_0,axi_vip_v1_1_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vip,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_PROTOCOL=2,C_AXI_INTERFACE_MODE=0,C_AXI_ADDR_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_AXI_RDATA_WIDTH=32,C_AXI_WID_WIDTH=0,C_AXI_RID_WIDTH=0,C_AXI_AWUSER_WIDTH=0,C_AXI_ARUSER_WIDTH=0,C_AXI_WUSER_WIDTH=0,C_AXI_RUSER_WIDTH=0,C_AXI_BUSER_WIDTH=0,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_BURST=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_C\ +ACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=1,C_AXI_HAS_QOS=0,C_AXI_HAS_WSTRB=1,C_AXI_HAS_BRESP=1,C_AXI_HAS_RRESP=1,C_AXI_HAS_ARESETN=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axi_mst_0 ( + aclk, + aresetn, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [31 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [3 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [31 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B\ +ITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(2), + .C_AXI_INTERFACE_MODE(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_WDATA_WIDTH(32), + .C_AXI_RDATA_WIDTH(32), + .C_AXI_WID_WIDTH(0), + .C_AXI_RID_WIDTH(0), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(0), + .C_AXI_HAS_BURST(0), + .C_AXI_HAS_LOCK(0), + .C_AXI_HAS_CACHE(0), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(0), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) inst ( + .aclk(aclk), + .aclken(1'B1), + .aresetn(aresetn), + .s_axi_awid(1'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B1), + .s_axi_awlock(1'B0), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'B0), + .s_axi_awready(), + .s_axi_wid(1'B0), + .s_axi_wdata(32'B0), + .s_axi_wstrb(4'HF), + .s_axi_wlast(1'B0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'B0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'B0), + .s_axi_arid(1'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B1), + .s_axi_arlock(1'B0), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arregion(4'B0), + .s_axi_arqos(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'B0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'B0), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(1'B0), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'B0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(1'B0), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(1'B0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp new file mode 100755 index 000000000..dfa25ea80 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp @@ -0,0 +1,140 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "axi_vip.h" +#include + +axi_vip::axi_vip(sc_core::sc_module_name module_name, + xsc::common_cpp::properties model_param_props) : + sc_module(module_name), S_TARGET_rd_socket(nullptr), S_TARGET_wr_socket( + nullptr), M_INITIATOR_rd_socket(nullptr), M_INITIATOR_wr_socket( + nullptr), P1(nullptr), P2(nullptr), m_ipc_master(nullptr), m_ipc_slave( + nullptr) +{ + int int_type = model_param_props.getLongLong("C_AXI_INTERFACE_MODE"); + if (int_type == 1) + { + M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_rd_socket", 32); + M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_wr_socket", 32); + S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket( + "target_rd_socket", 32); + S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket( + "target_wr_socket", 32); + P1 = new xtlm::xtlm_aximm_passthru_module("P1"); + P2 = new xtlm::xtlm_aximm_passthru_module("P2"); + P1->initiator_socket->bind(*M_INITIATOR_rd_socket); + P2->initiator_socket->bind(*M_INITIATOR_wr_socket); + S_TARGET_rd_socket->bind(*(P1->target_socket)); + S_TARGET_wr_socket->bind(*(P2->target_socket)); + } + if (int_type == 0) + { + if (std::getenv("ENABLE_XTLM_IPC_IN_VIP") == nullptr) + { + M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_rd_socket", 32); + M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_wr_socket", 32); + auto *stubWr = new xtlm::xtlm_aximm_initiator_stub("ifWrStubskt0", + 32); + stubWr->initiator_socket->bind(*M_INITIATOR_wr_socket); + auto *stubRd = new xtlm::xtlm_aximm_initiator_stub("ifRdStubskt0", + 32); + stubRd->initiator_socket->bind(*M_INITIATOR_rd_socket); + stubInitSkt.push_back(stubWr); + stubInitSkt.push_back(stubRd); + } + else + { + m_ipc_master = new sim_ipc_aximm_master(this->name(), + model_param_props); + M_INITIATOR_rd_socket = m_ipc_master->rd_socket; + M_INITIATOR_wr_socket = m_ipc_master->wr_socket; + m_ipc_master->m_aximm_aclk(aclk); + m_ipc_master->m_aximm_aresetn(aresetn); + } + } + if (int_type == 2) + { + if (std::getenv("ENABLE_XTLM_IPC_IN_VIP") == nullptr) + { + S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket( + "target_rd_socket", 32); + S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket( + "target_wr_socket", 32); + auto *stubWr = new xtlm::xtlm_aximm_target_stub("ifWrStubskt0", 32); + S_TARGET_wr_socket->bind(stubWr->target_socket); + auto *stubRd = new xtlm::xtlm_aximm_target_stub("ifRdStubskt0", 32); + S_TARGET_rd_socket->bind(stubRd->target_socket); + stubTargetSkt.push_back(stubWr); + stubTargetSkt.push_back(stubRd); + } + else + { + m_ipc_slave = new sim_ipc_aximm_slave(this->name(), + model_param_props); + S_TARGET_rd_socket = m_ipc_slave->rd_socket; + S_TARGET_wr_socket = m_ipc_slave->wr_socket; + m_ipc_slave->s_aximm_aclk(aclk); + m_ipc_slave->s_aximm_aresetn(aresetn); + } + } +} +axi_vip::~axi_vip() +{ + delete M_INITIATOR_wr_socket; + delete M_INITIATOR_rd_socket; + delete S_TARGET_wr_socket; + delete S_TARGET_rd_socket; + delete P1; + delete P2; + delete m_ipc_master; + delete m_ipc_slave; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h new file mode 100644 index 000000000..b11098ef2 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h @@ -0,0 +1,81 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include +#include "utils/xtlm_aximm_target_stub.h" +#include "utils/xtlm_aximm_initiator_stub.h" +#include +#include +#include "sim_ipc_aximm_master.h" +#include "sim_ipc_aximm_slave.h" + +class axi_vip: public sc_core::sc_module +{ +public: + axi_vip(sc_core::sc_module_name module_name, + xsc::common_cpp::properties model_param_props); + virtual ~axi_vip(); + SC_HAS_PROCESS (axi_vip); + xtlm::xtlm_aximm_target_socket *S_TARGET_rd_socket; + xtlm::xtlm_aximm_target_socket *S_TARGET_wr_socket; + xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_rd_socket; + xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_wr_socket; + std::vector stubTargetSkt; + std::vector stubInitSkt; + sc_core::sc_in aclk; + sc_core::sc_in aresetn; +private: + xtlm::xtlm_aximm_passthru_module *P1; + xtlm::xtlm_aximm_passthru_module *P2; + sim_ipc_aximm_master* m_ipc_master; + sim_ipc_aximm_slave* m_ipc_slave; + +}; + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp new file mode 100755 index 000000000..59bf57a2e --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp @@ -0,0 +1,144 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "sim_ipc_aximm_master.h" +using namespace xtlm; + +sim_ipc_aximm_master::sim_ipc_aximm_master(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts):sc_module(name), + rd_util(sc_gen_unique_name("rd_util"),xtlm::aximm::TRANSACTION,0), + wr_util(sc_gen_unique_name("wr_util"),xtlm::aximm::TRANSACTION,0), + m_logger((std::string) name) +{ + rd_socket = new xtlm::xtlm_aximm_initiator_socket( + sc_gen_unique_name("rd_socket"), 0); + wr_socket = new xtlm::xtlm_aximm_initiator_socket( + sc_gen_unique_name("wr_socket"), 0); + + //TODO Supporting outstanding transactions + rd_util.rd_socket.bind(*rd_socket); + wr_util.wr_socket.bind(*wr_socket); + + m_ipc2aximm_socket = new xsc::ipc2aximm_socket( + sc_gen_unique_name("ipc2aximm_socket"), get_ipi_name(this->name())); + + SC_METHOD(ipc2aximm_receive); + sensitive << m_ipc2aximm_socket->event(); + sensitive << wr_util.resp_available; + sensitive << rd_util.data_available; + //As of now only 1 outstanding transaction is supported. + //If we support more, this may need to be updated. + dont_initialize(); + + SC_METHOD(send_response); + sensitive << wr_util.resp_available; + sensitive << rd_util.data_available; + dont_initialize(); +} + +sim_ipc_aximm_master::~sim_ipc_aximm_master() +{ + delete m_ipc2aximm_socket; + delete rd_socket; + delete wr_socket; +} + +void sim_ipc_aximm_master::ipc2aximm_receive() +{ + if(!m_ipc2aximm_socket->peek_payload()) + return; + + if (wr_util.is_slave_ready() && + (m_ipc2aximm_socket->peek_payload()->get_command() + == xtlm::XTLM_WRITE_COMMAND)) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Write Request", DEBUG); + //We Can do transaction on Write Channel + wr_util.send_transaction(*m_ipc2aximm_socket->get_payload(), delay); + + } + + //Don't proceed further if there's no transaction + if (!m_ipc2aximm_socket->peek_payload()) + return; + + if (rd_util.is_slave_ready() + && (m_ipc2aximm_socket->peek_payload()->get_command() + == xtlm::XTLM_READ_COMMAND)) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Read Request", DEBUG); + rd_util.send_transaction(*m_ipc2aximm_socket->get_payload(), delay); + } +} + +void sim_ipc_aximm_master::send_response() +{ + if(wr_util.is_resp_available()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Write Response", DEBUG); + m_ipc2aximm_socket->send_response(wr_util.get_resp()); + } + if(rd_util.is_data_available()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Read Response", DEBUG); + m_ipc2aximm_socket->send_response(rd_util.get_data()); + } +} + +std::string sim_ipc_aximm_master::get_ipi_name(std::string s) +{ + s = s.substr(0, s.find_last_of("./")); // Adding "/" to support QUESTA + s = s.substr(s.find_last_of("./") + 1); + return s; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h new file mode 100755 index 000000000..6691a81e2 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include "xtlm.h" +#include "ipc2aximm_socket.h" +#include + +class sim_ipc_aximm_master : public sc_core::sc_module +{ +public: + SC_HAS_PROCESS(sim_ipc_aximm_master); + + sim_ipc_aximm_master(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts); + + ~sim_ipc_aximm_master(); + + sc_core::sc_in m_aximm_aresetn; + sc_core::sc_in m_aximm_aclk; + + //Read & Write Sockets + xtlm::xtlm_aximm_initiator_socket* rd_socket; + xtlm::xtlm_aximm_initiator_socket* wr_socket; + + xtlm::xtlm_aximm_initiator_rd_socket_util rd_util; + xtlm::xtlm_aximm_initiator_wr_socket_util wr_util; +private: + //! SystemC Method to Read incoming data from ipc... + void ipc2aximm_receive(); + void send_response(); + std::string get_ipi_name(std::string s); + + xsc::ipc2aximm_socket* m_ipc2aximm_socket; + xsc::common_cpp::report_handler m_logger; +}; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp new file mode 100755 index 000000000..1a9dad1e8 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp @@ -0,0 +1,134 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "sim_ipc_aximm_slave.h" + +sim_ipc_aximm_slave::sim_ipc_aximm_slave(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts) : + sc_module(name), + rd_util(sc_gen_unique_name("rd_util"),xtlm::aximm::TRANSACTION,0), + wr_util(sc_gen_unique_name("wr_util"),xtlm::aximm::TRANSACTION,0), + m_logger(static_cast(name)) +{ + rd_socket = new xtlm::xtlm_aximm_target_socket( + sc_gen_unique_name("rd_socket"), 0); + wr_socket = new xtlm::xtlm_aximm_target_socket( + sc_gen_unique_name("wr_socket"), 0); + wr_socket->bind(wr_util.wr_socket); + rd_socket->bind(rd_util.rd_socket); + + m_aximm2ipc_socket = new xsc::aximm2ipc_socket("aximm2ipc_socket", + get_ipi_name(this->name())); + + SC_METHOD(aximm2ipc_send); + sensitive << wr_util.transaction_available; + sensitive << rd_util.transaction_available; + m_aximm2ipc_socket->event(); + dont_initialize(); + + SC_METHOD(aximm_resp_handler); + sensitive << m_aximm2ipc_socket->event(); + sensitive << wr_util.transaction_available; + sensitive << rd_util.transaction_available; + dont_initialize(); +} + +sim_ipc_aximm_slave::~sim_ipc_aximm_slave() +{ + delete m_aximm2ipc_socket; +} + +void sim_ipc_aximm_slave::aximm2ipc_send() +{ + if(wr_util.is_trans_available() && m_aximm2ipc_socket->is_ready()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Write Request", DEBUG); + m_aximm2ipc_socket->transport(wr_util.get_transaction()); + } + if(rd_util.is_trans_available() && m_aximm2ipc_socket->is_ready()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Read Request", DEBUG); + m_aximm2ipc_socket->transport(rd_util.get_transaction()); + } +} + +void sim_ipc_aximm_slave::aximm_resp_handler() +{ + //if there's no payload response. Return + if(!m_aximm2ipc_socket->peek_resp()) + return; + if (wr_util.is_master_ready() + && m_aximm2ipc_socket->peek_resp()->get_command() + == xtlm::XTLM_WRITE_COMMAND) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Write Response", DEBUG); + wr_util.send_resp(*m_aximm2ipc_socket->get_resp(),delay); + } + //if there's no payload response. Return + if(!m_aximm2ipc_socket->peek_resp()) + return; + + if(rd_util.is_master_ready() && m_aximm2ipc_socket->peek_resp()->get_command() == xtlm::XTLM_READ_COMMAND) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Read Data", DEBUG); + rd_util.send_data(*m_aximm2ipc_socket->get_resp(), delay); + } +} + +std::string sim_ipc_aximm_slave::get_ipi_name(std::string s) +{ + s = s.substr(0, s.find_last_of("./")); // Adding "/" to support QUESTA + s = s.substr(s.find_last_of("./") + 1); + return s; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h new file mode 100755 index 000000000..74bd633fb --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include "xtlm.h" +#include "aximm2ipc_socket.h" + +class sim_ipc_aximm_slave : public sc_core::sc_module +{ +public: + SC_HAS_PROCESS(sim_ipc_aximm_slave); + sim_ipc_aximm_slave(sc_core::sc_module_name name, + xsc::common_cpp::properties& ppts); + ~sim_ipc_aximm_slave(); + + sc_core::sc_in s_aximm_aclk; + sc_core::sc_in s_aximm_aresetn; + + xtlm::xtlm_aximm_target_socket* rd_socket; + xtlm::xtlm_aximm_target_socket* wr_socket; + + xtlm::xtlm_aximm_target_rd_socket_util rd_util; + xtlm::xtlm_aximm_target_wr_socket_util wr_util; + +private: + //! SystemC method to send the AXIMM data to external process + void aximm2ipc_send(); + + //! SystemC Method to handle AXIMM Response + void aximm_resp_handler(); + + std::string get_ipi_name(std::string s); + + xsc::aximm2ipc_socket* m_aximm2ipc_socket; + xsc::common_cpp::report_handler m_logger; +}; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd b/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd new file mode 100644 index 000000000..8621d437a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd @@ -0,0 +1,544 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + AVG_START_REG : out std_logic; + AVG_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_LEN_REG : out std_logic_vector (31 downto 0); + AVG_PHOTON_MODE_REG : out std_logic; + AVG_H_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_L_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_DR_START_REG: out std_logic; + AVG_DR_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_DR_LEN_REG : out std_logic_vector (31 downto 0); + BUF_START_REG : out std_logic; + BUF_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_LEN_REG : out std_logic_vector (31 downto 0); + BUF_DR_START_REG: out std_logic; + BUF_DR_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_DR_LEN_REG : out std_logic_vector (31 downto 0); + WGT_DW_ADDR_REG : out std_logic_vector (31 downto 0); + WGT_DW_START_REG: out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + + -- Output Registers. + AVG_START_REG <= slv_reg0(0); + AVG_ADDR_REG <= slv_reg1; + AVG_LEN_REG <= slv_reg2; + AVG_DR_START_REG <= slv_reg3(0); + AVG_DR_ADDR_REG <= slv_reg4; + AVG_DR_LEN_REG <= slv_reg5; + BUF_START_REG <= slv_reg0(1); + BUF_ADDR_REG <= slv_reg6; + BUF_LEN_REG <= slv_reg7; + BUF_DR_START_REG <= slv_reg3(1); + BUF_DR_ADDR_REG <= slv_reg8; + BUF_DR_LEN_REG <= slv_reg9; + AVG_PHOTON_MODE_REG <= slv_reg10(0); + AVG_H_THRSH_REG <= slv_reg11; + AVG_L_THRSH_REG <= slv_reg12; + WGT_DW_ADDR_REG <= slv_reg13; + WGT_DW_START_REG <= slv_reg3(2); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v b/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v new file mode 100644 index 000000000..7967dde20 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v @@ -0,0 +1,299 @@ +// AXIS AVG BUFFER. +// s_axi_aclk : clock for s_axi_* +// s_axis_aclk : clock for s_axis_* +// m_axis_aclk : clock for m0_axis_* and m1_axis_* +// +module axis_weighted_buffer + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Trigger input. + trigger , + + // AXIS Slave for memory programming + s1_axis_tvalid, + s1_axis_tdata, + s1_axis_tready, + + // AXIS Slave for input data. + s_axis_aclk , + s_axis_aresetn , + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0 and m1. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata + ); + + /**************/ + /* Parameters */ + /**************/ + // Memory depth. + parameter N_AVG = 14; + parameter N_BUF = 14; + parameter N_WGT = 14; + + // Number of bits. + parameter B = 16; + + /*********/ + /* Ports */ + /*********/ + input s_axi_aclk; + input s_axi_aresetn; + + input [5:0] s_axi_awaddr; + input [2:0] s_axi_awprot; + input s_axi_awvalid; + output s_axi_awready; + + input [31:0] s_axi_wdata; + input [3:0] s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + + output [1:0] s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + + input [5:0] s_axi_araddr; + input [2:0] s_axi_arprot; + input s_axi_arvalid; + output s_axi_arready; + + output [31:0] s_axi_rdata; + output [1:0] s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + + input trigger; + + input s_axis_aclk; + input s_axis_aresetn; + input s_axis_tvalid; + output s_axis_tready; + input [2*B-1:0] s_axis_tdata; + + input s1_axis_tvalid; + output s1_axis_tready; + input [2*B-1:0] s1_axis_tdata; + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [2*B-1:0] m1_axis_tdata; + output m1_axis_tlast; + + output m2_axis_tvalid; + input m2_axis_tready; + output [4*B-1:0] m2_axis_tdata; + + + /********************/ + /* Internal signals */ + /********************/ + // Registers. + wire AVG_START_REG; + wire [N_AVG-1:0] AVG_ADDR_REG; + wire [31:0] AVG_LEN_REG; + wire AVG_PHOTON_MODE_REG; + wire [B-1:0] AVG_H_THRSH_REG; + wire [B-1:0] AVG_L_THRSH_REG; + wire AVG_DR_START_REG; + wire [N_AVG-1:0] AVG_DR_ADDR_REG; + wire [N_AVG-1:0] AVG_DR_LEN_REG; + wire BUF_START_REG; + wire [N_BUF-1:0] BUF_ADDR_REG; + wire [N_BUF-1:0] BUF_LEN_REG; + wire BUF_DR_START_REG; + wire [N_BUF-1:0] BUF_DR_ADDR_REG; + wire [N_BUF-1:0] BUF_DR_LEN_REG; + wire [N_WGT-1:0] WGT_DW_ADDR_REG; + wire WGT_DW_START_REG; + + + + /**********************/ + /* Begin Architecture */ + /**********************/ + // AXI Slave. + axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG ), + .WGT_DW_ADDR_REG (WGT_DW_ADDR_REG ), + .WGT_DW_START_REG (WGT_DW_START_REG) + ); + + // Averager + Buffer Top. + avg_buffer + #( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .N_WGT (N_WGT ), + .B (B ) + ) + avg_buffer_i + ( + // Reset and clock for readout data path + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + + // Reset and clock for writing weights + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for memory programming + .s1_axis_tvalid(s1_axis_tvalid), + .s1_axis_tdata(s1_axis_tdata), + .s1_axis_tready(s1_axis_tready), + + // AXIS Slave for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG[N_AVG-1:0] ), + .AVG_LEN_REG (AVG_LEN_REG[2*B-1:0] ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG[N_BUF-1:0] ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG[B-1:0] ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG[N_AVG-1:0] ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG[N_AVG-1:0] ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG[N_BUF-1:0] ), + .BUF_LEN_REG (BUF_LEN_REG[N_BUF-1:0] ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG[N_BUF-1:0] ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG[N_BUF-1:0] ), + .WGT_DW_ADDR_REG (WGT_DW_ADDR_REG[N_WGT-1:0] ), + .WGT_DW_START_REG (WGT_DW_START_REG) + ); + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/buffer.sv b/firmware/ip/axis_weighted_buffer/src/buffer.sv new file mode 100644 index 000000000..f794cd3b6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/buffer.sv @@ -0,0 +1,174 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module buffer ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input din_valid_i; +input [2*B-1:0] din_i; + +output mem_we_o; +output [N-1:0] mem_addr_o; +output [2*B-1:0] mem_di_o; + +input START_REG; +input [N-1:0] ADDR_REG; +input [N-1:0] LEN_REG; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + MEMW_ST , + WAIT_TRIGGER_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg start_state; +reg trigger_state; +reg memw_state; + +// Counter. +reg [N-1:0] cnt; + +// Registers. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= MEMW_ST; + + MEMW_ST: + if ( cnt == len_r && din_valid_i == 1'b1 ) + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( memw_state == 1'b1 ) begin + if (din_valid_i == 1'b1) + cnt <= cnt + 1; + end + else begin + cnt <= 0; + end + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG - 1; + end + else if ( memw_state == 1'b1 && din_valid_i == 1'b1) begin + addr_r <= addr_r + 1; + end + end +end + +// FSM outputs. +always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + memw_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + MEMW_ST: + memw_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase +end + +// Assign outputs. +assign mem_we_o = memw_state & din_valid_i; +assign mem_addr_o = addr_r; +assign mem_di_o = din_i; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/buffer_top.v b/firmware/ip/axis_weighted_buffer/src/buffer_top.v new file mode 100644 index 000000000..3a5259a92 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/buffer_top.v @@ -0,0 +1,185 @@ +module buffer_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // AXIS Master for output. + m_axis_aclk , + m_axis_aresetn , + m_axis_tvalid , + m_axis_tready , + m_axis_tdata , + m_axis_tlast , + + // Registers. + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 10; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + input m_axis_aclk; + input m_axis_aresetn; + output m_axis_tvalid; + input m_axis_tready; + output [2*B-1:0] m_axis_tdata; + output m_axis_tlast; + + input BUF_START_REG; + input [N-1:0] BUF_ADDR_REG; + input [N-1:0] BUF_LEN_REG; + input DR_START_REG; + input [N-1:0] DR_ADDR_REG; + input [N-1:0] DR_LEN_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + wire mem_we_int; + wire [N-1:0] mem_addra_int, mem_addrb_int; + wire [2*B-1:0] mem_di_int, mem_do_int; + + wire BUF_START_REG_resync; + wire DR_START_REG_resync; + + ////////////////// + // Architecture // + ////////////////// + + // BUF_START_REG_resync + synchronizer_n + #( + .N (2) + ) + BUF_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (BUF_START_REG ), + .data_out (BUF_START_REG_resync ) + ); + + //DR_START_REG_resync + synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + + // Buffer block. + buffer + #( + .N (N), + .B (B) + ) + buffer_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_valid_i (din_valid_i ), + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (BUF_START_REG_resync ), + .ADDR_REG (BUF_ADDR_REG ), + .LEN_REG (BUF_LEN_REG ) + ); + + // Dual port BRAM. + bram_dp + #( + .N (N ), + .B (2*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + + // Data reader. + data_reader + #( + .N (N ), + .B (2*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m_axis_tdata ), + .dready (m_axis_tready ), + .dvalid (m_axis_tvalid ), + .dlast (m_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/data_reader.vhd b/firmware/ip/axis_weighted_buffer/src/data_reader.vhd new file mode 100644 index 000000000..fa640f235 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/data_reader.vhd @@ -0,0 +1,301 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_reader is + Generic + ( + -- Address map of memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic; + ADDR_REG : in std_logic_vector (N-1 downto 0); + LEN_REG : in std_logic_vector (N-1 downto 0) + ); +end entity; + +architecture rtl of data_reader is + +constant NPOW : Integer := 2**N; + +-- Fifo to drive AXI Stream Master I/F. +component fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +type fsm_state is ( INIT_ST, + REGS_ST, + READ_BRAM_ST, + WRITE_FIFO_ST, + -- READ_LAST_ST, + -- WRITE_LAST_ST, + FIFO_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; +signal regs_state : std_logic; +signal read_state : std_logic; +signal write_state : std_logic; +signal fifo_state : std_logic; +signal read_en : std_logic; + +-- Counter for memory address and samples. +signal cnt_wr : unsigned(N-1 downto 0); +signal cnt_rd : unsigned(N-1 downto 0); +signal addr_cnt : unsigned(N-1 downto 0); + +-- Length register. +signal len_r : unsigned(N-1 downto 0); + +-- Fifo signals. +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_din : std_logic_vector (B-1 downto 0); +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +-- Fifo pipeline. +-- signal fifo_dout_r : std_logic_vector (B-1 downto 0); +-- signal fifo_empty_r : std_logic; + +begin + +-- Fifo to drive AXI Stream Master I/F. +fifo_i : fifo_axi + Generic map + ( + -- Data width. + B => B , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => fifo_wr_en , + din => fifo_din , + + -- Read I/F. + rd_en => fifo_rd_en , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections - write +fifo_wr_en <= write_state and not fifo_full; +fifo_din <= mem_dout; + +-- Fifo connections - read +fifo_rd_en <= read_en and not fifo_empty and dready; + +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counter for memory address and samples. + cnt_wr <= (others => '0'); + cnt_rd <= (others => '0'); + addr_cnt <= (others => '0'); + + -- Length register. + len_r <= (others => '0'); + + -- Fifo pipeline. + -- fifo_dout_r <= (others => '0'); + -- fifo_empty_r <= '1'; + else + -- State register. + current_state <= next_state; + + -- Memory address and data. + if ( init_state = '1' ) then + cnt_wr <= (others => '0'); + addr_cnt <= (others => '0'); + len_r <= (others => '0'); + elsif ( regs_state = '1' ) then + cnt_wr <= (others => '0'); + addr_cnt <= unsigned(ADDR_REG); + len_r <= unsigned(LEN_REG); + cnt_rd <= unsigned(LEN_REG)-1; + end if; + if ( read_state = '1' ) then + cnt_wr <= cnt_wr + 1; + end if; + if ( fifo_rd_en = '1' ) then + cnt_rd <= cnt_rd - 1; + end if; + if ( write_state = '1' and fifo_full = '0') then + addr_cnt <= addr_cnt + 1; + end if; + + -- Fifo pipeline. + -- if ( dready = '1' ) then + -- fifo_dout_r <= fifo_dout; + -- fifo_empty_r <= fifo_empty; + -- end if; + + end if; + end if; +end process; + +-- Next state logic. +process (current_state, START_REG, len_r, cnt_wr, fifo_full, cnt_rd, fifo_rd_en) +begin + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= REGS_ST; + end if; + + when REGS_ST => + next_state <= READ_BRAM_ST; + + when READ_BRAM_ST => + next_state <= WRITE_FIFO_ST; + + when WRITE_FIFO_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_FIFO_ST; + elsif ( cnt_wr < len_r ) then + next_state <= READ_BRAM_ST; + else + next_state <= FIFO_ST; + end if; + + -- when READ_LAST_ST => + -- next_state <= WRITE_LAST_ST; + + -- when WRITE_LAST_ST => + -- if ( fifo_full = '1' ) then + -- next_state <= WRITE_LAST_ST; + -- else + -- next_state <= FIFO_ST; + -- end if; + + when FIFO_ST => + if ( cnt_rd = 0 and fifo_rd_en = '1' ) then + next_state <= END_ST; + else + next_state <= FIFO_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin + init_state <= '0'; + regs_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when REGS_ST => + regs_state <= '1'; + + when READ_BRAM_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_FIFO_ST => + write_state <= '1'; + read_en <= '1'; + + -- when READ_LAST_ST => + -- read_state <= '1'; + -- read_en <= '1'; + + -- when WRITE_LAST_ST => + -- write_state <= '1'; + -- read_en <= '1'; + + when FIFO_ST => + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +mem_en <= '1'; +mem_we <= '0'; +mem_addr <= std_logic_vector(addr_cnt); + +dout <= fifo_dout; +dvalid <= fifo_rd_en and dready; +dlast <= '1' when (cnt_rd = 0) else '0'; --fifo_state and fifo_empty; + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/data_writer.vhd b/firmware/ip/axis_weighted_buffer/src/data_writer.vhd new file mode 100644 index 000000000..d7d8046f7 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/data_writer.vhd @@ -0,0 +1,225 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.MATH_REAL.all; +use IEEE.NUMERIC_STD.all; + +entity data_writer is + generic + ( + -- Number of tables. + NT : integer := 16; + -- Address map of each table. + N : integer := 16; + -- Data width. + B : integer := 16 + ); + port + ( + rstn : in std_logic; + clk : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. + constant NT_LOG2 : integer := integer(ceil(log2(real(NT)))); + +-- Synchronizer. + component synchronizer_n is + generic ( + N : integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + +-- State machine. + type fsm_state is (INIT_ST, + READ_START_ADDR_ST, + WAIT_TVALID_ST, + RW_TDATA_ST); + signal state : fsm_state; + + signal read_start_addr_state : std_logic; + signal rw_tdata_state : std_logic; + +-- WE_REG_resync. + signal WE_REG_resync : std_logic; + +-- Axis registers. + signal tready_i : std_logic; + signal tready_r : std_logic; + signal tdata_r : std_logic_vector(B-1 downto 0); + signal tdata_rr : std_logic_vector(B-1 downto 0); + signal tdata_rrr : std_logic_vector(B-1 downto 0); + signal tvalid_r : std_logic; + signal tvalid_rr : std_logic; + signal tvalid_rrr : std_logic; + +-- Memory Enable. + signal mem_en_i : std_logic_vector (NT-1 downto 0); + signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. + signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); + signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); + signal mem_addr_high : unsigned (N-1 downto 0); + signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync + WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn, + clk => clk, + data_in => WE_REG, + data_out => WE_REG_resync + ); + +-- Enable logic generation. + GEN : for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I, mem_addr_low'length) else + '0'; + + end generate GEN; + + process (clk) + begin + if (rising_edge(clk)) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if (read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)), mem_addr_full'length); + elsif (rw_tdata_state = '1') then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; + end process; + +-- Address computation. + mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); + mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. + process (clk) + begin + if (rising_edge(clk)) then + if (rstn = '0') then + state <= INIT_ST; + else + case state is + when INIT_ST => + if (WE_REG_resync = '1') then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if (WE_REG_resync = '1') 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"xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel5_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "sclrd_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclra_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrb_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrconcat_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrc_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrm_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrp_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrsel_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd new file mode 100644 index 000000000..4ecc09ba6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd new file mode 100644 index 000000000..d57aad106 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd new file mode 100644 index 000000000..1494332f6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd new file mode 100644 index 000000000..957362b4f --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd new file mode 100644 index 000000000..e1f76f7f7 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd new file mode 100644 index 000000000..c214faea1 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd new file mode 100644 index 000000000..e23f8af97 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd new file mode 100644 index 000000000..babadc678 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd new file mode 100644 index 000000000..ff87e9d21 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd b/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd new file mode 100644 index 000000000..66025c3c0 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd @@ -0,0 +1,279 @@ +------------------------------------------------------------------------------- +-- Title : Matched Filter Time-Domain Multiplier +-- Project : +------------------------------------------------------------------------------- +-- File : matched_filter.vhd +-- Author : +-- Company : +-- Created : 2025-02-27 +-- Last update: 2025-03-03 +-- Platform : +-- Standard : VHDL'08 +------------------------------------------------------------------------------- +-- Description: Stores filter envelope and processes DSP +-- Inputs are single precision (B), outputs double (2*B) +------------------------------------------------------------------------------- +-- Copyright (c) 2025 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2025-02-27 1.0 javierc Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity matched_filter is + generic ( + B : natural := 16; + N : natural := 10 + ); + port ( + -- clock+reset for readout data path + clk : in std_logic; + + -- clock+reset for writing weights + write_rstn : in std_logic; + write_clk : in std_logic; + + trigger_i : in std_logic; + trigger_o : out std_logic; + + -- AXIS programming interface from DMA + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Input and output readout streams + din_valid_i : in std_logic; + din_i : in std_logic_vector(2*B-1 downto 0); + dout_o : out std_logic_vector(2*B-1 downto 0); + dout_valid_o : out std_logic; + + -- Configuration registers + -- active length of the weights buffer (how many samples of incoming data will be weighted) + LEN_REG : in std_logic_vector (31 downto 0); + -- data writer start address and write-enable + DW_ADDR_REG : in std_logic_vector(31 downto 0); + WE_REG : in std_logic + ); +end matched_filter; + +architecture rtl of matched_filter is + signal mem_envelope_wea, mem_envelope_ena : std_logic := '0'; + signal mem_envelope_addra : std_logic_vector(N-1 downto 0); + signal mem_envelope_addrb : std_logic_vector(31 downto 0); + signal mem_envelope_dia : std_logic_vector(2*B-1 downto 0); + signal envelope_iq : std_logic_vector(2*B-1 downto 0); + signal envelope_iq_r : std_logic_vector(2*B-1 downto 0); + signal envelope_ii, envelope_qq : std_logic_vector (B-1 downto 0); + + signal ac, bd, ad, bc : std_logic_vector(47 downto 0); + signal ac_signed, bd_signed, ad_signed, bc_signed : signed(2*B-1 downto 0); + + signal din_ii, din_qq : std_logic_vector(B-1 downto 0); + signal filt_ii, filt_qq : std_logic_vector(2*B-1 downto 0); + signal filt_ii_quant, filt_qq_quant : std_logic_vector(B-1 downto 0); + signal filt_ii_quant_r, filt_qq_quant_r : std_logic_vector(B-1 downto 0); + + -- Higher precision + signal dfiltered_ii, dfiltered_qq : std_logic_vector (2*N-1 downto 0); + + -- Compensate memory latency for data + constant WGT_LATENCY : natural := 4; + -- Compensate DSP latency for trigger & valid + constant DSP_LATENCY : natural := 3; + + type reg_t is array (WGT_LATENCY-1 downto 0) of std_logic_vector (2*B-1 downto 0); + signal din_reg : reg_t; + + signal trigger_reg : std_logic_vector(0 to WGT_LATENCY+DSP_LATENCY-1); + signal dout_valid_reg : std_logic_vector(0 to WGT_LATENCY+DSP_LATENCY-1); + + -- Read address + signal cnt : unsigned (31 downto 0) := to_unsigned(0, 32); + signal length : unsigned (31 downto 0) := to_unsigned(0, 32); + + type fsm_state is (INIT_ST, + WAIT_ST, + READ_ST); + signal state : fsm_state; + + component dsp_macro_0 + port ( + CLK : in std_logic; + CE : in std_logic; + A : in std_logic_vector(B-1 downto 0); + B : in std_logic_vector(B-1 downto 0); + C : in std_logic_vector(47 downto 0); + P : out std_logic_vector(47 downto 0) + ); + end component; +begin + + data_writer_i : entity work.data_writer + generic map ( + NT => 1, + N => N, + B => 2*B) + port map ( + rstn => write_rstn, + clk => write_clk, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tvalid => s_axis_tvalid, + mem_en(0) => mem_envelope_ena, + mem_we => mem_envelope_wea, + mem_addr => mem_envelope_addra, + mem_di => mem_envelope_dia, + START_ADDR_REG => DW_ADDR_REG, + WE_REG => WE_REG); + + bram_envelope_iq : entity work.bram_dp + generic map ( + N => N, + B => 2*B) + port map ( + clka => write_clk, + clkb => clk, + ena => '1', + enb => '1', + wea => mem_envelope_wea, + web => '0', + addra => mem_envelope_addra, + addrb => mem_envelope_addrb(N-1 downto 0), + dia => mem_envelope_dia, + dib => (others => '0'), + doa => open, + dob => envelope_iq); + + + matched_filter_mult_ac : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_ii, + B => envelope_ii, + C => (others => '0'), + P => ac + ); + + matched_filter_mult_bd : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_qq, + B => envelope_qq, + C => (others => '0'), + P => bd + ); + + matched_filter_mult_ad : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_ii, + B => envelope_qq, + C => (others => '0'), + P => ad + ); + + matched_filter_mult_bc : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_qq, + B => envelope_ii, + C => (others => '0'), + P => bc + ); + + latency_compensation : process (clk) is + variable i : integer; + begin + if (rising_edge(clk)) then + din_reg(0) <= din_i; + trigger_reg(0) <= trigger_i; + dout_valid_reg(0) <= din_valid_i; + for i in 1 to WGT_LATENCY-1 loop + din_reg(i) <= din_reg(i-1); + end loop; + for i in 1 to WGT_LATENCY+DSP_LATENCY-1 loop + trigger_reg(i) <= trigger_reg(i-1); + dout_valid_reg(i) <= dout_valid_reg(i-1); + end loop; + end if; + end process; + + proc_read_addr : process(clk) is + begin + if (rising_edge(clk)) then + if (state = READ_ST) then + if (din_valid_i = '1') then + cnt <= cnt + 1; + end if; + else + cnt <= to_unsigned(0, 32); + end if; + end if; + end process; + + proc_state : process (clk) is + begin + if (rising_edge(clk)) then + case state is + when INIT_ST => + state <= WAIT_ST; + when WAIT_ST => + if (trigger_i = '1') then + state <= READ_ST; + end if; + + when READ_ST => + if (cnt > length) then + state <= INIT_ST; + end if; + end case; + end if; + end process; + + reg_output : process(clk) is + begin + if (rising_edge(clk)) then + envelope_iq_r <= envelope_iq; + filt_ii_quant_r <= filt_ii_quant; + filt_qq_quant_r <= filt_qq_quant; + end if; + end process; + + din_ii <= din_reg(WGT_LATENCY-1)(2*B-1 downto B); + din_qq <= din_reg(WGT_LATENCY-1)(B-1 downto 0); + + trigger_o <= trigger_reg(WGT_LATENCY+DSP_LATENCY - 1); + dout_valid_o <= dout_valid_reg(WGT_LATENCY+DSP_LATENCY - 1); + + mem_envelope_addrb <= std_logic_vector(cnt); + envelope_ii <= envelope_iq_r(2*B-1 downto B); + envelope_qq <= envelope_iq_r(B-1 downto 0); + + + ac_signed <= signed(ac(2*B-1 downto 0)); + bd_signed <= signed(bd(2*B-1 downto 0)); + ad_signed <= signed(ad(2*B-1 downto 0)); + bc_signed <= signed(bc(2*B-1 downto 0)); + + filt_ii <= std_logic_vector(ac_signed - bd_signed); + filt_qq <= std_logic_vector(ad_signed + bc_signed); + + -- Keep only MSBs + filt_ii_quant <= filt_ii(2*B-1 downto B); + filt_qq_quant <= filt_qq(2*B-1 downto B); + + dout_o(2*B-1 downto B) <= filt_ii_quant_r; + dout_o(B-1 downto 0) <= filt_qq_quant_r; + + length <= unsigned(LEN_REG); + + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/outreg.sv b/firmware/ip/axis_weighted_buffer/src/outreg.sv new file mode 100644 index 000000000..d35357ab6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/outreg.sv @@ -0,0 +1,113 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module outreg ( + // Reset and clock. + rstn , + clk , + + // Data input. + wen , + din , + + // M_AXIS. + m_axis_tdata , + m_axis_tready , + m_axis_tvalid + ); + +//////////////// +// Parameters // +//////////////// +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input wen; +input [B-1:0] din; + +output [B-1:0] m_axis_tdata; +input m_axis_tready; +output m_axis_tvalid; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { WAIT_IN_ST , + READ_IN_ST , + WRITE_OUT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Data register. +reg [B-1:0] din_r; + +reg din_en_i; +reg valid_i; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= WAIT_IN_ST; + + // Data register. + din_r <= 0; + end + else begin + // State register. + case (state) + WAIT_IN_ST: + if ( wen == 1'b1) + state <= READ_IN_ST; + + READ_IN_ST: + if ( wen == 1'b0 ) + state <= WRITE_OUT_ST; + + WRITE_OUT_ST: + if ( m_axis_tready == 1'b1 ) + state <= WAIT_IN_ST; + endcase + + // Data register. + if (din_en_i == 1'b1) + din_r <= din; + end +end + +// FSM outputs. +always_comb begin + // Default. + din_en_i = 0; + valid_i = 0; + + case (state) + //WAIT_IN_ST: + + READ_IN_ST: + din_en_i = 1'b1; + + WRITE_OUT_ST: + valid_i = 1'b1; + endcase +end + +// Assign outputs. +assign m_axis_tdata = din_r; +assign m_axis_tvalid = valid_i; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd b/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd new file mode 100644 index 000000000..a29bd9be1 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt b/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt new file mode 100644 index 000000000..301691a09 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt @@ -0,0 +1,10000 @@ +16392,0 +3219,0 +-15142,0 +-9091,0 +11604,0 +13648,0 +-6276,0 +-16068,0 +11,0 +16054,0 +6273,0 +-13649,0 +-11616,0 +9106,0 +15132,0 +-3192,0 +-16399,0 +-3234,0 +15152,0 +9107,0 +-11593,0 +-13656,0 +6261,0 +16068,0 +-33,0 +-16070,0 +-6267,0 +13617,0 +11569,0 +-9125,0 +-15134,0 +3218,0 +16370,0 +3175,0 +-15157,0 +-9123,0 +11589,0 +13654,0 +-6280,0 +-16043,0 +-18,0 +16062,0 +6261,0 +-13626,0 +-11596,0 +9094,0 +15131,0 +-3187,0 +-16385,0 +-3199,0 +15154,0 +9090,0 +-11588,0 +-13611,0 +6289,0 +16084,0 +14,0 +-16091,0 +-6292,0 +13607,0 +11584,0 +-9127,0 +-15153,0 +3189,0 +16375,0 +3200,0 +-15147,0 +-9130,0 +11565,0 +13630,0 +-6269,0 +-16083,0 +-9,0 +16060,0 +6282,0 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interfase. + reg s_axi_aclk; + reg s_axi_aresetn; + wire [5:0] s_axi_araddr; + wire [2:0] s_axi_arprot; + wire s_axi_arready; + wire s_axi_arvalid; + wire [5:0] s_axi_awaddr; + wire [2:0] s_axi_awprot; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; + wire [31:0] s_axi_rdata; + wire s_axi_rready; + wire [1:0] s_axi_rresp; + wire s_axi_rvalid; + wire [31:0] s_axi_wdata; + wire s_axi_wready; + wire [3:0] s_axi_wstrb; + wire s_axi_wvalid; + + reg trigger; + + + reg s_axis_aclk; + reg s_axis_aresetn; + reg s_axis_tvalid; + wire s_axis_tready; + reg [2*B-1:0] s_axis_tdata; + + // From DMA + reg s1_axis_tvalid; + wire s1_axis_tready; + reg [2*B-1:0] s1_axis_tdata; + + reg m_axis_aclk; + reg m_axis_aresetn; + + wire m0_axis_tvalid; + reg m0_axis_tready; + wire [4*B-1:0] m0_axis_tdata; + wire m0_axis_tlast; + + wire m1_axis_tvalid; + reg m1_axis_tready; + wire [2*B-1:0] m1_axis_tdata; + wire m1_axis_tlast; + + wire m2_axis_tvalid; + reg m2_axis_tready; + wire [4*B-1:0] m2_axis_tdata; + + // AXI VIP master address. + xil_axi_ulong avg_start_reg = 0; + xil_axi_ulong avg_addr_reg = 1; + xil_axi_ulong avg_len_reg = 2; + xil_axi_ulong avg_dr_start_reg = 3; + xil_axi_ulong avg_dr_addr_reg = 4; + xil_axi_ulong avg_dr_len_reg = 5; + xil_axi_ulong buf_start_reg = 6; + xil_axi_ulong buf_addr_reg = 7; + xil_axi_ulong buf_len_reg = 8; + xil_axi_ulong buf_dr_start_reg = 9; + xil_axi_ulong buf_dr_addr_reg = 10; + xil_axi_ulong buf_dr_len_reg = 11; + xil_axi_ulong filter_start_addr_reg = 15; + + xil_axi_prot_t prot = 0; + reg[31:0] data_wr = 32'h12345678; + reg[31:0] data; + xil_axi_resp_t resp; + + // Test bench control. + reg tb_load_mem = 0; + reg tb_load_mem_done = 0; + reg tb_input = 0; + reg tb_input_done = 0; + + // axi_mst_0. + axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + axis_weighted_buffer + # + ( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .B (B ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for input data. + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Slave for memory programming + .s1_axis_tvalid(s1_axis_tvalid), + .s1_axis_tdata(s1_axis_tdata), + .s1_axis_tready(s1_axis_tready), + + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ) + ); + + // VIP Agents + axi_mst_0_mst_t axi_mst_0_agent; + + // Main TB Control. + initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s_axis_aresetn <= 0; + m_axis_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + m2_axis_tready <= 1; + trigger <= 0; + #500; + s_axi_aresetn <= 1; + s_axis_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + $display("##############"); + $display("### Test 0 ###"); + $display("##############"); + $display("t = %0t", $time); + // Average/buffer: + // * addr = 0. + // * len = 1280. + + // avg_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_addr_reg, prot, data_wr, resp); + #10; + + // avg_len_reg + data_wr = 1800; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_len_reg, prot, data_wr, resp); + #10; + + // buf_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_addr_reg, prot, data_wr, resp); + #10; + + // buf_len_reg + data_wr = 1280; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_len_reg, prot, data_wr, resp); + #10; + + // {filter_we_reg, avg_start_reg} + data_wr = 3; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // filter_start_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*filter_start_addr_reg, prot, data_wr, resp); + #10; + + tb_load_mem <= 1; + + wait (tb_load_mem_done); + + + // Start sending input data. + tb_input <= 1; + + trigger_gen(5,4*1280); + + wait (tb_input_done); + + tb_input <= 0; + + // avg_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // Average DR. + // * addr = 0. + // * len = 10; + + // avg_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_addr_reg, prot, data_wr, resp); + #10; + + // avg_dr_len_reg + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_len_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + #100; + + // Buffer DR. + // * addr = 0. + // * len = 1280*5 = 6400, I use 7000; + + // buf_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_addr_reg, prot, data_wr, resp); + #10; + + // buf_dr_len_reg + data_wr = 7000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_len_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + #20000; + end + + + // Load data into memroy. + initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s1_axis_tvalid <= 0; + s1_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../src/tb/gauss.txt","r"); + + wait (s1_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s_axis_aclk); + s1_axis_tvalid <= 1; + s1_axis_tdata <= {qq,ii}; + end + + @(posedge s_axis_aclk); + s1_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + + end + + // Input data. + initial begin + int fd; + int vali, valq; + + s_axis_tvalid <= 0; + s_axis_tdata <= 0; + tb_input_done <= 0; + + wait (tb_input); + + fd = $fopen("../../../../../src/tb/data_iq.txt","r"); + + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + $display("Time %t: I = %d, Q = %d", $time, vali, valq); + @(posedge s_axis_aclk); + s_axis_tvalid <= 1; + s_axis_tdata[0 +: 16] <= vali; + s_axis_tdata[16 +: 16] <= valq; + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + @(posedge s_axis_aclk); + @(posedge s_axis_aclk); + end + + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + tb_input_done <= 1; + + end + + // s_axi_aclk. + always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; + end + + // s_axis_aclk. + always begin + s_axis_aclk <= 0; + #7; + s_axis_aclk <= 1; + #7; + end + + // m_axis_aclk. + always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; + end + + task trigger_gen (input int cnt, input int waitc); + for (int i=0; i + + QICK + QICK + mr_buffer_et + 1.1 + + + m00_axis + + + + + + + TDATA + + + m00_axis_tdata + + + + + TSTRB + + + m00_axis_tstrb + + + + + TLAST + + + m00_axis_tlast + + + + + TVALID + + + m00_axis_tvalid + + + + + TREADY + + + m00_axis_tready + + + + + + s00_axis + + + + + + + TDATA + + + s00_axis_tdata + + + + + TSTRB + + + s00_axis_tstrb + + + + + TLAST + + + s00_axis_tlast + + + + + TVALID + + + s00_axis_tvalid + + + + + TREADY + + + s00_axis_tready + + + + + + s00_axi + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + m00_axis_aresetn + + + + + + + RST + + + m00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s00_axi_aresetn + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s00_axis_aresetn + + + + + + + RST + + + s00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m00_axis_aclk + + + + + + + CLK + + + m00_axis_aclk + + + + + + ASSOCIATED_BUSIF + m00_axis + + + ASSOCIATED_RESET + m00_axis_aresetn + + + + + s00_axi_aclk + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + s00_axi + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + s00_axis_aclk + + + + + + + CLK + + + s00_axis_aclk + + + + + + ASSOCIATED_BUSIF + s00_axis + + + ASSOCIATED_RESET + s00_axis_aresetn + + + + + + + s00_axi + + reg0 + 0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + mr_buffer_v1_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f1b39ed6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + mr_buffer_v1_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f1b39ed6 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + bd3e64f2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5c442cfe + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + trigger + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_tstrb + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s00_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tdata + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tstrb + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_dbg_probe + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + m_dbg_probe + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + NM + Nm + 8 + + + N + N + 8 + + + B + B + 16 + + + C_S00_AXI_DATA_WIDTH + C S00 Axi Data Width + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 Axi Addr Width + 6 + + + DEBUG + Debug + 0 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/bram_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo.vhd + vhdlSource + + + src/mr_buffer.vhd + vhdlSource + + + src/mr_buffer_v1_0_S00_AXI.vhd + vhdlSource + + + src/synchronizer.vhd + vhdlSource + + + src/mr_buffer_v1_0.vhd + vhdlSource + CHECKSUM_0a79e04f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/bram_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo.vhd + vhdlSource + + + src/mr_buffer.vhd + vhdlSource + + + src/mr_buffer_v1_0_S00_AXI.vhd + vhdlSource + + + src/synchronizer.vhd + vhdlSource + + + src/mr_buffer_v1_0.vhd + vhdlSource + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + + + src/tb/tb_behav_waves.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + src/tb/axi4stream_vip_0/axi4stream_vip_0.xci + xci + + + src/tb/axi_vip_0/axi_vip_0.xci + xci + + + src/tb/axi4stream_vip_1/axi4stream_vip_1.xci + xci + + + + xilinx_xpgui_view_fileset + + xgui/mr_buffer_et_v1_1.tcl + tclSource + CHECKSUM_5c442cfe + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + Multi-Rate Buffer with External Trigger. + + + NM + Nm + 8 + + + N + N + 8 + + + B + B + 16 + + + C_S00_AXI_DATA_WIDTH + C S00 Axi Data Width + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 Axi Addr Width + 6 + + + Component_Name + mr_buffer_v1_0_v1_0 + + + DEBUG + Debug + 0 + + + + + + zynquplus + + + /QICK/Miscellaneous + + Multi-Rate Buffer ET + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 1 + + QICK:QICK:mr_buffer_et:1.0 + + 2025-05-30T20:00:48Z + + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/bram_dp.vhd b/firmware/ip/mr_buffer_et/src/bram_dp.vhd new file mode 100644 index 000000000..86df6aca8 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/bram_dp.vhd @@ -0,0 +1,88 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/02/2019 09:12:29 AM +-- Design Name: +-- Module Name: bram_dp - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture Behavioral of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/data_reader.vhd b/firmware/ip/mr_buffer_et/src/data_reader.vhd new file mode 100644 index 000000000..154da8e97 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/data_reader.vhd @@ -0,0 +1,338 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2019 12:08:45 PM +-- Design Name: +-- Module Name: data_reader - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_reader is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (NM*B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic + ); +end entity; + +architecture Behavioral of data_reader is + +constant NM_LOG2 : Integer := Integer(ceil(log2(real(NM)))); +constant NPOW : Integer := 2**N; + +-- Fifo to drive AXI Stream Master I/F. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +type fsm_state is ( INIT_ST, + READ_ST, + WRITE_ST, + READ_LAST_ST, + WRITE_LAST_ST, + FIFO_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; +signal read_state : std_logic; +signal write_state : std_logic; +signal fifo_state : std_logic; +signal read_en : std_logic; + +-- Counter for memory address. +signal addr_cnt : unsigned(N-1 downto 0); + +-- Counter for memory selection. +signal sel_cnt : unsigned(NM_LOG2-1 downto 0); + +-- Counter for read data. +signal read_cnt : unsigned(NM_LOG2-1 downto 0); + +-- Fifo signals. +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_din : std_logic_vector (B-1 downto 0); +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +signal mem_dout_r : std_logic_vector (NM*B-1 downto 0); + +signal dlast_i : std_logic; + +begin + +-- Fifo to drive AXI Stream Master I/F. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn, + clk => clk, + + -- Write I/F. + wr_en => fifo_wr_en, + din => fifo_din, + + -- Read I/F. + rd_en => fifo_rd_en, + dout => fifo_dout, + + -- Flags. + full => fifo_full, + empty => fifo_empty + ); + +-- Fifo connections. +fifo_wr_en <= write_state; + +fifo_rd_en <= dready when read_en = '1' else + '0'; + +-- Mux for fifo_din. +process(sel_cnt,mem_dout_r) +begin + fifo_din <= (others => '0'); + for I in 0 to NM-1 loop + if ( sel_cnt = to_unsigned(I,sel_cnt'length) ) then + fifo_din <= mem_dout_r((I+1)*B-1 downto I*B); + end if; + end loop; +end process; + +-- dlast generation. +dlast_i <= '1' when (read_cnt = to_unsigned(NM-1,read_cnt'length)) and (fifo_state = '1') else + '0'; + +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + current_state <= INIT_ST; + + addr_cnt <= (others => '0'); + sel_cnt <= (others => '0'); + read_cnt <= (others => '0'); + + mem_dout_r <= (others => '0'); + else + current_state <= next_state; + + if ( init_state = '1' ) then + mem_dout_r <= (others => '0'); + addr_cnt <= (others => '0'); + sel_cnt <= (others => '0'); + elsif ( read_state = '1' ) then + mem_dout_r <= mem_dout; + addr_cnt <= addr_cnt + 1; + elsif ( write_state = '1' ) then + if ( fifo_full = '0' ) then + sel_cnt <= sel_cnt + 1; + end if; + end if; + + if ( init_state = '1' ) then + read_cnt <= (others => '0'); + else + if ( dready = '1' and fifo_empty = '0' ) then + read_cnt <= read_cnt + 1; + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, START_REG, addr_cnt, sel_cnt, fifo_full, fifo_empty) +begin + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= READ_ST; + end if; + + when READ_ST => + next_state <= WRITE_ST; + + when WRITE_ST => + if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then + next_state <= WRITE_ST; + elsif ( addr_cnt < to_unsigned(NPOW-1,addr_cnt'length) ) then + next_state <= READ_ST; + else + next_state <= READ_LAST_ST; + end if; + + when READ_LAST_ST => + next_state <= WRITE_LAST_ST; + + when WRITE_LAST_ST => + if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then + next_state <= WRITE_LAST_ST; + else + next_state <= FIFO_ST; + end if; + + when FIFO_ST => + if ( fifo_empty = '0' ) then + next_state <= FIFO_ST; + else + next_state <= END_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + + when READ_ST => + init_state <= '0'; + read_state <= '1'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '1'; + + when WRITE_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '1'; + fifo_state <= '0'; + read_en <= '1'; + + when READ_LAST_ST => + init_state <= '0'; + read_state <= '1'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '1'; + + when WRITE_LAST_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '1'; + fifo_state <= '0'; + read_en <= '1'; + + when FIFO_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + + end case; +end process; + +-- Assign outputs. +mem_en <= '1'; +mem_we <= '0'; +mem_addr <= std_logic_vector(addr_cnt); + +dout <= fifo_dout; +dvalid <= not(fifo_empty); +dlast <= dlast_i; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/data_writer.vhd b/firmware/ip/mr_buffer_et/src/data_writer.vhd new file mode 100644 index 000000000..32a7d1782 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/data_writer.vhd @@ -0,0 +1,212 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Trigger. + trigger : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + CAPTURE_REG : in std_logic + ); +end entity; + +architecture Behavioral of data_writer is + +constant NPOW : Integer := 2**N; + +-- Fifo to interfase with AXI Stream. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST, + TRIGGER_ST, + CAPTURE_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; + +signal write_en : std_logic; + +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +signal addr_cnt : unsigned (N-1 downto 0); + +begin + +-- Fifo to interface with AXI stream. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn, + clk => clk, + + -- Write I/F. + wr_en => fifo_wr_en, + din => s_axis_tdata, + + -- Read I/F. + rd_en => fifo_rd_en, + dout => fifo_dout, + + -- Flags. + full => fifo_full, + empty => fifo_empty + ); + +-- Mux for fifo_wr_en. +fifo_wr_en <= s_axis_tvalid when write_en = '1' else + '0'; + +-- fifo_rd_en. +fifo_rd_en <= not fifo_empty; + +-- Registers. +process (clk) +begin + if (rising_edge(clk)) then + if ( rstn = '0' ) then + current_state <= INIT_ST; + else + current_state <= next_state; + + -- Address counter + if ( write_en = '1' ) then + if ( fifo_rd_en = '1' and fifo_empty = '0' ) then + addr_cnt <= addr_cnt + 1; + end if; + else + addr_cnt <= (others => '0'); + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, CAPTURE_REG, trigger, addr_cnt, fifo_rd_en, fifo_empty) +begin + case current_state is + when INIT_ST => + if (CAPTURE_REG = '0') then + next_state <= INIT_ST; + else + next_state <= TRIGGER_ST; + end if; + + when TRIGGER_ST => + if (trigger = '0') then + next_state <= TRIGGER_ST; + else + next_state <= CAPTURE_ST; + end if; + + when CAPTURE_ST => + if ( addr_cnt = to_unsigned(NPOW-1,addr_cnt'length) and fifo_rd_en = '1' and fifo_empty = '0' ) then + next_state <= END_ST; + else + next_state <= CAPTURE_ST; + end if; + + when END_ST => + if ( CAPTURE_REG = '0' and fifo_empty = '1') then + -- Wait until input FIFO is flushed out + next_state <= INIT_ST; + else + next_state <= END_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin + init_state <= '0'; + write_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when TRIGGER_ST => + + when CAPTURE_ST => + write_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +s_axis_tready <= not(fifo_full) when write_en = '1' else + '0'; + +mem_en <= '1'; +mem_we <= write_en; +mem_addr <= std_logic_vector(addr_cnt); +mem_di <= fifo_dout; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/fifo.vhd b/firmware/ip/mr_buffer_et/src/fifo.vhd new file mode 100644 index 000000000..2795bb6ab --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/fifo.vhd @@ -0,0 +1,115 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/18/2019 08:35:37 AM +-- Design Name: +-- Module Name: fifo - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4; + + -- Almost full. + AF : Integer := 3 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture Behavioral of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Registers. +type array_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal regs : array_t; + +-- Pointers. +signal wr_ptr : unsigned (N_LOG2-1 downto 0); +signal rd_ptr : unsigned (N_LOG2-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- Full/empty signals. +full_i <= '1' when wr_ptr = rd_ptr - 1 else + '0'; +empty_i <= '1' when wr_ptr = rd_ptr else + '0'; + +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wr_ptr <= (others => '0'); + rd_ptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + regs(to_integer(wr_ptr)) <= din; + + -- Increment pointer. + wr_ptr <= wr_ptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Increment pointer. + rd_ptr <= rd_ptr + 1; + end if; + + end if; + end if; +end process; + +-- Assign outputs. +dout <= regs(to_integer(rd_ptr)); +full <= full_i; +empty <= empty_i; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer.vhd new file mode 100644 index 000000000..4c669d971 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer.vhd @@ -0,0 +1,370 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity mr_buffer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Trigger. + trigger : in std_logic; + + -- AXI Stream Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXI Stream Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tready : in std_logic; + + -- Registers. + DW_CAPTURE_REG : in std_logic; + DR_START_REG : in std_logic; + DEBUG_REG : in std_logic_vector(31 downto 0); + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + + ); +end mr_buffer; + +architecture Behavioral of mr_buffer is + +-- Synchronizer. +component synchronizer is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- Memory. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Data writer. +component data_writer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Trigger. + trigger : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + CAPTURE_REG : in std_logic + ); +end component; + +-- Data reader. +component data_reader is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (NM*B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic + ); +end component; + +-- Re-sync trigger and registers. +signal DW_CAPTURE_REG_resync: std_logic; +signal DR_START_REG_resync : std_logic; +signal trigger_or_dbg : std_logic; +signal trigger_resync : std_logic; + +-- ena/enb/wea/web. +signal ena : std_logic_vector (NM-1 downto 0); +signal enb : std_logic; +signal wea : std_logic_vector (NM-1 downto 0); +signal web : std_logic; + +-- addra/addrb. +type addr_array_t is array (NM-1 downto 0) of std_logic_vector (N-1 downto 0); +signal addra : addr_array_t; +signal addrb : std_logic_vector (N-1 downto 0); + +-- dia/dib/doa/dob/dout. +type di_do_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); +signal dia : di_do_array_t; +signal dib : std_logic_vector (B-1 downto 0); +signal doa : di_do_array_t; +signal dob : di_do_array_t; +signal dout : std_logic_vector (B-1 downto 0); + +-- Concatenated data for reader. +signal dob_c: std_logic_vector (NM*B-1 downto 0); + +-- s_axis_tdata. +type tdata_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); +signal s_axis_tdata_i : tdata_array_t; + +-- s_axis_tvalid/tready. +signal s_axis_tvalid_i : std_logic_vector (NM-1 downto 0); +signal s_axis_tready_i : std_logic_vector (NM-1 downto 0); + +signal dtvalid : std_logic; +signal dtlast : std_logic; +signal dtdata : std_logic_vector(B-1 downto 0); + +-- Debug signals +signal trigger_dbg : std_logic; +signal s_axis_tready_force : std_logic; + +begin + + trigger_dbg <= DEBUG_REG(0); + s_axis_tready_force <= DEBUG_REG(1); + +-- DW_CAPTURE_REG_resync. +DW_CAPTURE_REG_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => s_axis_aresetn, + clk => s_axis_aclk, + data_in => DW_CAPTURE_REG, + data_out => DW_CAPTURE_REG_resync + ); + +-- DR_START_REG_resync. +DR_START_REG_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => m_axis_aresetn, + clk => m_axis_aclk, + data_in => DR_START_REG, + data_out => DR_START_REG_resync + ); + + trigger_or_dbg <= trigger or trigger_dbg; + +-- trigger_resync. +trigger_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => s_axis_aresetn, + clk => s_axis_aclk, + data_in => trigger_or_dbg, + data_out => trigger_resync + ); + +GEN: for I in 0 to NM-1 generate + + -- Memory instantiation. + bram_dp_i : bram_dp + Generic map + ( + -- Memory address size. + N => N, + -- Data width. + B => B + ) + Port map + ( + clka => s_axis_aclk, + clkb => m_axis_aclk, + ena => ena(I), + enb => enb, + wea => wea(I), + web => web, + addra => addra(I), + addrb => addrb, + dia => dia(I), + dib => dib, + doa => doa(I), + dob => dob(I) + ); + + -- Data writer. + data_writer_i : data_writer + Generic map + ( + -- Number of memories. + NM => NM, + -- Address map of each memory. + N => N, + -- Data width. + B => B + ) + Port map + ( + rstn => s_axis_aresetn , + clk => s_axis_aclk , + + -- Trigger. + trigger => trigger_resync , + + -- AXI Stream I/F. + s_axis_tready => s_axis_tready_i(I) , + s_axis_tdata => s_axis_tdata_i(I) , + s_axis_tvalid => s_axis_tvalid_i(I) , + + -- Memory I/F. + mem_en => ena(I) , + mem_we => wea(I) , + mem_addr => addra(I) , + mem_di => dia(I) , + + -- Registers. + CAPTURE_REG => DW_CAPTURE_REG_resync + ); + + -- Input tdata. + s_axis_tdata_i(I) <= s_axis_tdata((I+1)*B-1 downto I*B); + s_axis_tvalid_i(I) <= s_axis_tvalid; + + -- Concatenate output data for port b. + dob_c((I+1)*B-1 downto I*B) <= dob(I); + +end generate GEN; + +-- Data reader instantiation. +data_reader_i : data_reader +Generic map +( + -- Number of memories. + NM => NM, + -- Memory address size. + N => N, + -- Data width. + B => B +) +Port map +( + -- Reset and clock. + rstn => m_axis_aresetn, + clk => m_axis_aclk, + + -- Memory I/F. + mem_en => enb, + mem_we => web, + mem_addr => addrb, + mem_dout => dob_c, + + -- Data out. + dready => m_axis_tready, + dout => dtdata, + dvalid => dtvalid, + dlast => dtlast, + + -- Registers. + START_REG => DR_START_REG_resync +); + +-- Output assignment. +s_axis_tready <= s_axis_tready_i(0) or s_axis_tready_force; +m_axis_tstrobe <= (others => '1'); + +m_axis_tvalid <= dtvalid; +m_axis_tlast <= dtlast; +m_axis_tdata <= dtdata; + + +-- Debug ILA probe +s_dbg_probe(7 downto 0) <= "000" & DW_CAPTURE_REG_resync & trigger_resync & wea(0) & s_axis_tvalid_i(0) & s_axis_tready_i(0); +s_dbg_probe(15 downto 8) <= s_axis_tdata_i(0)(7 downto 0); +s_dbg_probe(23 downto 16) <= std_logic_vector(resize(unsigned(addra(0)),8)); +s_dbg_probe(31 downto 24) <= dia(0)(7 downto 0); + + +m_dbg_probe(7 downto 0) <= "000" & DR_START_REG_resync & web & dtlast & dtvalid & m_axis_tready; +m_dbg_probe(15 downto 8) <= dtdata(7 downto 0); +m_dbg_probe(23 downto 16) <= std_logic_vector(resize(unsigned(addrb),8)); +m_dbg_probe(31 downto 24) <= dob_c(7 downto 0); + +end Behavioral; + diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd new file mode 100644 index 000000000..fe2d2124e --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mr_buffer_v1_0 is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6; + + -- Enable Debug + DEBUG : Integer := 0 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + s00_axis_aclk : in std_logic; + s00_axis_aresetn: in std_logic; + s00_axis_tready : out std_logic; + s00_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s00_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s00_axis_tlast : in std_logic; + s00_axis_tvalid : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + m00_axis_aclk : in std_logic; + m00_axis_aresetn : in std_logic; + m00_axis_tvalid : out std_logic; + m00_axis_tdata : out std_logic_vector(B-1 downto 0); + m00_axis_tstrb : out std_logic_vector((B/8)-1 downto 0); + m00_axis_tlast : out std_logic; + m00_axis_tready : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + + ); +end mr_buffer_v1_0; + +architecture arch_imp of mr_buffer_v1_0 is + + -- component declaration + component mr_buffer_v1_0_S00_AXI is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); + S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK : in std_logic; + M_AXIS_ARESETN : in std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); + end component mr_buffer_v1_0_S00_AXI; + + signal s_dbg_probe_int : std_logic_vector(31 downto 0); + signal m_dbg_probe_int : std_logic_vector(31 downto 0); + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +mr_buffer_v1_0_S00_AXI_inst : mr_buffer_v1_0_S00_AXI + generic map ( + NM => NM, + N => N, + B => B, + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + -- Trigger. + trigger => trigger, + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready, + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK => s00_axis_aclk, + S_AXIS_ARESETN => s00_axis_aresetn, + S_AXIS_TREADY => s00_axis_tready, + S_AXIS_TDATA => s00_axis_tdata, + S_AXIS_TSTRB => s00_axis_tstrb, + S_AXIS_TLAST => s00_axis_tlast, + S_AXIS_TVALID => s00_axis_tvalid, + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK => m00_axis_aclk, + M_AXIS_ARESETN => m00_axis_aresetn, + M_AXIS_TVALID => m00_axis_tvalid, + M_AXIS_TDATA => m00_axis_tdata, + M_AXIS_TSTRB => m00_axis_tstrb, + M_AXIS_TLAST => m00_axis_tlast, + M_AXIS_TREADY => m00_axis_tready, + + s_dbg_probe => s_dbg_probe_int, + m_dbg_probe => m_dbg_probe_int + ); + + DEBUG_GEN: if DEBUG = 1 generate + -- Debug ILA probe + s_dbg_probe <= s_dbg_probe_int; + m_dbg_probe <= m_dbg_probe_int; + end generate; + DEBUG_NOGEN: if DEBUG /= 1 generate + s_dbg_probe <= (others => '0'); + m_dbg_probe <= (others => '0'); + end generate; + +end arch_imp; + diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd new file mode 100644 index 000000000..0f2b6f747 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd @@ -0,0 +1,613 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mr_buffer_v1_0_S00_AXI is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); + S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK : in std_logic; + M_AXIS_ARESETN : in std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); +end mr_buffer_v1_0_S00_AXI; + +architecture arch_imp of mr_buffer_v1_0_S00_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + component mr_buffer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Trigger. + trigger : in std_logic; + + -- AXI Stream Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXI Stream Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tready : in std_logic; + + -- Registers. + DW_CAPTURE_REG : in std_logic; + DR_START_REG : in std_logic; + DEBUG_REG : in std_logic_vector(31 downto 0); + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); + end component; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + mr_buffer_i : mr_buffer + Generic map + ( + -- Number of memories. + NM => NM, + -- Address map of each memory. + N => N, + -- Data width. + B => B + ) + Port map + ( + -- Trigger. + trigger => trigger, + + -- AXI Stream Slave I/F. + s_axis_aclk => S_AXIS_ACLK, + s_axis_aresetn => S_AXIS_ARESETN, + s_axis_tready => S_AXIS_TREADY, + s_axis_tdata => S_AXIS_TDATA, + s_axis_tstrb => S_AXIS_TSTRB, + s_axis_tlast => S_AXIS_TLAST, + s_axis_tvalid => S_AXIS_TVALID, + + -- AXI Stream Master I/F. + m_axis_aclk => M_AXIS_ACLK, + m_axis_aresetn => M_AXIS_ARESETN, + m_axis_tvalid => M_AXIS_TVALID, + m_axis_tdata => M_AXIS_TDATA, + m_axis_tstrobe => M_AXIS_TSTRB, + m_axis_tlast => M_AXIS_TLAST, + m_axis_tready => M_AXIS_TREADY, + + -- Registers. + DW_CAPTURE_REG => slv_reg0(0), + DR_START_REG => slv_reg1(0), + DEBUG_REG => slv_reg15, + + s_dbg_probe => s_dbg_probe, + m_dbg_probe => m_dbg_probe + ); + +end arch_imp; + diff --git a/firmware/ip/mr_buffer_et/src/synchronizer.vhd b/firmware/ip/mr_buffer_et/src/synchronizer.vhd new file mode 100644 index 000000000..3eefc6f21 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/synchronizer.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer; + +architecture rtl of synchronizer is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +attribute ASYNC_REG : string; +attribute ASYNC_REG of data_int_reg: signal is "TRUE"; + +begin + +process(clk,rstn) +begin + if (rstn = '0') then + data_int_reg <= (others => '0'); -- 1 FF. + elsif (clk'event and clk='1') then + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho new file mode 100644 index 000000000..2fcd3f25d --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho @@ -0,0 +1,84 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi4stream_vip_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi4stream_vip_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi4stream_vip_0.vhd when simulating +-- the core, axi4stream_vip_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci new file mode 100644 index 000000000..7c9b893ba --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci @@ -0,0 +1,128 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi4stream_vip_0", + "component_reference": "xilinx.com:ip:axi4stream_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "INTERFACE_MODE": [ { "value": "SLAVE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": 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"value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0" } ], + "aresetn": [ { "direction": "in", "driver_value": "1" } ], + "s_axis_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "s_axis_tready": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": 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"physical_name": "s_axis_tvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xml b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xml new file mode 100644 index 000000000..5bebb9859 --- /dev/null +++ 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+ + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axi4stream_vip_0 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + + xtlm + protobuf + xtlm_ipc_v1_0 + sim_ipc_multi_intf_v1_0 + + 14 + true + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho new file mode 100644 index 000000000..2d3e7f0ba --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho @@ -0,0 +1,84 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi4stream_vip_1 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi4stream_vip_1 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi4stream_vip_1.vhd when simulating +-- the core, axi4stream_vip_1. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci new file mode 100644 index 000000000..b872481b1 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci @@ -0,0 +1,128 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi4stream_vip_1", + "component_reference": "xilinx.com:ip:axi4stream_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "HAS_TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TID_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "axi4stream_vip_1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_AXI4STREAM_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_AXI4STREAM_INTERFACE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_DEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu111:part0:1.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu28dr" } ], + "PACKAGE": [ { "value": "ffvg1517" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "14" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "." } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0" } ], + "aresetn": [ { "direction": "in", "driver_value": "1" } ], + "m_axis_tvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "m_axis_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": 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"TVALID": [ { "physical_name": "m_axis_tvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": 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sysc/axi_stream_vip.cpp + systemCSource + axi4stream_vip_v1_1_14 + + + sysc/axi_stream_vip.h + systemCSource + true + axi4stream_vip_v1_1_14 + + + sysc/sim_ipc_axis_multi_intf.h + systemCSource + true + axi4stream_vip_v1_1_14 + + + sysc/sim_ipc_axis_multi_intf.cpp + systemCSource + axi4stream_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi4stream_vip_1_sc.h + systemCSource + true + + + sim/axi4stream_vip_1_sc.cpp + systemCSource + + + sim/axi4stream_vip_1.h + systemCSource + true + + + sim/axi4stream_vip_1.cpp + systemCSource + + + sim/axi4stream_vip_1_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi4stream_vip_1_pkg.sv + systemVerilogSource + + + hdl/axi4stream_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi4stream_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi4stream_vip_1.vho + vhdlTemplate + + + axi4stream_vip_1.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi4stream_vip_1.sv + systemVerilogSource + xil_defaultlib + + + + The AXI4-Stream Verification IP. + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + TDATA_NUM_BYTES + TDATA WIDTH(BYTES) + 4 + + + USER_BITS_PER_BYTE + TUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_TUSER_BITS_PER_BYTE + HAS TUSER_BITS_PER_BYTE + 0 + + + TID_WIDTH + TID WIDTH(BITS) + 0 + + + TDEST_WIDTH + TDEST WIDTH(BITS) + 0 + + + TUSER_WIDTH + TUSER WIDTH(BITS) + 0 + + + HAS_TREADY + ENABLE TREADY + 1 + + + HAS_TSTRB + ENABLE TSTRB + 0 + + + HAS_TKEEP + ENABLE TKEEP + 0 + + + HAS_TLAST + ENABLE TLAST + 0 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axi4stream_vip_1 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + + xtlm + protobuf + xtlm_ipc_v1_0 + sim_ipc_multi_intf_v1_0 + + 14 + true + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho new file mode 100644 index 000000000..8f42c2086 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_vip_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_vip_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_vip_0.vhd when simulating +-- the core, axi_vip_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci new file mode 100644 index 000000000..ce4358819 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_vip_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_vip_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } 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xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.h + systemCSource + true + + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.h + systemCSource + true + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.h + systemCSource + true + axi_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_vip_0_sc.h + systemCSource + true + + + sim/axi_vip_0_sc.cpp + systemCSource + + + sim/axi_vip_0.h + systemCSource + true + + + sim/axi_vip_0.cpp + systemCSource + + + sim/axi_vip_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_vip_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_vip_0.vho + vhdlTemplate + + + axi_vip_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_vip_0.sv + systemVerilogSource + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_vip_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/tb.sv b/firmware/ip/mr_buffer_et/src/tb/tb.sv new file mode 100644 index 000000000..cd00ce972 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/tb.sv @@ -0,0 +1,361 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/19/2019 01:38:28 PM +// Design Name: +// Module Name: tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +import axi_vip_pkg::*; +import axi_vip_0_pkg::*; +import axi4stream_vip_pkg::*; +import axi4stream_vip_0_pkg::*; +import axi4stream_vip_1_pkg::*; + +module tb( + ); + +// AXI signals. +reg aclk = 0; +reg aresetn; +reg trigger; +wire [31:0] m_axi_awaddr; +wire [2:0] m_axi_awprot; +wire m_axi_awvalid; +wire m_axi_awready; +wire [31:0] m_axi_wdata; +wire [3:0] m_axi_wstrb; +wire m_axi_wvalid; +wire m_axi_wready; +wire [1:0] m_axi_bresp; +wire m_axi_bvalid; +wire m_axi_bready; +wire [31:0] m_axi_araddr; +wire [2:0] m_axi_arprot; +wire m_axi_arvalid; +wire m_axi_arready; +wire [31:0] m_axi_rdata; +wire [1:0] m_axi_rresp; +wire m_axi_rvalid; +wire m_axi_rready; + +// AXIS Master signals. +reg m_axis_aclk = 0; +reg m_axis_aresetn; +wire m_axis_tvalid; +wire m_axis_tready; +wire [7:0] m_axis_tdata; + +// AXIS Slave signals. +reg s_axis_aclk = 0; +reg s_axis_aresetn; +wire s_axis_tready; +wire [31:0] s_axis_tdata; +wire s_axis_tvalid; + +axi4stream_transaction wr_transaction; +axi4stream_ready_gen ready_gen; + +xil_axi_ulong addr_DW_CAPTURE_REG = 32'h44A00000; // 0 +xil_axi_ulong addr_DR_START_REG = 32'h44A00004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr=32'h01234567; +reg[31:0] data_rd=32'h01234567; +xil_axi_resp_t resp; + +// AXI Master VIP. +axi_vip_0 axi_vip_i ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); + +// AXIS Master VIP. +axi4stream_vip_1 axis_mst_vip_i ( + .aclk(s_axis_aclk), // input wire aclk + .aresetn(s_axis_aresetn), // input wire aresetn + .m_axis_tvalid(s_axis_tvalid), // output wire [0 : 0] m_axis_tvalid + .m_axis_tready(s_axis_tready), // input wire [0 : 0] m_axis_tready + .m_axis_tdata(s_axis_tdata) // output wire [7 : 0] m_axis_tdata +); + +// AXIS Slave VIP. +axi4stream_vip_0 axis_slv_vip_i ( + .aclk(m_axis_aclk), // input wire aclk + .aresetn(m_axis_aresetn), // input wire aresetn + .s_axis_tvalid(m_axis_tvalid), // input wire [0 : 0] s_axis_tvalid + .s_axis_tready(m_axis_tready), // output wire [0 : 0] s_axis_tready + .s_axis_tdata(m_axis_tdata) // input wire [31 : 0] s_axis_tdata +); + +// Instantiate DUT. +mr_buffer_v1_0 + #(.NM(4), .N(4), .B(8)) + DUT ( + .trigger(trigger), + .s00_axi_aclk(aclk), + .s00_axi_aresetn(aresetn), + .s00_axi_awaddr(m_axi_awaddr), + .s00_axi_awprot(m_axi_awprot), + .s00_axi_awvalid(m_axi_awvalid), + .s00_axi_awready(m_axi_awready), + .s00_axi_wdata(m_axi_wdata), + .s00_axi_wstrb(m_axi_wstrb), + .s00_axi_wvalid(m_axi_wvalid), + .s00_axi_wready(m_axi_wready), + .s00_axi_bresp(m_axi_bresp), + .s00_axi_bvalid(m_axi_bvalid), + .s00_axi_bready(m_axi_bready), + .s00_axi_araddr(m_axi_araddr), + .s00_axi_arprot(m_axi_arprot), + .s00_axi_arvalid(m_axi_arvalid), + .s00_axi_arready(m_axi_arready), + .s00_axi_rdata(m_axi_rdata), + .s00_axi_rresp(m_axi_rresp), + .s00_axi_rvalid(m_axi_rvalid), + .s00_axi_rready(m_axi_rready), + .s00_axis_aclk(s_axis_aclk), + .s00_axis_aresetn(s_axis_aresetn), + .s00_axis_tready(s_axis_tready), + .s00_axis_tdata({s_axis_tdata^s_axis_tdata,s_axis_tdata}), + .s00_axis_tstrb(), + .s00_axis_tlast(), + .s00_axis_tvalid(s_axis_tvalid), + .m00_axis_aclk(m_axis_aclk), + .m00_axis_aresetn(m_axis_aresetn), + .m00_axis_tvalid(m_axis_tvalid), + .m00_axis_tdata(m_axis_tdata), + .m00_axis_tstrb(), + .m00_axis_tlast(), + .m00_axis_tready(m_axis_tready)); + +// Declare AXI master VIP agent. +axi_vip_0_mst_t mst_agent; + +// Declare AXIS master VIP agent. +axi4stream_vip_1_mst_t axis_mst_agent; + +// Declare AXIS slave VIP agent. +axi4stream_vip_0_slv_t axis_slv_agent; + +initial begin + // Create agentt. + mst_agent = new("axi master vip agent", axi_vip_i.inst.IF); + axis_mst_agent = new("axis master vip agent", axis_mst_vip_i.inst.IF); + axis_slv_agent = new("axis slave vip agent", axis_slv_vip_i.inst.IF); + + // Set tag for agent to ease debug. + mst_agent.set_agent_tag("AXI Master VIP"); + axis_mst_agent.set_agent_tag("AXIS Master VIP"); + axis_slv_agent.set_agent_tag("AXIS Slave VIP"); + + // Set print verbosity level. + mst_agent.set_verbosity(400); + axis_mst_agent.set_verbosity(400); + axis_slv_agent.set_verbosity(400); + + /*************************************************************************************************** + * When bus is in idle, it must drive everything to 0.otherwise it will + * trigger false assertion failure from axi_protocol_chekcer + ***************************************************************************************************/ + + axis_mst_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + axis_slv_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + + /* + DW_CAPTURE_REG : 1 bit. + -> 0 : disable capture. + -> 1 : enable capture. + + DR_START_REG : 1 bit. + -> 0 : stop. + -> 1 : start. + + trigger : 1 bit. + -> 0 : wait. + -> 1 : start capture. + */ + + // Start the agent. + mst_agent.start_master(); + axis_mst_agent.start_master(); + axis_slv_agent.start_slave(); + + // dready generator. + ready_gen = axis_slv_agent.driver.create_ready("ready_gen"); + ready_gen.set_ready_policy(XIL_AXI4STREAM_READY_GEN_EVENTS); + ready_gen.set_low_time(4); + ready_gen.set_event_count(25); + + trigger <= 0; + + // Reset sequence. + aresetn = 0; + m_axis_aresetn = 0; + s_axis_aresetn = 0; + #200ns; + + repeat(16) @(negedge aclk); + + aresetn = 1; + m_axis_aresetn = 1; + s_axis_aresetn = 1; + #200ns; + + repeat(2) begin + + // Write DW_CAPTURE_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + // // Send data. + // fork + // gen_0(8,10); + // join_none + + // #1us; + + // Trigger. + trigger <= 1; + #1us; + + // Send data. + fork + gen_0(8,0); + join + + #1us; + trigger <= 0; + + // Write DW_CAPTURE_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + #1us; + + // Write DW_CAPTURE_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + #200ns; + + // Write DW_CAPTURE_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + // Send data. + fork + gen_0(16,10); + join_none + + #100ns; + trigger <= 1; + + #1us; + + // Write DR_START_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + // Write DR_START_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + #2us; + + axis_slv_agent.driver.send_tready(ready_gen); + + // Write DR_START_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + // Write DR_START_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + trigger <= 0; + + #1us; + + end + + $finish(); +end + +// aclk. +always begin + #10; aclk = ~aclk; +end + +//m_axis_aclk +always begin + #4; m_axis_aclk = ~m_axis_aclk; +end + +//s_axis_aclk +always begin + #3; s_axis_aclk = ~s_axis_aclk; +end + +task gen_0(input bit [31:0] cnt, input bit [31:0] delay); + static int data_val_cnt = 0; + // Create transaction. + axi4stream_transaction wr_transaction; + wr_transaction = axis_mst_agent.driver.create_transaction("Master 0 VIP write transaction"); + + // Set transaction parameters. +// wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_RANDOM); + wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_ALL_SET); + wr_transaction.set_delay(0); + + // Send transactions. + for (int i=0; i < cnt; i++) + begin + // WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); + wr_transaction.set_data('{data_val_cnt+1,data_val_cnt+2,data_val_cnt+3,data_val_cnt+4}); + axis_mst_agent.driver.send(wr_transaction); + data_val_cnt += 4; + end +endtask + +endmodule diff --git a/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg b/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg new file mode 100644 index 000000000..3e0a9a0a0 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg @@ -0,0 +1,306 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + NM + NM + + + N + N + + + B + B + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_tready + s_axis_tready + + + s_axis_tvalid + s_axis_tvalid + + + s_axis_tdata[31:0] + s_axis_tdata[31:0] + + + DW_CAPTURE_REG + DW_CAPTURE_REG + + + DR_START_REG + DR_START_REG + + + trigger + trigger + + + DATA_WR_FSM_0 + label + + + addr_cnt[3:0] + addr_cnt[3:0] + UNSIGNEDDECRADIX + + + current_state + current_state + + + init_state + init_state + + + write_en + write_en + + + + WR_FIFO_0 + label + + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[7:0] + din[7:0] + UNSIGNEDDECRADIX + + + full + full + + + rd_en + rd_en + + + dout[7:0] + dout[7:0] + UNSIGNEDDECRADIX + + + empty + empty + + + + WR_MEM_0 + label + + + clka + clka + + + ena + ena + + + wea + wea + + + dia[7:0] + dia[7:0] + UNSIGNEDDECRADIX + + + addra[3:0] + addra[3:0] + UNSIGNEDDECRADIX + + + doa[7:0] + doa[7:0] + + + clkb + clkb + + + enb + enb + + + web + web + + + dib[7:0] + dib[7:0] + + + addrb[3:0] + addrb[3:0] + UNSIGNEDDECRADIX + + + dob[7:0] + dob[7:0] + UNSIGNEDDECRADIX + + + + DATA_READER_FSM + label + + + mem_dout[31:0] + mem_dout[31:0] + + + mem_dout_r[31:0] + mem_dout_r[31:0] + + + NPOW + NPOW + + + current_state + current_state + + + addr_cnt[3:0] + addr_cnt[3:0] + UNSIGNEDDECRADIX + + + read_cnt[1:0] + read_cnt[1:0] + + + sel_cnt[1:0] + sel_cnt[1:0] + + + mem_addr[3:0] + mem_addr[3:0] + UNSIGNEDDECRADIX + + + + mem_dout_r[31:0] + mem_dout_r[31:0] + + + DATA_READER_FIFO + label + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[7:0] + din[7:0] + + + full + full + + + rd_en + rd_en + + + dout[7:0] + dout[7:0] + + + empty + empty + + + + M_AXIS + label + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_aclk + m_axis_aclk + + + m_axis_tready + m_axis_tready + + + m_axis_tvalid + m_axis_tvalid + + + m_axis_tdata[7:0] + m_axis_tdata[7:0] + UNSIGNEDDECRADIX + + + m_axis_tstrobe[0:0] + m_axis_tstrobe[0:0] + + + m_axis_tlast + m_axis_tlast + + + + NPOW + NPOW + + diff --git a/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl new file mode 100644 index 000000000..2f38e18a3 --- /dev/null +++ b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl @@ -0,0 +1,99 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NM" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to update NM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to validate NM + return true +} + + +proc update_MODELPARAM_VALUE.NM { MODELPARAM_VALUE.NM PARAM_VALUE.NM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NM}] ${MODELPARAM_VALUE.NM} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl new file mode 100644 index 000000000..2f38e18a3 --- /dev/null +++ b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl @@ -0,0 +1,99 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NM" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to update NM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to validate NM + return true +} + + +proc update_MODELPARAM_VALUE.NM { MODELPARAM_VALUE.NM PARAM_VALUE.NM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NM}] ${MODELPARAM_VALUE.NM} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_com/component.xml b/firmware/ip/qick_com/component.xml new file mode 100644 index 000000000..f5c937880 --- /dev/null +++ b/firmware/ip/qick_com/component.xml @@ -0,0 +1,1307 @@ + + + QICK + QICK + qick_com + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_clk + + + + + + + CLK + + + c_clk + + + + + + ASSOCIATED_RESET + c_aresetn + + + ASSOCIATED_BUSIF + QCOM + + + + + ps_clk + + + + + + + CLK + + + ps_clk + + + + + + ASSOCIATED_RESET + ps_aresetn + + + ASSOCIATED_BUSIF + s_axi + + + + + QCOM + + + + + + + a_dt + + + qcom_dt1_i + + + + + flag + + + qcom_flag_o + + + + + rdy + + + qcom_rdy_o + + + + + Enable + + + qcom_en_i + + + + + dt_in_2 + + + qcom_dt2_o + + + + + Operation + + + qcom_op_i + + + + + dt_in_1 + + + qcom_dt1_o + + + + + dt_valid + + + qcom_vld_o + + + + + + t_aresetn + + + + + + + RST + + + t_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + t_clk + + + + + + + CLK + + + t_clk + + + + + + ASSOCIATED_RESET + t_aresetn:qproc_start_o + + + ASSOCIATED_BUSIF + QPROC_CTRL + + + + + QPROC_CTRL + Processor Control + + + + + + + start + + + qproc_start_o + + + + + + + false + + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_qick_com + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6f4768b4 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_qick_com + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6f4768b4 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb_qcom + + xilinx_testbench_view_fileset + + + + viewChecksum + a040b0f3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 12885887 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + c_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + c_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + t_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + t_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_en_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_op_i + + in + + 4 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt1_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_rdy_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt1_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt2_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_vld_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_flag_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qproc_start_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + pmod_i + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pmod_o + + out + + 3 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + qcom_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + DEBUG + Debug + 0 + + + SYNC + Sync + 0 + + + + + + choice_list_98b8ce5c + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_8098f617 + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qcom_ips.sv + systemVerilogSource + + + src/qcom_link.sv + systemVerilogSource + + + src/qick_cmd.sv + systemVerilogSource + + + src/qick_com.sv + systemVerilogSource + + + src/axi_slv_qcom.vhd + vhdlSource + + + src/axi_qick_com.sv + systemVerilogSource + CHECKSUM_4b928db9 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qcom_ips.sv + systemVerilogSource + + + src/qcom_link.sv + systemVerilogSource + + + src/qick_cmd.sv + systemVerilogSource + + + src/qick_com.sv + systemVerilogSource + + + src/axi_slv_qcom.vhd + vhdlSource + + + src/axi_qick_com.sv + systemVerilogSource + + + + xilinx_testbench_view_fileset + + src/TB/tb_qcom.sv + systemVerilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + src/TB/tb_behav.wcfg + unknown + USED_IN_simulation + + + + xilinx_xpgui_view_fileset + + xgui/qick_com_v1_0.tcl + tclSource + CHECKSUM_12885887 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + qick_com + + + DEBUG + Debug + 0 + + + Component_Name + axis_qick_com_v1_0 + + + SYNC + Processor Syncronization + 0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /QICK/QICK_Peripheral + + qick_com + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 7 + 2024-06-20T14:01:58Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/qick_com/src/TB/tb_behav.wcfg b/firmware/ip/qick_com/src/TB/tb_behav.wcfg new file mode 100644 index 000000000..adc8c9fff --- /dev/null +++ b/firmware/ip/qick_com/src/TB/tb_behav.wcfg @@ -0,0 +1,408 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk + ps_clk + + + c_clk + c_clk + + + rst_ni + rst_ni + + + cmd_ack_i + cmd_ack_i + + + p_op_r[3:0] + p_op_r[3:0] + + + cmd_op[3:0] + cmd_op[3:0] + + + cmd_req_o + cmd_req_o + + + cmd_op_o[3:0] + cmd_op_o[3:0] + + + QCOM_CFG[3:0] + QCOM_CFG[3:0] + + + QCOM_CTRL[7:0] + QCOM_CTRL[7:0] + + + RAXI_DT1[31:0] + RAXI_DT1[31:0] + SIGNEDDECRADIX + + + c_en_i + c_en_i + + + c_op_i[4:0] + c_op_i[4:0] + UNSIGNEDDECRADIX + + + cmd_op[3:0] + cmd_op[3:0] + + + cmd_cnt[7:0] + cmd_cnt[7:0] + HEXRADIX + + + cmd_req + cmd_req + + + ready + ready + + + qcom_header[3:0] + qcom_header[3:0] + + + tx_vld_i + tx_vld_i + #E0FFFF + true + + + tx_header_i[3:0] + tx_header_i[3:0] + #E0FFFF + true + + + tx_data_i[31:0] + tx_data_i[31:0] + #E0FFFF + true + + + c_cmd_i + c_cmd_i + #00FFFF + true + + + c_cmd_i + c_cmd_i + #00FFFF + true + + + c_dt1_i[31:0] + c_dt1_i[31:0] + #00FFFF + true + UNSIGNEDDECRADIX + + + c_op_i[4:0] + c_op_i[4:0] + #00FFFF + true + UNSIGNEDDECRADIX + + + qcom_dt1_o + qcom_dt1_o + #0000FF + true + + + qcom_dt2_o + qcom_dt2_o + #0000FF + true + + + qcom_vld_o + qcom_vld_o + #0000FF + true + + + qcom_flag_o + qcom_flag_o + #0000FF + true + + + qproc_start_o + qproc_start_o + #0000FF + true + + + pmod_o[3:0] + pmod_o[3:0] + #0000FF + true + + + + QCOM_CFG[3:0] + QCOM_CFG[3:0] + UNSIGNEDDECRADIX + + + qcom_dt1_o[31:0] + qcom_dt1_o[31:0] + SIGNEDDECRADIX + + + qcom_dt2_o[31:0] + qcom_dt2_o[31:0] + UNSIGNEDDECRADIX + + + qcom_flag_o + qcom_flag_o + + + qcom_tx_st[31:0] + qcom_tx_st[31:0] + #FF00FF + true + + + qcom_rx_st[31:0] + qcom_rx_st[31:0] + #FF00FF + true + + + qctrl_st[31:0] + qctrl_st[31:0] + #FF00FF + true + + + tx_vld + tx_vld + + + qcom_sync + qcom_sync + + + qctrl_sync + qctrl_sync + + + start_req + start_req + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + + + start_ack + start_ack + + + tx_vld_i + tx_vld_i + #808000 + true + + + tx_header_i[3:0] + tx_header_i[3:0] + #808000 + true + + + tx_data_i[31:0] + tx_data_i[31:0] + #808000 + true + + + qcom_rx_st[31:0] + qcom_rx_st[31:0] + #FF00FF + true + + + qctrl_st[31:0] + qctrl_st[31:0] + + + rx_vld_o + rx_vld_o + #808000 + true + + + rx_header_o[2:0] + rx_header_o[2:0] + #808000 + true + + + rx_data_o[32:0] + rx_data_o[32:0] + #808000 + true + SIGNEDDECRADIX + + + qcom_vld_o + qcom_vld_o + + + cmd_req_i + cmd_req_i + + + cmd_op_i[3:0] + cmd_op_i[3:0] + + + qcom_flag_o + qcom_flag_o + + + qcom_dt1_o[31:0] + qcom_dt1_o[31:0] + + + qcom_dt2_o[31:0] + qcom_dt2_o[31:0] + + + c_clk + c_clk + + + t_clk + t_clk + + + ps_clk + ps_clk + + + sync_i + sync_i + #00FFFF + true + + + label + qproc_start_o + qproc_start_o + #0000FF + true + qproc_start_1 + + + label + qproc_start_o + qproc_start_o + #0000A0 + true + qproc_start_2 + + + qctrl_st[31:0] + qctrl_st[31:0] + + + tx_sync + tx_sync + + + rx_sync + rx_sync + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + + + start_ack + start_ack + + + qctrl_st[31:0] + qctrl_st[31:0] + + + tx_sync + tx_sync + #808000 + true + + + rx_sync + rx_sync + #808000 + true + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + #808000 + true + + + start_ack + start_ack + #808000 + true + + diff --git a/firmware/ip/qick_com/src/TB/tb_qcom.sv b/firmware/ip/qick_com/src/TB/tb_qcom.sv new file mode 100644 index 000000000..a3ea22373 --- /dev/null +++ b/firmware/ip/qick_com/src/TB/tb_qcom.sv @@ -0,0 +1,409 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_T_CLK 1 // 1.66 // Half Clock Period for Simulation +`define T_C_CLK 2 +`define T_PS_CLK 5 // Half Clock Period for Simulation + +localparam DEBUG = 0; // Debugging + +module tb_qcom(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, t_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +reg sync_i; +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + t_clk = 1'b0; + forever # (`T_T_CLK) t_clk = ~t_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + sync_i = 1'b0; + forever # (1000) sync_i = ~sync_i; +end + + + + +reg c_cmd_i ; +reg [4 :0] c_op_i; + +// Register ADDRESS +parameter QCOM_CTRL = 0 * 4 ; +parameter QCOM_CFG = 1 * 4 ; +parameter RAXI_DT1 = 2 * 4 ; +parameter QCOM_FLAG = 7 * 4 ; +parameter QCOM_DT1 = 8 * 4 ; +parameter QCOM_DT2 = 9 * 4 ; +parameter QCOM_STATUS = 10 * 4 ; + + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk (ps_clk ), + .aresetn (rst_ni ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) +); + +reg [ 3:0] pmod_si ; +wire[ 3:0] pmod_o1, pmod_o2, pmod_i ; +reg [31:0] c_dt1_i, c_dt2_i, c_dt3_i ; + +////////////////////////////////////////////////////////////////////////// +// QCOM1 +axi_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_1 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .t_clk ( t_clk ) , + .t_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( c_cmd_i ) , + .qcom_op_i ( c_op_i ) , + .qcom_dt1_i ( c_dt1_i ) , + .qcom_rdy_o ( ready ) , + .qcom_dt1_o ( qcom_dt1_o ) , + .qcom_dt2_o ( qcom_dt2_o ) , + .qcom_vld_o ( qcom_vld_o ) , + .qcom_flag_o ( qcom_flag_o ) , + .qproc_start_o ( qproc_start_o1 ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o1 ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .qcom_do ( qcom_do ) +); +////////////////////////////////////////////////////////////////////////// +// QCOM +axi_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_2 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .t_clk ( t_clk ) , + .t_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( 0 ) , + .qcom_op_i ( 0 ) , + .qcom_dt1_i ( 0 ) , + .qcom_rdy_o ( ) , + .qcom_dt1_o ( ) , + .qcom_dt2_o ( ) , + .qcom_vld_o ( ) , + .qcom_flag_o ( ) , + .qproc_start_o ( qproc_start_o2 ) , + .pmod_i ( pmod_o1 ) , + .pmod_o ( pmod_o2 ) , + .s_axi_awaddr ( 0 ) , + .s_axi_awprot ( 0 ) , + .s_axi_awvalid ( 0 ) , + .s_axi_awready ( ) , + .s_axi_wdata ( 0 ) , + .s_axi_wstrb ( 0 ) , + .s_axi_wvalid ( 0 ) , + .s_axi_wready ( ) , + .s_axi_bresp ( ) , + .s_axi_bvalid ( ) , + .s_axi_bready ( ) , + .s_axi_araddr ( 0 ) , + .s_axi_arprot ( 0 ) , + .s_axi_arvalid ( 0 ) , + .s_axi_arready ( ) , + .s_axi_rdata ( ) , + .s_axi_rresp ( ) , + .s_axi_rvalid ( ) , + .s_axi_rready ( ) , + .qcom_do ( ) +); + + + +reg tx_loop; + +initial begin + START_SIMULATION(); + SIM_BUG(); + //SIM_CMD_TPROC(); + //SIM_CMD_PYTHON(); + //TEST_AXI () ; + //#2000; + // SIM_RX(); + // SIM_TX(); + +end + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qcom.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + c_cmd_i = 1'b0 ; + c_op_i = 5'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + pmod_si = 0; + tx_loop = 1'b0 ; + #25; + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + +end +endtask + +assign pmod_i = tx_loop ? pmod_o1 : pmod_si; + +integer conf; + +task SIM_BUG(); begin + $display("SIM BUG"); + + for (conf = 1 ; conf <= 15; conf=conf+1) begin + WRITE_AXI( QCOM_CFG , conf); // DATA + WRITE_AXI( RAXI_DT1 , 1001001*conf); // DATA + CMD_SEND_32B_DT1 (); + #1000; + WRITE_AXI( RAXI_DT1 , 2002001*conf); // DATA + CMD_SEND_32B_DT2 (); + #1000; + end +end +endtask + + +task SIM_CMD_PYTHON(); begin + $display("SIM Command from PYTHON"); + @ (posedge c_clk); #0.1; + WRITE_AXI( RAXI_DT1 , -1); // DATA + CMD_SET_FLG (); + CMD_CLR_FLG (); + WRITE_AXI( QCOM_CFG , 7); // DATA + WRITE_AXI( RAXI_DT1 , 700000007); // DATA + + CMD_SEND_8B_DT1 (); + CMD_SEND_8B_DT2 (); + CMD_SEND_16B_DT1 (); + #250; + CMD_SEND_16B_DT2 (); + #250; + CMD_SEND_32B_DT1 (); + #500; + CMD_SEND_32B_DT2 (); + #500; + CMD_SYNC_START (); + #4000; + WRITE_AXI( RAXI_DT1 , 0 ); // DATA + CMD_SEND_32B_DT1 (); + #500; + CMD_SEND_32B_DT2 (); + #500; +end +endtask + +task CMD_RUN(); begin + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + wait (ready == 1'b1); +end +endtask + +task SIM_CMD_TPROC(); begin + $display("SIM Command from TPROC"); + c_dt1_i = -1; + + @ (posedge c_clk); #0.1; + c_op_i = 5'd8; //SET FLAG + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd0; //CLR FLAG + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd2; //SEND 8_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd3; //SEND 8_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd4; //SEND 16_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd5; //SEND 16_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd6; //SEND 32_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd7; //SEND 32_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd10; //SYNC + CMD_RUN(); + end + #4000; +endtask + +task CMD_CLR_FLG (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 0); +endtask +task CMD_SEND_8B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 2); +endtask +task CMD_SEND_8B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 3); +endtask +task CMD_SEND_16B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 4); +endtask +task CMD_SEND_16B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 5); +endtask +task CMD_SEND_32B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 6); +endtask +task CMD_SEND_32B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 7); +endtask +task CMD_SET_FLG (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 8); +endtask +task CMD_SYNC_START (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 10); +endtask + + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QCOM_CTRL , 1 *2+1); // Set Flag + WRITE_AXI( QCOM_CTRL , 0 *2+1); // Clear Flag + WRITE_AXI( QCOM_CTRL , 1 *2+1); // Set Flag + WRITE_AXI( QCOM_CTRL , 0 *2+1); // Clear Flag + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 2 *2+1); // Send 8bit (1) + WRITE_AXI( RAXI_DT1 , 8); // DATA + WRITE_AXI( QCOM_CTRL , 10 *2+1); // Send 8bit (2) + WRITE_AXI( QCOM_CTRL , 3 *2+1); // SYNC_START + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 4 *2+1); // Send 16bit (1) + WRITE_AXI( RAXI_DT1 , 16); // DATA + WRITE_AXI( QCOM_CTRL , 12 *2+1); // Send 16bit (2) + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 6 *2+1); // Send 32bit (1) + WRITE_AXI( RAXI_DT1 , 32); // DATA + WRITE_AXI( QCOM_CTRL , 14 *2+1); // Send 32bit (2) +end +endtask + + + +endmodule + + + + diff --git a/firmware/ip/qick_com/src/_qcom_ips.sv b/firmware/ip/qick_com/src/_qcom_ips.sv new file mode 100644 index 000000000..e22486dd8 --- /dev/null +++ b/firmware/ip/qick_com/src/_qcom_ips.sv @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +/// Clock Domain Register Change +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_cdc, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_cdc <= 0; + data_r <= 0; + end else begin + data_cdc <= dt_i; + data_r <= data_cdc; + end +assign dt_o = data_r ; + +endmodule diff --git a/firmware/ip/qick_com/src/axi_qick_com.sv b/firmware/ip/qick_com/src/axi_qick_com.sv new file mode 100644 index 000000000..38bd41117 --- /dev/null +++ b/firmware/ip/qick_com/src/axi_qick_com.sv @@ -0,0 +1,196 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_6_20 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Board Communication Peripheral +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_com # ( + parameter SYNC = 0 , + parameter DEBUG = 0 +)( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire t_clk , + input wire t_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// QCOM INTERFACE (c_clk) + input wire qcom_en_i , + input wire [4:0] qcom_op_i , + input wire [31:0] qcom_dt1_i , + output reg qcom_rdy_o , + output reg [31:0] qcom_dt1_o , + output reg [31:0] qcom_dt2_o , + output reg qcom_vld_o , + output reg qcom_flag_o , +// TPROC CONTROL (t_clk) + input wire sync_i , + output reg qproc_start_o , +// PMOD COM (c_clk) + input wire [ 3:0] pmod_i , + output reg [ 3:0] pmod_o , +// AXI-Lite DATA Slave I/F (ps_clk) + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// DEBUG + output wire [31:0] qcom_do +); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// + +wire [31:0] qcom_flag, qcom_dt_1, qcom_dt_2 ; // QCOM Outputs +wire [31:0] qcom_tx_dt_ds, qcom_rx_dt_ds, qcom_status_ds, qcom_ds; +wire [15:0] qcom_debug_ds ; + +wire [31:0] xreg_tx_dt, xreg_rx_dt ; +wire [23:0] xreg_debug ; + +// QCOM Control (From Python and tProc) +wire [ 3:0] cmd_op ; +wire [31:0] cmd_dt ; +wire [ 7:0] cmd_cnt ; + +wire [ 7:0] QCOM_CTRL ; +wire [ 3:0] QCOM_CFG ; +wire [31:0] RAXI_DT1 ; + +wire sync_s ; +reg qproc_start_s ; + + +qick_cmd #( + .OP_DW ( 4 ), + .DT_QTY ( 1 ) +) CMD ( + .clk_i ( c_clk ), + .rst_ni ( c_aresetn ), + .ps_clk_i ( ps_clk ), + .ps_rst_ni ( ps_aresetn ), + .c_en_i ( qcom_en_i ), + .c_op_i ( qcom_op_i ), + .c_dt_i ( '{qcom_dt1_i} ), + .p_ctrl_i ( QCOM_CTRL[4:0] ), + .p_dt_i ( '{RAXI_DT1} ), + .cmd_req_o ( cmd_req ), + .cmd_ack_i ( cmd_ack ), + .cmd_op_o ( cmd_op ), + .cmd_dt_o ( '{cmd_dt} ), + .cmd_cnt_do ( cmd_cnt )); + +qick_com QCOM ( + .c_clk_i ( c_clk ), + .c_rst_ni ( c_aresetn ), + .t_clk_i ( t_clk ), + .t_rst_ni ( t_aresetn ), + .qcom_cfg_i ( QCOM_CFG[3:0] ), + .pulse_i ( sync_s ), + .cmd_req_i ( cmd_req ), + .cmd_ack_o ( cmd_ack ), + .cmd_op_i ( cmd_op ), + .cmd_dt_i ( cmd_dt ), + .qcom_rdy_o ( qcom_rdy_o ), + .qcom_dt1_o ( qcom_dt1_o ), + .qcom_dt2_o ( qcom_dt2_o ), + .qcom_vld_o ( qcom_vld_o ), + .qcom_flag_o ( qcom_flag_o ), + .qproc_start_o ( qproc_start_s ), + .pmod_i ( pmod_i ), + .pmod_o ( pmod_o ), + .qcom_tx_dt_do ( qcom_tx_dt_ds ), + .qcom_rx_dt_do ( qcom_rx_dt_ds ), + .qcom_status_do ( qcom_status_ds ), + .qcom_debug_do ( qcom_debug_ds ), + .qcom_do ( qcom_ds )); + + + +/////////////////////////////////////////////////////////////////////////////// +// AXI Registers +/////////////////////////////////////////////////////////////////////////////// +axi_slv_qcom QCOM_xREG ( + .aclk ( ps_clk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( s_axi_awaddr [5:0] ) , + .awprot ( s_axi_awprot ) , + .awvalid ( s_axi_awvalid ) , + .awready ( s_axi_awready ) , + .wdata ( s_axi_wdata ) , + .wstrb ( s_axi_wstrb ) , + .wvalid ( s_axi_wvalid ) , + .wready ( s_axi_wready ) , + .bresp ( s_axi_bresp ) , + .bvalid ( s_axi_bvalid ) , + .bready ( s_axi_bready ) , + .araddr ( s_axi_araddr ) , + .arprot ( s_axi_arprot ) , + .arvalid ( s_axi_arvalid ) , + .arready ( s_axi_arready ) , + .rdata ( s_axi_rdata ) , + .rresp ( s_axi_rresp ) , + .rvalid ( s_axi_rvalid ) , + .rready ( s_axi_rready ) , + .QCOM_CTRL ( QCOM_CTRL ) , + .QCOM_CFG ( QCOM_CFG ) , + .RAXI_DT1 ( RAXI_DT1 ) , + .QCOM_FLAG ( qcom_flag_o ) , + .QCOM_DT_1 ( qcom_dt1_o ) , + .QCOM_DT_2 ( qcom_dt2_o ) , + .QCOM_STATUS ( qcom_status_ds ) , + .QCOM_TX_DT ( xreg_tx_dt ) , + .QCOM_RX_DT ( xreg_rx_dt ) , + .QCOM_DEBUG ( xreg_debug ) ); + + + +/////////////////////////////////////////////////////////////////////////////// +// SYNC OPTION +/////////////////////////////////////////////////////////////////////////////// +generate + if (SYNC == 0) begin : SYNC_NO + assign sync_s = 0 ; + assign qproc_start_o = 0 ; + end else if (SYNC == 1) begin : SYNC_YES + assign sync_s = sync_i ; + assign qproc_start_o = qproc_start_s ; + end +endgenerate +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + +generate + if (DEBUG == 0) begin : DEBUG_NO + assign xreg_tx_dt = '{default:'0} ; + assign xreg_rx_dt = '{default:'0} ; + assign xreg_debug = '{default:'0} ; + end else if (DEBUG == 1) begin : DEBUG_YES + assign xreg_tx_dt = qcom_tx_dt_ds; + assign xreg_rx_dt = qcom_rx_dt_ds; + assign xreg_debug = {qcom_debug_ds, cmd_cnt}; + end +endgenerate + +endmodule diff --git a/firmware/ip/qick_com/src/axi_slv_qcom.vhd b/firmware/ip/qick_com/src/axi_slv_qcom.vhd new file mode 100644 index 000000000..2eb37749c --- /dev/null +++ b/firmware/ip/qick_com/src/axi_slv_qcom.vhd @@ -0,0 +1,521 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qcom is Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + QCOM_CTRL : out std_logic_vector ( 7 downto 0) ; + QCOM_CFG : out std_logic_vector ( 3 downto 0) ; + RAXI_DT1 : out std_logic_vector (31 downto 0) ; + QCOM_FLAG : in std_logic ; + QCOM_DT_1 : in std_logic_vector (31 downto 0) ; + QCOM_DT_2 : in std_logic_vector (31 downto 0) ; + QCOM_STATUS : in std_logic_vector ( 7 downto 0) ; + QCOM_TX_DT : in std_logic_vector (31 downto 0) ; + QCOM_RX_DT : in std_logic_vector (31 downto 0) ; + QCOM_DEBUG : in std_logic_vector (23 downto 0) ); +end axi_slv_qcom; + +architecture rtl of axi_slv_qcom is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= "00000000000000000000000000000011"; + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, QCOM_FLAG, QCOM_DT_1, QCOM_DT_2, QCOM_STATUS, QCOM_TX_DT, QCOM_RX_DT, QCOM_DEBUG, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0101" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0110" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0111" => + reg_data_out <= "0000000000000000000000000000000" & QCOM_FLAG; + when b"1000" => + reg_data_out <= QCOM_DT_1; + when b"1001" => + reg_data_out <= QCOM_DT_2; + when b"1010" => + reg_data_out <= "000000000000000000000000" & QCOM_STATUS; + when b"1011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1101" => + reg_data_out <= QCOM_TX_DT; + when b"1110" => + reg_data_out <= QCOM_RX_DT; + when b"1111" => + reg_data_out <= "00000000" & QCOM_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. + +QCOM_CTRL <= slv_reg0( 7 downto 0); +QCOM_CFG <= slv_reg1( 3 downto 0); +RAXI_DT1 <= slv_reg2(31 downto 0); + +end rtl; + + + + diff --git a/firmware/ip/qick_com/src/qcom_link.sv b/firmware/ip/qick_com/src/qcom_link.sv new file mode 100644 index 000000000..2035e0a5c --- /dev/null +++ b/firmware/ip/qick_com/src/qcom_link.sv @@ -0,0 +1,372 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qcom_link ( +// Core and AXI CLK & RST + input wire c_clk_i , + input wire c_rst_ni , +// Config + input wire [ 3:0] tick_cfg , // Pulse Duration of PMOD measured in c_clk +// Transmittion + input wire tx_vld_i , + output reg tx_ready_o , + input wire [ 3:0] tx_header_i , + input wire [31:0] tx_data_i , +// Command Processing + output reg rx_vld_o , + output reg [ 2:0] rx_header_o , + output reg [32:0] rx_data_o , +// PMOD COM + input wire [ 3:0] pmod_i , + output reg [ 3:0] pmod_o , +///// DEBUG + output wire [31:0] qcom_link_do + ); + +/////////////////////////////////////////////////////////////////////////////// +// ###### # # +// # # # # +// # # # # +// ###### # +// # # # # +// # # # # +// # # # # +/////////////////////////////////////////////////////////////////////////////// +reg rx_idle_s, rx_header_s, rx_end_s, rx_fault_s ; + + +/////////////////////////////////////////////////////////////////////////////// +// Sync Input and PMOD[3] edge detection +reg [3:0] pmod_r, pmod_r2; +(* ASYNC_REG = "TRUE" *) reg [3:0] pmod_cdc ; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + pmod_cdc <= 4'd0; + pmod_r <= 4'd0; + pmod_r2 <= 4'd0; + end else begin + pmod_cdc <= pmod_i; + pmod_r <= pmod_cdc; + pmod_r2 <= pmod_r; + end +end +assign rx_new_dt = pmod_r2[3] ^ pmod_r[3]; + +/////////////////////////////////////////////////////////////////////////////// +// RX Store Data +reg [32:0] rx_dt; +reg [2:0] rx_header_r ; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + rx_dt <= '{default:'0} ; + rx_header_r <= '{default:'0} ; + end else begin + if (rx_new_dt) begin + if ( rx_idle_s ) rx_header_r <= { pmod_r[2], pmod_r[1], pmod_r[0] } ; + else rx_dt <= { rx_dt[29:0], pmod_r[2], pmod_r[1], pmod_r[0] } ; + end else if (rx_end_s | rx_fault_s) begin + rx_dt <= '{default:'0} ; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +// RX Decoding +reg [3:0] rx_pack_size; +always_comb begin + case ( rx_header_r ) + 3'b000 : rx_pack_size = 4'd1 ; // CLEAR FLAG (1) + 3'b001 : rx_pack_size = 4'd1 ; // SET FLAG (1) + 3'b010 : rx_pack_size = 4'd4 ; // Receive 8 Bits (4) + 3'b011 : rx_pack_size = 4'd4 ; // Receive SYNC Command + 3'b100 : rx_pack_size = 4'd7 ; // Receive 16 Bits (7) + 3'b110 : rx_pack_size = 4'd12; // Receive 32 Bits (12) + default : rx_pack_size = 4'd0; + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// RX Measurment +reg [4:0] rx_time_out_cnt, rx_tick_cnt ; +reg [3:0] rx_pack_cnt ; + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + rx_tick_cnt <= 5'd1; + rx_time_out_cnt <= 5'd0; + rx_pack_cnt <= 8'd1; + end else begin + if (rx_new_dt) begin + rx_pack_cnt <= rx_pack_cnt + 1'b1 ; + rx_time_out_cnt <= 4'd0; + end else begin + if (rx_header_s) rx_tick_cnt <= rx_tick_cnt + 1'b1; + else if ( rx_idle_s ) rx_tick_cnt <= 5'd1; + if (rx_idle_s) begin + rx_pack_cnt <= 8'd1; + rx_time_out_cnt <= 4'd0; + end else + rx_time_out_cnt <= rx_time_out_cnt + 1'b1 ; + end + end +end + +wire rx_time_out, rx_last_dt, rx_single_dt; +assign rx_last_dt = rx_new_dt & (rx_pack_size == rx_pack_cnt) ; // Last Data Received +assign rx_single_dt = rx_new_dt & (rx_pack_size == 4'd1) ; // Package has only Header +assign rx_time_out = rx_time_out_cnt > rx_tick_cnt ; // New Data was not received in time + +/////////////////////////////////////////////////////////////////////////////// +///// RX STATE +typedef enum { RX_IDLE, RX_HEADER, RX_DATA, RX_END, RX_FAULT, RX_CHECK, RX_RTZ } TYPE_RX_ST ; +(* fsm_encoding = "one_hot" *) TYPE_RX_ST rx_st; +TYPE_RX_ST rx_st_nxt; + + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) rx_st <= RX_IDLE; + else rx_st <= rx_st_nxt; +end +always_comb begin + rx_st_nxt = rx_st; // Default Current + rx_idle_s = 1'b0; + rx_header_s = 1'b0; + rx_end_s = 1'b0; + rx_fault_s = 1'b0; + case (rx_st) + RX_IDLE : begin + rx_idle_s = 1'b1; + if ( rx_new_dt ) begin + if (pmod_r[3]) rx_st_nxt = RX_HEADER; // First Transition 0 to 1 + else rx_st_nxt = RX_RTZ; // Tx is returning to Zero + end + end + RX_HEADER : begin + rx_header_s = 1'b1; + if ( rx_single_dt ) rx_st_nxt = RX_END; // Package has only Header + else if ( rx_new_dt ) rx_st_nxt = RX_DATA; // New Data Received + else if ( rx_time_out ) rx_st_nxt = RX_FAULT; + end + RX_DATA : begin + if ( rx_last_dt ) rx_st_nxt = RX_END; // Last Data Received + else if ( rx_time_out ) rx_st_nxt = RX_FAULT; // No Data Received + end + RX_END : begin + rx_end_s = 1'b1; + rx_st_nxt = RX_CHECK; + end + RX_CHECK : begin + if ( rx_new_dt ) begin + if ( pmod_r[3] ) rx_st_nxt = RX_FAULT; // Extra Data Received + else rx_st_nxt = RX_RTZ; // Tx is returning to Zero + end else if (rx_time_out) rx_st_nxt = RX_IDLE; // No more Data is received + end + RX_FAULT : begin + rx_fault_s = 1'b1; + rx_st_nxt = RX_IDLE; + end + RX_RTZ : begin + rx_st_nxt = RX_IDLE; + end + endcase +end + + + +/////////////////////////////////////////////////////////////////////////////// +// ####### # # +// # # # +// # # # +// # # +// # # # +// # # # +// # # # +/////////////////////////////////////////////////////////////////////////////// +reg tx_idle_s, tx_header_s, tx_data_s, tx_end_s; +reg tick_clk ; //Clock (PMOD[3})should be updated +reg tick_dt ; //Data (PMOD[2:0})should be updated +reg tick_en ; // Enable tick Generation + + +/////////////////////////////////////////////////////////////////////////////// +// TX Encode Header and Check Command +reg [ 3:0] tx_pack_size, tx_pack_size_r; +reg [35:0] tx_dt ; +reg tx_ok; + +always_comb begin + tx_pack_size = 4'd0; + tx_dt = 33'd0 ; + tx_ok = 1'b0; + case ( tx_header_i[3:1] ) + 3'b000 : begin // CLEAR FLAG (1) + tx_pack_size = 4'd1; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b001 : begin // SET FLAG (1) + tx_pack_size = 4'd1; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b010 : begin // Send 8 Bits (4) + tx_pack_size = 4'd4; + tx_dt = {tx_header_i, tx_data_i[7:0], 24'd0}; + tx_ok = 1'b1; + end + 3'b011 : begin // Send SYNC COMMAND + tx_pack_size = 4'd4; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b100 : begin // Send 16 Bits (7) + tx_pack_size = 4'd7; + tx_dt = {tx_header_i, 1'b0, tx_data_i[15:0], 15'd0}; + tx_ok = 1'b1; + end + 3'b110 : begin // Send 32 Bits (12) + tx_pack_size = 4'd12; + tx_dt = {tx_header_i, tx_data_i[31:0]}; + tx_ok = 1'b1; + end + default : begin + tx_pack_size = 4'd0; + tx_dt = 33'd0 ; + tx_ok = 1'b0; + end + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// TX Registers + +reg [ 3:0] tx_pmod ; // PMOD values for OUTPUT [3]Clk [2:0]Data +reg [35:0] tx_buff ; //Shift Register For Par 2 Ser. (Data encoded on tx_dt) +reg [ 3:0] tx_pack_cnt; //Number of Packages transmited (Total Defined in tx_pack_size) + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + tx_pmod <= '{default:'0} ; + tx_buff <= '{default:'0} ; + tx_pack_cnt <= 4'd0; + tx_pack_size_r <= 4'd0; + end else begin + if (tx_vld_i) begin + tx_buff <= tx_dt; + tx_pack_cnt <= 8'd0; + tx_pack_size_r <= tx_pack_size; + end else if ( tx_idle_s ) begin + tx_pmod[3] <= 1'b0; + end else if ( tick_clk ) + tx_pmod[3] <= ~tx_pmod[3]; + if (tick_dt) begin + tx_pack_cnt <= tx_pack_cnt + 1'b1 ; + tx_buff <= tx_buff << 3; + tx_pmod[2] <= tx_buff[35] ; + tx_pmod[1] <= tx_buff[34] ; + tx_pmod[0] <= tx_buff[33] ; + end + end +end + +assign tx_last_dt = (tx_pack_cnt == tx_pack_size_r) ; + + +/////////////////////////////////////////////////////////////////////////////// +// TICK GENERATOR + +reg [ 3:0] tx_tick_cnt ; // NUmber of c_clk in current PMOD Pulse + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + tx_tick_cnt <= 1'b0; + tick_clk <= 1'b0; + tick_dt <= 1'b0; + end else begin + if (tick_en) begin + if (tx_tick_cnt == tick_cfg) begin + tick_clk <= 1'b1; + tx_tick_cnt <= 4'd1; + end else begin + tick_clk <= 1'b0; + tx_tick_cnt <= tx_tick_cnt + 1'b1 ; + end + if (tx_tick_cnt == tick_cfg>>1) tick_dt <= 1'b1; + else tick_dt <= 1'b0; + end else begin + tx_tick_cnt <= tick_cfg>>1 ; + tick_dt <= 1'b0; + tick_clk <= 1'b0; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +///// TX STATE +typedef enum { TX_IDLE, TX_DT, TX_CLK, TX_END, TX_RTZ, TX_WAIT } TYPE_TX_ST ; +(* fsm_encoding = "one_hot" *) TYPE_TX_ST tx_st; +TYPE_TX_ST tx_st_nxt; + + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) tx_st <= TX_IDLE; + else tx_st <= tx_st_nxt; +end +always_comb begin + tx_st_nxt = tx_st; // Default Current + tick_en = 1'b0; + tx_idle_s = 1'b0; + case (tx_st) + TX_IDLE : begin + tx_idle_s = 1'b1; + if ( tx_vld_i & tx_ok ) tx_st_nxt = TX_DT; + end + TX_DT : begin + tick_en = 1'b1; + tx_data_s = 1'b1; + if ( tick_clk ) tx_st_nxt = TX_CLK; + end + TX_CLK : begin + tick_en = 1'b1; + tx_header_s = 1'b1; + if ( tick_dt ) begin + if ( tx_last_dt ) tx_st_nxt = TX_END; + else tx_st_nxt = TX_DT; + end + end + TX_END : begin + tick_en = 1'b1; + tx_end_s = 1'b1; + if (tx_pmod[3]) tx_st_nxt = TX_RTZ; + else tx_st_nxt = TX_WAIT; + end + TX_RTZ : begin + tick_en = 1'b1; + if ( tick_clk ) tx_st_nxt = TX_WAIT; + end + TX_WAIT : begin + tick_en = 1'b1; + if ( tick_dt ) tx_st_nxt = TX_IDLE; + end + + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +assign tx_ready_o = tx_idle_s; +assign rx_vld_o = rx_end_s; +assign rx_header_o = rx_header_r; +assign rx_data_o = rx_dt; +assign pmod_o = tx_pmod; +assign qcom_link_do = 0; + +endmodule + diff --git a/firmware/ip/qick_com/src/qick_cmd.sv b/firmware/ip/qick_com/src/qick_cmd.sv new file mode 100644 index 000000000..852d1fa41 --- /dev/null +++ b/firmware/ip/qick_com/src/qick_cmd.sv @@ -0,0 +1,119 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// This module receives commands from the Processor and from Python and generates the Request signal +/* +qick_cmd #( + .OP_DW ( 5 ), + .DT_QTY ( 4 ) +) CMD_SYNC ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .c_en_i ( c_en_i ), + .c_op_i ( c_op_i ), + .c_dt_i ( c_dt_i ), + .p_ctrl_i ( p_ctrl_i ), + .p_dt_i ( p_dt_i ), + .cmd_req_o ( cmd_req_o ), + .cmd_ack_i ( cmd_ack_i ), + .cmd_op_o ( cmd_op_o ), + .cmd_dt_o ( cmd_dt_o ), + .cmd_cnt_do ( cmd_cnt_do )); +*/ + +module qick_cmd #( + parameter OP_DW = 5 , + parameter DT_QTY = 4 +)( + input wire clk_i , + input wire rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + // Command from tProcessor + input wire c_en_i , + input wire [4:0] c_op_i , + input wire [31:0] c_dt_i [DT_QTY] , + // Command from Python + input wire [OP_DW:0] p_ctrl_i , + input wire [31:0] p_dt_i [DT_QTY] , + // Command Execution + output wire cmd_req_o , + input wire cmd_ack_i , + output wire [OP_DW-1:0] cmd_op_o , + output wire [31:0] cmd_dt_o [DT_QTY], + output wire [7 :0] cmd_cnt_do ); + +// PS to Core Sincronization +/////////////////////////////////////////////////////////////////////////////// +// Register the Operation and generates one clock later the Enable. +reg [OP_DW-1:0] p_op_r; +reg p_ctrl_en, p_ctrl_en_r; +always_ff @(posedge ps_clk_i) + if (!ps_rst_ni) begin + p_op_r <= 0; + p_ctrl_en <= 1'b0; + p_ctrl_en_r <= 1'b0; + end else begin + if (p_ctrl_i[0]) + p_op_r <= p_ctrl_i[OP_DW:1]; + p_ctrl_en <= p_ctrl_i[0]; + p_ctrl_en_r <= p_ctrl_en; + end +wire p_en_r, p_en_r_t01; +sync_reg # ( + .DW ( 1 ) +) sync_tx_i ( + .dt_i ( p_ctrl_en_r ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( p_en_r ) ); + +reg p_en_2r; +always_ff @(posedge clk_i) if (!rst_ni) p_en_2r <= 1'b0; else p_en_2r <= p_en_r; + +assign p_en_r_t01 = !p_en_2r & p_en_r; + +// COMMAND OPERATON +reg cmd_req; +reg [OP_DW-1:0] cmd_op; +reg [31:0] cmd_dt [DT_QTY]; +// Command Debug +reg [ 3:0] p_cmd_cnt, c_cmd_cnt; + +always_ff @(posedge clk_i) + if (!rst_ni) begin + cmd_req <= 1'b0; + cmd_op <= '{default:'0}; + cmd_dt <= '{default:'0}; + p_cmd_cnt <= 3'd0; + c_cmd_cnt <= 3'd0; + end else begin + if (p_en_r_t01 & !cmd_ack_i) begin + cmd_req <= 1'b1; + cmd_op <= p_op_r ; + cmd_dt <= p_dt_i ; + p_cmd_cnt <= p_cmd_cnt + 1'b1; + end else if (c_en_i & !cmd_ack_i) begin + cmd_req <= 1'b1; + cmd_op <= c_op_i ; + cmd_dt <= c_dt_i ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + end else + if ( cmd_ack_i ) cmd_req <= 1'b0; + end + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +assign cmd_req_o = cmd_req; +assign cmd_op_o = cmd_op; +assign cmd_dt_o = cmd_dt; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign cmd_cnt_do ={ c_cmd_cnt, p_cmd_cnt }; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_com/src/qick_com.sv b/firmware/ip/qick_com/src/qick_com.sv new file mode 100644 index 000000000..0fbb70049 --- /dev/null +++ b/firmware/ip/qick_com/src/qick_com.sv @@ -0,0 +1,407 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qick_com ( +// Core and AXI CLK & RST + input wire c_clk_i , + input wire c_rst_ni , + input wire t_clk_i , + input wire t_rst_ni , +// QCOM INTERFACE + input wire pulse_i , + input wire [3:0] qcom_cfg_i , +// QCOM INTERFACE + input wire cmd_req_i , + output wire cmd_ack_o , + input wire [3:0] cmd_op_i , + input wire [31:0] cmd_dt_i , + output reg qcom_rdy_o , + output reg [31:0] qcom_dt1_o , + output reg [31:0] qcom_dt2_o , + output reg qcom_vld_o , + output reg qcom_flag_o , +// TPROC CONTROL + output reg qproc_start_o , +// PMOD COM + input wire [ 3:0] pmod_i , + output wire [ 3:0] pmod_o , +// DEBUG + output wire [31:0] qcom_tx_dt_do , + output wire [31:0] qcom_rx_dt_do , + output wire [31:0] qcom_status_do , + output wire [15:0] qcom_debug_do , + output wire [31:0] qcom_do ); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// +reg t_start_ack; +reg cmd_end, start_req; + +// Register Inputs +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qcom_dt ; +wire [ 3:0] qcom_header ; +wire [ 1:0] qcom_dt_size ; + +assign qcom_type = cmd_op_i[3]; +assign qcom_dt_size = cmd_op_i[2:1] ; +assign qcom_dt_dst = cmd_op_i[0]; + +assign qcom_header = { qcom_dt_size, qcom_type, qcom_dt_dst}; +assign qcom_dt = cmd_dt_i; +assign qcom_sync = ( cmd_op_i[3:0] == 4'b1010 ); + + + +/////////////////////////////////////////////////////////////////////////////// +// C CLOCK SYNC +reg c_sync_r2 ; +sync_reg # ( + .DW ( 1 ) +) c_sync_pulse ( + .dt_i ( pulse_i ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( c_sync_r ) ); +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) c_sync_r2 <= 1'b0; + else c_sync_r2 <= c_sync_r; +end +assign c_sync_t01 = !c_sync_r2 & c_sync_r ; + + +/////////////////////////////////////////////////////////////////////////////// +// ####### # # +// # # # +// # # # +// # # +// # # # +// # # # +// # # # +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// TX Control state +typedef enum { TX_IDLE, TX_SEND, TX_WSYNC, TX_WRDY, TX_WCMD } TYPE_TX_ST ; +(* fsm_encoding = "sequential" *) TYPE_TX_ST qcom_tx_st; +TYPE_TX_ST qcom_tx_st_nxt; + +reg tx_sync ; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qcom_tx_st <= TX_IDLE; + else qcom_tx_st <= qcom_tx_st_nxt; +end +reg tx_vld, qready; + +always_comb begin + qcom_tx_st_nxt = qcom_tx_st; // Default Current + tx_vld = 1'b0; + qready = 1'b0; + tx_sync = 1'b0; + case (qcom_tx_st) + TX_IDLE : begin + qready = 1'b1; + if ( cmd_req_i ) + if ( qcom_sync ) + qcom_tx_st_nxt = TX_WSYNC; + else begin + qcom_tx_st_nxt = TX_SEND; + tx_vld = 1'b1; + end + end + TX_WSYNC : begin + if ( c_sync_t01 ) begin + tx_vld = 1'b1; + qcom_tx_st_nxt = TX_SEND; + end + end + TX_SEND : begin + if ( qcom_sync ) qcom_tx_st_nxt = TX_WCMD; + else qcom_tx_st_nxt = TX_WRDY; + end + TX_WRDY : begin + if ( tx_ready ) qcom_tx_st_nxt = TX_IDLE; + end + TX_WCMD : begin + tx_sync = 1'b1; + if ( cmd_end ) qcom_tx_st_nxt = TX_IDLE; + end + endcase +end + + +/////////////////////////////////////////////////////////////////////////////// +// ###### # # +// # # # # +// # # # # +// ###### # +// # # # # +// # # # # +// # # # # +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// RX Decoding +wire [32:0] rx_data; // Data Received +wire [ 2:0] rx_header; // Header Received +reg reg_sel ; // Write Register Selection +reg [31:0] new_dt ; // New Data to Register reg_sel +wire [ 1:0] reg_wr_size; // Write Size 1, 8, 16, or 32 Bits +reg rx_wreg, rx_wflg, rx_sync; + +assign reg_wr_size = rx_header[2:1]; + +always_comb begin + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + rx_sync = 1'b0; + rx_wreg = 1'b0; + rx_wflg = 1'b0; + case ( reg_wr_size ) + 2'b00 : begin // 1 BIT + rx_wflg = 1'b1; + end + 2'b01 : begin // 8 BITS | SYNC + if ( rx_header[0] ) + rx_sync = 1'b1 ; + else begin + rx_wreg = 1'b1; + reg_sel = rx_data[8]; + new_dt = {24'd0, rx_data[7:0]}; + end + end + 2'b10 : begin // 16 BITS + rx_wreg = 1'b1; + reg_sel = rx_data[17]; + new_dt = {16'd0, rx_data[15:0]}; + end + 2'b11 : begin // 32 BIT + rx_wreg = 1'b1; + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + end + default : begin // :P + rx_wreg = 1'b1; + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + end + endcase +end + +assign rx_wreg_en = rx_vld & rx_wreg; +assign rx_wflg_en = rx_vld & rx_wflg; + +/////////////////////////////////////////////////////////////////////////////// +// Register Update +reg qflag_dt, rx_wreg_r ; +reg [31:0] qreg1_dt, qreg2_dt; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + qflag_dt <= 1'b0; + qreg1_dt <= '{default:'0} ; + qreg2_dt <= '{default:'0} ; + rx_wreg_r <= 1'b0; + end else begin + rx_wreg_r <= rx_wreg_en ; + if ( rx_wreg_en ) + case ( reg_sel ) + 1'b0 : qreg1_dt <= new_dt; // Reg_dt1 + 1'b1 : qreg2_dt <= new_dt; // Reg_dt2 + endcase + else if ( rx_wflg_en ) + qflag_dt <= rx_header[0]; // FLAG + + + end + +end + + +/////////////////////////////////////////////////////////////////////////////// +// RX +typedef enum { RX_IDLE, RX_CMD } TYPE_RX_ST ; + (* fsm_encoding = "sequential" *) TYPE_RX_ST qcom_rx_st; + TYPE_RX_ST qcom_rx_st_nxt; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qcom_rx_st <= RX_IDLE; + else qcom_rx_st <= qcom_rx_st_nxt; +end + +always_comb begin + qcom_rx_st_nxt = qcom_rx_st; // Default Current + case (qcom_rx_st) + RX_IDLE : + if ( rx_vld ) qcom_rx_st_nxt = RX_CMD; + RX_CMD : begin + qcom_rx_st_nxt = RX_IDLE; + end + endcase +end + + + + + +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR RESTART +assign qctrl_sync = tx_sync | rx_sync; + +// PULSE SYNC +/////////////////////////////////////////////////////////////////////////////// +// T CLOCK SYNC +reg t_sync_r2 ; +sync_reg # ( + .DW ( 1 ) +) t_sync_pulse ( + .dt_i ( pulse_i ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( t_sync_r ) ); + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) t_sync_r2 <= 1'b0; + else t_sync_r2 <= t_sync_r; +end +assign t_sync_t01 = !t_sync_r2 & t_sync_r ; + + + + +/////////////////////////////////////////////////////////////////////////////// +typedef enum { QRST_IDLE, QRST_REQ, QRST_WSYNC, QRST_CMD } TYPE_QCTRL_ST ; + (* fsm_encoding = "sequential" *) TYPE_QCTRL_ST qctrl_st; + TYPE_QCTRL_ST qctrl_st_nxt; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qctrl_st <= QRST_IDLE; + else qctrl_st <= qctrl_st_nxt; +end + +always_comb begin + qctrl_st_nxt = qctrl_st; // Default Current + cmd_end = 1'b0; + start_req = 1'b0; + case (qctrl_st) + QRST_IDLE : + if ( qctrl_sync ) qctrl_st_nxt = QRST_REQ; + QRST_REQ : begin + start_req = 1'b1; + if ( start_ack ) qctrl_st_nxt = QRST_WSYNC; + end + QRST_WSYNC : begin + if ( c_sync_t01 ) qctrl_st_nxt = QRST_CMD; + end + QRST_CMD : begin + cmd_end = 1'b1; + if ( !start_ack ) qctrl_st_nxt = QRST_IDLE; + end + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// REQ - ACK SYNC +sync_reg # (.DW(1)) t_sync_start_req ( + .dt_i ( start_req ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( t_start_req ) ); + +sync_reg # (.DW(1)) c_sync_start_ack ( + .dt_i ( t_start_ack ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( start_ack ) ); + +reg [2:0] t_start_cnt; +reg t_start_r; + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) begin + t_start_cnt <= 0; + t_start_ack <= 1'b0; + t_start_r <= 1'b0; + end else begin + if ( t_start_req ) t_start_ack <= 1'b1; + else if ( qproc_hit ) t_start_ack <= 1'b0; + + if ( qproc_hit ) t_start_r <= 1'b1; + else if ( t_start_cnt==3'd7 ) t_start_r <= 1'b0; + + if ( t_start_r ) t_start_cnt <= t_start_cnt+1'b1; + else t_start_cnt <= 0; + end +end + +assign qproc_hit = t_start_ack & t_sync_t01; + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +wire [3:0] tick_cfg ; +assign tick_cfg = qcom_cfg_i[3:0]; + +qcom_link QCOM_LINK ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .tick_cfg ( tick_cfg ) , + .tx_vld_i ( tx_vld ) , + .tx_ready_o ( tx_ready ) , + .tx_header_i ( qcom_header ) , + .tx_data_i ( qcom_dt ) , + .rx_vld_o ( rx_vld ) , + .rx_header_o ( rx_header ) , + .rx_data_o ( rx_data ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o ) , + .qcom_link_do ( ) +); + +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +reg [3:0] sync_cnt; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + sync_cnt <= 0; + end else begin + if ( c_sync_t01 ) sync_cnt <= sync_cnt + 1'b1; + end +end + +assign qcom_tx_dt_do = qcom_dt; +assign qcom_rx_dt_do = rx_data; +assign qcom_status_do = {tx_ready, qctrl_st[1:0], qcom_tx_st[2:0], qcom_rx_st[1:0] }; +assign qcom_debug_do = {pulse_i, tx_ready, reg_wr_size[1:0], reg_sel, qcom_header[2:0], rx_header[2:0], sync_cnt[3:0] }; +assign qcom_do = 0; + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +// OUT SIGNALS +assign qcom_rdy_o = qready; +assign qcom_dt1_o = qreg1_dt; +assign qcom_dt2_o = qreg2_dt; +assign qcom_vld_o = rx_wreg_r; +assign qcom_flag_o = qflag_dt; +assign qcom_do = 0; +assign qproc_start_o = t_start_r; +assign cmd_ack_o = ~qready; + + + + + +endmodule + + diff --git a/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl b/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl new file mode 100644 index 000000000..95980b7ae --- /dev/null +++ b/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl b/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl new file mode 100644 index 000000000..63a791000 --- /dev/null +++ b/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl @@ -0,0 +1,46 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Communication_Options [ipgui::add_group $IPINST -name "Communication Options" -parent ${Page_0}] + ipgui::add_param $IPINST -name "SYNC" -parent ${Communication_Options} -widget checkBox + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.SYNC { PARAM_VALUE.SYNC } { + # Procedure called to update SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC { PARAM_VALUE.SYNC } { + # Procedure called to validate SYNC + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.SYNC { MODELPARAM_VALUE.SYNC PARAM_VALUE.SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC}] ${MODELPARAM_VALUE.SYNC} +} + diff --git a/firmware/ip/qick_interfaces/Debug_Core.xml b/firmware/ip/qick_interfaces/Debug_Core.xml new file mode 100644 index 000000000..467fce461 --- /dev/null +++ b/firmware/ip/qick_interfaces/Debug_Core.xml @@ -0,0 +1,11 @@ + + + QICK + QICK + Debug_Core + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/Debug_Core_rtl.xml b/firmware/ip/qick_interfaces/Debug_Core_rtl.xml new file mode 100644 index 000000000..ce16fb016 --- /dev/null +++ b/firmware/ip/qick_interfaces/Debug_Core_rtl.xml @@ -0,0 +1,114 @@ + + + QICK + QICK + Debug_Core_rtl + 1.0 + + + + Data_32_0 + 32 BIt Data + + + true + + + required + 32 + + + 32 + in + + 0 + + + + Data_32_1 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_2 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_3 + 32 BIt Data + + + true + + + 32 + + + required + 32 + in + + 0 + + + + Data_32_4 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_5 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qick_peripheral.xml b/firmware/ip/qick_interfaces/qick_peripheral.xml new file mode 100644 index 000000000..27668539f --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_peripheral.xml @@ -0,0 +1,11 @@ + + + QICK + QICK + qick_peripheral + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml b/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml new file mode 100644 index 000000000..dba63db28 --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml @@ -0,0 +1,202 @@ + + + QICK + QICK + qick_peripheral_rtl + 1.0 + + + + Enable + Peripheral Enable + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + Operation + Peripheral Operation + + + true + + + required + 5 + + + required + 5 + in + + 0 + + + + a_dt + Peripheral Data A + + + true + + + required + 32 + + + required + 32 + in + + 0 + + + + b_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + c_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + d_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + rdy + Peripheral Ready + + + required + 1 + in + + + required + 1 + + 1 + + + + dt_in_1 + Peripheral Data Out + + + true + + + 32 + in + + + 32 + + 0 + + + + dt_in_2 + Peripheral Data Out + + + true + + + 32 + in + + + 32 + + 0 + + + + flag + Flag + + + true + + + 1 + in + + + 1 + + 0 + + + + dt_valid + Data Valid + + + true + + + 1 + in + + + 1 + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml b/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml new file mode 100644 index 000000000..ad316aa62 --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml @@ -0,0 +1,11 @@ + + + QICK + QICK + qick_qproc_control + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml b/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml new file mode 100644 index 000000000..374c9855f --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml @@ -0,0 +1,36 @@ + + + QICK + QICK + qick_qproc_control_rtl + 1.0 + + + + start + + + 1 + + + 1 + in + + 0 + + + + stop + + + 1 + + + 1 + in + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qproc_time_ctrl.xml b/firmware/ip/qick_interfaces/qproc_time_ctrl.xml new file mode 100644 index 000000000..efc3b8044 --- /dev/null +++ b/firmware/ip/qick_interfaces/qproc_time_ctrl.xml @@ -0,0 +1,11 @@ + + + QICK + QICK + qick_time_control + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml b/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml new file mode 100644 index 000000000..8caac8c4d --- /dev/null +++ b/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml @@ -0,0 +1,65 @@ + + + QICK + QICK + qick_time_control_rtl + 1.0 + + + + time_rst + + + 1 + + + 1 + in + + 0 + + + + time_updt + + + 1 + + + 1 + in + + 0 + + + + time_init + + + 1 + + + 1 + in + + 0 + + + + time_dt + + + true + + + 32 + + + 32 + in + + 0 + + + + diff --git a/firmware/ip/qick_peripheral_template/component.xml b/firmware/ip/qick_peripheral_template/component.xml new file mode 100644 index 000000000..52cf8c6cc --- /dev/null +++ b/firmware/ip/qick_peripheral_template/component.xml @@ -0,0 +1,1226 @@ + + + QICK + QICK + qick_peripheral + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_clk + + + + + + + CLK + + + c_clk + + + + + + ASSOCIATED_RESET + c_aresetn + + + ASSOCIATED_BUSIF + QP + + + + + ps_clk + + + + + + + CLK + + + ps_clk + + + + + + ASSOCIATED_RESET + ps_aresetn + + + ASSOCIATED_BUSIF + s_axi + + + + + QP + + + + + + + b_dt + + + qp_dt2_i + + + + + c_dt + + + qp_dt3_i + + + + + a_dt + + + qp_dt1_i + + + + + flag + + + qp_flag_o + + + + + d_dt + + + qp_dt4_i + + + + + rdy + + + qp_rdy_o + + + + + Enable + + + qp_en_i + + + + + dt_in_2 + + + qp_dt2_o + + + + + Operation + + + qp_op_i + + + + + dt_in_1 + + + qp_dt1_o + + + + + dt_valid + + + qp_vld_o + + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_qick_peripheral + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c1aa1824 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_qick_peripheral + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c1aa1824 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8269e14c + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + c_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + c_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_en_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_op_i + + in + + 4 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt1_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt2_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt3_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt4_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_rdy_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt1_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt2_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_vld_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_flag_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_signal_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qp_vector_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qp_signal_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_vector_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + qp_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DEBUG + Debug + 1 + + + INPUTS + Inputs + 0 + + + + + + choice_list_98b8ce5c + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qp_ips.sv + systemVerilogSource + + + src/qick_periph.sv + systemVerilogSource + + + src/axi_slv_qp.vhd + vhdlSource + + + src/axi_qick_peripheral.sv + systemVerilogSource + CHECKSUM_25be0871 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qp_ips.sv + systemVerilogSource + + + src/qick_periph.sv + systemVerilogSource + + + src/axi_slv_qp.vhd + vhdlSource + + + src/axi_qick_peripheral.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/qick_peripheral_v1_0.tcl + tclSource + CHECKSUM_8269e14c + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + qick_peripheral + + + Component_Name + axis_qick_com_v1_0 + + + DEBUG + Debug + 1 + + + INPUTS + Inputs + 0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /QICK/QICK_Peripheral + + qick_peripheral + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 8 + 2024-01-04T12:49:10Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv b/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv new file mode 100644 index 000000000..25070ebef --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv @@ -0,0 +1,203 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define HP_PS_CLK 50 // Half Clock Period for Simulation +`define HP_C_CLK 5 // Half Clock Period for Simulation +`define HP_T_CLK 2 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_enc(); + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg c_clk, t_clk, ps_clk; +reg rst_n; +reg sync; +// CLK Generation +////////////////////////////////////////////////////////////////////////// +initial begin + ps_clk = 1'b0; + forever # (`HP_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + c_clk = 1'b0; + forever # (`HP_C_CLK) c_clk = ~c_clk; +end +initial begin + t_clk = 1'b0; + forever # (`HP_T_CLK) t_clk = ~t_clk; +end +// Other Periodical Signals +////////////////////////////////////////////////////////////////////////// +initial begin + sync = 1'b0; + forever # (1000) sync = ~sync; +end + + + +reg [SMP_DW:0] data ; +wire [SMP_DW*SMP_CK-1:0] data_v ; + +reg [SMP_DW-1:0] data_0,data_1, data_2, data_3, data_4,data_5, data_6, data_7 ; + +assign data_7 = data[SMP_DW-1:0] ; +assign data_6 = data[SMP_DW-1:0] +1; +assign data_5 = data[SMP_DW-1:0] +2; +assign data_4 = data[SMP_DW-1:0] +3; +assign data_3 = data[SMP_DW-1:0] +4; +assign data_2 = data[SMP_DW-1:0] +8; +assign data_1 = data[SMP_DW-1:0] +10; +assign data_0 = data[SMP_DW-1:0] +13; + +assign data_v = {data_7, data_6, data_5, data_4,data_3, data_2, data_1, data_0}; + +parameter EFF_DW = 14 ; //Effective DAta Width +parameter SMP_DW = 16 ; +parameter SMP_CK = 8 ; +parameter DW = $clog2(SMP_CK) ; + + + +/////////////////////////////////////////////// +// DESIGN +////////////////////////////////////////// +assign clk_i = c_clk; +assign rst_ni = rst_n; + +/// Time Counter +////////////////////////////////////////////////////////////////////////// + // Clk is 300Mhz, Deat ime 100ns > 32 + +reg [28:0] time_cnt; +always_ff @(posedge clk_i) + if(!rst_ni) begin + time_cnt <= 0; + end else begin + if (cmp_event & !inhibit) + inhibit <= 1'b1; + else if (inhibit & !dead_time_hit) + time_cnt <= dead_time_cnt+1'b1; + else if (dead_time_hit) begin + inhibit <= 1'b0; + time_cnt <= 1'b1; + end + end + +assign trig = cmp_event & !inhibit ; + + + +wire [SMP_CK-1:0] cmp_unary_dt; + +threshold_comparator # ( + .EFF_DW ( EFF_DW ) , + .SMP_DW ( SMP_DW ) , + .SMP_CK ( SMP_CK ) + ) DUT_thc ( + .clk_i ( c_clk ) , + .rst_ni ( rst_n ) , + .en_i ( en_i ) , + .concat_dt_i ( data_v ) , + .th_i ( th_i ) , + .cmp_o ( cmp_unary_dt ) , + .vld_o ( cmp_event ) ); + +/// Priority Encoder +////////////////////////////////////////////////////////////////////////// +reg [DW-1:0] cmp_bin_dt ; + +priority_encoder # ( + .DW (DW) +) DUT ( + .clk_i ( c_clk ) , + .rst_ni ( rst_n ) , + .one_hot_dt_i ( cmp_unary_dt ) , + .bin_dt_o ( cmp_bin_dt ) , + .vld_o ( vld_o ) ); + +/// Dead Time +////////////////////////////////////////////////////////////////////////// + // Clk is 300Mhz, Deat ime 100ns > 32 +assign clk_i = c_clk; +assign rst_ni = rst_n; +reg [9:0] dead_time_cnt, dead_time_lenght; +reg inhibit; +assign dead_time_hit = dead_time_cnt == dead_time_lenght; +always_ff @(posedge clk_i) + if(!rst_ni) begin + dead_time_cnt <= 0; + inhibit <= 0; + end else begin + if (cmp_event & !inhibit) + inhibit <= 1'b1; + else if (inhibit & !dead_time_hit) + dead_time_cnt <= dead_time_cnt+1'b1; + else if (dead_time_hit) begin + inhibit <= 1'b0; + dead_time_cnt <= 1'b1; + end + end + +assign trig = cmp_event & !inhibit ; + + + + + + +initial begin + START_SIMULATION(); + SIM_ENC(); + +end +reg [EFF_DW-1:0]th_i; +reg en_i; + +integer i; + +task SIM_ENC(); begin + $display("SIM TX"); + # (5 * `HP_C_CLK); + + @ (posedge c_clk); #0.1; + + for (i=0;i<=2**EFF_DW;i=i+1) begin + @ (posedge tt ); + @ (posedge c_clk); #0.1; + data = i; + end +end +endtask + +assign tt = trig | ps_clk; + +task START_SIMULATION (); begin + $display("START SIMULATION"); +// Reset + rst_n = 1'b0; + en_i = 1'b0; + th_i = 15; + dead_time_lenght = 5; + data = 0; + #100; + @ (posedge ps_clk); #0.1; + rst_n = 1'b1; + + en_i = 1'b1; + + end +endtask + + +endmodule + + + + diff --git a/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv b/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv new file mode 100644 index 000000000..cc6b7da07 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv @@ -0,0 +1,417 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_C_CLK 3 // 1.66 // Half Clock Period for Simulation +`define T_PS_CLK 25 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_qperiph(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +reg sync_i; +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + sync_i = 1'b0; + forever # (1000) sync_i = ~sync_i; +end + + + + +reg c_cmd_i ; +reg [4 :0] c_op_i; + +// Register ADDRESS +parameter QCOM_CTRL = 0 * 4 ; +parameter QCOM_CFG = 1 * 4 ; +parameter RAXI_DT1 = 2 * 4 ; +parameter QCOM_FLAG = 7 * 4 ; +parameter QCOM_DT1 = 8 * 4 ; +parameter QCOM_DT2 = 9 * 4 ; +parameter QCOM_STATUS = 10 * 4 ; + + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk (ps_clk ), + .aresetn (rst_ni ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) +); + +reg [ 3:0] pmod_si ; +wire[ 3:0] pmod_o1, pmod_o2, pmod_i ; +reg [31:0] c_dt1_i, c_dt2_i, c_dt3_i ; + +////////////////////////////////////////////////////////////////////////// +// QCOM1 +axis_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_1 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( c_cmd_i ) , + .qcom_op_i ( c_op_i ) , + .qcom_dt1_i ( c_dt1_i ) , + .qcom_rdy_o ( ready ) , + .qcom_dt1_o ( qcom_dt1_o ) , + .qcom_dt2_o ( qcom_dt2_o ) , + .qcom_vld_o ( qcom_vld_o ) , + .qcom_flag_o ( qcom_flag_o ) , + .qproc_start_o ( qproc_start_o1 ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o1 ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .qcom_do ( qcom_do ) +); +////////////////////////////////////////////////////////////////////////// +// QCOM +axis_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_2 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( 0 ) , + .qcom_op_i ( 0 ) , + .qcom_dt1_i ( 0 ) , + .qcom_rdy_o ( ) , + .qcom_dt1_o ( ) , + .qcom_dt2_o ( ) , + .qcom_vld_o ( ) , + .qcom_flag_o ( ) , + .qproc_start_o ( qproc_start_o2 ) , + .pmod_i ( pmod_o1 ) , + .pmod_o ( pmod_o2 ) , + .s_axi_awaddr ( 0 ) , + .s_axi_awprot ( 0 ) , + .s_axi_awvalid ( 0 ) , + .s_axi_awready ( ) , + .s_axi_wdata ( 0 ) , + .s_axi_wstrb ( 0 ) , + .s_axi_wvalid ( 0 ) , + .s_axi_wready ( ) , + .s_axi_bresp ( ) , + .s_axi_bvalid ( ) , + .s_axi_bready ( ) , + .s_axi_araddr ( 0 ) , + .s_axi_arprot ( 0 ) , + .s_axi_arvalid ( 0 ) , + .s_axi_arready ( ) , + .s_axi_rdata ( ) , + .s_axi_rresp ( ) , + .s_axi_rvalid ( ) , + .s_axi_rready ( ) , + .qcom_do ( ) +); + + + +reg tx_loop; + +initial begin + START_SIMULATION(); + TEST_AXI () ; + // SIM_RX(); + SIM_TX(); + +end + +assign pmod_i = tx_loop ? pmod_o1 : pmod_si; + +task SIM_TX(); begin + $display("SIM TX"); + + tx_loop = 1'b0 ; + c_cmd_i = 1'b0 ; + c_op_i = 4'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + + + wait (ready == 1'b1) + @ (posedge c_clk); #0.1; + c_op_i = 5'b0001_0; //SET FLAG + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0000_0; //CLR FLAG + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0010_0; //SEND 8_BIT + c_dt1_i = 8'b10101010 ; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0100_0; //SEND 16_BIT + c_dt1_i = 16'b0100_0011_0010_0001 ; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0110_0; //SEND 32_BIT + c_dt1_i = 4660; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0110_1; //SEND 32_BIT + c_dt1_i =53758; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0011_0; //SYNC + c_dt1_i =53758; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + end +endtask + +task SIM_RX(); begin + tx_loop = 1'b0 ; + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0001; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1001; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1001; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0001; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0000; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1000; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1110; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0110; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0100; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1100; // Same DATA CLK + + # (33 * `T_C_CLK); + pmod_si = 4'b011; // Same DATA CLK + + # (18 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0111; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1111; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1110; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0110; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0101; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1101; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1100; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0100; // Same DATA CLK + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QCOM_CTRL , 5); // Set Flag + WRITE_AXI( QCOM_CTRL , 1); // Clear Flag + WRITE_AXI( QCOM_CTRL , 5); // Set Flag + WRITE_AXI( QCOM_CTRL , 1); // Clear Flag + + WRITE_AXI( RAXI_DT1 , 1); // DATA + WRITE_AXI( QCOM_CTRL , 9); // Send 8bit (1) + WRITE_AXI( RAXI_DT1 , 2); // DATA + WRITE_AXI( QCOM_CTRL , 11); // Send 8bit (2) + + WRITE_AXI( QCOM_CTRL , 13); // SYNC_START + + WRITE_AXI( RAXI_DT1 , 16); // DATA + WRITE_AXI( QCOM_CTRL , 17); // Send 16bit (1) + WRITE_AXI( RAXI_DT1 , 32); // DATA + WRITE_AXI( QCOM_CTRL , 19); // Send 16bit (2) + + WRITE_AXI( RAXI_DT1 , 256); // DATA + WRITE_AXI( QCOM_CTRL , 25); // Send 32bit (1) + WRITE_AXI( RAXI_DT1 , 512); // DATA + WRITE_AXI( QCOM_CTRL , 27); // Send 32bit (2) + + +end +endtask + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qcom.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + c_cmd_i = 1'b0 ; + c_op_i = 4'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + pmod_si = 0; + tx_loop = 1'b0 ; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + + end +endtask + + +endmodule + + + + diff --git a/firmware/ip/qick_peripheral_template/src/_qp_ips.sv b/firmware/ip/qick_peripheral_template/src/_qp_ips.sv new file mode 100644 index 000000000..377b2d34f --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/_qp_ips.sv @@ -0,0 +1,95 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + File to add all the custom IPs needed for the peripheral +*/ +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +/// Clock Domain Register Change +/////////////////////////////////////////////////////////////////////////////// +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_rcd, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_rcd <= 0; + data_r <= 0; + end else begin + data_rcd <= dt_i; + data_r <= data_rcd; + end +assign dt_o = data_r ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +// DUAL PORT RAM +/////////////////////////////////////////////////////////////////////////////// +module bram_dual_port_dc # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REGISTERED" // Select "NO_REGISTERED" or "REGISTERED" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] RAM [RAM_SIZE]; +reg [MEM_DW-1:0] ram_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] ram_dt_b = {MEM_DW{1'b0}}; + +always @(posedge clk_a_i) + if (en_a_i) begin + ram_dt_a <= RAM[addr_a_i] ; + if (we_a_i) + RAM[addr_a_i] <= dt_a_i; + //else + // ram_dt_a <= RAM[addr_a_i] ; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + RAM[addr_b_i] <= dt_b_i; + else + ram_dt_b <= RAM[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REGISTERED") begin: no_output_register // 1 clock cycle read + assign dt_a_o = ram_dt_a ; + assign dt_b_o = ram_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] ram_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] ram_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) ram_dt_a_r <= ram_dt_a; + always @(posedge clk_b_i) ram_dt_b_r <= ram_dt_b; + assign dt_a_o = ram_dt_a_r ; + assign dt_b_o = ram_dt_b_r ; + end +endgenerate + +endmodule + diff --git a/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv b/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv new file mode 100644 index 000000000..04713b15a --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv @@ -0,0 +1,171 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + Top Level of the Peripheral Template. It includes two modules + 1) The axi_qick_peripheral core processing unit + 2) The Axi Register, used to read and write from Python. +*/ +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_peripheral # ( + parameter DEBUG = 1 , + parameter INPUTS = 1 +) ( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// QPERIPH INTERFACE + input wire qp_en_i , // + input wire [ 4:0] qp_op_i , // + input wire [31:0] qp_dt1_i , // + input wire [31:0] qp_dt2_i , // + input wire [31:0] qp_dt3_i , // + input wire [31:0] qp_dt4_i , // + output reg qp_rdy_o , // + output reg [31:0] qp_dt1_o , // + output reg [31:0] qp_dt2_o , // + output reg qp_vld_o , // + output reg qp_flag_o , // +// INPUTS + input wire qp_signal_i , + input wire [31:0] qp_vector_i , +// OUTPUTS + output reg qp_signal_o , + output reg [31:0] qp_vector_o , +// AXI-Lite DATA Slave I/F. + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// DEBUG + output wire [31:0] qp_do + ); + + +/////////////////////////////////////////////////////////////////////////////// +// AXI Register. +wire [ 7:0] r_qp_ctrl; +wire [ 7:0] r_qp_cfg; +wire [31:0] r_axi_dt1, r_axi_dt2, r_axi_dt3, r_axi_dt4; +wire [31:0] r_qp_dt1, r_qp_dt2, r_qp_dt3, r_qp_dt4; +reg [31:0] r_qp_status, r_qp_debug; + +axi_slv_qp AXI_REG ( + .aclk ( ps_aclk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( s_axi_awaddr[5:0] ) , + .awprot ( s_axi_awprot ) , + .awvalid ( s_axi_awvalid ) , + .awready ( s_axi_awready ) , + .wdata ( s_axi_wdata ) , + .wstrb ( s_axi_wstrb ) , + .wvalid ( s_axi_wvalid ) , + .wready ( s_axi_wready ) , + .bresp ( s_axi_bresp ) , + .bvalid ( s_axi_bvalid ) , + .bready ( s_axi_bready ) , + .araddr ( s_axi_araddr ) , + .arprot ( s_axi_arprot ) , + .arvalid ( s_axi_arvalid ) , + .arready ( s_axi_arready ) , + .rdata ( s_axi_rdata ) , + .rresp ( s_axi_rresp ) , + .rvalid ( s_axi_rvalid ) , + .rready ( s_axi_rready ) , +// Registers + .QP_CTRL ( r_qp_ctrl ) , + .QP_CFG ( r_qp_cfg ) , + .AXI_DT1 ( r_axi_dt1 ) , + .AXI_DT2 ( r_axi_dt2 ) , + .AXI_DT3 ( r_axi_dt3 ) , + .AXI_DT4 ( r_axi_dt4 ) , + .QP_DT1 ( r_qp_dt1 ) , + .QP_DT2 ( r_qp_dt2 ) , + .QP_DT3 ( r_qp_dt3 ) , + .QP_DT4 ( r_qp_dt4 ) , + .QP_STATUS ( r_qp_status ) , + .QP_DEBUG ( r_qp_debug ) ); + +wire [31:0] qp_do_s; +qick_periph # ( + .PARAM ( 1 ) +) QP ( + .clk_i ( c_clk ) , + .rst_ni ( c_aresetn ) , + .qp_en_i ( qp_en_i ) , + .qp_op_i ( qp_op_i ) , + .qp_dt1_i ( qp_dt1_i ) , + .qp_dt2_i ( qp_dt2_i ) , + .qp_dt3_i ( qp_dt3_i ) , + .qp_dt4_i ( qp_dt4_i ) , + .qp_rdy_o ( qp_rdy_o ) , + .qp_dt1_o ( qp_dt1_o ) , + .qp_dt2_o ( qp_dt2_o ) , + .qp_vld_o ( qp_vld_o ) , + .qp_flag_o ( qp_flag_o ) , + .QP_CTRL ( r_qp_ctrl ) , + .QP_CFG ( r_qp_cfg ) , + .AXI_DT1 ( r_axi_dt1 ) , + .AXI_DT2 ( r_axi_dt2 ) , + .AXI_DT3 ( r_axi_dt3 ) , + .AXI_DT4 ( r_axi_dt4 ) , + .QP_DT1 ( r_qp_dt1 ) , + .QP_DT2 ( r_qp_dt2 ) , + .QP_DT3 ( r_qp_dt3 ) , + .QP_DT4 ( r_qp_dt4 ) , + .QP_STATUS ( r_qp_status ) , + .QP_DEBUG ( r_qp_debug ) , + .qp_signal_i ( qp_signal_i ) , + .qp_vector_i ( qp_vector_i ) , + .qp_signal_o ( qp_signal_o ) , + .qp_vector_o ( qp_vector_o ) , + .qp_do ( qp_do_s ) ); + + + + +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qp_debug_s ; +// Assign AXI Debug Signbals +assign qp_debug_s[31:16] = r_axi_dt3[15:0] ; +assign qp_debug_s[15: 0] = r_axi_dt4[15:0] ; + +generate + if (DEBUG == 0 ) begin: DEBUG_NO + assign qp_debug = 0; + assign qp_do = 0; + end else if (DEBUG == 1) begin: DEBUG_REG + assign r_qp_debug = qp_debug_s; + assign qp_do = 0; + end else begin: DEBUG_OUT + assign r_qp_debug = qp_debug_s; + assign qp_do = qp_do_s; + end +endgenerate + +endmodule diff --git a/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd b/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd new file mode 100644 index 000000000..33a783279 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd @@ -0,0 +1,522 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qp is + Generic ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6); + Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + QP_CTRL : out std_logic_vector ( 7 downto 0) ; + QP_CFG : out std_logic_vector ( 7 downto 0) ; + AXI_DT1 : out std_logic_vector (31 downto 0) ; + AXI_DT2 : out std_logic_vector (31 downto 0) ; + AXI_DT3 : out std_logic_vector (31 downto 0) ; + AXI_DT4 : out std_logic_vector (31 downto 0) ; + QP_DT1 : in std_logic_vector (31 downto 0) ; + QP_DT2 : in std_logic_vector (31 downto 0) ; + QP_DT3 : in std_logic_vector (31 downto 0) ; + QP_DT4 : in std_logic_vector (31 downto 0) ; + QP_STATUS : in std_logic_vector (31 downto 0) ; + QP_DEBUG : in std_logic_vector (31 downto 0) ); +end axi_slv_qp; + +architecture rtl of axi_slv_qp is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, QP_DT1, QP_DT2, QP_DT3, QP_DT4, QP_STATUS, QP_DEBUG, axi_araddr) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0111" => + reg_data_out <= QP_DT1; + when b"1000" => + reg_data_out <= QP_DT2; + when b"1001" => + reg_data_out <= QP_DT3; + when b"1010" => + reg_data_out <= QP_DT4; + when b"1011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1101" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1110" => + reg_data_out <= QP_STATUS; + when b"1111" => + reg_data_out <= QP_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. + +QP_CTRL <= slv_reg0( 7 downto 0); +QP_CFG <= slv_reg1( 7 downto 0); +AXI_DT1 <= slv_reg2(31 downto 0); +AXI_DT2 <= slv_reg3(31 downto 0); +AXI_DT3 <= slv_reg4(31 downto 0); +AXI_DT4 <= slv_reg5(31 downto 0); + +end rtl; diff --git a/firmware/ip/qick_peripheral_template/src/qick_periph.sv b/firmware/ip/qick_peripheral_template/src/qick_periph.sv new file mode 100644 index 000000000..db42e0b5e --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/qick_periph.sv @@ -0,0 +1,164 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + Core processing unit: implement here the peripheral. +*/ +////////////////////////////////////////////////////////////////////////////// +module qick_periph # ( + parameter PARAM = 1 +)( +// Core CLK & RST + input wire clk_i , + input wire rst_ni , +// QPERIPH INTERFACE + input wire qp_en_i , // + input wire [ 4:0] qp_op_i , // + input wire [31:0] qp_dt1_i , // + input wire [31:0] qp_dt2_i , // + input wire [31:0] qp_dt3_i , // + input wire [31:0] qp_dt4_i , // + output reg qp_rdy_o , // + output reg [31:0] qp_dt1_o , // + output reg [31:0] qp_dt2_o , // + output reg qp_vld_o , // + output reg qp_flag_o , // +// AXI REG + input wire [ 7:0] QP_CTRL , + input wire [ 7:0] QP_CFG , + input wire [31:0] AXI_DT1 , + input wire [31:0] AXI_DT2 , + input wire [31:0] AXI_DT3 , + input wire [31:0] AXI_DT4 , + output reg [31:0] QP_DT1 , + output reg [31:0] QP_DT2 , + output reg [31:0] QP_DT3 , + output reg [31:0] QP_DT4 , + output reg [31:0] QP_STATUS , + output reg [31:0] QP_DEBUG , +// INPUTS + input wire qp_signal_i , + input wire [31:0] qp_vector_i , +// OUTPUTS + output reg qp_signal_o , + output reg [31:0] qp_vector_o , +// DEBUG + output wire [31:0] qp_do ); + + +/////////////////////////////////////////////////////////////////////////////// +// Python Command SYNCRONIZATION +/////////////////////////////////////////////////////////////////////////////// +// Control Signal SYNC +wire [ 5:0] axi_ctrl ; +sync_reg # ( + .DW ( 6 ) +)cmd_sync ( + .dt_i ( QP_CTRL[5:0] ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( axi_ctrl ) ); + +assign p_cmd_in = axi_ctrl[0] ; + +reg [ 7:0] p_cmd_in_r ; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) p_cmd_in_r <= 1'b0; + else p_cmd_in_r <= p_cmd_in; +end +//Single Pulse Control Signal +assign p_cmd_in_t01 = !p_cmd_in_r & p_cmd_in; + + +/////////////////////////////////////////////////////////////////////////////// +// Input Command and Data +/////////////////////////////////////////////////////////////////////////////// +reg [ 4:0] c_op_r ; +reg [31:0] c_dt1_r, c_dt2_r ; + +// REGISTERES INs +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + c_op_r <= 1'b0; + c_dt1_r <= '{default:'0} ; + c_dt2_r <= '{default:'0} ; + end else if (p_cmd_in_t01) begin + // Command from Python Interface + c_op_r <= axi_ctrl[5:1]; + c_dt1_r <= AXI_DT1; + c_dt2_r <= AXI_DT2; + end else if (qp_en_i) begin + // Command from QPROC Interface + c_op_r <= qp_op_i[4:0]; + c_dt1_r <= qp_dt1_i; + c_dt2_r <= qp_dt1_i; + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// ASYNCHONOUS INPUT SYNCRONIZATION +/////////////////////////////////////////////////////////////////////////////// +wire qp_signal_r; +sync_reg # ( + .DW ( 1 ) +) sg_sync ( + .dt_i ( qp_signal_i ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( qp_signal_r ) ); + +wire [31:0] qp_vector_r; +sync_reg # ( + .DW ( 32 ) +) vec_sync ( + .dt_i ( qp_vector_i ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( qp_vector_r ) ); + +/////////////////////////////////////////////////////////////////////////////// +// PERIPHERAL PROCESSING +/////////////////////////////////////////////////////////////////////////////// +assign xreg_QP_DT1 = AXI_DT1 ; +assign xreg_QP_DT2 = AXI_DT2 ; +assign xreg_QP_DT3 = AXI_DT3 ; +assign xreg_QP_DT4 = AXI_DT4 ; + + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +// AXI REGISTERS +assign QP_DT1 = xreg_QP_DT1 ; +assign QP_DT2 = xreg_QP_DT2 ; +assign QP_DT3 = xreg_QP_DT3 ; +assign QP_DT4 = xreg_QP_DT4 ; +assign QP_STATUS = 0 ; + +// REGISTERES OUTs +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + qp_signal_o <= 1'b0; + qp_vector_o <= '{default:'0} ; + end else begin + qp_signal_o <= qp_signal_r; + qp_vector_o <= qp_vector_r; + end +end + +endmodule diff --git a/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl new file mode 100644 index 000000000..95980b7ae --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl new file mode 100644 index 000000000..95980b7ae --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl new file mode 100644 index 000000000..f2d9383dc --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} + ipgui::add_param $IPINST -name "INPUTS" -parent ${Page_0} -widget checkBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.INPUTS { PARAM_VALUE.INPUTS } { + # Procedure called to update INPUTS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INPUTS { PARAM_VALUE.INPUTS } { + # Procedure called to validate INPUTS + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.INPUTS { MODELPARAM_VALUE.INPUTS PARAM_VALUE.INPUTS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INPUTS}] ${MODELPARAM_VALUE.INPUTS} +} + diff --git a/firmware/ip/qick_processor/component.xml b/firmware/ip/qick_processor/component.xml new file mode 100644 index 000000000..02d856065 --- /dev/null +++ b/firmware/ip/qick_processor/component.xml @@ -0,0 +1,6752 @@ + + + QICK + QICK + qick_processor + 2.0 + + + m0_axis + + + + + + + TVALID + + + m0_axis_tvalid + + + + + TDATA + + + m0_axis_tdata + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + TDATA + + + m1_axis_tdata + + + + + + + false + + + + + + m2_axis + + + + + + + TVALID + + + m2_axis_tvalid + + + + + TDATA + + + m2_axis_tdata + + + + + TREADY + + + m2_axis_tready + + + + + + + false + + + + + + m3_axis + + + + + + + TVALID + + + m3_axis_tvalid + + + + + TDATA + + + m3_axis_tdata + + + + + TREADY + + + m3_axis_tready + + + + + + + false + + + + + + m4_axis + + + + + + + TVALID + + + m4_axis_tvalid + + + + + TDATA + + + m4_axis_tdata + + + + + TREADY + + + m4_axis_tready + + + + + + + false + + + + + + m5_axis + + + + + + + TVALID + + + m5_axis_tvalid + + + + + TDATA + + + m5_axis_tdata + + + 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+ USED_IN_testbench + + + src/tb/wave_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/dmem_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/prog_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/tb_qick_processor_issue35.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + + + + xilinx_xpgui_view_fileset + + xgui/qick_processor_v2_0.tcl + tclSource + CHECKSUM_4ab07b4f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + qick_processor + + + PMEM_AW + Program Mem Address Width + 8 + + + DMEM_AW + Data Mem Address Width + 8 + + + WMEM_AW + WaveParam Mem Address Width + 8 + + + REG_AW + General Purpose Register Address Width + 4 + + + IN_PORT_QTY + Data IN Port Quantity + 1 + + + OUT_DPORT_QTY + DPORT - Data Port Quantity + 1 + + + OUT_WPORT_QTY + WPORT - Wave Port Quantity + 1 + + + Component_Name + axis_tproc_B_v1_0 + + + LFSR + Random Number Generator + 1 + + + DIVIDER + Integer Divider + 0 + + + ARITH + Arithmetic Co-Processor + 0 + + + TIME_READ + Time User Read (Python and qProc) + 1 + + + CUSTOM_PERIPH + Custom Peripheral Interface + 0 + + + DEBUG + Debug + 1 + + + IO_CTRL + IO Control + 0 + + + DUAL_CORE + Number of Cores (Not Available YET) + 0 + + + OUT_DPORT_DW + DPORT - Data Port Width + 4 + + + OUT_TRIG_QTY + TRIG - Trigger Port Quantity + 2 + + + FIFO_DEPTH + FIFO Depth + 9 + + + EXT_FLAG + External Flag + 0 + + + QCOM + QCOM > QICK Communication Interface + 0 + + + CALL_DEPTH + Call Depth + 255 + + + OUT_TIME + Out Time + 0 + + + QNET + QNET > QICK Network Communication + 0 + + + TIME_CTRL + Time Ctrl + 0 + + + CORE_CTRL + Core Ctrl + 0 + + + GEN_SYNC + Gen Sync + 0 + + + + + + /QICK/Timed_Processor + + qick_processor + level_2 + package_project + + XPM_FIFO + + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 27 + 2025-09-11T21:28:22Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/qick_processor/src/_qproc_defines.svh b/firmware/ip/qick_processor/src/_qproc_defines.svh new file mode 100644 index 000000000..ec9d4fc17 --- /dev/null +++ b/firmware/ip/qick_processor/src/_qproc_defines.svh @@ -0,0 +1,106 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// GENERAL +`ifndef DEFINES + `define DEFINES + // Data Comming from the AXI Stream + `define AXIS_IN_DW 32 // 14 - 30 + `define AXI_WDATA_WIDTH 32 + `define AXI_RDATA_WIDTH 32 + `define AXI_WSTRB_WIDTH 4 + + parameter CFG = 3'b000; + parameter BRANCH = 3'b001; + parameter INT_CTRL = 3'b010; + parameter EXT_CTRL = 3'b011; + parameter REG_WR = 3'b100; + parameter MEM_WR = 3'b101; + parameter PORT_WR = 3'b110; + + typedef struct packed { + bit we ; + bit r_wave_we ; + bit [6:0] addr ; + bit [1:0] src ; + bit port_re ; + } CTRL_REG; + + typedef struct packed { + reg cfg_addr_imm ; + reg cfg_dt_imm ; + reg cfg_port_src ; + reg cfg_port_type ; + reg cfg_port_time ; + reg [3:0] cfg_cond ; + reg cfg_alu_src ; + reg [3:0] cfg_alu_op ; + reg [8:0] usr_ctrl ; + reg flag_we ; + reg dmem_we ; + reg wmem_we ; + reg port_we ; + } CTRL_FLOW; + + typedef struct packed { + logic [31:0] p_time ; + logic p_type ; // 00-WAVE 01-DATA 10- + logic [5:0] p_addr ; + logic [167:0] p_data ; + } PORT_DT; + + typedef struct packed { + logic [47:0] qtp_time ; + logic [7 :0] qtp_version ; + logic [7 :0] qtp_cfg ; + logic [7 :0] qtp_ctrl ; + logic [7 :0] qtp_dst ; + logic [15:0] qtp_len ; + } QTP_CTRL; + +// AXI-Lite DATA Slave I/F. +interface TYPE_IF_AXI_REG #( ); + logic [5:0] axi_awaddr ; + logic [2:0] axi_awprot ; + logic axi_awvalid ; + logic axi_awready ; + logic [31:0] axi_wdata ; + logic [3:0] axi_wstrb ; + logic axi_wvalid ; + logic axi_wready ; + logic [1:0] axi_bresp ; + logic axi_bvalid ; + logic axi_bready ; + logic [5:0] axi_araddr ; + logic [2:0] axi_arprot ; + logic axi_arvalid ; + logic axi_arready ; + logic [31:0] axi_rdata ; + logic [1:0] axi_rresp ; + logic axi_rvalid ; + logic axi_rready ; + + modport master ( output axi_awaddr,axi_awprot, axi_awvalid,axi_wdata,axi_wstrb,axi_wvalid,axi_bready,axi_araddr,axi_arprot,axi_arvalid,axi_rready, + input axi_awready,axi_wready,axi_bresp,axi_bvalid,axi_arready,axi_rdata,axi_rresp,axi_rvalid ); + modport slave ( input axi_awaddr,axi_awprot, axi_awvalid,axi_wdata,axi_wstrb,axi_wvalid,axi_bready,axi_araddr,axi_arprot,axi_arvalid,axi_rready, + output axi_awready,axi_wready,axi_bresp,axi_bvalid,axi_arready,axi_rdata,axi_rresp,axi_rvalid ); + +endinterface + +interface TYPE_IF_MEM #( + parameter DW = 32, + parameter AW = 8 +); + logic dmem_en ; + logic dmem_we ; + logic [ AW-1 : 0 ] dmem_addr; + logic [ DW-1 : 0 ] dmem_w_dt; + logic [ DW-1 : 0 ] dmem_r_dt; +// modport slave ( input dmem_en, dmem_we, dmem_addr, dmem_w_dt, output dmem_r_dt); +// modport master ( input dmem_en, dmem_we, dmem_addr, dmem_w_dt, output dmem_r_dt); +endinterface + +`endif + diff --git a/firmware/ip/qick_processor/src/_qproc_ips.sv b/firmware/ip/qick_processor/src/_qproc_ips.sv new file mode 100644 index 000000000..b8681eb0d --- /dev/null +++ b/firmware/ip/qick_processor/src/_qproc_ips.sv @@ -0,0 +1,1296 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 3-2024 +// Version : 3 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : qick_processor tProc_v2 +/* Description: +IPs used in the design of the qick_processor + +* SYNCHRONIZATION REGISTER +* DUAL PORT RAM +* LIFO +* GRAY CODE COUNTER +* FIFO DUAL CLOCK +* TWO inputs ALU +* DSP ARITH BLOCK +* DIVIDER REGISTERED +* INTERLEAVING DUACL CLOCK EN +- DIVISION Pipelined 32 BIT integer +- gray_2_bin +- bin_2_gray + +*/ +////////////////////////////////////////////////////////////////////////////// + +`define USE_XPM_MACROS + +/////////////////////////////////////////////////////////////////////////////// +/// SYNC - Clock Domain Data Syncronization +/////////////////////////////////////////////////////////////////////////////// +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +// FAST REGISTER GRAY TRANSFORM OF INPUT +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_cdc, data_r; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_cdc <= 0; + data_r <= 0; + end else begin + data_cdc <= dt_i; + data_r <= data_cdc; + end +assign dt_o = data_r ; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DUAL PORT RAM +/////////////////////////////////////////////////////////////////////////////// +module bram_dual_port_dc # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REGISTERED" // Select "NO_REGISTERED" or "REGISTERED" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] RAM [RAM_SIZE]; +reg [MEM_DW-1:0] ram_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] ram_dt_b = {MEM_DW{1'b0}}; + +initial begin + for (int i=0; i < RAM_SIZE; i=i+1) begin + RAM[i] = 'd0; + end +end + +always @(posedge clk_a_i) + if (en_a_i) begin + ram_dt_a <= RAM[addr_a_i] ; + if (we_a_i) + RAM[addr_a_i] <= dt_a_i; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + RAM[addr_b_i] <= dt_b_i; + else + ram_dt_b <= RAM[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REGISTERED") begin: no_output_register // 1 clock cycle read + assign dt_a_o = ram_dt_a ; + assign dt_b_o = ram_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] ram_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] ram_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) ram_dt_a_r <= ram_dt_a; + always @(posedge clk_b_i) ram_dt_b_r <= ram_dt_b; + assign dt_a_o = ram_dt_a_r ; + assign dt_b_o = ram_dt_b_r ; + end +endgenerate + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// LIFO +/////////////////////////////////////////////////////////////////////////////// +module LIFO # ( + parameter WIDTH = 16 , + parameter DEPTH = 8 // MAX 8 +) ( + input wire clk_i , + input wire rst_ni , + input wire [WIDTH - 1:0] data_i , + input wire push , + input wire pop , + output wire [WIDTH - 1:0] data_o , + output wire full_o ); + +wire [2:0] ptr_p1, ptr_m1 ; +reg [2:0] ptr ; +reg [WIDTH-1:0] stack [DEPTH] ; + +assign ptr_p1 = ptr + 1'b1; +assign ptr_m1 = ptr - 1'b1; + +// Pointer +always_ff @(posedge clk_i) begin + if (!rst_ni) ptr <= 0; + else if (push & !full_o) ptr <= ptr_p1; + else if (pop & !empty_o) ptr <= ptr_m1; +end + +// Data +always_ff @(posedge clk_i) begin + if (!rst_ni) stack <= '{default:'0} ; + if(push & !full_o) stack[ptr] <= data_i ; +end + +assign empty_o = !(|ptr) ; +assign full_o = !(|(ptr ^ DEPTH)); +assign data_o = stack[ptr_m1]; + +endmodule + +`ifndef USE_XPM_MACROS +/////////////////////////////////////////////////////////////////////////////// +//GRAY CODE COUNTER +/////////////////////////////////////////////////////////////////////////////// +module gcc # ( + parameter DW = 32 +)( + input wire clk_i , + input wire rst_ni , + input wire async_clear_i , + output wire clear_o , + input wire cnt_en_i , + output wire [DW-1:0] count_bin_o , + output wire [DW-1:0] count_gray_o , + output wire [DW-1:0] count_bin_p1_o , + output wire [DW-1:0] count_gray_p1_o); + +reg [DW-1:0] count_bin ; // count turned into binary number +wire [DW-1:0] count_bin_p1; // count_bin+1 + +reg [DW-1:0] count_bin_r, count_gray_r; + +integer ind; +always_comb begin + count_bin[DW-1] = count_gray_r[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin[ind] = count_bin[ind+1]^count_gray_r[ind]; + end +end + +(* ASYNC_REG = "TRUE" *) reg clear_cdc, clear_r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + clear_cdc <= 0; + clear_r <= 0; + end else begin + clear_cdc <= async_clear_i; + clear_r <= clear_cdc; + end + +assign count_bin_p1 = count_bin + 1 ; + +reg [DW-1:0] count_bin_2r, count_gray_2r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else begin + if (clear_r) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else if (cnt_en_i) begin + count_gray_r <= count_bin_p1 ^ {1'b0,count_bin_p1[DW-1:1]}; + count_bin_r <= count_bin_p1; + count_gray_2r <= count_gray_r; + count_bin_2r <= count_bin_r; + + end + end + +assign clear_o = clear_r ; +assign count_bin_o = count_bin_2r ; +assign count_gray_o = count_gray_2r ; +assign count_bin_p1_o = count_bin_r ; +assign count_gray_p1_o = count_gray_r ; + +endmodule +`endif + + +`ifdef USE_XPM_MACROS + +module BRAM_FIFO_DC_2 # ( + parameter FIFO_DW = 16 , + parameter FIFO_AW = 8 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + input wire flush_i , + output logic [FIFO_DW - 1:0] data_o , + output logic async_empty_o , + output logic async_full_o +); + + // XPM_FIFO instantiation template for Asynchronous FIFO configurations + // Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation + // ======================================================================================================================= + + // Parameter usage table, organized as follows: + // +---------------------------------------------------------------------------------------------------------------------+ + // | Parameter name | Data type | Restrictions, if applicable | + // |---------------------------------------------------------------------------------------------------------------------| + // | Description | + // +---------------------------------------------------------------------------------------------------------------------+ + // +---------------------------------------------------------------------------------------------------------------------+ + // | CASCADE_HEIGHT | Integer | Range: 0 - 64. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | 0- No Cascade Height, Allow Vivado Synthesis to choose. | + // | 1 or more - Vivado Synthesis sets the specified value as Cascade Height. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | CDC_SYNC_STAGES | Integer | Range: 2 - 8. Default value = 2. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the number of synchronization stages on the CDC path | + // | | + // | Must be < 5 if FIFO_WRITE_DEPTH = 16 | + // +---------------------------------------------------------------------------------------------------------------------+ + // | DOUT_RESET_VALUE | String | Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Reset value of read data path. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | ECC_MODE | String | Allowed values: no_ecc, en_ecc. Default value = no_ecc. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | "no_ecc" - Disables ECC | + // | "en_ecc" - Enables both ECC Encoder and Decoder | + // | | + // | NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_MEMORY_TYPE | String | Allowed values: auto, block, distributed. Default value = auto. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Designate the fifo memory primitive (resource type) to use. | + // | | + // | "auto"- Allow Vivado Synthesis to choose | + // | "block"- Block RAM FIFO | + // | "distributed"- Distributed RAM FIFO | + // | | + // | NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".| + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_READ_LATENCY | Integer | Range: 0 - 10. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Number of output register stages in the read data path. | + // | | + // | If READ_MODE = "fwft", then the only applicable value is 0. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_WRITE_DEPTH | Integer | Range: 16 - 4194304. Default value = 2048. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the FIFO Write Depth, must be power of two. | + // | | + // | In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH-1 | + // | In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+1 | + // | | + // | NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | FULL_RESET_VALUE | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset | + // +---------------------------------------------------------------------------------------------------------------------+ + // | PROG_EMPTY_THRESH | Integer | Range: 3 - 4194301. Default value = 10. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted. | + // | | + // | Min_Value = 3 + (READ_MODE_VAL*2) | + // | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2) | + // | | + // | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | + // | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | + // | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | PROG_FULL_THRESH | Integer | Range: 5 - 4194301. Default value = 10. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. | + // | | + // | Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))+CDC_SYNC_STAGES | + // | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) | + // | | + // | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | + // | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | + // | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | RD_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1. | + // | | + // | FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH | + // +---------------------------------------------------------------------------------------------------------------------+ + // | READ_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the width of the read data port, dout | + // | | + // | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | + // | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | + // | | + // | NOTE: | + // | | + // | READ_DATA_WIDTH should be equal to WRITE_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // | The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | READ_MODE | String | Allowed values: std, fwft. Default value = std. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | "std"- standard read mode | + // | "fwft"- First-Word-Fall-Through read mode | + // +---------------------------------------------------------------------------------------------------------------------+ + // | RELATED_CLOCKS | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios | + // +---------------------------------------------------------------------------------------------------------------------+ + // | SIM_ASSERT_CHK | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. | + // | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | USE_ADV_FEATURES | String | Default value = 0707. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, | + // | prog_full, overflow features. | + // | | + // | Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0 | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WAKEUP_TIME | Integer | Range: 0 - 2. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | 0 - Disable sleep | + // | 2 - Use Sleep Pin | + // | | + // | NOTE: WAKEUP_TIME should be 0 if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WRITE_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the width of the write data port, din | + // | | + // | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | + // | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | + // | | + // | NOTE: | + // | | + // | WRITE_DATA_WIDTH should be equal to READ_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // | The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WR_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1. | + // +---------------------------------------------------------------------------------------------------------------------+ + + // Port usage table, organized as follows: + // +---------------------------------------------------------------------------------------------------------------------+ + // | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused | + // |---------------------------------------------------------------------------------------------------------------------| + // | Description | + // +---------------------------------------------------------------------------------------------------------------------+ + // +---------------------------------------------------------------------------------------------------------------------+ + // | almost_empty | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to| + // | empty. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | almost_full | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | data_valid | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout). | + // +---------------------------------------------------------------------------------------------------------------------+ + // | dbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | din | Input | WRITE_DATA_WIDTH | wr_clk | NA | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Data: The input data bus used when writing the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | dout | Output | READ_DATA_WIDTH | rd_clk | NA | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data: The output data bus is driven when reading the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | empty | Output | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Empty Flag: When asserted, this signal indicates that the FIFO is empty. | + // | Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | full | Output | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Full Flag: When asserted, this signal indicates that the FIFO is full. | + // | Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive | + // | to the contents of the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | injectdbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or | + // | UltraRAM macros. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | injectsbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or | + // | UltraRAM macros. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | overflow | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, | + // | because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | prog_empty | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal | + // | to the programmable empty threshold value. | + // | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | prog_full | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal | + // | to the programmable full threshold value. | + // | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_clk | Input | 1 | NA | Rising edge | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read clock: Used for read operation. rd_clk must be a free running clock. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_data_count | Output | RD_DATA_COUNT_WIDTH | rd_clk | NA | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data Count: This bus indicates the number of words read from the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_en | Input | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO. | + // | | + // | Must be held active-low when rd_rst_busy is active high. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_rst_busy | Output | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rst | Input | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | sbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | sleep | Input | 1 | NA | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | underflow | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected | + // | because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_ack | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_clk | Input | 1 | NA | Rising edge | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write clock: Used for write operation. wr_clk must be a free running clock. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Data Count: This bus indicates the number of words written into the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_en | Input | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO. | + // | | + // | Must be held active-low when rst or wr_rst_busy is active high. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_rst_busy | Output | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. | + // +---------------------------------------------------------------------------------------------------------------------+ + + logic rd_rst_busy, wr_rst_busy; + logic wr_full, rd_empty; + logic [FIFO_DW - 1:0] dout; + + // Hold full high during Flush or Reset + assign async_full_o = wr_full | flush_i | wr_rst_busy; + + assign async_empty_o = rd_empty; + + // Clear data output when empty + assign data_o = rd_empty ? 'd0 : dout; + + + // xpm_fifo_async: Asynchronous FIFO + // Xilinx Parameterized Macro, version 2023.1 + xpm_fifo_async #( + .CASCADE_HEIGHT (0), // DECIMAL + .CDC_SYNC_STAGES (2), // DECIMAL + .DOUT_RESET_VALUE ("0"), // String + .ECC_MODE ("no_ecc"), // String + .FIFO_MEMORY_TYPE ("auto"), // String + .FIFO_READ_LATENCY (1), // DECIMAL + .FIFO_WRITE_DEPTH (2**FIFO_AW), // DECIMAL + .FULL_RESET_VALUE (1), // DECIMAL + .PROG_EMPTY_THRESH (10), // DECIMAL + .PROG_FULL_THRESH (10), // DECIMAL + .RD_DATA_COUNT_WIDTH (1), // DECIMAL + .READ_DATA_WIDTH (FIFO_DW), // DECIMAL + // .READ_MODE ("std"), // String + .READ_MODE ("fwft"), // String + .RELATED_CLOCKS (0), // DECIMAL + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .USE_ADV_FEATURES ("0000"), // String + .WAKEUP_TIME (0), // DECIMAL + .WRITE_DATA_WIDTH (FIFO_DW), // DECIMAL + .WR_DATA_COUNT_WIDTH (1) // DECIMAL + ) + xpm_fifo_async_inst ( + .almost_empty (), // 1-bit output: Almost Empty : When asserted, this signal indicates that + // only one more read can be performed before the FIFO goes to empty. + + .almost_full (), // 1-bit output: Almost Full: When asserted, this signal indicates that + // only one more write can be performed before the FIFO is full. + + .data_valid (), // 1-bit output: Read Data Valid: When asserted, this signal indicates + // that valid data is available on the output bus (dout). + + .dbiterr (), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected + // a double-bit error and data in the FIFO core is corrupted. + + .dout (dout), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven + // when reading the FIFO. + + .empty (rd_empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the + // FIFO is empty. Read requests are ignored when the FIFO is empty, + // initiating a read while empty is not destructive to the FIFO. + + .full (wr_full), // 1-bit output: Full Flag: When asserted, this signal indicates that the + // FIFO is full. Write requests are ignored when the FIFO is full, + // initiating a write when the FIFO is full is not destructive to the + // contents of the FIFO. + + .overflow (), // 1-bit output: Overflow: This signal indicates that a write request + // (wren) during the prior clock cycle was rejected, because the FIFO is + // full. Overflowing the FIFO is not destructive to the contents of the + // FIFO. + + .prog_empty (), // 1-bit output: Programmable Empty: This signal is asserted when the + // number of words in the FIFO is less than or equal to the programmable + // empty threshold value. It is de-asserted when the number of words in + // the FIFO exceeds the programmable empty threshold value. + + .prog_full (), // 1-bit output: Programmable Full: This signal is asserted when the + // number of words in the FIFO is greater than or equal to the + // programmable full threshold value. It is de-asserted when the number of + // words in the FIFO is less than the programmable full threshold value. + + .rd_data_count (), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the + // number of words read from the FIFO. + + .rd_rst_busy (rd_rst_busy), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read + // domain is currently in a reset state. + + .sbiterr (), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected + // and fixed a single-bit error. + + .underflow (), // 1-bit output: Underflow: Indicates that the read request (rd_en) during + // the previous clock cycle was rejected because the FIFO is empty. Under + // flowing the FIFO is not destructive to the FIFO. + + .wr_ack (), // 1-bit output: Write Acknowledge: This signal indicates that a write + // request (wr_en) during the prior clock cycle is succeeded. + + .wr_data_count (), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates + // the number of words written into the FIFO. + + .wr_rst_busy (wr_rst_busy), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO + // write domain is currently in a reset state. + + .din (data_i), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when + // writing the FIFO. + + .injectdbiterr (1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .injectsbiterr (1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .rd_clk (rd_clk_i), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free + // running clock. + + .rd_en (~rd_rst_busy & rd_en_i & pop_i), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this + // signal causes data (on dout) to be read from the FIFO. Must be held + // active-low when rd_rst_busy is active high. + + .rst (~wr_rst_ni | flush_i), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be + // unstable at the time of applying reset, but reset must be released only + // after the clock(s) is/are stable. + + .sleep (1'b0), // 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo + // block is in power saving mode. + + .wr_clk (wr_clk_i), // 1-bit input: Write clock: Used for write operation. wr_clk must be a + // free running clock. + + .wr_en (~wr_rst_busy & wr_rst_ni & wr_en_i & push_i) // 1-bit input: Write Enable: If the FIFO is not full, asserting this + // signal causes data (on din) to be written to the FIFO. Must be held + // active-low when rst or wr_rst_busy is active high. + ); + + // End of xpm_fifo_async_inst instantiation + +endmodule + +`else + +/////////////////////////////////////////////////////////////////////////////// +// FIFO DUAL CLOCK +/////////////////////////////////////////////////////////////////////////////// +module BRAM_FIFO_DC_2 # ( + parameter FIFO_DW = 16 , + parameter FIFO_AW = 8 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + output wire [FIFO_DW - 1:0] data_o , + input wire flush_i , + output wire async_empty_o , + output wire async_full_o ); + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value +wire [FIFO_AW-1:0] rd_gptr_p1 ; +wire [FIFO_AW-1:0] wr_gptr_p1 ; +wire [FIFO_AW-1:0] rd_gptr, wr_gptr ; +wire clr_wr, clr_rd; +reg async_empty_r; +wire busy; +wire [FIFO_DW - 1:0] mem_dt; +wire async_empty, async_full; + +// Sample Pointers +(* ASYNC_REG = "TRUE" *) reg [FIFO_AW-1:0] wr_gptr_cdc, wr_gptr_r; +always_ff @(posedge rd_clk_i) begin + wr_gptr_cdc <= wr_gptr; + wr_gptr_r <= wr_gptr_cdc; + async_empty_r <= async_empty; +end + +(* ASYNC_REG = "TRUE" *) reg [FIFO_AW-1:0] rd_gptr_cdc, rd_gptr_r; +always_ff @(posedge wr_clk_i) begin + rd_gptr_cdc <= rd_gptr; + rd_gptr_r <= rd_gptr_cdc; +end + +reg clr_fifo_req, clr_fifo_ack; +always_ff @(posedge wr_clk_i, negedge wr_rst_ni) begin + if (!wr_rst_ni) begin + clr_fifo_req <= 0 ; + clr_fifo_ack <= 0 ; + end else begin + if (flush_i) + clr_fifo_req <= 1 ; + else if (clr_fifo_ack ) + clr_fifo_req <= 0 ; + + if (clr_rd & clr_wr) + clr_fifo_ack <= 1 ; + else if (clr_fifo_ack & !clr_rd & !clr_wr) + clr_fifo_ack <= 0 ; + end +end + +assign busy = clr_fifo_ack | clr_fifo_req ; + +//SYNC with POP (RD_CLK) +assign async_empty = (rd_gptr == wr_gptr_r) ; + +//SYNC with PUSH (WR_CLK) +assign async_full = (rd_gptr_r == wr_gptr_p1) ; + +wire do_pop, do_push; +assign do_pop = pop_i & !async_empty; +assign do_push = wr_en_i & push_i & !async_full; + +//assign async_empty_o = async_empty | busy; // While RESETTING, Shows EMPTY +assign async_empty_o = async_empty_r | busy; // While RESETTING, Shows EMPTY + +assign async_full_o = async_full | busy; +assign data_o = mem_dt; + +gcc #( + .DW ( FIFO_AW ) +) gcc_wr_ptr ( + .clk_i ( wr_clk_i ) , + .rst_ni ( wr_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_wr ) , + .cnt_en_i ( do_push ) , + .count_bin_o ( ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( FIFO_AW ) +) gcc_rd_ptr ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rd_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_rd ) , + .cnt_en_i ( do_pop ) , + .count_bin_o ( ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +// Data +bram_dual_port_dc # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( FIFO_DW ) , + //.RAM_OUT ( "NO_REGISTERED" ) // Select "NO_REGISTERED" or "REGISTERED" + .RAM_OUT ( "REGISTERED" ) // Select "NO_REGISTERED" or "REGISTERED" +) fifo_mem ( + .clk_a_i ( wr_clk_i ) , + .en_a_i ( wr_en_i ) , + .we_a_i ( do_push ) , + .addr_a_i ( wr_gptr ) , + .dt_a_i ( data_i ) , + .dt_a_o ( ) , + .clk_b_i ( rd_clk_i ) , + .en_b_i ( rd_en_i ) , + .we_b_i ( 1'b0 ) , + .addr_b_i ( rd_gptr ) , + .dt_b_i ( ) , + .dt_b_o ( mem_dt ) ); + +endmodule + +`endif + + +/////////////////////////////////////////////////////////////////////////////// +// TWO inputs ALU +////////////////////////////////////////////////////////////////////////////// +module AB_alu ( +// input wire clk_i , + input wire signed [31:0] A_i , + input wire signed [31:0] B_i , + input wire [3:0] alu_op_i , + output wire Z_o , + output wire C_o , + output wire S_o , + output wire signed [31:0] alu_result_o ); + +reg [32:0] result; +wire zero_flag, carry_flag, sign_flag; + +wire[3:0] shift ; +assign shift = B_i[3:0]; + +wire [31:0] neg_B, a_plus_b, a_minus_b, abs_b; +wire [31:0] msh_a, lsh_a, swap_a; +wire [31:0] a_cat_b, a_sl_b, a_lsr_b, a_asr_b ; + +assign neg_B = -B_i ; +assign a_plus_b = A_i + B_i; +assign a_minus_b = A_i + neg_B; +assign abs_b = B_i[31] ? neg_B : B_i; +assign msh_a = {16'b00000000_00000000, A_i[31:16]} ; +assign lsh_a = {16'b00000000_00000000, A_i[15: 0]} ; +assign swap_a = {A_i[15:0], A_i[31:16]} ; +assign a_cat_b = {A_i[15:0], B_i[15:0]}; +assign a_sl_b = A_i << shift ; +assign a_lsr_b = A_i >> shift ; +assign a_asr_b = A_i >>> shift ; + +always_comb begin + if (~alu_op_i[0]) + // ARITHMETIC + case ( alu_op_i[3:1] ) + 3'b000: result = a_plus_b ; + 3'b001: result = a_minus_b ; + 3'b010: result = A_i & B_i ; + 3'b011: result = a_asr_b ; + 3'b100: result = abs_b ; + 3'b101: result = msh_a ; + 3'b110: result = lsh_a ; + 3'b111: result = swap_a ; + endcase + else + // LOGIC + case ( alu_op_i[3:1] ) + 3'b000: result = ~A_i ; + 3'b001: result = A_i | B_i ; + 3'b010: result = A_i ^ B_i ; + 3'b011: result = a_cat_b ; + 3'b100: result = 0 ; + 3'b101: result = {31'b0, ^A_i} ; + 3'b110: result = a_sl_b ; + 3'b111: result = a_lsr_b ; + endcase +end + +assign zero_flag = (result == 0) ; +assign carry_flag = result[32]; +assign sign_flag = result[31]; + +assign alu_result_o = result[31:0] ; +assign Z_o = zero_flag ; +assign C_o = carry_flag ; +assign S_o = sign_flag ; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DSP ARITH BLOCK +/////////////////////////////////////////////////////////////////////////////// +module arith ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire signed [31:0] A_i , + input wire signed [31:0] B_i , + input wire signed [31:0] C_i , + input wire signed [31:0] D_i , + input wire [4:0] alu_op_i , + output wire ready_o , + output wire signed [63:0] arith_result_o ); + +// DSP OUTPUTS +wire [45:0] arith_result ; +// DSP INPUTS +reg [3:0] ALU_OP ; + +reg signed [26:0] A_dt ; +reg signed [17:0] B_dt ; +reg signed [31:0] C_dt ; +reg signed [26:0] D_dt ; +reg working, working_r, working_r2, working_r3 ; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + A_dt <= 0; + B_dt <= 0; + C_dt <= 0; + D_dt <= 0; + ALU_OP <= 0; + working <= 1'b0 ; + working_r <= 1'b0 ; + working_r2 <= 1'b0 ; + working_r3 <= 1'b0 ; + end else begin + working_r <= working ; + working_r2 <= working_r ; + working_r3 <= working_r2 ; + if (start_i) begin + A_dt <= A_i[26:0] ; + B_dt <= B_i[17:0] ; + C_dt <= C_i[31:0] ; + D_dt <= D_i[26:0] ; + ALU_OP <= { alu_op_i[3:0]} ; + working <= 1'b1 ; + end else if (working_r3) begin + working <= 1'b0; + working_r <= 1'b0; + working_r2 <= 1'b0; + working_r3 <= 1'b0; + + end + end +end + + +dsp_macro_0 ARITH_DSP ( + .CLK ( clk_i ), // input wire CLK + .SEL ( ALU_OP ), // input wire [3 : 0] SEL + .A ( A_dt[26:0] ), // input wire [26 : 0] A + .B ( B_dt[17:0] ), // input wire [17 : 0] B + .C ( C_dt[31:0] ), // input wire [31 : 0] C + .D ( D_dt[26:0] ), // input wire [26 : 0] D + .P ( arith_result ) // output wire [45 : 0] P +); + +//signed extension of +assign arith_result_o = { {18{arith_result[45]}}, arith_result }; +// assign ready_o = ~ ( working | working_r ); +assign ready_o = ~ ( working ); + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DIVIDER REGISTERED +/////////////////////////////////////////////////////////////////////////////// +module div_r #( + parameter DW = 32 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [DW-1:0] A_i , + input wire [DW-1:0] B_i , + output wire ready_o , + output reg [DW-1:0] div_quotient_o , + output reg [DW-1:0] div_remainder_o ); + +// Registers +reg [DW-1:0] inB ; +reg [DW-1:0] r_temp, q_temp; +reg [4:0] ind_bit; + +reg working; + +reg qtb; +reg [2*DW-1 :0] sub_temp ; +reg [DW-1 :0] r_temp_nxt ; + +wire [31:0] ind_bit_m1; + + +assign ind_bit_m1 = ind_bit - 1'b1; +assign div_start = start_i; +assign div_end = (ind_bit==0) ; + +// State Machine +/////////////////////////////////////////////////////////////////////////// +enum {IDLE, WORKING} div_st, div_st_nxt; + +always_ff @(posedge clk_i) + if (!rst_ni) div_st <= IDLE; + else div_st <= div_st_nxt; + + +always_comb begin + div_st_nxt = div_st; + working = 1'b0; + case (div_st) + IDLE: begin + if ( div_start ) div_st_nxt = WORKING; + end + WORKING: begin + working = 1'b1; + if ( div_end ) div_st_nxt = IDLE; + end + default:; + endcase +end + +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= 0 ; + end else if (div_start) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= A_i ; + inB <= B_i ; + end else if (div_end) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= A_i ; + inB <= B_i ; + end else if (working) begin + ind_bit <= ind_bit_m1; + r_temp <= r_temp_nxt ; + q_temp[ind_bit_m1] <= qtb ; + end +end // Always + +/////////////////////////////////////////////////////////////////////////// +// COMBINATORIAL PART +always_comb begin + qtb = 1'b0; + r_temp_nxt = r_temp ; + sub_temp = inB << ind_bit_m1 ; + if (r_temp_nxt >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt = r_temp_nxt - sub_temp ; + end +end + +/////////////////////////////////////////////////////////////////////////// +// OUT REG +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + div_quotient_o <= 0; + div_remainder_o <= 0 ; + end else if (div_end) begin + div_quotient_o <= q_temp; + div_remainder_o <= r_temp_nxt ; + end +end // Always + +assign ready_o = ~working; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// LFSR +/////////////////////////////////////////////////////////////////////////////// +module LFSR ( + input wire clk_i , + input wire rst_ni , + input wire en_i , + input wire load_we_i , + input wire [31:0] load_dt_i , + output wire [31:0] lfsr_dt_o ); + +// LFSR +/////////////////////////////////////////////////////////////////////////////// + +reg [31:0] reg_lfsr ; + +always_ff @(posedge clk_i, negedge rst_ni) + if (!rst_ni) + reg_lfsr <= 0;//32'h00000000; + else begin + if (load_we_i) + reg_lfsr <= load_dt_i ; + else if (en_i) begin + //reg_lfsr[0] <= ~^{reg_lfsr[31], reg_lfsr[21], reg_lfsr[1:0]}; + reg_lfsr[31:1] <= reg_lfsr[30:0]; + reg_lfsr[0] <= ~^{reg_lfsr[31], reg_lfsr[21], reg_lfsr[1:0]}; + end + end +assign lfsr_dt_o = reg_lfsr ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +// INTERLEAVING DUACL CLOCK EN +/////////////////////////////////////////////////////////////////////////////// +/* +sync_ab_en sync_pulse_inst ( + .clk_a_i ( ) , + .rst_a_ni ( ) , + .clk_b_i ( ) , + .rst_b_ni ( ) , + .a_en_o ( ) , + .b_en_o ( ) ); + */ +module sync_ab_en ( + input wire clk_a_i , + input wire rst_a_ni , + input wire clk_b_i , + input wire rst_b_ni , + output wire a_en_o , + output wire b_en_o +); + +reg a_pulse_req; +(* ASYNC_REG = "TRUE" *) reg a_pulse_req_cdc; +(* ASYNC_REG = "TRUE" *) reg a_pulse_ack ; +(* ASYNC_REG = "TRUE" *) reg b_pulse_ack_cdc; +(* ASYNC_REG = "TRUE" *) reg b_pulse_req ; +reg pulse_b_req_r; +reg b_pulse_ack; + +/// REQ Time from C to T +/////////////////////////////////////////////////////////////////////////////// +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + a_pulse_req <= 1'b0; + end else + if ( a_pulse_ack ) a_pulse_req <= 1'b0; + else if ( !a_pulse_ack ) a_pulse_req <= 1'b1; +end + +/// Generate B PULSE +/////////////////////////////////////////////////////////////////////////////// +always_ff @(posedge clk_b_i) + if(!rst_b_ni) begin + a_pulse_req_cdc <= 0; + b_pulse_req <= 0; + pulse_b_req_r <= 0; + end else begin + a_pulse_req_cdc <= a_pulse_req; + b_pulse_req <= a_pulse_req_cdc; + pulse_b_req_r <= b_pulse_req; + end + +assign pulse_b = b_pulse_req ^ pulse_b_req_r; + +/// ACK +/////////////////////////////////////////////////////////////////////////////// +always_ff @ (posedge clk_b_i, negedge rst_b_ni) begin + if ( !rst_b_ni ) begin + b_pulse_ack <= 1'b0; + end else + if ( b_pulse_req ) b_pulse_ack <= 1'b1; + else if ( !b_pulse_req ) b_pulse_ack <= 1'b0; +end + +always_ff @(posedge clk_a_i) + if(!rst_a_ni) begin + b_pulse_ack_cdc <= 0; + a_pulse_ack <= 0; + end else begin + b_pulse_ack_cdc <= b_pulse_ack; + a_pulse_ack <= b_pulse_ack_cdc; + end + +assign pulse_a = a_pulse_req ~^ a_pulse_ack ; + +assign a_en_o = pulse_a; +assign b_en_o = pulse_b; + +endmodule + +/* +//////////////////////////////////////////////////////////////////////////////// +// DIVISION Pipelined 32 BIT integer +/////////////////////////////////////////////////////////////////////////////// +module div_p #( + parameter DW = 32 , + parameter N_PIPE = 32 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [DW-1:0] A_i , + input wire [DW-1:0] B_i , + output wire ready_o , + output wire [DW-1:0] div_quotient_o , + output wire [DW-1:0] div_remainder_o ); + +localparam comb_per_reg = DW / N_PIPE; + +reg [DW-1 : 0 ] inB ; +reg [DW-1 : 0 ] q_temp ; +reg [DW-1 : 0 ] r_temp [N_PIPE] ; +reg [DW-1 : 0 ] r_temp_nxt [N_PIPE] ; +reg [2*DW-1 : 0 ] sub_temp [N_PIPE] ; + +integer ind_comb_stage [N_PIPE]; +integer ind_bit[N_PIPE]; + +wire working; +reg [N_PIPE-1:0] en_r ; + +assign working = |en_r; + + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + en_r <= 0 ; + r_temp[0] <= 0 ; + inB <= 0 ; + end else + if (start_i) begin + en_r <= {en_r[N_PIPE-2:0], 1'b1} ; + r_temp [0] <= A_i ; + inB <= B_i ; + end else if (working) + en_r <= {en_r[N_PIPE-2:0], 1'b0} ; +end // Always + + +/////////////////////////////////////////////////////////////////////////// +// FIRST STAGE +always @ (r_temp[0], r_temp_nxt[0], inB) begin + r_temp_nxt[0] = r_temp[0]; + for (ind_comb_stage[0]=0; ind_comb_stage[0] < comb_per_reg ; ind_comb_stage[0]=ind_comb_stage[0]+1) begin + ind_bit[0] = (DW-1) - ( ind_comb_stage[0] ) ; + sub_temp[0] = inB << ind_bit[0] ; + if (r_temp_nxt[0] >= sub_temp[0]) begin + q_temp [ind_bit[0]] = 1'b1 ; + r_temp_nxt[0] = r_temp_nxt[0] - sub_temp[0]; + end else + q_temp [ind_bit[0]] = 1'b0; + end +end + +genvar ind_reg_stage; +for (ind_reg_stage=1; ind_reg_stage < N_PIPE ; ind_reg_stage=ind_reg_stage+1) begin + // SEQUENCIAL PART + always_ff @ (posedge clk_i) begin + r_temp [ind_reg_stage] = r_temp_nxt [ind_reg_stage-1] ; + end + // COMBINATORIAL PART + always_comb begin + r_temp_nxt[ind_reg_stage] = r_temp[ind_reg_stage]; + for (ind_comb_stage[ind_reg_stage]=0; ind_comb_stage[ind_reg_stage] < comb_per_reg ; ind_comb_stage[ind_reg_stage]=ind_comb_stage[ind_reg_stage]+1) begin + ind_bit[ind_reg_stage] = (DW-1) - (ind_comb_stage[ind_reg_stage] + (ind_reg_stage * comb_per_reg)) ; + sub_temp[ind_reg_stage] = inB << ind_bit[ind_reg_stage] ; + if (r_temp_nxt[ind_reg_stage] >= sub_temp[ind_reg_stage]) begin + q_temp [ind_bit[ind_reg_stage]] = 1'b1 ; + r_temp_nxt[ind_reg_stage] = r_temp_nxt[ind_reg_stage] - sub_temp[ind_reg_stage]; + end else + q_temp [ind_bit[ind_reg_stage]] = 1'b0; + end + end +end + +assign ready_o = ~working; +assign div_quotient_o = q_temp; +assign div_remainder_o = r_temp_nxt[N_PIPE-1]; + +endmodule +module bin_2_gray # ( + parameter DW = 32 +)( + input wire [DW-1:0] count_bin_i , + output wire [DW-1:0] count_gray_o ); +assign count_gray_o = count_bin_i ^ {1'b0,count_bin_i[DW-1:1]}; +endmodule + +module gray_2_bin # ( + parameter DW = 32 +)( + input wire [DW-1:0] count_gray_i , + output reg [DW-1:0] count_bin_o ); +integer ind; +always_comb begin + count_bin_o[DW-1] = count_gray_i[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin_o[ind] = count_bin_o[ind+1]^count_gray_i[ind]; + end +end + +endmodule +*/ + + diff --git a/firmware/ip/qick_processor/src/axi_slv_qproc.vhd b/firmware/ip/qick_processor/src/axi_slv_qproc.vhd new file mode 100644 index 000000000..c2df5959b --- /dev/null +++ b/firmware/ip/qick_processor/src/axi_slv_qproc.vhd @@ -0,0 +1,536 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qproc is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + TPROC_CTRL : out std_logic_vector (15 downto 0) ; -- Register AUTORESET + TPROC_CFG : out std_logic_vector (15 downto 0) ; + MEM_ADDR : out std_logic_vector (15 downto 0) ; + MEM_LEN : out std_logic_vector (15 downto 0) ; + MEM_DT_I : out std_logic_vector (31 downto 0) ; + TPROC_W_DT1 : out std_logic_vector (31 downto 0) ; + TPROC_W_DT2 : out std_logic_vector (31 downto 0) ; + CORE_CFG : out std_logic_vector (7 downto 0) ; + READ_SEL : out std_logic_vector (7 downto 0) ; + MEM_DT_O : in std_logic_vector (31 downto 0) ; + TPROC_R_DT1 : in std_logic_vector (31 downto 0) ; + TPROC_R_DT2 : in std_logic_vector (31 downto 0) ; + TIME_USR : in std_logic_vector (31 downto 0) ; + TPROC_STATUS : in std_logic_vector (31 downto 0) ; + TPROC_DEBUG : in std_logic_vector (31 downto 0) ); + end axi_slv_qproc; + +architecture rtl of axi_slv_qproc is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, MEM_DT_O, TPROC_R_DT1, TPROC_R_DT2, TIME_USR, TPROC_STATUS, TPROC_DEBUG, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= "00000000000000000000000000001001"; + when b"1010" => + reg_data_out <= MEM_DT_O; + when b"1011" => + reg_data_out <= TPROC_R_DT1; + when b"1100" => + reg_data_out <= TPROC_R_DT2; + when b"1101" => + reg_data_out <= TIME_USR; + when b"1110" => + reg_data_out <= TPROC_STATUS; + when b"1111" => + reg_data_out <= TPROC_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. +TPROC_CTRL <= slv_reg0(15 downto 0); +TPROC_CFG <= slv_reg1(15 downto 0); +MEM_ADDR <= slv_reg2(15 downto 0); +MEM_LEN <= slv_reg3(15 downto 0); +MEM_DT_I <= slv_reg4(31 downto 0); +TPROC_W_DT1 <= slv_reg5(31 downto 0); +TPROC_W_DT2 <= slv_reg6(31 downto 0); +CORE_CFG <= slv_reg7(7 downto 0); +READ_SEL <= slv_reg8(7 downto 0); + + +end rtl; diff --git a/firmware/ip/qick_processor/src/axis_qick_processor.sv b/firmware/ip/qick_processor/src/axis_qick_processor.sv new file mode 100644 index 000000000..9265700e4 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_qick_processor.sv @@ -0,0 +1,663 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-10-2 +// Version : 4 +// Revision : 22 (Use Assembler Version 3 Rev-23) +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +qick_processor top level file +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module axis_qick_processor # ( + parameter DUAL_CORE = 0 , // 0-Single Core 1-Dual core + parameter GEN_SYNC = 0 , // Generate Sync Signal + parameter IO_CTRL = 0 , // 0-No IO control 1-Add proc_strat and Proc Stop IN + parameter TIME_CTRL = 0 , // 0-No NET control 1-Add proc_strat and Proc Stop IN + parameter CORE_CTRL = 0 , // 0-No NET control 1-Add proc_strat and Proc Stop IN + parameter OUT_TIME = 0 , // + parameter DEBUG = 1 , // 0-No Debug 1-AXI control 2-Only Registers 3-Registers and OUT Signals + parameter QNET = 0 , // QNET Interfrace 0-No 1-Yes + parameter QCOM = 0 , // QCOM Interfrace 0-No 1-Yes + parameter CUSTOM_PERIPH = 0 , // PERIPH Interfrace 0-No 1-ONE 2-Two + parameter LFSR = 1 , // LFSR 0-No 1-Yes + parameter DIVIDER = 0 , // DIVIDER 0-No 1-Yes + parameter ARITH = 0 , // Arith 0-No 1-Yes + parameter EXT_FLAG = 0 , // External Flag Input 0-No 1-Yes + parameter TIME_READ = 1 , // Time in sreg and AXI-Reg 0-No 1-Yes + parameter FIFO_DEPTH = 9 , // 9 Bits in Dispatcher FIFOs address + parameter PMEM_AW = 8 , // Bits in Program Memory address + parameter DMEM_AW = 8 , // Bits in Data Memory address + parameter WMEM_AW = 8 , // Bits in WaveParam Memory address + parameter REG_AW = 4 , // Bits to address DREG + parameter IN_PORT_QTY = 1 , // Number of Input Ports + parameter OUT_TRIG_QTY = 2 , // Number of Output Trigger Ports + parameter OUT_DPORT_QTY = 1 , // Number of Output Data Ports + parameter OUT_DPORT_DW = 4 , // BitSize of Output Data Ports + parameter OUT_WPORT_QTY = 1 , // Number of Output Wave Ports + parameter CALL_DEPTH = 255 // Nested Functions + +)( +// Core, Time and AXI CLK & RST. + input wire t_clk_i , + input wire t_resetn , + input wire c_clk_i , + input wire c_resetn , + input wire ps_clk_i , + input wire ps_resetn , +// External Control + input wire ext_flag_i , + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_init_i , + input wire time_updt_i , + input wire [31:0] time_dt_i , + output wire [47:0] t_time_abs_o , + output wire pulse_sync_o , +//QNET + output wire qnet_en_o , + output wire [4 :0] qnet_op_o , + output wire [31:0] qnet_a_dt_o , + output wire [31:0] qnet_b_dt_o , + output wire [31:0] qnet_c_dt_o , + input wire qnet_rdy_i , + input wire [31 :0] qnet_dt1_i , + input wire [31 :0] qnet_dt2_i , + input wire qnet_vld_i , + input wire qnet_flag_i , +//QCOM + output wire qcom_en_o , + output wire [4 :0] qcom_op_o , + output wire [31:0] qcom_dt_o , + input wire qcom_rdy_i , + input wire [31 :0] qcom_dt1_i , + input wire [31 :0] qcom_dt2_i , + input wire qcom_vld_i , + input wire qcom_flag_i , +// QP1 + output wire qp1_en_o , + output wire [4 :0] qp1_op_o , + output wire [31:0] qp1_a_dt_o , + output wire [31:0] qp1_b_dt_o , + output wire [31:0] qp1_c_dt_o , + output wire [31:0] qp1_d_dt_o , + input wire qp1_rdy_i , + input wire [31 :0] qp1_dt1_i , + input wire [31 :0] qp1_dt2_i , + input wire qp1_vld_i , + input wire qp1_flag_i , +// QP2 + output wire qp2_en_o , + output wire [4 :0] qp2_op_o , + output wire [31:0] qp2_a_dt_o , + output wire [31:0] qp2_b_dt_o , + output wire [31:0] qp2_c_dt_o , + output wire [31:0] qp2_d_dt_o , + input wire qp2_rdy_i , + input wire [31 :0] qp2_dt1_i , + input wire [31 :0] qp2_dt2_i , + input wire qp2_vld_i , +// DMA AXIS FOR READ AND WRITE MEMORY + input wire [255 :0] s_dma_axis_tdata_i , + input wire s_dma_axis_tlast_i , + input wire s_dma_axis_tvalid_i , + output wire s_dma_axis_tready_o , + output wire [255 :0] m_dma_axis_tdata_o , + output wire m_dma_axis_tlast_o , + output wire m_dma_axis_tvalid_o , + input wire m_dma_axis_tready_i , +// AXI-Lite DATA Slave I/F. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + +/// DATA PORT INPUT + input wire [63:0] s0_axis_tdata , + input wire s0_axis_tvalid , + output wire s0_axis_tready , + input wire [63:0] s1_axis_tdata , + input wire s1_axis_tvalid , + output wire s1_axis_tready , + input wire [63:0] s2_axis_tdata , + input wire s2_axis_tvalid , + output wire s2_axis_tready , + input wire [63:0] s3_axis_tdata , + input wire s3_axis_tvalid , + output wire s3_axis_tready , + input wire [63:0] s4_axis_tdata , + input wire s4_axis_tvalid , + output wire s4_axis_tready , + input wire [63:0] s5_axis_tdata , + input wire s5_axis_tvalid , + output wire s5_axis_tready , + input wire [63:0] s6_axis_tdata , + input wire s6_axis_tvalid , + output wire s6_axis_tready , + input wire [63:0] s7_axis_tdata , + input wire s7_axis_tvalid , + output wire s7_axis_tready , + input wire [63:0] s8_axis_tdata , + input wire s8_axis_tvalid , + output wire s8_axis_tready , + input wire [63:0] s9_axis_tdata , + input wire s9_axis_tvalid , + output wire s9_axis_tready , + input wire [63:0] s10_axis_tdata , + input wire s10_axis_tvalid , + output wire s10_axis_tready , + input wire [63:0] s11_axis_tdata , + input wire s11_axis_tvalid , + output wire s11_axis_tready , + input wire [63:0] s12_axis_tdata , + input wire s12_axis_tvalid , + output wire s12_axis_tready , + input wire [63:0] s13_axis_tdata , + input wire s13_axis_tvalid , + output wire s13_axis_tready , + input wire [63:0] s14_axis_tdata , + input wire s14_axis_tvalid , + output wire s14_axis_tready , + input wire [63:0] s15_axis_tdata , + input wire s15_axis_tvalid , + output wire s15_axis_tready , +// OUT WAVE PORTS + // AXI Stream Master 0 /// + output wire [167:0] m0_axis_tdata , + output wire m0_axis_tvalid , + input wire m0_axis_tready , + output wire [167:0] m1_axis_tdata , + output wire m1_axis_tvalid , + input wire m1_axis_tready , + output wire [167:0] m2_axis_tdata , + output wire m2_axis_tvalid , + input wire m2_axis_tready , + output wire [167:0] m3_axis_tdata , + output wire m3_axis_tvalid , + input wire m3_axis_tready , + output wire [167:0] m4_axis_tdata , + output wire m4_axis_tvalid , + input wire m4_axis_tready , + output wire [167:0] m5_axis_tdata , + output wire m5_axis_tvalid , + input wire m5_axis_tready , + output wire [167:0] m6_axis_tdata , + output wire m6_axis_tvalid , + input wire m6_axis_tready , + output wire [167:0] m7_axis_tdata , + output wire m7_axis_tvalid , + input wire m7_axis_tready , + output wire [167:0] m8_axis_tdata , + output wire m8_axis_tvalid , + input wire m8_axis_tready , + output wire [167:0] m9_axis_tdata , + output wire m9_axis_tvalid , + input wire m9_axis_tready , + output wire [167:0] m10_axis_tdata , + output wire m10_axis_tvalid , + input wire m10_axis_tready , + output wire [167:0] m11_axis_tdata , + output wire m11_axis_tvalid , + input wire m11_axis_tready , + output wire [167:0] m12_axis_tdata , + output wire m12_axis_tvalid , + input wire m12_axis_tready , + output wire [167:0] m13_axis_tdata , + output wire m13_axis_tvalid , + input wire m13_axis_tready , + output wire [167:0] m14_axis_tdata , + output wire m14_axis_tvalid , + input wire m14_axis_tready , + output wire [167:0] m15_axis_tdata , + output wire m15_axis_tvalid , + input wire m15_axis_tready , + ///// TRIGGERS + output reg trig_0_o , + output reg trig_1_o , + output reg trig_2_o , + output reg trig_3_o , + output reg trig_4_o , + output reg trig_5_o , + output reg trig_6_o , + output reg trig_7_o , + output reg trig_8_o , + output reg trig_9_o , + output reg trig_10_o , + output reg trig_11_o , + output reg trig_12_o , + output reg trig_13_o , + output reg trig_14_o , + output reg trig_15_o , + output reg trig_16_o , + output reg trig_17_o , + output reg trig_18_o , + output reg trig_19_o , + output reg trig_20_o , + output reg trig_21_o , + output reg trig_22_o , + output reg trig_23_o , + output reg trig_24_o , + output reg trig_25_o , + output reg trig_26_o , + output reg trig_27_o , + output reg trig_28_o , + output reg trig_29_o , + output reg trig_30_o , + output reg trig_31_o , +// OUT DATA PORTS + output reg [OUT_DPORT_DW-1:0] port_0_dt_o , + output reg [OUT_DPORT_DW-1:0] port_1_dt_o , + output reg [OUT_DPORT_DW-1:0] port_2_dt_o , + output reg [OUT_DPORT_DW-1:0] port_3_dt_o , +// Debug Signals + output wire [31:0] ps_debug_do , + output wire [31:0] t_debug_do , + output wire [31:0] t_fifo_do , + output wire [31:0] c_time_usr_do , + output wire [31:0] c_debug_do , + output wire [31:0] c_time_ref_do , + output wire [31:0] c_proc_do , + output wire [31:0] c_port_do , + output wire [31:0] c_core_do + ); + +// DATA IN INTERFACE +reg port_tvalid_si [16]; +reg [63:0] port_tdata_si [16]; + +// TRIGGER INTERFACE +wire port_trig_so [32] ; + +// DATA OUT INTERFACE +wire [OUT_DPORT_DW-1:0] port_tdata_so [4] ; +wire port_tvalid_so [4] ; + +wire [167:0] m_axis_tdata_s [16] ; +wire m_axis_tvalid_s[16] ; +wire m_axis_tready_s[16] ; + +wire [31:0] periph_a_dt, periph_b_dt, periph_c_dt, periph_d_dt ; +wire [ 4:0] periph_op, periph_addr ; + +///// AXI LITE PORT ///// +/////////////////////////////////////////////////////////////////////////////// +TYPE_IF_AXI_REG IF_s_axireg() ; +assign IF_s_axireg.axi_awaddr = s_axi_awaddr ; +assign IF_s_axireg.axi_awprot = s_axi_awprot ; +assign IF_s_axireg.axi_awvalid = s_axi_awvalid; +assign IF_s_axireg.axi_wdata = s_axi_wdata ; +assign IF_s_axireg.axi_wstrb = s_axi_wstrb ; +assign IF_s_axireg.axi_wvalid = s_axi_wvalid ; +assign IF_s_axireg.axi_bready = s_axi_bready ; +assign IF_s_axireg.axi_araddr = s_axi_araddr ; +assign IF_s_axireg.axi_arprot = s_axi_arprot ; +assign IF_s_axireg.axi_arvalid = s_axi_arvalid; +assign IF_s_axireg.axi_rready = s_axi_rready ; +assign s_axi_awready = IF_s_axireg.axi_awready; +assign s_axi_wready = IF_s_axireg.axi_wready ; +assign s_axi_bresp = IF_s_axireg.axi_bresp ; +assign s_axi_bvalid = IF_s_axireg.axi_bvalid ; +assign s_axi_arready = IF_s_axireg.axi_arready; +assign s_axi_rdata = IF_s_axireg.axi_rdata ; +assign s_axi_rresp = IF_s_axireg.axi_rresp ; +assign s_axi_rvalid = IF_s_axireg.axi_rvalid ; + + +///// DATA IN PORTS ///// +/////////////////////////////////////////////////////////////////////////////// +always_comb begin + port_tdata_si[0] <= s0_axis_tdata ; + port_tdata_si[1] <= s1_axis_tdata ; + port_tdata_si[2] <= s2_axis_tdata ; + port_tdata_si[3] <= s3_axis_tdata ; + port_tdata_si[4] <= s4_axis_tdata ; + port_tdata_si[5] <= s5_axis_tdata ; + port_tdata_si[6] <= s6_axis_tdata ; + port_tdata_si[7] <= s7_axis_tdata ; + port_tdata_si[8] <= s8_axis_tdata ; + port_tdata_si[9] <= s9_axis_tdata ; + port_tdata_si[10] <= s10_axis_tdata ; + port_tdata_si[11] <= s11_axis_tdata ; + port_tdata_si[12] <= s12_axis_tdata ; + port_tdata_si[13] <= s13_axis_tdata ; + port_tdata_si[14] <= s14_axis_tdata ; + port_tdata_si[15] <= s15_axis_tdata ; + port_tvalid_si[0] <= s0_axis_tvalid ; + port_tvalid_si[1] <= s1_axis_tvalid ; + port_tvalid_si[2] <= s2_axis_tvalid ; + port_tvalid_si[3] <= s3_axis_tvalid ; + port_tvalid_si[4] <= s4_axis_tvalid ; + port_tvalid_si[5] <= s5_axis_tvalid ; + port_tvalid_si[6] <= s6_axis_tvalid ; + port_tvalid_si[7] <= s7_axis_tvalid ; + port_tvalid_si[8] <= s8_axis_tvalid ; + port_tvalid_si[9] <= s9_axis_tvalid ; + port_tvalid_si[10] <= s10_axis_tvalid ; + port_tvalid_si[11] <= s11_axis_tvalid ; + port_tvalid_si[12] <= s12_axis_tvalid ; + port_tvalid_si[13] <= s13_axis_tvalid ; + port_tvalid_si[14] <= s14_axis_tvalid ; + port_tvalid_si[15] <= s15_axis_tvalid ; +end + + +(* ASYNC_REG = "TRUE" *) reg proc_start_cdc, proc_start_r; +reg proc_start_r2; +(* ASYNC_REG = "TRUE" *) reg proc_stop_cdc , proc_stop_r; +reg proc_stop_r2; + +// Synchronize to C_CLK +always_ff @(posedge c_clk_i) + if (!c_resetn) begin + proc_start_cdc <= 0 ; + proc_start_r <= 0 ; + proc_start_r2 <= 0 ; + proc_stop_cdc <= 0 ; + proc_stop_r <= 0 ; + proc_stop_r2 <= 0 ; + end else begin + proc_start_cdc <= proc_start_i ; + proc_start_r <= proc_start_cdc ; + proc_start_r2 <= proc_start_r ; + proc_stop_cdc <= proc_stop_i ; + proc_stop_r <= proc_stop_cdc ; + proc_stop_r2 <= proc_stop_r ; + end + +// The C_TPROC_CTRL is only ONE clock. +assign proc_start_t01 = proc_start_r & ~proc_start_r2 ; +assign proc_stop_t01 = proc_stop_r & ~proc_stop_r2 ; + + +qick_processor# ( + .DEBUG ( DEBUG ), + .DUAL_CORE ( DUAL_CORE ), + .LFSR ( LFSR ), + .DIVIDER ( DIVIDER ), + .ARITH ( ARITH ), + .TIME_READ ( TIME_READ ), + .FIFO_DEPTH ( FIFO_DEPTH ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .OUT_TRIG_QTY ( OUT_TRIG_QTY ), + .OUT_DPORT_QTY ( OUT_DPORT_QTY ), + .OUT_DPORT_DW ( OUT_DPORT_DW ), + .OUT_WPORT_QTY ( OUT_WPORT_QTY ) +) QPROC ( + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_resetn ) , + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_resetn ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_resetn ) , +// CTRL + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_t01 ) , + .proc_stop_i ( proc_stop_t01 ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_updt_dt_i ( time_dt_i ) , + .time_abs_o ( t_time_abs_o ) , +// PERIPHERALS + .periph_a_dt_o ( periph_a_dt ) , + .periph_b_dt_o ( periph_b_dt ) , + .periph_c_dt_o ( periph_c_dt ) , + .periph_d_dt_o ( periph_d_dt ) , + .periph_op_o ( periph_op ) , + .qnet_en_o ( qnet_en_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt_i ( {qnet_dt1_i, qnet_dt2_i} ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + .qcom_en_o ( qcom_en_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt_i ( {qcom_dt1_i, qcom_dt2_i} ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + .qp1_en_o ( qp1_en_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt_i ( {qp1_dt1_i, qp1_dt2_i}) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + .qp2_en_o ( qp2_en_o ) , + .qp2_rdy_i ( qp2_rdy_i ) , + .qp2_dt_i ( {qp2_dt1_i, qp2_dt2_i}) , + .qp2_vld_i ( qp2_vld_i ) , +// PS + .IF_s_axireg ( IF_s_axireg ) , + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , +// PORTS + .port_tvalid_i ( port_tvalid_si [0:IN_PORT_QTY-1] ) , + .port_tdata_i ( port_tdata_si [0:IN_PORT_QTY-1] ) , + .port_trig_o ( port_trig_so [0:OUT_TRIG_QTY-1] ) , + .port_tvalid_o ( port_tvalid_so [0:OUT_DPORT_QTY-1] ) , + .port_tdata_o ( port_tdata_so [0:OUT_DPORT_QTY-1] ) , + .m_axis_tdata ( m_axis_tdata_s [0:OUT_WPORT_QTY-1] ) , + .m_axis_tvalid ( m_axis_tvalid_s [0:OUT_WPORT_QTY-1] ) , + .m_axis_tready ( m_axis_tready_s [0:OUT_WPORT_QTY-1] ) , +//DEBUG + .dport_di ( port_tdata_so[0][3:0] ) , + .ps_debug_do ( ps_debug_do ) , + .c_time_usr_do ( c_time_usr_do ) , + .t_debug_do ( t_debug_do ) , + .t_fifo_do ( t_fifo_do ) , + .c_debug_do ( c_debug_do ) , + .c_time_ref_do ( c_time_ref_do ) , + .c_proc_do ( c_proc_do ) , + .c_port_do ( c_port_do ) , + .c_core_do ( c_core_do ) +); + + + +// OUTPUT ASSIGNMENT +/////////////////////////////////////////////////////////////////////////////// + +///// QNET_DT +assign qnet_op_o = periph_op ; +assign qnet_a_dt_o = periph_a_dt ; +assign qnet_b_dt_o = periph_b_dt ; +assign qnet_c_dt_o = periph_c_dt ; + +///// QCOM_DT +assign qcom_op_o = periph_op ; +assign qcom_dt_o = periph_b_dt ; + +///// P1 +assign qp1_op_o = periph_op ; +assign qp1_a_dt_o = periph_a_dt ; +assign qp1_b_dt_o = periph_b_dt ; +assign qp1_c_dt_o = periph_c_dt ; +assign qp1_d_dt_o = periph_d_dt ; + +///// P2 +assign qp2_op_o = periph_op ; +assign qp2_a_dt_o = periph_a_dt ; +assign qp2_b_dt_o = periph_b_dt ; +assign qp2_c_dt_o = periph_c_dt ; +assign qp2_d_dt_o = periph_d_dt ; + +///// TRIGGER PORTS +genvar ind_t; +generate + if (OUT_TRIG_QTY < 31) + for (ind_t=31; ind_t >= OUT_TRIG_QTY; ind_t=ind_t-1) begin: TRIGGER_PORT_NOT_PRESENT + assign port_trig_so [ind_t] = 0; + end +endgenerate + +///// TRIGGERS +assign trig_0_o = port_trig_so[0] ; +assign trig_1_o = port_trig_so[1] ; +assign trig_2_o = port_trig_so[2] ; +assign trig_3_o = port_trig_so[3] ; +assign trig_4_o = port_trig_so[4] ; +assign trig_5_o = port_trig_so[5] ; +assign trig_6_o = port_trig_so[6] ; +assign trig_7_o = port_trig_so[7] ; +assign trig_8_o = port_trig_so[8] ; +assign trig_9_o = port_trig_so[9] ; +assign trig_10_o = port_trig_so[10] ; +assign trig_11_o = port_trig_so[11] ; +assign trig_12_o = port_trig_so[12] ; +assign trig_13_o = port_trig_so[13] ; +assign trig_14_o = port_trig_so[14] ; +assign trig_15_o = port_trig_so[15] ; +assign trig_16_o = port_trig_so[16] ; +assign trig_17_o = port_trig_so[17] ; +assign trig_18_o = port_trig_so[18] ; +assign trig_19_o = port_trig_so[19] ; +assign trig_20_o = port_trig_so[20] ; +assign trig_21_o = port_trig_so[21] ; +assign trig_22_o = port_trig_so[22] ; +assign trig_23_o = port_trig_so[23] ; +assign trig_24_o = port_trig_so[24] ; +assign trig_25_o = port_trig_so[25] ; +assign trig_26_o = port_trig_so[26] ; +assign trig_27_o = port_trig_so[27] ; +assign trig_28_o = port_trig_so[28] ; +assign trig_29_o = port_trig_so[29] ; +assign trig_30_o = port_trig_so[30] ; +assign trig_31_o = port_trig_so[31] ; + +///// DATA OUT PORTS +genvar ind; +generate + if (OUT_DPORT_QTY < 3) + for (ind=3; ind >= OUT_DPORT_QTY; ind=ind-1) begin: DATA_PORT_NOT_PRESENT + assign port_tdata_so [ind] = '{default:'0} ; + assign port_tvalid_so[ind] = 0; + end +endgenerate + +assign port_0_dt_o = port_tdata_so[0] ; +assign port_1_dt_o = port_tdata_so[1] ; +assign port_2_dt_o = port_tdata_so[2] ; +assign port_3_dt_o = port_tdata_so[3] ; + +///// WAVE OUT PORTS +generate + if (OUT_WPORT_QTY < 16) + for (ind=15; ind >= OUT_WPORT_QTY; ind=ind-1) begin: WAVE_PORT_NOT_PRESENT + assign m_axis_tdata_s[ind] = '{default:'0} ; + assign m_axis_tvalid_s[ind] = 0 ; + end +endgenerate + +assign s0_axis_tready = 1'b1; +assign s1_axis_tready = 1'b1; +assign s2_axis_tready = 1'b1; +assign s3_axis_tready = 1'b1; +assign s4_axis_tready = 1'b1; +assign s5_axis_tready = 1'b1; +assign s6_axis_tready = 1'b1; +assign s7_axis_tready = 1'b1; +assign s8_axis_tready = 1'b1; +assign s9_axis_tready = 1'b1; +assign s10_axis_tready = 1'b1; +assign s11_axis_tready = 1'b1; +assign s12_axis_tready = 1'b1; +assign s13_axis_tready = 1'b1; +assign s14_axis_tready = 1'b1; +assign s15_axis_tready = 1'b1; + +assign m_axis_tready_s[0] = m0_axis_tready ; +assign m_axis_tready_s[1] = m1_axis_tready ; +assign m_axis_tready_s[2] = m2_axis_tready ; +assign m_axis_tready_s[3] = m3_axis_tready ; +assign m_axis_tready_s[4] = m4_axis_tready ; +assign m_axis_tready_s[5] = m5_axis_tready ; +assign m_axis_tready_s[6] = m6_axis_tready ; +assign m_axis_tready_s[7] = m7_axis_tready ; +assign m_axis_tready_s[8] = m8_axis_tready ; +assign m_axis_tready_s[9] = m9_axis_tready ; +assign m_axis_tready_s[10] = m10_axis_tready ; +assign m_axis_tready_s[11] = m11_axis_tready ; +assign m_axis_tready_s[12] = m12_axis_tready ; +assign m_axis_tready_s[13] = m13_axis_tready ; +assign m_axis_tready_s[14] = m14_axis_tready ; +assign m_axis_tready_s[15] = m15_axis_tready ; + +assign m0_axis_tdata = m_axis_tdata_s [0] ; +assign m0_axis_tvalid = m_axis_tvalid_s[0] ; +assign m1_axis_tdata = m_axis_tdata_s [1] ; +assign m1_axis_tvalid = m_axis_tvalid_s[1] ; +assign m2_axis_tdata = m_axis_tdata_s [2] ; +assign m2_axis_tvalid = m_axis_tvalid_s[2] ; +assign m3_axis_tdata = m_axis_tdata_s [3] ; +assign m3_axis_tvalid = m_axis_tvalid_s[3] ; +assign m4_axis_tdata = m_axis_tdata_s [4] ; +assign m4_axis_tvalid = m_axis_tvalid_s[4] ; +assign m5_axis_tdata = m_axis_tdata_s [5] ; +assign m5_axis_tvalid = m_axis_tvalid_s[5] ; +assign m6_axis_tdata = m_axis_tdata_s [6] ; +assign m6_axis_tvalid = m_axis_tvalid_s[6] ; +assign m7_axis_tdata = m_axis_tdata_s [7] ; +assign m7_axis_tvalid = m_axis_tvalid_s[7] ; +assign m8_axis_tdata = m_axis_tdata_s [8] ; +assign m8_axis_tvalid = m_axis_tvalid_s[8] ; +assign m9_axis_tdata = m_axis_tdata_s [9] ; +assign m9_axis_tvalid = m_axis_tvalid_s[9] ; +assign m10_axis_tdata = m_axis_tdata_s [10] ; +assign m10_axis_tvalid = m_axis_tvalid_s[10] ; +assign m11_axis_tdata = m_axis_tdata_s [11] ; +assign m11_axis_tvalid = m_axis_tvalid_s[11] ; +assign m12_axis_tdata = m_axis_tdata_s [12] ; +assign m12_axis_tvalid = m_axis_tvalid_s[12] ; +assign m13_axis_tdata = m_axis_tdata_s [13] ; +assign m13_axis_tvalid = m_axis_tvalid_s[13] ; +assign m14_axis_tdata = m_axis_tdata_s [14] ; +assign m14_axis_tvalid = m_axis_tvalid_s[14] ; +assign m15_axis_tdata = m_axis_tdata_s [15] ; +assign m15_axis_tvalid = m_axis_tvalid_s[15] ; + + +generate + if (GEN_SYNC == 1) begin : SYNC_OUT + reg net_sync; + always_ff @ (posedge t_clk_i, negedge t_resetn) begin + if (!t_resetn) net_sync <= 1'b0; + else net_sync <= t_time_abs_o[29]; + end + assign pulse_sync_o = net_sync; + end else + assign pulse_sync_o = 0; +endgenerate + +endmodule diff --git a/firmware/ip/qick_processor/src/axis_read.v b/firmware/ip/qick_processor/src/axis_read.v new file mode 100644 index 000000000..3df9d36e9 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_read.v @@ -0,0 +1,138 @@ +module axis_read # ( + parameter N = 10 , // Memory depth (2**N). + parameter B = 16 // Memory width. +)( + input aclk_i , + input aresetn_i , + input [N-1:0] addr_i , + input [N-1:0] len_i , + input exec_i , + output exec_ack_o , + output mem_we_o , + output [N-1:0] mem_addr_o , + input [B-1:0] mem_do_i , + input m_axis_tready_i , + output [B-1:0] m_axis_tdata_o , + output m_axis_tlast_o , + output m_axis_tvalid_o ); + +// States. +localparam INIT_ST = 0; +localparam LOAD0_ST = 1; +localparam LOAD1_ST = 2; +localparam SEND_ST = 3; +localparam ACK_ST = 4; +localparam END_ST = 5; + +// State register. +reg [2:0] state; +// State flags. +reg load0_state; +reg load1_state; +reg send_state; +reg ack_int; +// Start address and length. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; +// Counter. +reg [N-1:0] cnt; +// Selection (0: mem, 1: reg). +reg sel_r; + +// Data register. +reg [B-1:0] data_r; +wire data_en; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + // Start address and length. + addr_r <= 0; + len_r <= 0; + // Counter. + cnt <= 0; + // Selection (0: mem, 1: reg). + sel_r <= 0; + // Data register. + data_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= LOAD0_ST; + LOAD0_ST: + state <= LOAD1_ST; + + LOAD1_ST: + state <= SEND_ST; + + SEND_ST: + if (cnt == len_r-1 && m_axis_tready_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Start address and length. + if (load0_state) + addr_r <= addr_i; + else if (load1_state || (send_state && m_axis_tready_i)) + addr_r <= addr_r + 1; + if (load0_state) + len_r <= len_i; + // Counter. + if (load0_state) + cnt <= 0; + else if (send_state && m_axis_tready_i) + cnt <= cnt + 1; + + // Selection (0: mem, 1: reg). + if (send_state && ~m_axis_tready_i) + sel_r <= 1; + else + sel_r <= 0; + + // Data register. + if (data_en) + data_r <= mem_do_i; + end +end + +// FSM outputs. +always @(state) begin + // Default. + load0_state = 0; + load1_state = 0; + send_state = 0; + ack_int = 0; + case (state) + //INIT_ST: + LOAD0_ST: load0_state = 1; + LOAD1_ST: load1_state = 1; + SEND_ST: send_state = 1; + ACK_ST: ack_int = 1; + //END_ST: + default:; + endcase +end + +// Data enable. +assign data_en = m_axis_tready_i | ~sel_r; + +// Assign outputs. +assign m_axis_tdata_o = (sel_r == 1)? data_r : mem_do_i; +assign m_axis_tlast_o = (cnt == len_r-1) & send_state; +assign m_axis_tvalid_o = send_state; +assign mem_we_o = 1'b0; +assign mem_addr_o = addr_r; +assign exec_ack_o = ack_int; + +endmodule diff --git a/firmware/ip/qick_processor/src/axis_write.v b/firmware/ip/qick_processor/src/axis_write.v new file mode 100644 index 000000000..26ddb39c2 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_write.v @@ -0,0 +1,152 @@ +module axis_write ( + // Reset and clock. + aclk_i , + aresetn_i , + + // AXIS Slave for receiving data. + s_axis_tdata_i , + s_axis_tlast_i , + s_axis_tvalid_i , + s_axis_tready_o , + + // Memory interface. + mem_we_o , + mem_di_o , + mem_addr_o , + + // Handshake. + exec_i , + exec_ack_o , + + // Start address. + addr_i +); + +// Parameters. +parameter N = 10; // Memory depth (2**N). +parameter B = 16; // Memory width. + +// Ports. +input aclk_i; +input aresetn_i; +input [B-1:0] s_axis_tdata_i; +input s_axis_tlast_i; +input s_axis_tvalid_i; +output s_axis_tready_o; +output mem_we_o; +output [B-1:0] mem_di_o; +output [N-1:0] mem_addr_o; +input exec_i; +output exec_ack_o; +input [N-1:0] addr_i; + +// States. +localparam INIT_ST = 0; +localparam WRITE_ST = 1; +localparam ACK_ST = 2; +localparam END_ST = 3; + +// State register. +reg [1:0] state; + +// State flags. +reg init_state; +reg write_state; +reg ack_int; + +// Address generation. +reg [N-1:0] addr_cnt; +reg [N-1:0] addr_cnt_r; + +// Data. +reg [B-1:0] data_r; + +// we generation. +wire we_int; +reg we_int_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Address generation. + addr_cnt <= 0; + addr_cnt_r <= 0; + + // Data. + data_r <= 0; + + // we generation. + we_int_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= WRITE_ST; + + WRITE_ST: + if (s_axis_tlast_i && s_axis_tvalid_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Address generation. + if (init_state) + addr_cnt <= addr_i; + else if (s_axis_tvalid_i) + addr_cnt <= addr_cnt + 1; + + addr_cnt_r <= addr_cnt; + + // Data. + data_r <= s_axis_tdata_i; + + // we generation. + we_int_r <= we_int; + + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + write_state = 0; + ack_int = 0; + + case (state) + INIT_ST: + init_state = 1; + + WRITE_ST: + write_state = 1; + + ACK_ST: + ack_int = 1; + + //END_ST: + default:; + endcase +end + +// we generation. +assign we_int = s_axis_tvalid_i & write_state; + +// Assign outputs. +assign s_axis_tready_o = write_state; +assign mem_we_o = we_int_r; +assign mem_di_o = data_r; +assign mem_addr_o = addr_cnt_r; +assign exec_ack_o = ack_int; + +endmodule + diff --git a/firmware/ip/qick_processor/src/data_mem_ctrl.v b/firmware/ip/qick_processor/src/data_mem_ctrl.v new file mode 100644 index 000000000..3de3a45f5 --- /dev/null +++ b/firmware/ip/qick_processor/src/data_mem_ctrl.v @@ -0,0 +1,122 @@ +// Control arbiter for memory access operations. +// +// The block arbitrates access to the memory. While executing +// either AXIS Read or Write, busy flag is asserted. If the +// busy flag is not asserted, memory can be accessed using +// single mode (external block). +// +// mem_op_i: +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// mem_start_i: +// * 0 : Stop. +// * 1 : Execute Operation. +module data_mem_ctrl #( + parameter N = 16 +)( + input wire aclk_i , + input wire aresetn_i , + output wire [1:0] sel_o , + output wire ar_exec_o , + input wire ar_exec_ack_i , + output wire aw_exec_o , + input wire aw_exec_ack_i , + output wire busy_o , + input wire mem_op_i , + input wire mem_start_i ); + +// States. +localparam INIT_ST = 0; +localparam AXIS_READ_ST = 1; +localparam AXIS_READ_ACK_ST = 2; +localparam AXIS_WRITE_ST = 3; +localparam AXIS_WRITE_ACK_ST = 4; +localparam END_ST = 6; + +// State register. +reg [2:0] state; +// State flags. +reg busy_int ; +reg ar_exec_int ; +reg aw_exec_int ; +reg [1:0] sel_int ; // 0: single, 1: axis_read, 2: axis_write. + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + end + else begin + // State register. + case(state) + INIT_ST: + if (mem_start_i == 1'b1) + if (mem_op_i == 1'b0) + // AXIS read (from memory to m_axis). + state <= AXIS_READ_ST; + else + // AXIS write (from s_axis to memory). + state <= AXIS_WRITE_ST; + AXIS_READ_ST: + state <= AXIS_READ_ACK_ST; + AXIS_READ_ACK_ST: + if (ar_exec_ack_i == 1'b1) + state <= END_ST; + AXIS_WRITE_ST: + state <= AXIS_WRITE_ACK_ST; + AXIS_WRITE_ACK_ST: + if (aw_exec_ack_i == 1'b1) + state <= END_ST; + END_ST: + if (mem_start_i == 1'b0) + state <= INIT_ST; + endcase + + end +end + +// FSM outputs. +always @(state) begin + // Default. + busy_int = 0; + ar_exec_int = 0; + aw_exec_int = 0; + sel_int = 0; + + case (state) + //INIT_ST: + + AXIS_READ_ST: begin + busy_int = 1; + sel_int = 1; + end + AXIS_READ_ACK_ST: begin + ar_exec_int = 1; + busy_int = 1; + sel_int = 1; + end + AXIS_WRITE_ST: begin + busy_int = 1; + sel_int = 2; + end + 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+ "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "p_intf": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "master", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "P" } ] + } + }, + "ced_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ced1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ced2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ced3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cea_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cea1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cea2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cea3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cea4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceb_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceb1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceb2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceb3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceb4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceconcat_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceconcat3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceconcat4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "ceconcat5_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cec5_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cem_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cep_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel1_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel5_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "sclrd_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclra_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrb_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrconcat_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrc_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrm_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrp_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrsel_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/logoQICK_128x128.png b/firmware/ip/qick_processor/src/logoQICK_128x128.png new file mode 100644 index 000000000..209264ba8 Binary files /dev/null and b/firmware/ip/qick_processor/src/logoQICK_128x128.png differ diff --git a/firmware/ip/qick_processor/src/mem_rw.v b/firmware/ip/qick_processor/src/mem_rw.v new file mode 100644 index 000000000..ca9b3f318 --- /dev/null +++ b/firmware/ip/qick_processor/src/mem_rw.v @@ -0,0 +1,104 @@ +// Block to execute single read/write operation over a memory. +module mem_rw # ( + parameter N = 10 , // Memory depth (2**N). + parameter B = 16 // Memory width. +)( + input wire aclk_i , + input wire aresetn_i , + input wire rw_i , //0-READ , 1-Write + input wire exec_i , + output wire exec_ack_o , + input wire [N-1:0] addr_i , + input wire [B-1:0] di_i , + output wire [B-1:0] do_o , + output wire mem_we_o , + output wire [B-1:0] mem_di_o , + input wire [B-1:0] mem_do_i , + output wire [N-1:0] mem_addr_o ); + +// States. +localparam INIT_ST = 0; +localparam READ0_ST = 1; +localparam READ1_ST = 2; +localparam WRITE_ST = 3; +localparam ACK_ST = 4; + +// State register. +reg [2:0] state; + +// Flags. +reg init_state; +reg re_int; +reg we_int; +reg ack_int; + +// Address/data register. +reg [N-1:0] addr_r; +reg [B-1:0] din_r; +reg [B-1:0] dout_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + state <= INIT_ST; + addr_r <= 0; + din_r <= 0; + dout_r <= 0; + end else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + if (rw_i == 1'b0) + state <= READ0_ST; + else + state <= WRITE_ST; + READ0_ST: + state <= READ1_ST; + READ1_ST: + state <= ACK_ST; + WRITE_ST: + state <= ACK_ST; + ACK_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Address/data register. + if (init_state) begin + addr_r <= addr_i; + din_r <= di_i; + end + if (re_int) + dout_r <= mem_do_i; + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + re_int = 0; + we_int = 0; + ack_int = 0; + case (state) + INIT_ST: + init_state = 1; + //READ0_ST: + READ1_ST: + re_int = 1; + WRITE_ST: + we_int = 1; + ACK_ST: + ack_int = 1; + default:; + endcase +end + +// Assign outputs. +assign exec_ack_o = ack_int; +assign do_o = dout_r ; +assign mem_we_o = we_int ; +assign mem_di_o = din_r ; +assign mem_addr_o = addr_r ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qcore_cpu.sv b/firmware/ip/qick_processor/src/qcore_cpu.sv new file mode 100644 index 000000000..7bb1e2e7c --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_cpu.sv @@ -0,0 +1,727 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qcore_cpu # ( + parameter LFSR = 1 , + parameter PMEM_AW = 8 , + parameter DMEM_AW = 8 , + parameter WMEM_AW = 8 , + parameter REG_AW = 4 +)( + input wire clk_i , + input wire rst_ni , + input wire restart_i , + input wire en_i , + input wire [1:0] lfsr_cfg_i , // CONFIGURATION (LFSR) + output wire [31:0] lfsr_o , +// DEBUG + output wire [31:0] core_do , // Core Signal Debug +// CONDITIONS + input wire flag_i , // External Condition +// DATA INPUT + output wire [7:0] sreg_cfg_o , + output wire [7:0] sreg_ctrl_o , + input wire [31:0] sreg_arith_i , + input wire [31:0] sreg_div_i [2] , + input wire [31:0] sreg_status_i , + input wire [31:0] sreg_core_r_dt_i[2] , + input wire [31:0] sreg_port_dt_i [2] , + input wire [31:0] sreg_time_dt_i , + output wire [31:0] sreg_core_w_dt_o[2] , + output wire usr_en_o , // CONTROL Enable + output wire [7:0] usr_ctrl_o , // CONTROL from Current Instruction + output wire [31:0] usr_dt_a_o , // Data A from Current Instruction (rsD0) + output wire [31:0] usr_dt_b_o , // Data B from Current Instruction (rsD1) + output wire [31:0] usr_dt_c_o , // Data C from Current Instruction (rsA0) + output wire [31:0] usr_dt_d_o , // Data D from Current Instruction (rsA1m) +// PROGRAM MEMORY + output wire [PMEM_AW-1:0] pmem_addr_o , + output wire pmem_en_o , + input wire [71:0] pmem_dt_i , +// DATA MEMORY + output wire dmem_we_o , + output wire [DMEM_AW-1:0] dmem_addr_o , + output wire [31:0] dmem_w_dt_o , + input wire [31:0] dmem_r_dt_i , +// WAVE MEMORY + output wire wmem_we_o , + output wire [WMEM_AW-1:0] wmem_addr_o , + output wire [167:0] wmem_w_dt_o , + input wire [167:0] wmem_r_dt_i , +//OUTPUT PORTS + output wire port_we_o , + output wire port_re_o , + output PORT_DT port_o + ); + +/////////////////////////////////////////////////////////////////////////////// +// Signal Declaration + +// Address Signals +reg [10:0] r_id_imm_addr, r_rd_imm_addr ; +reg [5:0] r_rd_rsA1_addr ; +wire [PMEM_AW-1:0] reg_addr; +//Data Signals +reg [31 :0] r_id_imm_dt, r_rd_imm_dt, r_x1_imm_dt; +reg [31 :0] r_x1_alu_dt ; +// Data Signals +wire [31:0] x1_alu_dt ; +wire x1_alu_fZ, x1_alu_fC, x1_alu_fS ; +wire [WMEM_AW-1:0] x1_wave_addr ; +// Pipeline registers. +reg [PMEM_AW-1 : 0] PC_curr, PC_nxt, PC_prev ; +reg [2:0] cfg_pc_nxt; + +wire id_pc_change; +reg r_id_pc_change ; +reg [5:0] r_id_rs_A_addr [2] ; // Address in the RegBank +reg [6:0] r_id_rs_D_addr [2] ; // Address in the RegBank +wire [31:0] reg_D_fwd_dt [2] ; +wire [31:0] reg_A_fwd_dt [2] ; +wire [31:0] reg_time ; + +// PROCESSOR STATUS +/////////////////////////////////////////////////////////////////////////////// +wire halt, flush, stall, bubble_id, bubble_rd; + +assign halt = ~en_i ; +assign flush = id_pc_change | r_id_pc_change ; +assign stall = bubble_id | bubble_rd; +assign fetch_en = ~stall & ~halt; + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// IF - 1 FIRST Stage IF_ ( Instruction FECTH ) +/////////////////////////////////////////////////////////////////////////////////////////////////// + +wire [ 15 : 0 ] if_op_code ; +wire [ 55 : 0 ] if_op_data ; +reg [ 15 : 0 ] r_if_op_code ; +reg [ 55 : 0 ] r_if_op_data ; +reg r_mem_rst; +assign if_op_code = pmem_dt_i [ 71 : 56 ] ; +assign if_op_data = pmem_dt_i [ 55 : 0 ] ; + +// empty memory Pipeline +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + r_mem_rst <= 1; + r_if_op_code <= 0; + r_if_op_data <= 0; + end else if (restart_i) begin + r_mem_rst <= 1; + r_if_op_code <= 0; + r_if_op_data <= 0; + end else begin + r_mem_rst <= 0; + if (r_mem_rst) begin + r_if_op_code <= 0; + r_if_op_data <= 0; + end + else if (pmem_en_o) begin + if (flush) begin + r_if_op_code <= 0; + r_if_op_data <= 0; + end else begin + r_if_op_code <= if_op_code; + r_if_op_data <= if_op_data; + end + end + end + +end + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// +// ID - 2 SECOND STAGE ID_ INSTRUCTION DECODER +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// CONTROL +/////////////////////////////////////////////////////////// +wire [2:0] id_HEADER ; +wire id_AI ; +wire [1:0] id_DF ; +wire [2:0] id_COND; +wire id_SO, id_TO; + +assign id_HEADER = r_if_op_code [ 15 : 13 ] ; +assign id_AI = r_if_op_code [ 12 ] ; +assign id_DF = r_if_op_code [ 11 : 10] ; +assign id_COND = r_if_op_code [ 9 : 7 ] ; +assign id_SO = r_if_op_code [ 6 ] ; +assign id_TO = r_if_op_code [ 5 ] ; + + +reg id_type_cfg, id_type_br, id_type_int_ctrl, id_type_ext_ctrl; +reg id_type_wr, id_type_wrd, id_type_wrw, id_type_wra ; +reg id_type_wp, id_type_wpd, id_type_wpw ; +reg id_type_wm, id_type_wmd, id_type_wmw; + +reg id_cfg_port_src, id_cfg_alu_src, id_cfg_dt_imm ; +reg [3:0] id_cfg_alu_op ; +reg [1:0] id_cfg_reg_src ; +reg cfg_dual_regs_en, cfg_flag_en, cfg_dual_port_en, cfg_dual_wmem_en ; +reg cfg_dual_regs_we, cfg_dual_port_we, cfg_dual_wmem_we ; +reg id_flag_we; +reg id_dmem_we , id_wmem_we ; +reg id_dreg_we , id_r_wave_we ; +reg id_dport_re, id_dport_we, id_wport_we ; + +reg id_call, id_ret ; + +reg [8:0] id_usr_ctrl; // MSB indicate Internal or External +reg id_cond_ok, id_exec_ok, id_branch_cond_ok; +reg alu_fZ_r, alu_fS_r; + +reg id_wpd_imm, id_periph_imm; + +always_comb begin : DECODER + id_type_cfg = ( id_HEADER == CFG ) ; + id_type_br = ( id_HEADER == BRANCH ) ; + id_type_wr = ( id_HEADER == REG_WR ) ; + id_type_wm = ( id_HEADER == MEM_WR ) ; + id_type_wp = ( id_HEADER == PORT_WR ) ; + id_type_int_ctrl = ( id_HEADER == INT_CTRL ) ; + id_type_ext_ctrl = ( id_HEADER == EXT_CTRL ) ; + id_type_wra = id_type_wr & (~id_SO & ~id_TO) ; // Write Data Register from ALU + id_type_wrd = id_type_wr & ~(id_SO & ~id_TO) ; // Write Data Register (ALU, MEM, or IMM) + id_type_wrw = id_type_wr & (id_SO & ~id_TO) ; // Write Wave Data Register + id_type_wmd = id_type_wm & ~id_SO ; // Write Data Memory + id_type_wmw = id_type_wm & id_SO ; // Write Wave Memory + id_type_wpd = id_type_wp & ~id_SO ; // Write Data Port + id_type_wpw = id_type_wp & id_SO ; // Write Wave Port + + id_cfg_port_src = r_if_op_code[8] ; + //id_wpd_imm = id_type_wpd & id_cfg_port_src ; + //id_periph_imm = id_type_int_ctrl & id_AI; + //id_cfg_dt_imm = &id_DF | ( (id_type_wm | id_type_cfg) & id_TO ) | id_wpd_imm | id_periph_imm ; // Immediate input Data + id_cfg_dt_imm = &id_DF | ( (id_type_wm | id_type_cfg) & id_TO ) | (id_type_wpd & id_cfg_port_src) ; // Immediate input Data + id_cfg_alu_src = ( id_DF == 2'b10) ; //With DI=10 Source =1 + id_cfg_alu_op = id_type_wra ? r_if_op_code[3:0] : {1'b0, r_if_op_code[1:0], 1'b0 } ; + id_cfg_reg_src = id_type_wrd ? r_if_op_code[6:5] : {2{r_if_op_code [2]}} ; // When Writing WAVE Second OPTION + cfg_dual_regs_en = ( id_type_wrw | id_type_wm | id_type_wp | id_type_br | id_type_cfg ) ; // Is Possible to + cfg_flag_en = cfg_dual_regs_en | id_type_wr ; // Is Possible to Update Flag + cfg_dual_port_en = id_type_wrw | id_type_wmw ; // Is Possible to Dual PORT WRITE + cfg_dual_wmem_en = id_type_wrw | id_type_wpw ; // Is Possible to Dual WaveForm MEM WRITE + cfg_dual_regs_we = cfg_dual_regs_en & r_if_op_code[3] ; // Dual REGISTER WRITE ENABLE + cfg_dual_port_we = cfg_dual_port_en & r_if_op_code[7] ; // Dual PORT WRITE ENABLE + cfg_dual_wmem_we = cfg_dual_wmem_en & r_if_op_code[9] ; // Dual WMEM WRITE ENABLE + id_flag_we = id_exec_ok & cfg_flag_en & r_if_op_code[4] ; // Flag WRITE ENABLE + id_dreg_we = id_exec_ok & ( id_type_wrd | cfg_dual_regs_we ) ; // DREG WRITE ENABLE + id_r_wave_we = id_type_wrw ; // WREG WRITE ENABLE (The 167 Bits) + id_dmem_we = id_exec_ok & ( id_type_wmd ) ; // DMEM WRITE ENABLE + id_wmem_we = id_type_wmw | cfg_dual_wmem_we & r_if_op_code[9] ; // WMEM WRITE ENABLE + id_dport_we = id_type_wpd & r_if_op_code[7] ; // DPORT WRITE ENABLE + id_dport_re = id_type_wpd & ~r_if_op_code[7] ; // DPORT READ ENABLE + id_wport_we = id_type_wpw | cfg_dual_port_we ; // WPORT WRITE ENABLE + id_call = id_branch_cond_ok & id_SO & ~id_TO ; // Execute CALL Instruction (Push) + id_ret = id_type_br & id_SO & id_TO ; // Execute RET Instruction (Pull) + id_usr_ctrl = id_type_int_ctrl ? {id_exec_ok, 1'b0, r_if_op_code[6:0]} : id_type_ext_ctrl ? {id_exec_ok,1'b1,r_if_op_code[6:0]} : 9'b000000000 ; +end + + + +reg [ 31 : 0 ] id_imm_dt ; +reg [15:0] id_imm_addr ; +reg [5 :0] id_rs_A_addr [2]; +reg [6 :0] id_rs_D_addr [2]; +reg [6 :0] id_rd_addr ; +wire [PMEM_AW-1:0] pc_stack; + +/////////////////////////////////////////////////////////////////////////////// +// DATA +always_comb + unique case (id_DF) + 2'b00 : id_imm_dt = id_imm_addr ; // Data Immediate is 16 Bits Address Space + 2'b01 : id_imm_dt = { {16{r_if_op_data[22]}} , r_if_op_data [22:7]} ; // Data Immediate is 16 Bits SIGNED + 2'b10 : id_imm_dt = { { 8{r_if_op_data[30]}} , r_if_op_data [30:7]} ; // Data Immediate is 24 Bits SIGNED + 2'b11 : id_imm_dt = r_if_op_data [38:7] ; // Data Immediate is 32 Bits + endcase + +/////////////////////////////////////////////////////////////////////////////// +// ADDRESS +// Immediate DATA is not Register ADDRESS +//assign id_use_RA0 = id_AI; +//assign id_use_RA1 = id_type_wmd | (id_type_wr & (~id_SO & id_TO)); +assign id_use_RD0 = id_DF != 2'b11; +assign id_use_RD1 = id_DF == 2'b01; + +assign id_type_wr_dmem = id_type_wr & (~id_SO & id_TO); // Write Data Register from DMEM + +always_comb begin + id_imm_addr = r_if_op_data [ 55 : 45 ] ; + id_rs_A_addr[0] = r_if_op_data [ 50 : 45 ] ; + id_rs_A_addr[1] = r_if_op_data [ 44 : 39 ] ; + id_rs_D_addr[0] = id_use_RD0 ? r_if_op_data [ 37 : 31 ] : 0 ; + id_rs_D_addr[1] = id_use_RD1 ? r_if_op_data [ 29 : 23 ] : 0 ; + id_rd_addr = r_if_op_data [ 6 : 0 ] ; +end + +assign id_reg.we = id_dreg_we ; +assign id_reg.r_wave_we = id_r_wave_we ; +assign id_reg.addr = id_rd_addr ; +assign id_reg.src = id_cfg_reg_src ; +assign id_reg.port_re = id_dport_re ; + +assign id_ctrl.cfg_addr_imm = id_AI ; +assign id_ctrl.cfg_dt_imm = id_cfg_dt_imm ; +assign id_ctrl.cfg_port_src = id_cfg_port_src ; +assign id_ctrl.cfg_port_type = id_type_wpd ; +assign id_ctrl.cfg_port_time = id_type_wp & id_TO ; +assign id_ctrl.cfg_cond = id_COND ; +assign id_ctrl.cfg_alu_src = id_cfg_alu_src ; +assign id_ctrl.cfg_alu_op = id_cfg_alu_op ; +assign id_ctrl.usr_ctrl = id_usr_ctrl ; +assign id_ctrl.flag_we = id_flag_we ; +assign id_ctrl.dmem_we = id_dmem_we ; +assign id_ctrl.wmem_we = id_wmem_we ; +assign id_ctrl.port_we = id_wport_we | id_dport_we ; + + +// CONDITION +///////////////////////////////////////////////// + +reg id_cond_used, id_flag_used ; +always_comb begin + unique case ( id_COND ) + 3'b000: id_cond_ok = 1 ; // ALWAYS + 3'b001: id_cond_ok = alu_fZ_r ; //EQ - Z + 3'b010: id_cond_ok = alu_fS_r ; //LT - S + 3'b011: id_cond_ok = ~alu_fZ_r ; //NZ -not(Z) + 3'b100: id_cond_ok = ~alu_fS_r ; //NS -not(S) + 3'b101: id_cond_ok = flag_i ; // External Flag + 3'b110: id_cond_ok = ~flag_i ; // NOT External Flag + 3'b111: id_cond_ok = 0 ; // RFU + endcase + id_cond_used = id_type_cfg | id_type_wra | id_type_wrd | id_type_wmd | id_type_br | id_type_int_ctrl | id_type_ext_ctrl ; // Conditional Instruction + id_flag_used = id_cond_used & |id_COND ; // Condition should be checked + id_exec_ok = id_cond_ok | ~id_cond_used ; // Execute Instruction + id_branch_cond_ok = id_type_br & id_exec_ok ; // Execute BRANCH +end + + +// PC_ADDR CALCULATION +///////////////////////////////////////////////// +always_comb begin + cfg_pc_nxt = 2'b00; // Move to Next Address + if ( id_ret ) cfg_pc_nxt = 2'b11; // Return from CALL RET is NOT conditional + else if (id_branch_cond_ok) + if (id_AI) cfg_pc_nxt = 2'b01 ; // Jump to IMM Address + else cfg_pc_nxt = 2'b10; // Jump to REG Address +end + +wire id_jmp_reg_used; +assign id_jmp_reg_used = (cfg_pc_nxt == 2'b10) ; + +assign id_pc_change = |cfg_pc_nxt; + +always_comb begin + PC_nxt = PC_curr + 1 ; + unique case (cfg_pc_nxt ) + 2'b00: PC_nxt = PC_curr + 1 ; + 2'b01: PC_nxt = id_imm_addr ; + 2'b10: PC_nxt = reg_addr ; + 2'b11: PC_nxt = pc_stack ; + default:; + endcase +end + +always @(posedge clk_i) begin + if (!rst_ni) begin + PC_curr <= 0; + PC_prev <= 0; + end else begin + if (restart_i) begin + PC_curr <= 0; + PC_prev <= 0; + end else if (fetch_en) begin + PC_curr <= PC_nxt; + PC_prev <= PC_curr; + end + end +end + + + +// X1 - 4 FOURTH STAGE - ADDRESS CALCULATION - EXECUTE_1 +/////////////////////////////////////////////////////////////////////////////////////////////////// + +wire [31:0] x1_rsD0_dt, x1_rsD1_dt ; +wire [31:0] x1_rsA1_dt, x1_rsA0_dt ; +wire [31:0] rs_A_dt [2] ; +wire [31:0] rs_D_dt [2] ; + + +assign x1_rsA0_dt = x1_ctrl.cfg_addr_imm ? r_rd_imm_addr : reg_A_fwd_dt[0] ; +assign x1_rsA1_dt = reg_A_fwd_dt[1] ; +assign x1_rsD0_dt = reg_D_fwd_dt[0] ; +assign x1_rsD1_dt = reg_D_fwd_dt[1] ; + +// ARITHMETIC UNIT +///////////////////////////////////////////////// +reg [31:0] x1_alu_in_A, x1_alu_in_B ; +assign x1_alu_in_A = x1_rsD0_dt; +assign x1_alu_in_B = x1_ctrl.cfg_alu_src ? r_rd_imm_dt : x1_rsD1_dt ; + +// DATA MEMORY +///////////////////////////////////////////////// +wire [DMEM_AW-1:0] x1_mem_addr ; +wire [31:0] x1_mem_w_dt ; +assign x1_mem_addr = x1_rsA0_dt + x1_rsA1_dt ; +assign x1_mem_w_dt = x1_ctrl.cfg_dt_imm ? r_rd_imm_dt : x1_alu_dt ; + +// WAVE MEMORY +/////////////////////////////////////////////////////////////////////////////// +assign x1_wave_addr = x1_rsA0_dt[WMEM_AW-1:0] ; + +// PORT +/////////////////////////////////////////////////////////////////////////////// +wire [5:0] x1_port_w_addr; +assign x1_port_w_addr = r_rd_rsA1_addr[5:0] ; + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// +// X2 - 5 FIFTH STAGE X2_ - EXECUTE_2 +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// + +reg [167:0] reg_wave_dt ; + +// Input to Register Bank +reg [31:0] x2_reg_w_dt ; + +always_comb begin +// Data Input + case (x2_reg.src) + 2'b00: x2_reg_w_dt = r_x1_alu_dt ; + 2'b01: x2_reg_w_dt = dmem_r_dt_i ; + 2'b10: x2_reg_w_dt = r_x1_alu_dt ; + 2'b11: x2_reg_w_dt = r_x1_imm_dt ; + + endcase +end + + +// WAVE +///////////////////////////////////////////////// +wire [167:0] x2_wave_w_dt; +assign x2_wave_w_dt = x2_ctrl.cfg_port_src ? reg_wave_dt : wmem_r_dt_i ; + +// PORT +///////////////////////////////////////////////// +wire [167:0] x2_port_w_dt ; +reg [5:0] r_x1_port_w_addr; + + +reg [31:0] r_x1_port_dt; + +assign x2_port_w_dt = x2_ctrl.cfg_port_type ? r_x1_port_dt : x2_wave_w_dt ; + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + +CTRL_REG id_reg, rd_reg, x1_reg, x2_reg, wr_reg ; +CTRL_FLOW id_ctrl, rd_ctrl, x1_ctrl, x2_ctrl ; + +qcore_ctrl_hazard ctrl_hzrd ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .halt_i ( halt ) , + .rs_A_addr_i ( r_id_rs_A_addr ) , + .rs_A_dt_i ( rs_A_dt ) , + .rs_D_addr_i ( r_id_rs_D_addr ) , + .rs_D_dt_i ( rs_D_dt ) , + // Register Write Enable + .id_reg_i ( id_reg ) , + .rd_reg_i ( rd_reg ) , + .x1_reg_i ( x1_reg ) , + .x2_reg_i ( x2_reg ) , + .wr_reg_i ( wr_reg ) , + // Peripheral + .rd_periph_use ( rd_ctrl.usr_ctrl[8] ) , + .x1_periph_use ( x1_ctrl.usr_ctrl[8] ) , + .x2_periph_use ( x2_ctrl.usr_ctrl[8] ) , + // Port Write + .id_type_wp ( id_type_wp ), + .port_we ( rd_ctrl.port_we | x1_ctrl.port_we /*| x2_ctrl.port_we*/ ), + // Wave Register + .id_wmem_we ( id_wmem_we ) , //r_wave will be READ + // FLAG + .id_flag_used ( id_flag_used ) , // SELECCIONAR CORRECTAMENTE WR/MEM_WR and JUMPD + .flag_we ( rd_ctrl.flag_we | x1_ctrl.flag_we ) , + // PC JUMP + .id_jmp_i ( id_jmp_reg_used ) , + // ALU (00) Data in each Pipeline Stage + .x1_alu_dt_i ( x1_alu_dt ) , + .x2_alu_dt_i ( r_x1_alu_dt ) , + // DMEM (01) in each Pipeline Stage + .x2_dmem_dt_i (dmem_r_dt_i) , + // Imm Data in each Pipeline Stage + .rd_imm_dt_i ( r_id_imm_dt ) , + .x1_imm_dt_i ( r_rd_imm_dt ) , + .x2_imm_dt_i ( r_x1_imm_dt ) , + // Data Memory Write Enable + .reg_A_dt_o ( reg_A_fwd_dt ) , + .reg_D_dt_o ( reg_D_fwd_dt ) , + .bubble_id_o ( bubble_id ) , + .bubble_rd_o ( bubble_rd ) ); + +// REG BANK +///////////////////////////////////////////////// +qcore_reg_bank # ( + .LFSR (LFSR) , + .PMEM_AW (PMEM_AW) , + .REG_AW (REG_AW) +) reg_bank ( + .clk_i ( clk_i ) , + .halt_i ( halt ) , + .rst_ni ( rst_ni ) , + .clear_i ( restart_i ) , + .lfsr_cfg_i ( lfsr_cfg_i ) , + .reg_arith_i ( sreg_arith_i ) , + .reg_div_i ( sreg_div_i ) , + .reg_port_i ( sreg_port_dt_i ) , + .tproc_ext_i ( sreg_core_r_dt_i ) , + .status_i ( sreg_status_i ) , + .reg_cfg_o ( sreg_cfg_o ) , + .reg_ctrl_o ( sreg_ctrl_o ) , + .time_dt_i ( sreg_time_dt_i ) , + .wave_we_i ( x2_reg.r_wave_we ) , + .we_i ( x2_reg.we ) , + .w_addr_i ( x2_reg.addr ) , + .w_dt_i ( x2_reg_w_dt ) , + .wave_dt_i ( x2_wave_w_dt ) , + .rs_A_addr_i ( r_id_rs_A_addr ) , + .rs_D_addr_i ( r_id_rs_D_addr ) , + .rs_A_dt_o ( rs_A_dt ) , + .rs_D_dt_o ( rs_D_dt ) , + .sreg_dt_o ( sreg_core_w_dt_o ) , + .out_addr_o ( reg_addr ) , + .out_time_o ( reg_time ) , + .out_wreg_o ( reg_wave_dt ) , + .lfsr_o ( lfsr_o ) );// + +// ALU - 2 Inputs +///////////////////////////////////////////////// +AB_alu alu ( + // .clk_i ( clk_i ) , + .A_i ( x1_alu_in_A ) , + .B_i ( x1_alu_in_B ) , + .alu_op_i ( x1_ctrl.cfg_alu_op ) , + .Z_o ( x1_alu_fZ ) , + .C_o ( x1_alu_fC ) , + .S_o ( x1_alu_fS ) , + .alu_result_o ( x1_alu_dt ) ); + + +wire pc_stack_full; +// PC STACK +///////////////////////////////////////////////// +LIFO # ( + .WIDTH ( PMEM_AW ) , + .DEPTH ( 8 ) +) pc_stack_inst ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .data_i ( PC_prev ) , + .push ( id_call & fetch_en ) , + .pop ( id_ret & fetch_en ) , + .data_o ( pc_stack ) , + .full_o ( pc_stack_full ) ); + + + +/////////////////////////////////////////////////////////////////////////////// +// PIPELINE +/////////////////////////////////////////////////////////////////////////////// + +assign id_stage_keep = !fetch_en ; +assign rd_stage_keep = bubble_rd ; +assign rd_stage_zero = bubble_id & !bubble_rd ; +assign x1_stage_zero = bubble_rd ; + + +// DATA & ADDRESS PIPELINE +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + // CONTROL SIGNALS + r_id_pc_change <= 0 ; + rd_ctrl <= '{default:'0}; + x1_ctrl <= '{default:'0}; + x2_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + x1_reg <= '{default:'0}; + x2_reg <= '{default:'0}; + wr_reg <= '{default:'0}; + //Address Signals + r_id_imm_addr <= 0 ; + r_rd_imm_addr <= 0 ; +// r_rd_rsA0_addr <= 0 ; + r_rd_rsA1_addr <= 0 ; + r_id_rs_A_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + //Data Signals + r_id_imm_dt <= 0 ; + r_rd_imm_dt <= 0 ; + r_x1_imm_dt <= 0 ; + r_x1_alu_dt <= 0 ; + r_x1_port_dt <= 0 ; + alu_fZ_r <= 0 ; + alu_fS_r <= 0 ; + end else if (restart_i ) begin + r_id_pc_change <= 0 ; + rd_ctrl <= '{default:'0}; + x1_ctrl <= '{default:'0}; + x2_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + x1_reg <= '{default:'0}; + x2_reg <= '{default:'0}; + wr_reg <= '{default:'0}; + r_id_imm_addr <= 0 ; + r_rd_imm_addr <= 0 ; +// r_rd_rsA0_addr <= 0 ; + r_rd_rsA1_addr <= 0 ; + r_id_rs_A_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + r_id_imm_dt <= 0 ; + r_rd_imm_dt <= 0 ; + r_x1_imm_dt <= 0 ; + r_x1_alu_dt <= 0 ; + r_x1_port_dt <= 0 ; + alu_fZ_r <= 0 ; + alu_fS_r <= 0 ; + r_x1_port_w_addr <= 0 ; + end else begin + if (~halt) begin + + ///////////////////////////////////////////////////////// + // STAGE > READ + if ( rd_stage_zero ) begin + rd_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + r_id_pc_change <= 1'b0; + r_id_imm_dt <= '{default:'0}; + r_id_imm_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + r_id_rs_A_addr <= '{default:'0}; + end else if ( rd_stage_keep ) begin + rd_ctrl <= rd_ctrl; + rd_reg <= rd_reg; + r_id_pc_change <= r_id_pc_change; + r_id_imm_dt <= r_id_imm_dt; + r_id_imm_addr <= r_id_imm_addr; + r_id_rs_D_addr <= r_id_rs_D_addr; + r_id_rs_A_addr <= r_id_rs_A_addr; + end else begin + //Control Signals + rd_ctrl <= id_ctrl ; + rd_reg <= id_reg ; + r_id_pc_change <= id_pc_change ; + //Data Signals + r_id_imm_dt <= id_imm_dt ; + r_id_imm_addr <= id_imm_addr ; + r_id_rs_D_addr <= id_rs_D_addr ; + r_id_rs_A_addr <= id_rs_A_addr; + end + + ///////////////////////////////////////////////////////// + // STAGE > EXECUTE 1 + if ( x1_stage_zero ) begin + x1_ctrl <= '{default:'0}; + x1_reg <= '{default:'0}; + r_rd_imm_dt <= '{default:'0}; + r_rd_imm_addr <= '{default:'0}; + r_rd_rsA1_addr <= '{default:'0}; + end else begin + x1_ctrl <= rd_ctrl ; + x1_reg <= rd_reg ; + r_rd_imm_dt <= r_id_imm_dt ; + r_rd_imm_addr <= r_id_imm_addr ; + r_rd_rsA1_addr <= r_id_rs_A_addr[1] ; + end + + ///////////////////////////////////////////////////////// + // STAGE > EXECUTE 2 + //Control Signals + x2_ctrl <= x1_ctrl ; + x2_reg <= x1_reg ; + //Data Signals + r_x1_imm_dt <= r_rd_imm_dt ; + r_x1_alu_dt <= x1_alu_dt ; + r_x1_port_dt <= x1_rsA0_dt ; + r_x1_port_w_addr <= x1_port_w_addr ; + if (x1_ctrl.flag_we) begin + alu_fZ_r <= x1_alu_fZ ; + alu_fS_r <= x1_alu_fS ; + end + + ///////////////////////////////////////////////////////// + // STAGE > WRITE + //Control Signals + wr_reg <= x2_reg ; + + end //(~HALT) + end //NotRST +end //ALWAYS + +///////////////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +///////////////////////////////////////////////////////////////////////////////////////// + +// PROGRAM MEMORY +assign pmem_en_o = fetch_en | r_mem_rst; +assign pmem_addr_o = PC_curr ; // Disable next instruction with pc_jump + +// DATA MEMORY +assign dmem_we_o = halt ? 0 : x1_ctrl.dmem_we; +assign dmem_addr_o = x1_mem_addr ; +assign dmem_w_dt_o = x1_mem_w_dt ; + +// WAVE MEMORY +assign wmem_we_o = halt ? 0 : x1_ctrl.wmem_we; +assign wmem_addr_o = x1_wave_addr ; +assign wmem_w_dt_o = reg_wave_dt ; + +// PERIPH OUT +// assign = <1-bit_select> ? : ; +assign usr_en_o = halt ? 0 : x1_ctrl.usr_ctrl[8] ; +assign usr_ctrl_o = halt ? 0 : x1_ctrl.usr_ctrl[7:0] ; +assign usr_dt_a_o = x1_rsD0_dt ; +assign usr_dt_b_o = x1_ctrl.cfg_dt_imm ? r_rd_imm_dt : x1_rsD1_dt ; +assign usr_dt_c_o = x1_rsA0_dt ; +assign usr_dt_d_o = x1_rsA1_dt; + +// PORT OUTPUT +assign port_we_o = halt ? 0 : x2_ctrl.port_we ; +assign port_re_o = halt ? 0 : x2_reg.port_re ; + +assign port_o.p_time = x2_ctrl.cfg_port_time ? r_x1_imm_dt : reg_time; +assign port_o.p_type = x2_ctrl.cfg_port_type ; +assign port_o.p_addr = r_x1_port_w_addr ; +assign port_o.p_data = x2_port_w_dt ; + +// DEBUG +assign core_do [31:24] = {restart_i, stall, flush, id_flag_we, alu_fZ_r, alu_fS_r, x2_ctrl.port_we, x2_reg.port_re}; +assign core_do [23:16] = {id_type_ext_ctrl, id_type_int_ctrl, id_type_cfg, id_type_br, id_type_wr, id_type_wm, id_type_wp, pc_stack_full } ; +assign core_do [15:8] = r_x1_alu_dt[7:0] ; +assign core_do [7:0] = port_o.p_time[7:0] ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv b/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv new file mode 100644 index 000000000..70e5e3023 --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv @@ -0,0 +1,326 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +DATA HAZARD +Data hazards are caused when the execution of one instruction depends on the results of a previous instruction +that is still being processed in the pipeline. + +-DATA FORWARDING +The Data Forwaring occurs when Data from different pipeline stages should be used in the read stage (RD) of the Pipeline. + +This block compares the Source of the instruction in RD Stage with the Destination address of all the instruction in the pipeline +to see if the Data used in the current instruction is going to be written and is in the Pipeline + +-STALLING +The Stalling occurs when Data still not processed should be used in the read stage (RD) of the Pipeline. +This block compares the Source of the instruction in RD Stage with all the possible incomes of data +to see if the Data used in the current instruction is being processed. + +Possible Sources are > +-A) DSW_REG +-B) DMEM +-C) R_WAVE +-D) CORE_R_DT +-E) IN_PORT_DT +-F) STATUS +-G) time_usr +-H) s_addr +-I) Flags ( -if() ) +-J) Random Number + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + + +module qcore_ctrl_hazard ( + input wire clk_i , + input wire rst_ni , + input wire halt_i , + input wire [5:0] rs_A_addr_i [2] , + input wire [31:0] rs_A_dt_i [2] , + input wire [6:0] rs_D_addr_i [2] , + input wire [31:0] rs_D_dt_i [2] , + // Register + input CTRL_REG id_reg_i , + input CTRL_REG rd_reg_i , + input CTRL_REG x1_reg_i , + input CTRL_REG x2_reg_i , + input CTRL_REG wr_reg_i , + // Peripheral + input wire rd_periph_use , + input wire x1_periph_use , + input wire x2_periph_use , + // Wave Register + input wire id_wmem_we , + // Port Write + input wire id_type_wp , + input wire port_we , + // Flag + input wire id_flag_used , + input wire flag_we , + // JUMP + input wire id_jmp_i , + // ALU (00) Data in each Pipeline Stage + input wire [31:0] x1_alu_dt_i , + input wire [31:0] x2_alu_dt_i , + // DMEM (01) in each Pipeline Stage + input wire [31:0] x2_dmem_dt_i , + // IMM Data (11) in each Pipeline Stage + input wire [31:0] rd_imm_dt_i , + input wire [31:0] x1_imm_dt_i , + input wire [31:0] x2_imm_dt_i , + // New Data to avoid Hazard + output wire [31:0] reg_A_dt_o [2] , + output wire [31:0] reg_D_dt_o [2] , + // Bubble in RD and Wait for DATA + output wire bubble_id_o , + output wire bubble_rd_o ); + + +// DATA HAZARD + +// STALLING +reg stall_id_w ; // Give time to update R_WAVE +reg stall_id_wp ; // Give time to process PORT_WR +reg stall_id_f ; // Give time to update FLAG +reg stall_id_j ; // Give time to update S_ADDR when JUMP +reg stall_id_rand ; // Gives time to update rand number + +reg stall_rd_core_rdt ; // Gives time to update core_r_dt after Peripheral or S_CTRL +reg stall_rd_port ; // Gives time to update PORT_L & PORT_H after DPORT_RD +reg stall_rd_status ; // Gives time to update STATUS after Peripheral or S_CTRL +reg stall_rd_stime ; // Gives time to update s_out_time after TIME instruction +reg [ 1:0] w_stall_D_rd ; // Gives time to update R_WAVE when REG_WR r_wave +reg [ 1:0] d_stall_D_rd ; // Gives time to READ MEMORY +reg [ 1:0] stall_A_rd ; // Gives time to READ MEMORY + +// DATA FORWARDING +reg [ 1:0] fwd_D_X1, fwd_D_X2 ; +reg [31:0] reg_D_nxt [2] ; + +// ADDRESS FORWARDING +reg [ 1:0] fwd_A_X1, fwd_A_X2 ; +reg [31:0] reg_A_nxt [2] ; + +reg [1:0] rfrom_rand_r, rfrom_core_r, rfrom_port_r, rfrom_status_r, rfrom_stime_r; + + +assign rfrom_rand = |rfrom_rand_r ; // READ FROM S_RAND (s1) +assign rfrom_core_rdt = |rfrom_core_r ; // READ FROM CORE_R_DT(s6, s7) +assign rfrom_port = |rfrom_port_r ; // READ FROM IN_PORT (s8, s9)) +assign rfrom_status = |rfrom_status_r ; // READ FROM STATUS (s10) +assign rfrom_stime = |rfrom_stime_r ; // READ FROM TIME_USR (s11) +assign port_re = rd_reg_i.port_re | x1_reg_i.port_re | x2_reg_i.port_re ; //PORT READ COMMAND + +// WREG IS BEING UPDATED +assign wto_r_wave = rd_reg_i.r_wave_we | x1_reg_i.r_wave_we | x2_reg_i.r_wave_we ; +assign wto_wreg = rd_reg_i.addr[6:5] == 2'b10 | x1_reg_i.addr[6:5] == 2'b10 | x2_reg_i.addr[6:5] == 2'b10; +// PERIPHERAL IS BEING UPDATED +assign wto_qp = rd_periph_use | x1_periph_use | x2_periph_use; +// SFR CFG OR CTRL IS BEING UPDATED +assign wto_s_cfg = (rd_reg_i.addr == 7'b0000010) | (x1_reg_i.addr == 7'b0000010) | (x2_reg_i.addr == 7'b0000010) | (wr_reg_i.addr == 7'b0000010) ; +// SFR S_ADDR IS BEING UPDATED +assign wto_s_addr = (rd_reg_i.addr == 7'b00_01111) | (x1_reg_i.addr == 7'b00_01111) | (x2_reg_i.addr == 7'b00_01111) ; +// SFR S_RAND RAND IS BEING UPDATED +assign wto_s_rand = (rd_reg_i.addr == 7'b00_00001) | (x1_reg_i.addr == 7'b00_00001) | (x2_reg_i.addr == 7'b00_00001) ; + + +// (A and B) READ dreg, sreg, wreg or DMEM +/////////////////////////////////////////////////////////////////////////////// +// REG_WR after REG_WR +genvar ind_D; +generate + for (ind_D=0; ind_D <2 ; ind_D=ind_D+1) begin + // Check for read + always_comb begin + rfrom_rand_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_00001) ; //sfr(s1) _00_000001 + rfrom_status_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_01010) ; //sfr(s10) _00_001010 + rfrom_stime_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_01011) ; //sfr(s11) _00_001011 + rfrom_core_r[ind_D] = (rs_D_addr_i[ind_D][6:1] == 6'b00_0011) ; //sfr _00_ Address 6 or 7 + rfrom_port_r[ind_D] = (rs_D_addr_i[ind_D][6:1] == 6'b00_0100) ; //sfr _00_ Address 8 or 9 + end + // 1- Use DataRegister after REG_WR to Register + always_comb begin + reg_D_nxt[ind_D] = rs_D_dt_i[ind_D]; + d_stall_D_rd[ind_D] = 1'b0; + fwd_D_X1[ind_D] = ( (rs_D_addr_i[ind_D] == x1_reg_i.addr ) & x1_reg_i.we ); //Data is in X1 STage + fwd_D_X2[ind_D] = ( (rs_D_addr_i[ind_D] == x2_reg_i.addr ) & x2_reg_i.we ); //Data is in X2 STage + if ( fwd_D_X1[ind_D] ) //Data is in X1 STage + unique case (x1_reg_i.src) + 2'b00 : reg_D_nxt[ind_D] = x1_alu_dt_i ; // Data Comes from ALU + 2'b01 : d_stall_D_rd[ind_D] = 1'b1 ; // Data Comes from DATA MEMORY + 2'b11 : reg_D_nxt[ind_D] = x1_imm_dt_i ; // Data Comes from Imm + default:; + endcase + else if ( fwd_D_X2[ind_D] ) //Data is in X2 STage + unique case (x2_reg_i.src) + 2'b00 : reg_D_nxt[ind_D] = x2_alu_dt_i ; // Data Comes from ALU + 2'b01 : reg_D_nxt[ind_D] = x2_dmem_dt_i ; // Data Comes from DATA MEMORY + 2'b11 : reg_D_nxt[ind_D] = x2_imm_dt_i ; // Data Comes from Imm + default:; + endcase + end // always_comb + // 2) Use WREG after REG_WR r_wave + always_comb begin + w_stall_D_rd[ind_D] = rs_D_addr_i[ind_D][6:5] == 2'b10 & (wto_r_wave) ; //WREG Read and modified + end + end //for +endgenerate + +genvar ind_A; +generate + for (ind_A=0; ind_A <2 ; ind_A=ind_A+1) begin + // 1-ADDRESS) REG_WR from AddresRegister after REG_WR to Register + always_comb begin + reg_A_nxt[ind_A] = rs_A_dt_i[ind_A]; + stall_A_rd[ind_A] = 1'b0; + fwd_A_X1[ind_A] = ( ( {1'b0,rs_A_addr_i[ind_A]} == x1_reg_i.addr ) & x1_reg_i.we ); //Address is in X1 STage + fwd_A_X2[ind_A] = ( ( {1'b0,rs_A_addr_i[ind_A]} == x2_reg_i.addr ) & x2_reg_i.we ); //Address is in X2 STage + if ( fwd_A_X1[ind_A] ) //Address is in X1 STage + unique case (x1_reg_i.src) + 2'b00 : reg_A_nxt[ind_A] = x1_alu_dt_i ; // Address Comes from ALU + 2'b01 : stall_A_rd[ind_A] = 1'b1 ; // Address Comes from DATA MEMORY + 2'b11 : reg_A_nxt[ind_A] = x1_imm_dt_i ; // Address Comes from Imm + default:; + endcase + else if ( fwd_A_X2[ind_A] ) //Address is in X2 STage + unique case (x2_reg_i.src) + 2'b00 : reg_A_nxt[ind_A] = x2_alu_dt_i ; // Address Comes from ALU + 2'b01 : reg_A_nxt[ind_A] = x2_dmem_dt_i ; // Address Comes from DATA MEMORY + 2'b11 : reg_A_nxt[ind_A] = x2_imm_dt_i ; // Address Comes from Imm + default:; + endcase + end // always_comb + end //for +endgenerate + +// (C) READ r_wave +/////////////////////////////////////////////////////////////////////////////// +// 3) WMEM_WR after REG_WR r_wave or wreg wr +always_comb begin + stall_id_w = 1'b0 ; + if ( id_wmem_we ) + if ( wto_r_wave | wto_wreg ) + stall_id_w = 1'b1 ; +end + +always_comb begin + stall_id_wp = 1'b0 ; + if ( id_type_wp ) + if ( port_we ) + stall_id_wp = 1'b1 ; +end + + + +// (D) CORE_R_DT +/////////////////////////////////////////////////////////////////////////////// +// 4) CORE_R_DT read after S_CONF Write +always_comb begin + stall_rd_core_rdt = 1'b0 ; + if (rfrom_core_rdt) + if ( wto_qp | wto_s_cfg) + stall_rd_core_rdt = 1'b1 ; +end + +// (E) IN_PORT +/////////////////////////////////////////////////////////////////////////////// +// 5) IN_PORT read after DPORT_RD +always_comb begin + stall_rd_port = 1'b0 ; + if ( rfrom_port ) + if ( port_re ) + stall_rd_port = 1'b1 ; +end + +// (F) STATUS +/////////////////////////////////////////////////////////////////////////////// +// 6) STATUS read after S_CTRL Write or Write to Peripheral +always_comb begin + stall_rd_status = 1'b0 ; + if (rfrom_status ) + if ( wto_qp | wto_s_cfg) + stall_rd_status = 1'b1 ; +end + +// (G) TIME_USR +/////////////////////////////////////////////////////////////////////////////// +// 7) TIME_USR read after Peripheral (TIME inc_ref is Peripheral) +always_comb begin + stall_rd_stime = 1'b0 ; + if ( rfrom_stime ) + if ( wto_qp ) + stall_rd_stime = 1'b1 ; +end + +// (H) S_ADDR +/////////////////////////////////////////////////////////////////////////////// +// 8) JUMP after WRITE_REG s_addr >>> STALL +always_comb begin + stall_id_j = 1'b0 ; + if (wto_s_addr ) + if (id_jmp_i ) + stall_id_j = 1'b1 ; +end + +// (I) Flag Used +/////////////////////////////////////////////////////////////////////////////// +// 9) -if() after -uf >>> STALL +// 10) -if() after s_cfg >>> STALL +// 11) -if() after FLAG set or clr + +always_comb begin + stall_id_f = 1'b0 ; + if (id_flag_used) begin // FLAG IS USED + if ( flag_we ) // a) ALU Flag is being UPDATED + stall_id_f = 1'b1 ; + else if ( wto_s_cfg ) // b) SRC Flag could be Updated or clear + stall_id_f = 1'b1 ; + else if ( wto_qp ) // c) Peripheral was used + stall_id_f = 1'b1 ; + end +end + +// (J) RAND Used +/////////////////////////////////////////////////////////////////////////////// +// 12) RAND Read after READ >>> STALL +// 13) RAND Read after WRITE >>> STALL +always_comb begin + stall_id_rand = 1'b0 ; + if (wto_s_rand | rfrom_rand ) + stall_id_rand = 1'b1 ; +end + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +// Data Forwarding REGISTER +reg [31:0] reg_A [2] ; +reg [31:0] reg_D [2] ; + +//Register DATA & ADDRESS OUT +always_ff @ (posedge clk_i, negedge rst_ni) + if (!rst_ni) begin + reg_A <= '{default:'0}; + reg_D <= '{default:'0}; + end else begin + if (~halt_i) begin + reg_A <= reg_A_nxt ; + reg_D <= reg_D_nxt ; + end + end + +assign reg_A_dt_o = reg_A; +assign reg_D_dt_o = reg_D; +assign bubble_id_o = stall_id_j | stall_id_f | stall_id_w | stall_id_wp | stall_id_rand; +assign bubble_rd_o = |stall_A_rd | |d_stall_D_rd | |w_stall_D_rd | stall_rd_stime | stall_rd_status | stall_rd_port | stall_rd_core_rdt ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qcore_mem.v b/firmware/ip/qick_processor/src/qcore_mem.v new file mode 100644 index 000000000..b39024870 --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_mem.v @@ -0,0 +1,126 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + + +module qcore_mem # ( + parameter PMEM_AW = 16 , + parameter DMEM_AW = 16 , + parameter WMEM_AW = 16 +)( + // CLK & RST. + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + input wire [1: 0] ps_sel_i , + input wire ps_we_i , + input wire [15: 0] ps_addr_i , + input wire [167:0] ps_w_dt_i , + output wire [167:0] ps_r_dt_o , +// PROGRAM MEMORY + input wire c_pmem_en_i , + input wire [PMEM_AW-1:0] c_pmem_addr_i , + output wire [71:0] c_pmem_r_dt_o , +// DATA MEMORY + input wire c_dmem_we_i , + input wire [DMEM_AW-1:0] c_dmem_addr_i , + input wire [31:0] c_dmem_w_dt_i , + output wire [31:0] c_dmem_r_dt_o , +// WAVE MEMORY + input wire c_wmem_we_i , + input wire [WMEM_AW-1:0] c_wmem_addr_i , + input wire [167:0] c_wmem_w_dt_i , + output wire [167:0] c_wmem_r_dt_o ); + + +wire [71 :0] ps_P_r_dt; +wire [31 :0] ps_D_r_dt; +wire [167:0] ps_W_r_dt; + +// Memory Control +wire ext_P_mem_en, ext_D_mem_en, ext_W_mem_en; +wire ext_P_mem_we, ext_D_mem_we, ext_W_mem_we; + +assign ext_P_mem_en = (ps_sel_i== 2'b01) ; +assign ext_D_mem_en = (ps_sel_i== 2'b10) ; +assign ext_W_mem_en = (ps_sel_i== 2'b11) ; + +assign ext_P_mem_we = ext_P_mem_en & ps_we_i ; +assign ext_D_mem_we = ext_D_mem_en & ps_we_i ; +assign ext_W_mem_we = ext_W_mem_en & ps_we_i ; + +assign ps_r_dt_o = (ps_sel_i == 2'b01)? { 96'd0, ps_P_r_dt } : + (ps_sel_i == 2'b10)? { 136'd0, ps_D_r_dt }: + (ps_sel_i == 2'b11)? ps_W_r_dt : + 0; + +// PROGRAM MEMORY +/////////////////////////////////////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( PMEM_AW ), + .MEM_DW ( 72 ), + .RAM_OUT ("NO_REGISTERED" ) +) P_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( c_pmem_en_i ) , + .we_a_i ( 1'b0 ) , + .addr_a_i ( c_pmem_addr_i ) , + .dt_a_i ( 72'd0 ) , + .dt_a_o ( c_pmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_P_mem_en ) , + .we_b_i ( ext_P_mem_we ) , + .addr_b_i ( ps_addr_i[PMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i[71:0] ) , + .dt_b_o ( ps_P_r_dt ) ); +// DATA MEMORY +/////////////////////////////////////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( DMEM_AW ), + .MEM_DW ( 32 ), + .RAM_OUT ("NO_REGISTERED" ) +) D_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( 1'b1 ) , + .we_a_i ( c_dmem_we_i ) , + .addr_a_i ( c_dmem_addr_i ) , + .dt_a_i ( c_dmem_w_dt_i ) , + .dt_a_o ( c_dmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_D_mem_en ) , + .we_b_i ( ext_D_mem_we ) , + .addr_b_i ( ps_addr_i[DMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i[31:0] ) , + .dt_b_o ( ps_D_r_dt ) ); +// WAVE MEMORY +///////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( WMEM_AW ), + .MEM_DW ( 168 ), + .RAM_OUT ("NO_REGISTERED" ) +) W_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( 1'b1 ) , + .we_a_i ( c_wmem_we_i ) , + .addr_a_i ( c_wmem_addr_i ) , + .dt_a_i ( c_wmem_w_dt_i ) , + .dt_a_o ( c_wmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_W_mem_en ) , + .we_b_i ( ext_W_mem_we ) , + .addr_b_i ( ps_addr_i[WMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i ) , + .dt_b_o ( ps_W_r_dt ) ); + + +endmodule diff --git a/firmware/ip/qick_processor/src/qcore_reg_bank.sv b/firmware/ip/qick_processor/src/qcore_reg_bank.sv new file mode 100644 index 000000000..902b38a30 --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_reg_bank.sv @@ -0,0 +1,256 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qcore_reg_bank # ( + parameter LFSR = 1 , + parameter PMEM_AW = 8 , + parameter REG_AW = 4 +)( + input wire clk_i , + input wire halt_i , + input wire rst_ni , + input wire clear_i , + input wire [1:0] lfsr_cfg_i , + input wire [31:0] reg_arith_i , + input wire [31:0] reg_div_i [2] , + input wire [31:0] reg_port_i [2] , + input wire [31:0] tproc_ext_i[2] , + input wire [31:0] time_dt_i , + input wire [167:0] wave_dt_i , + input wire [31:0] status_i , + output wire [7:0] reg_cfg_o , + output wire [7:0] reg_ctrl_o , + input wire wave_we_i , + input wire we_i , + input wire [ 6 : 0 ] w_addr_i , + input wire [31:0] w_dt_i , + input wire [ 5 : 0 ] rs_A_addr_i[2] , + input wire [ 6 : 0 ] rs_D_addr_i[2] , + output wire [31:0] rs_D_dt_o [2] , + output wire [31:0] rs_A_dt_o [2] , + output wire [31:0] sreg_dt_o [2] , + output wire [PMEM_AW-1:0] out_addr_o , + output wire [31:0] out_time_o , + output wire [167:0] out_wreg_o , + output wire [31:0] lfsr_o ); + +/* +The memory is a group of REGs (ZERO, RAND, DIV, MULT, REGBANK), and connected with a generate +Input has 8 Bits> +XX-000000 2 Page and 64 Address +00-Special Registers (32 Bits) +01-User Register (32 Bits) +10-Wave Parameter Register (32 Bits) +11-RFU +*/ + +/////////////////////////////////////////////////////////////////////////////// +// PARAMETERS +localparam REG_QTY = (2 ** (REG_AW) ) ; + + +/////////////////////////////////////////////////////////////////////////////// +// SIGNALS +//LFSR +wire [31:0] lfsr_reg; +reg lfsr_en; +wire lfsr_sel, lfsr_we, lfsr_step; + +/////////////////////////////////////////////////////////////////////////////// +// SPECIAL REGISTER BANK 00_00000 to 00_11111 +reg [31:0] sreg_dt [4]; // Four SFR +wire sreg_en, sreg_we; + +reg [7:0] sreg_cfg_dt ; // Configuration Register(Lower 16Bit of s2) +reg [7:0] sreg_ctrl_dt ; // Control Register (Upper 16Bit of s2) +wire sreg_cfg_en, sreg_cfg_we; + +assign sreg_en = w_addr_i[6:2] == 5'b00_011 ; //Register 12 to 15 selected +assign sreg_we = we_i & sreg_en ; +assign sreg_cfg_en = w_addr_i == 7'b00_00010 ; //Register 2 Selected +assign sreg_cfg_we = we_i & sreg_cfg_en; + +/////////////////////////////////////////////////////////////////////////////// +// General Data Registers 01_00000 to 01_11111 +reg [31:0] dreg_32_dt [REG_QTY]; +wire [REG_AW-1:0] dreg_32_addr ; +wire dreg_32_en, dreg_32_we; + +assign dreg_32_addr = w_addr_i[REG_AW-1:0] ; +assign dreg_32_en = w_addr_i[6:5] == 2'b01; //~w_addr_i[6] & ~w_addr_i[5] ; +assign dreg_32_we = we_i & dreg_32_en ; + +/////////////////////////////////////////////////////////////////////////////// +// Wave Registers 10_00000 to 10_0110 +reg [31:0] wreg_32_dt [6] ; +wire [ 2:0] wreg_32_addr ; +wire wreg_32_en, wreg_32_we; +assign wreg_32_addr = w_addr_i[2:0] ; +assign wreg_32_en = w_addr_i[6:5] == 2'b10; //~w_addr_i[6] & w_addr_i[5] ; +assign wreg_32_we = we_i & wreg_32_en; + + + + +/////////////////////////////////////////////////////////////////////////////// +// DATA, WAVE and SFR REGISTER BANK +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + dreg_32_dt = '{default:'0}; + wreg_32_dt = '{default:'0}; + sreg_dt = '{default:'0}; + sreg_cfg_dt = 0; + sreg_ctrl_dt = 0; + end else if (clear_i) begin + dreg_32_dt = '{default:'0}; + wreg_32_dt = '{default:'0}; + sreg_dt = '{default:'0}; + sreg_cfg_dt = 0; + sreg_ctrl_dt = 0; + end else begin + if (~halt_i) begin + if (dreg_32_we) + dreg_32_dt [dreg_32_addr] = w_dt_i; + if (wreg_32_we) + wreg_32_dt [wreg_32_addr] = w_dt_i; + else if (wave_we_i) begin + wreg_32_dt [5] = wave_dt_i[167:152]; + wreg_32_dt [4] = wave_dt_i[151:120]; + wreg_32_dt [3] = wave_dt_i[119: 88]; + wreg_32_dt [2] = wave_dt_i[ 87: 64]; + wreg_32_dt [1] = wave_dt_i[ 63: 32]; + wreg_32_dt [0] = wave_dt_i[ 31: 0]; + end + if (sreg_we) + sreg_dt [w_addr_i[1:0]] = w_dt_i; + if (sreg_cfg_we) begin + sreg_cfg_dt = w_dt_i[7:0]; + sreg_ctrl_dt = w_dt_i[23:16]; + end else if (|sreg_ctrl_dt) + sreg_ctrl_dt = 8'd0; + + // Not Used Register to GND + sreg_dt [3][31:16] = '{default:'0}; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +// LFSR +// cfg_i 00_FreeRunning 10_Change WHen Read 11_Change when writes to 0 +generate + if (LFSR == 1) begin : LFSR_YES + (* ASYNC_REG = "TRUE" *) logic [1:0] lfsr_cfg_cdc, lfsr_cfg_sync; + always_ff @ (posedge clk_i) begin + lfsr_cfg_cdc <= lfsr_cfg_i; + lfsr_cfg_sync <= lfsr_cfg_cdc; + end + always_comb + unique case (lfsr_cfg_sync) + 2'b00 : lfsr_en = 1'b0 ; + 2'b01 : lfsr_en = 1'b1 ; + 2'b10 : lfsr_en = lfsr_sel ; + 2'b11 : lfsr_en = lfsr_step ; + endcase + assign lfsr_sel = (rs_D_addr_i[0] == 7'b0000001) ; + assign lfsr_we = we_i & (w_addr_i == 7'b0000001) ; + assign lfsr_step = we_i & (w_addr_i == 7'b0000000) ; + LFSR lfsr ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .en_i ( lfsr_en ) , + .load_we_i ( lfsr_we ) , + .load_dt_i ( w_dt_i ) , + .lfsr_dt_o ( lfsr_reg ) ); + end else begin : LFSR_NO + assign lfsr_sel = 0; + assign lfsr_we = 0; + assign lfsr_step = 0; + assign lfsr_reg = 0; + end +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// SFR ASSEMBLY +wire [31:0] sreg_32_dt [16] ; + +assign sreg_32_dt[0] = 0 ; +assign sreg_32_dt[1] = lfsr_reg ; +assign sreg_32_dt[2] = sreg_cfg_dt ; +assign sreg_32_dt[3] = reg_arith_i ; +assign sreg_32_dt[4] = reg_div_i[0] ; +assign sreg_32_dt[5] = reg_div_i[1] ; +assign sreg_32_dt[6] = tproc_ext_i [0] ; +assign sreg_32_dt[7] = tproc_ext_i [1] ; +assign sreg_32_dt[8] = reg_port_i [0] ; +assign sreg_32_dt[9] = reg_port_i [1] ; +assign sreg_32_dt[10] = status_i ; +assign sreg_32_dt[11] = time_dt_i ; +assign sreg_32_dt[12] = sreg_dt [0] ; // CORE_W_DT1 +assign sreg_32_dt[13] = sreg_dt [1] ; // CORE_W_DT2 +assign sreg_32_dt[14] = sreg_dt [2] ; // OUT TIME +assign sreg_32_dt[15] = sreg_dt [3] ; // PC_NXT_ADDR_REG + + +/////////////////////////////////////////////////////////////////////////////// +// out MUX for rsA[0] and rsA[1] +wire [31:0] data_A [2]; + +genvar ind_A; +generate + for (ind_A=0; ind_A <2 ; ind_A=ind_A+1) begin + assign data_A[ind_A] = rs_A_addr_i[ind_A][5] ? dreg_32_dt[rs_A_addr_i[ind_A][REG_AW-1:0]] : sreg_32_dt[rs_A_addr_i[ind_A][3:0]] ; + end +endgenerate + +reg [31:0] data_D [2] ; + +/////////////////////////////////////////////////////////////////////////////// +// out MUX for rsD[0] and rsD[1] +genvar ind_D; +generate + for (ind_D=0; ind_D <2 ; ind_D=ind_D+1) begin + always_comb begin + case (rs_D_addr_i[ind_D][6:5]) + 2'b00 : data_D[ind_D] = sreg_32_dt[ rs_D_addr_i[ind_D][3:0] ]; // 16 Registers + 2'b01 : data_D[ind_D] = dreg_32_dt[ rs_D_addr_i[ind_D][REG_AW-1:0] ]; + 2'b10 : data_D[ind_D] = wreg_32_dt[ rs_D_addr_i[ind_D][2:0] ]; // 6 Registers + 2'b11 : data_D[ind_D] = 0 ; + endcase + end + end +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUT ASSIGNMENT +assign rs_A_dt_o = data_A ; +assign rs_D_dt_o = data_D ; + +assign lfsr_o = lfsr_reg ; +assign reg_cfg_o = sreg_cfg_dt ; +assign reg_ctrl_o = sreg_ctrl_dt ; +assign sreg_dt_o[0] = sreg_32_dt[12] ; +assign sreg_dt_o[1] = sreg_32_dt[13] ; +assign out_time_o = sreg_32_dt[14] ; +assign out_addr_o = sreg_32_dt[15] [PMEM_AW-1:0]; + +assign out_wreg_o[167:152] = wreg_32_dt[5][15:0]; +assign out_wreg_o[151:120] = wreg_32_dt[4] ; +assign out_wreg_o[119: 88] = wreg_32_dt[3] ; +assign out_wreg_o[ 87: 64] = wreg_32_dt[2][23:0] ; +assign out_wreg_o[ 63: 32] = wreg_32_dt[1] ; +assign out_wreg_o[ 31: 0] = wreg_32_dt[0] ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qick_processor.sv b/firmware/ip/qick_processor/src/qick_processor.sv new file mode 100644 index 000000000..a21d1971d --- /dev/null +++ b/firmware/ip/qick_processor/src/qick_processor.sv @@ -0,0 +1,913 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2024 +// Version : 4 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qick_processor # ( + parameter DEBUG = 0 , + parameter DUAL_CORE = 0 , + parameter LFSR = 0 , + parameter DIVIDER = 1 , + parameter ARITH = 1 , + parameter TIME_READ = 1 , + parameter FIFO_DEPTH = 8 , + parameter PMEM_AW = 8 , + parameter DMEM_AW = 8 , + parameter WMEM_AW = 8 , + parameter REG_AW = 4 , + parameter IN_PORT_QTY = 1 , + parameter OUT_TRIG_QTY = 1 , + parameter OUT_DPORT_QTY = 1 , + parameter OUT_DPORT_DW = 4 , + parameter OUT_WPORT_QTY = 1 +)( +// Time, Core and AXI CLK & RST. + input wire t_clk_i , + input wire t_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , +// External Control + input wire ext_flag_i , + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_init_i , + input wire time_updt_i , + input wire [31:0] time_updt_dt_i , + output wire [47:0] time_abs_o , +// External PERIPHERALS + output wire [31:0] periph_a_dt_o , + output wire [31:0] periph_b_dt_o , + output wire [31:0] periph_c_dt_o , + output wire [31:0] periph_d_dt_o , + output wire [4 :0] periph_op_o , +//QNET_DT + output wire qnet_en_o , + input wire qnet_rdy_i , + input wire [31:0] qnet_dt_i [2] , + input wire qnet_vld_i , + input wire qnet_flag_i , +//QCOM_DT + output wire qcom_en_o , + input wire qcom_rdy_i , + input wire [31:0] qcom_dt_i [2] , + input wire qcom_vld_i , + input wire qcom_flag_i , +// QP1 + output wire qp1_en_o , + input wire qp1_rdy_i , + input wire [31:0] qp1_dt_i [2] , + input wire qp1_vld_i , + input wire qp1_flag_i , +// QP2 + output wire qp2_en_o , + input wire qp2_rdy_i , + input wire [31:0] qp2_dt_i [2] , + input wire qp2_vld_i , + +// DMA AXIS FOR READ AND WRITE MEMORY + input wire [255:0] s_dma_axis_tdata_i , + input wire s_dma_axis_tlast_i , + input wire s_dma_axis_tvalid_i , + output wire s_dma_axis_tready_o , + output wire [255:0] m_dma_axis_tdata_o , + output wire m_dma_axis_tlast_o , + output wire m_dma_axis_tvalid_o , + input wire m_dma_axis_tready_i , +// AXI-Lite DATA Slave I/F. + TYPE_IF_AXI_REG.slave IF_s_axireg , +// DATA INPUT INTERFACE + input wire port_tvalid_i[IN_PORT_QTY ] , + input wire [63:0] port_tdata_i [IN_PORT_QTY ] , +// TRIGGERS + output wire port_trig_o [OUT_TRIG_QTY] , +// DATA OUTPUT INTERFACE + output wire port_tvalid_o[OUT_DPORT_QTY] , + output wire [OUT_DPORT_DW-1:0] port_tdata_o [OUT_DPORT_QTY] , +// AXI Stream Master I/F. + output wire [167:0] m_axis_tdata [OUT_WPORT_QTY] , + output wire m_axis_tvalid [OUT_WPORT_QTY] , + input wire m_axis_tready [OUT_WPORT_QTY] , + +// DEBUG INTERFACE + input wire [ 3:0] dport_di , + output wire [31:0] ps_debug_do , + output wire [31:0] t_debug_do , + output wire [31:0] t_fifo_do , + output wire [31:0] c_time_usr_do , + output wire [31:0] c_debug_do , + output wire [31:0] c_time_ref_do , + output wire [31:0] c_proc_do , + output wire [31:0] c_port_do , + output wire [31:0] c_core_do ); + +// SIGNALS +/////////////////////////////////////////////////////////////////////////////// +// When signal start with t_ is in t_clk Domain +// When signal start with c_ is in c_clk Domain + +// TIME +wire [47:0] time_abs ; // Absolute Time Counter Value "out_abs_time" +reg [47:0] c_time_ref_dt ; // Reference time "ref_time" +wire [31:0] c_time_usr ; // User time "current_user_time" + +// AXI REGISTERS +wire [15:0] xreg_TPROC_CTRL , xreg_TPROC_CFG ; +wire [15:0] xreg_MEM_ADDR , xreg_MEM_LEN ; +wire [31:0] xreg_MEM_DT_I , xreg_MEM_DT_O ; +reg [31:0] xreg_TPROC_STATUS, xreg_TPROC_DEBUG ; +reg [31:0] xreg_TPROC_W_DT [2]; +wire [ 7:0] xreg_CORE_CFG; +wire [ 7:0] xreg_READ_SEL ; +reg [31:0] xreg_TPROC_R_DT [2]; + +// AXIS-INPUT +reg [63:0] in_port_dt_r [ IN_PORT_QTY ] ; // Data registerd from Input Port, Register with t_valid = 1 +wire [15:0] port_dt_new ; + +// CTRL Instruction ( TIME, FLAG, ARITH, DIV, NET, CUSTOM ) +wire [31:0] core_usr_a_dt, core_usr_b_dt, core_usr_c_dt, core_usr_d_dt ; +wire [ 4:0] core_usr_operation ; // 4 bits for internal 5 bits for external + +// Control +reg t_core_rst_prev_net; // NET Request to RESET the Processor and go to previous state + +///// DUAL CORE +reg [31:0] core1_w_dt [2]; + +// Memory Operations +wire [1:0] ext_core_sel; +wire [1:0] ext_mem_sel; +wire ext_mem_we; +wire [15:0] ext_mem_addr; +wire [167:0] ext_mem_w_dt; +wire [167:0] ext_mem_r_dt, ext_mem_r_0_dt, ext_mem_r_1_dt; + +// PERIPHERALS +wire div_rdy, arith_rdy; +wire [63:0] arith_result; +wire [31:0] div_remainder, div_quotient; +wire [31:0] core0_lfsr; +wire [31:0] core1_lfsr; + +// DEBUG SIGNALS +wire [31:0] axi_mem_ds ; +wire [31:0] core_r_d0 [2], core_r_d1 [2], core_r_d2[2], core_r_d3[2] ; +wire [31:0] core_ds ; + + +/////////////////////////////////////////////////////////////////////////////// +// CONTROL Signals +/////////////////////////////////////////////////////////////////////////////// + +wire [2:0] time_st_ds, core_st_ds; +wire [6:0] ctrl_t_ds, ctrl_c_ds; +qproc_ctrl # ( + .TIME_READ ( TIME_READ ) +) QPROC_CTRL ( + .t_clk_i ( t_clk_i ), + .t_rst_ni ( t_rst_ni ), + .c_clk_i ( c_clk_i ), + .c_rst_ni ( c_rst_ni ), + .proc_start_i ( proc_start_i ), + .proc_stop_i ( proc_stop_i ), + .core_start_i ( core_start_i ), + .core_stop_i ( core_stop_i ), + .time_rst_i ( time_rst_i ), + .time_updt_i ( time_updt_i ), + .time_updt_dt_i ( time_updt_dt_i ), + .int_time_en ( int_time_pen ), + .int_time_cmd ( core_usr_operation[3:0] ), + .int_time_dt ( core_usr_b_dt ), + .PS_TPROC_CTRL ( xreg_TPROC_CTRL ), + .PS_TPROC_CFG ( xreg_TPROC_CFG[11:9]), + .xreg_TPROC_W_DT ( xreg_TPROC_W_DT[0] ), + .all_fifo_full_i ( all_fifo_full ), + .some_fifo_full_i( some_fifo_full ), + .core_rst_o ( core_rst ), + .core_en_o ( core_en ), + .time_rst_o ( time_rst ), + .time_en_o ( time_en ), + .time_abs_o ( time_abs ), + .c_time_ref_o ( c_time_ref_dt ), + .c_time_usr_o ( c_time_usr ), + .time_st_do ( time_st_ds), + .core_st_do ( core_st_ds), + .t_debug_do ( ctrl_t_ds), + .c_debug_do ( ctrl_c_ds) +); + + +/////////////////////////////////////////////////////////////////////////////// +// Processor STATUS +/////////////////////////////////////////////////////////////////////////////// +wire [ 3:0] core0_src_dt, core1_src_dt; +wire arith_clr, div_clr, qnet_clr, qcom_clr, qp1_clr, qp2_clr, port_clr ; +reg arith_rdy_r , div_rdy_r , qnet_rdy_r , qcom_rdy_r , qp1_rdy_r , qp2_rdy_r; +reg arith_dt_new, div_dt_new, qnet_dt_new, qcom_dt_new, qp1_dt_new, qp2_dt_new ; +reg [31:0] qnet_dt_r [2], qcom_dt_r [2], qp1_dt_r[2], qp2_dt_r[2] ; + +wire [7:0] core0_cfg, core1_cfg; +wire [7:0] core0_ctrl, core1_ctrl; + +assign core0_src_dt = core0_cfg[3:0]; +assign core1_src_dt = core1_cfg[3:0]; + +assign arith_clr = core0_ctrl[0] | core1_ctrl[0] ; +assign div_clr = core0_ctrl[1] | core1_ctrl[1] ; +assign qnet_clr = core0_ctrl[2] | core1_ctrl[2] ; +assign qcom_clr = core0_ctrl[3] | core1_ctrl[3] ; +assign qp1_clr = core0_ctrl[4] | core1_ctrl[4] ; +assign qp2_clr = core0_ctrl[5] | core1_ctrl[5] ; +assign port_clr = core0_ctrl[6] | core1_ctrl[6] ; + +wire [31:0] sreg_status; +assign sreg_status[0] = arith_rdy ; +assign sreg_status[1] = arith_dt_new ; +assign sreg_status[2] = div_rdy ; +assign sreg_status[3] = div_dt_new ; +assign sreg_status[4] = qnet_rdy_r ; +assign sreg_status[5] = qnet_dt_new ; +assign sreg_status[6] = qcom_rdy_r ; +assign sreg_status[7] = qcom_dt_new ; +assign sreg_status[8] = qp1_rdy_r ; +assign sreg_status[9] = qp1_dt_new ; +assign sreg_status[10] = qp2_rdy_r ; +assign sreg_status[11] = qp2_dt_new ; +assign sreg_status[12] = 1'b0 ; +assign sreg_status[13] = 1'b0 ; +assign sreg_status[14] = some_fifo_full ; +assign sreg_status[15] = |port_dt_new; +assign sreg_status[31:16] = port_dt_new ; + + + +// With rising edge of RDY detect new values +always_ff @(posedge c_clk_i) begin + if (core_rst) begin + arith_rdy_r <= 1'b1 ; + div_rdy_r <= 1'b1 ; + qnet_rdy_r <= 1'b1 ; + qcom_rdy_r <= 1'b1 ; + qp1_rdy_r <= 1'b1 ; + qp2_rdy_r <= 1'b1 ; + arith_dt_new <= 1'b0 ; + div_dt_new <= 1'b0 ; + qnet_dt_new <= 1'b0 ; + qcom_dt_new <= 1'b0 ; + qp1_dt_new <= 1'b0 ; + qp2_dt_new <= 1'b0 ; + qnet_dt_r <= '{default:'0} ; + qcom_dt_r <= '{default:'0} ; + qp1_dt_r <= '{default:'0} ; + qp2_dt_r <= '{default:'0} ; + end else begin + arith_rdy_r <= arith_rdy ; + div_rdy_r <= div_rdy ; + qnet_rdy_r <= qnet_rdy_i ; + qcom_rdy_r <= qcom_rdy_i ; + qp1_rdy_r <= qp1_rdy_i; + qp2_rdy_r <= qp2_rdy_i; + // Arith Control + if ( arith_rdy & ~arith_rdy_r ) arith_dt_new <= 1 ; + else if (~arith_rdy & arith_rdy_r ) arith_dt_new <= 0 ; + else if ( arith_clr ) arith_dt_new <= 0 ; + // DIV Control + if ( div_rdy & ~div_rdy_r ) div_dt_new <= 1 ; + else if (~div_rdy & div_rdy_r ) div_dt_new <= 0 ; + else if ( div_clr ) div_dt_new <= 0 ; + // QNET Control + if ( qnet_vld_i ) begin + qnet_dt_new <= 1 ; + qnet_dt_r <= qnet_dt_i ; + end else if ( qnet_clr ) qnet_dt_new <= 0 ; + // QCOM Control + if ( qcom_vld_i ) begin + qcom_dt_new <= 1 ; + qcom_dt_r <= qcom_dt_i ; + end else if ( qcom_clr ) qcom_dt_new <= 0 ; + // Q-PERIPHERAL 1 Control + if ( qp1_vld_i ) begin + qp1_dt_new <= 1 ; + qp1_dt_r <= qp1_dt_i ; + end else if ( qp1_clr ) qp1_dt_new <= 0 ; + // Q-PERIPHERAL 2 Control + if ( qp2_vld_i ) begin + qp2_dt_new <= 1 ; + qp2_dt_r <= qp2_dt_i ; + end else if ( qp1_clr ) qp2_dt_new <= 0 ; + + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// FLAG +/////////////////////////////////////////////////////////////////////////////// + +// EXTERNAL Flag +/////////////////////////////////////////////////////////////////////////////// +sync_reg # (.DW ( 1 ) ) sync_flag_ext_c ( + .dt_i ( ext_flag_i ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( ext_flag_r ) ); + + +// INTERNAL Flag +/////////////////////////////////////////////////////////////////////////////// + +assign axi_flag_set = xreg_TPROC_CTRL[13] ; +assign axi_flag_clr = xreg_TPROC_CTRL[14] ; +assign int_flag_set = (int_flag_pen & core_usr_operation[0]); +assign int_flag_clr = (int_flag_pen & core_usr_operation[1]); +assign int_flag_inv = (int_flag_pen & core_usr_operation[2]); + +reg axi_flag_r, int_flag_r ; +always_ff @(posedge c_clk_i) begin + if (core_rst) begin + axi_flag_r <= 0; + int_flag_r <= 0; + end else begin + if ( axi_flag_set ) axi_flag_r <= 1 ; // SET EXTERNAL FLAG + else if ( axi_flag_clr ) axi_flag_r <= 0 ; // CLEAR EXTERNAL FLAG + if ( int_flag_set ) int_flag_r <= 1 ; // SET INTERNAL FLAG + else if ( int_flag_clr ) int_flag_r <= 0 ; // CLEAR INTERNAL FLAG + else if ( int_flag_inv ) int_flag_r <= ~int_flag_r ; // Flip INTERNAL FLAG + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + +// IN PORT DATA REGISTER +/////////////////////////////////////////////////////////////////////////////// +qproc_inport_reg # ( + .PORT_QTY (IN_PORT_QTY) +) IN_PORT_REG ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .c_clear ( port_clr ) , + .port_tvalid_i ( port_tvalid_i ) , + .port_tdata_i ( port_tdata_i ) , + .port_tnew_o ( port_dt_new ) , + .port_tdata_o ( in_port_dt_r ) ); + +// MEM CONTROL +/////////////////////////////////////////////////////////////////////////////// +assign ext_mem_r_dt = ext_mem_r_0_dt ; // From Core0 + +qproc_mem_ctrl # ( + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ) +) QMEM_CTRL ( + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .ext_core_sel_o ( ext_core_sel ) , + .ext_mem_sel_o ( ext_mem_sel ) , + .ext_mem_we_o ( ext_mem_we ) , + .ext_mem_addr_o ( ext_mem_addr ) , + .ext_mem_w_dt_o ( ext_mem_w_dt ) , + .ext_mem_r_dt_i ( ext_mem_r_dt ) , + .s_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_axis_tready_o ( s_dma_axis_tready_o ) , + .m_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_axis_tready_i ( m_dma_axis_tready_i ) , + .MEM_CTRL ( xreg_TPROC_CFG[6:0] ) , + .MEM_ADDR ( xreg_MEM_ADDR ) , + .MEM_LEN ( xreg_MEM_LEN ) , + .MEM_DT_I ( xreg_MEM_DT_I ) , + .MEM_DT_O ( xreg_MEM_DT_O ) , + .DEBUG_O ( axi_mem_ds) ); + + +// AXI REGISTERS +/////////////////////////////////////////////////////////////////////////////// +qproc_axi_reg QPROC_xREG ( + .ps_aclk ( ps_clk_i ) , + .ps_aresetn ( ps_rst_ni ) , + .IF_s_axireg ( IF_s_axireg ) , + .TPROC_CTRL ( xreg_TPROC_CTRL ) , + .TPROC_CFG ( xreg_TPROC_CFG ) , + .MEM_ADDR ( xreg_MEM_ADDR ) , + .MEM_LEN ( xreg_MEM_LEN ) , + .MEM_DT_I ( xreg_MEM_DT_I ) , + .TPROC_W_DT1 ( xreg_TPROC_W_DT [0] ) , + .TPROC_W_DT2 ( xreg_TPROC_W_DT [1] ) , + .CORE_CFG ( xreg_CORE_CFG ) , + .READ_SEL ( xreg_READ_SEL ) , + .MEM_DT_O ( xreg_MEM_DT_O ) , + .TPROC_R_DT1 ( xreg_TPROC_R_DT[0] ) , + .TPROC_R_DT2 ( xreg_TPROC_R_DT[1] ) , + .TIME_USR ( c_time_usr ) , + .TPROC_STATUS ( xreg_TPROC_STATUS ) , + .TPROC_DEBUG ( xreg_TPROC_DEBUG ) ); + +// AXI_REG TPROC_R_DT source selection +/////////////////////////////////////////////////////////////////////////////// +wire [ 3:0] tproc_src_dt; +assign tproc_src_dt = xreg_READ_SEL[3:0]; + +always_ff @ (posedge ps_clk_i, negedge ps_rst_ni) begin + if (!ps_rst_ni) begin + xreg_TPROC_R_DT <= '{default:'0} ; + end else begin + case (tproc_src_dt) + 4'd0 : xreg_TPROC_R_DT = xreg_TPROC_W_DT ; + 4'd1 : xreg_TPROC_R_DT = core0_w_dt ; + 4'd2 : xreg_TPROC_R_DT = core1_w_dt ; + 4'd3 : xreg_TPROC_R_DT = {div_quotient ,div_remainder }; + 4'd4 : xreg_TPROC_R_DT = '{arith_result[31:0], arith_result[63:32]}; + 4'd5 : xreg_TPROC_R_DT = qnet_dt_r ; + 4'd6 : xreg_TPROC_R_DT = qcom_dt_r; + 4'd7 : xreg_TPROC_R_DT = qp1_dt_r; + 4'd8 : xreg_TPROC_R_DT = qp2_dt_r; + 4'd9 : xreg_TPROC_R_DT = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + 4'd10: xreg_TPROC_R_DT = '{core0_lfsr, core1_lfsr}; + default: xreg_TPROC_R_DT = '{default:'0} ; + endcase + end +end + + + +/////////////////////////////////////////////////////////////////////////////// +// PERIPHERALS +/////////////////////////////////////////////////////////////////////////////// + +wire [7:0] usr_ctrl_s; +// Internal Peripherals Enable (MSB=0 - 8 possible Peripherals) +assign int_time_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0000 ); +assign int_flag_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0001 ); +assign int_arith_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0010 ); +assign int_div_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0011 ); +//assign int_A_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0100 ); +//assign int_B_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0101 ); +//assign int_C_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0110 ); +//assign int_D_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0111 ); + +// External Peripherals Enable (MSB=1 - 4 possible Peripherals) +assign ext_net_pen = usr_en & (usr_ctrl_s[7:5] == 3'b100 ); +assign ext_com_pen = usr_en & (usr_ctrl_s[7:5] == 3'b101 ); +assign ext_p1_pen = usr_en & (usr_ctrl_s[7:5] == 3'b110 ); +assign ext_p2_pen = usr_en & (usr_ctrl_s[7:5] == 3'b111 ); + +assign core_usr_operation = usr_ctrl_s[4:0]; + +// DIVIDER +/////////////////////////////////////////////////////////////////////////////// +generate + if (DIVIDER == 1) begin : QPER_DIV + wire [31:0] div_remainder_s, div_quotient_s; + reg [31:0] div_remainder_r, div_quotient_r; + div_r #( + .DW ( 32 ) + ) DIV ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .start_i ( int_div_pen ) , + .A_i ( core_usr_d_dt ) , + .B_i ( core_usr_b_dt ) , + .ready_o ( div_rdy ) , + .div_remainder_o ( div_remainder_s ) , + .div_quotient_o ( div_quotient_s ) ); + + always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + div_remainder_r <= 0 ; + div_quotient_r <= 0 ; + end else begin + div_remainder_r <= div_remainder_s ; + div_quotient_r <= div_quotient_s ; + end + end + assign div_remainder = div_remainder_r; + assign div_quotient = div_quotient_r; + end else begin : DIVIDER_NO + assign div_rdy = 0; + assign div_remainder = 0; + assign div_quotient = 0; + end +endgenerate + +// ARITH +/////////////////////////////////////////////////////////////////////////////// +generate + if (ARITH == 1) begin : QPER_ARITH + arith ARITH ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .start_i ( int_arith_pen ) , + .A_i ( core_usr_a_dt ) , + .B_i ( core_usr_b_dt ) , + .C_i ( core_usr_c_dt ) , + .D_i ( core_usr_d_dt ) , + .alu_op_i ( core_usr_operation[3:0] ) , + .ready_o ( arith_rdy ) , + .arith_result_o ( arith_result ) ); + end else begin : ARITH_NO + assign arith_rdy = 0; + assign arith_result = 0; + end +endgenerate + + + + +/////////////////////////////////////////////////////////////////////////////// +// T PROCESSOR CORE +wire [1:0] core0_lfsr_cfg; +assign core0_lfsr_cfg = xreg_CORE_CFG[1:0]; + +// Core0 FLAG source selection +/////////////////////////////////////////////////////////////////////////////// +wire [3:0] core0_src_flg; +assign core0_src_flg = core0_cfg[7:4]; +reg flag_c0; +always_comb begin + case (core0_src_flg) + 4'b000 : flag_c0 = int_flag_r ; + 4'b001 : flag_c0 = axi_flag_r ; + 4'b010 : flag_c0 = ext_flag_r ; + 4'b011 : flag_c0 = div_dt_new | arith_dt_new ; + 4'b100 : flag_c0 = |port_dt_new ; + 4'b101 : flag_c0 = qnet_flag_i; + 4'b110 : flag_c0 = qcom_flag_i ; + 4'b111 : flag_c0 = qp1_flag_i ; + default: flag_c0 = 0 ; + endcase +end + +// Core0 CORE_R_DT sreg(s7) source selection +/////////////////////////////////////////////////////////////////////////////// +reg [31:0] core0_r_dt [2], core0_w_dt [2]; +always_comb begin + case (core0_src_dt) + 4'b0000 : core0_r_dt = xreg_TPROC_W_DT ; + 4'b0001 : core0_r_dt = '{arith_result[31:0], arith_result[63:32]} ; + 4'b0010 : core0_r_dt = qnet_dt_r ; + 4'b0011 : core0_r_dt = qcom_dt_r; + 4'b0100 : core0_r_dt = qp1_dt_r; + 4'b0101 : core0_r_dt = qp2_dt_r; + 4'b0110 : core0_r_dt = core1_w_dt; + 4'b0111 : core0_r_dt = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + //DEBUG + 4'b1000: core0_r_dt = core_r_d0; + 4'b1001: core0_r_dt = core_r_d1; + 4'b1010: core0_r_dt = core_r_d2; + 4'b1011: core0_r_dt = core_r_d3; + default: core0_r_dt = xreg_TPROC_W_DT ; + endcase +end + +PORT_DT out_port_data ; // Port Data from the CORE + +qproc_core # ( + .LFSR ( LFSR ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ) +) CORE_0 ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .en_i ( core_en ) , + .restart_i ( core_rst ) , +// CORE CTRL + .lfsr_cfg_i ( core0_lfsr_cfg ) , + .core_status_o ( ) , + .core_debug_o ( ) , + .lfsr_o ( core0_lfsr ) , + .port_dt_i ( in_port_dt_r ) , //ALL The port Values + .flag_i ( flag_c0 ) , + .sreg_cfg_o ( core0_cfg ) , + .sreg_ctrl_o ( core0_ctrl ) , + .sreg_arith_i ( arith_result[31:0] ) , + .sreg_div_i ( {div_quotient ,div_remainder } ) , + .sreg_status_i ( sreg_status ) , + .sreg_core_r_dt_i ( core0_r_dt ) , + .sreg_time_dt_i ( c_time_usr ) , + .sreg_core_w_dt_o ( core0_w_dt ) , + .usr_en_o ( usr_en ) , + .usr_ctrl_o ( usr_ctrl_s ) , + .usr_dt_a_o ( core_usr_a_dt ) , + .usr_dt_b_o ( core_usr_b_dt ) , + .usr_dt_c_o ( core_usr_c_dt ) , + .usr_dt_d_o ( core_usr_d_dt ) , + .ps_mem_sel_i ( ext_mem_sel ) , + .ps_mem_we_i ( ext_mem_we ) , + .ps_mem_addr_i ( ext_mem_addr ) , + .ps_mem_w_dt_i ( ext_mem_w_dt ) , + .ps_mem_r_dt_o ( ext_mem_r_0_dt ) , + .port_we_o ( port_we ) , + .port_o ( out_port_data ) , + .core_do ( core_ds ) ); + + + +/////////////////////////////////////////////////////////////////////////////// +///// DUAL CORE +wire [1 :0] core1_lfsr_cfg; +assign core1_lfsr_cfg = xreg_CORE_CFG[3:2]; + +generate + if ( DUAL_CORE == 1) begin : DUAL_CORE_YES + reg [31:0] core1_r_dt [2]; + always_comb begin + case (core1_src_dt) + 4'b0000 : core1_r_dt = xreg_TPROC_W_DT ; + 4'b0001 : core1_r_dt = '{arith_result[31:0], arith_result[63:32]} ; + 4'b0010 : core1_r_dt = qnet_dt_r ; + 4'b0011 : core1_r_dt = qcom_dt_r; + 4'b0100 : core1_r_dt = qp1_dt_r; + 4'b0101 : core1_r_dt = qp2_dt_r; + 4'b0110 : core1_r_dt = core1_w_dt; + 4'b0111 : core1_r_dt = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + default : core1_r_dt = '{default:'0} ; + endcase + end + qproc_core # ( + .LFSR ( LFSR ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ) + ) CORE_1 ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .en_i ( core_en ) , + .restart_i ( core_rst ) , + .port_dt_i ( in_port_dt_r ) , + .sreg_arith_i ( {arith_result[31:0],arith_result[63:32]} ) , + .sreg_div_i ( {div_quotient ,div_remainder } ) , + .sreg_status_i ( sreg_status ) , + .sreg_core_r_dt_i ( core1_r_dt ) , + .sreg_core_w_dt_o ( core1_w_dt ) , + .sreg_time_dt_i ( c_time_usr ) , + .sreg_cfg_o ( core1_cfg ) , + .usr_dt_a_o ( ) , + .usr_dt_b_o ( ) , + .usr_dt_c_o ( ) , + .usr_dt_d_o ( ) , + .usr_ctrl_o ( ) , + .ps_mem_sel_i ( ) , + .ps_mem_we_i ( ) , + .ps_mem_addr_i ( ) , + .ps_mem_w_dt_i ( ) , + .ps_mem_r_dt_o ( ) , + .port_we_o ( ) , + .port_o ( ) , + .core_do ( ) ); + end else begin : DUAL_CORE_NO + assign core1_lfsr = '{default:'0} ; + assign core1_w_dt = '{default:'0} ; + assign core1_cfg = '{default:'0} ; + assign core1_ctrl = '{default:'0} ; + assign ext_mem_r_1_dt = '{default:'0} ; + end +endgenerate + + + + + +wire [31:0] fifo_dt_ds, axi_fifo_ds; +wire [15:0] c_fifo_ds, t_fifo_ds ; + +qproc_dispatcher # ( + .FIFO_DEPTH ( FIFO_DEPTH ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .OUT_TRIG_QTY ( OUT_TRIG_QTY ), + .OUT_DPORT_QTY ( OUT_DPORT_QTY ), + .OUT_DPORT_DW ( OUT_DPORT_DW ), + .OUT_WPORT_QTY ( OUT_WPORT_QTY ) +) DISPATCHER ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_rst_ni ) , + //Port + .core_en ( core_en ) , + .core_rst ( core_rst ) , + .time_en ( time_en ) , + .time_rst ( time_rst ) , + .c_time_ref_dt ( c_time_ref_dt ) , + .time_abs_i ( time_abs ) , + .all_fifo_full ( all_fifo_full ) , + .some_fifo_full ( some_fifo_full ), + .port_we ( port_we ) , + .out_port_data ( out_port_data ) , + // TRIGGERS + .port_trig_o ( port_trig_o ) , + // DATA OUTPUT INTERFACE + .port_tvalid_o ( port_tvalid_o ) , + .port_tdata_o ( port_tdata_o ) , + // WAVE OUTPUT INTERFACE + .m_axis_tdata ( m_axis_tdata ) , + .m_axis_tvalid ( m_axis_tvalid ) , + .m_axis_tready ( m_axis_tready ) , + // DEBUG outputs + .fifo_dt_do ( fifo_dt_ds ) , + .axi_fifo_do ( axi_fifo_ds ) , + .c_fifo_do ( c_fifo_ds ) , + .t_fifo_do ( t_fifo_ds ) +); + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + + + + + + + + +/////////////////////////////////////////////////////////////////////////////// +// NO REGISTERED OUTPUT + + +/////////////////////////////////////////////////////////////////////////////// +// OUT PERIPHERLAS (QNET, QCOM, P1 and P2) +assign qnet_en_o = ext_net_pen ; +assign qcom_en_o = ext_com_pen ; +assign qp1_en_o = ext_p1_pen ; +assign qp2_en_o = ext_p2_pen ; + +assign periph_a_dt_o = core_usr_a_dt; +assign periph_b_dt_o = core_usr_b_dt; +assign periph_c_dt_o = core_usr_c_dt; +assign periph_d_dt_o = core_usr_d_dt; +assign periph_op_o = core_usr_operation; + + +/////////////////////////////////////////////////////////////////////////////// +///// External Control +assign time_abs_o = time_abs ; + + + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + + + +//wire [ 3:0] c_fifo_data_dt; +//wire [31:0] c_fifo_data_time; + + +localparam DEBUG_AXI = (DEBUG > 0) ? 1 : 0; +localparam DEBUG_REG = (DEBUG > 1) ? 1 : 0; +localparam DEBUG_OUT = (DEBUG > 2) ? 1 : 0; + + +generate + +///// DEBUG AXI_REG +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_AXI == 1) begin : AXI_DB + wire [31:0] axi_status_ds, axi_port_ds; + + assign axi_status_ds[31:26] = { qp2_rdy_r , qp1_rdy_r , qcom_rdy_r , qnet_rdy_r, arith_rdy_r, div_rdy_r }; + assign axi_status_ds[25:20] = { qp2_dt_new, qp1_dt_new, qcom_dt_new, qnet_dt_new, div_dt_new, |port_dt_new }; + assign axi_status_ds[19:16] = { flag_c0, qp1_flag_i, qcom_flag_i, qnet_flag_i }; + assign axi_status_ds[15:13] = { ext_flag_r, axi_flag_r, int_flag_r }; + assign axi_status_ds[12: 8] = { core0_src_flg[2:0], core0_src_dt[1:0]}; + assign axi_status_ds[ 7: 4] = { time_en , time_st_ds[2:0] }; + assign axi_status_ds[ 3: 0] = { core_en , core_st_ds[2:0]}; + + assign axi_port_ds[31:28] = dport_di; + assign axi_port_ds[27] = port_trig_o[0] ; + assign axi_port_ds[26:24] = port_dt_new[2:0] ; + assign axi_port_ds[23: 0] = in_port_dt_r[0][23:0] ; + + always_ff @ (posedge ps_clk_i, negedge ps_rst_ni) begin + if (!ps_rst_ni) begin + xreg_TPROC_STATUS <= '{default:'0} ; + xreg_TPROC_DEBUG <= '{default:'0} ; + end else begin + xreg_TPROC_STATUS <= axi_status_ds; + case (tproc_src_dt[1:0]) + 4'd0 : xreg_TPROC_DEBUG <= axi_fifo_ds ; + 4'd1 : xreg_TPROC_DEBUG <= axi_mem_ds ; + 4'd2 : xreg_TPROC_DEBUG <= c_time_ref_dt ; + 4'd3 : xreg_TPROC_DEBUG <= axi_port_ds ; + endcase + end + end + end else begin + // NO DEBUG AXI_REG + assign xreg_TPROC_STATUS = 0 ; + assign xreg_TPROC_DEBUG = 0 ; + end + +///// DEBUG CORE_R_DT +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_REG == 1) begin : REG_DB + assign core_r_d0 = core0_w_dt ; + assign core_r_d1 = '{ in_port_dt_r[0], {15'd0, port_trig_o[0], 12'd0,dport_di} } ; + assign core_r_d2 = '{c_time_ref_dt[31:0], 32'd0} ; + end else begin + // NO DEBUG CORE_R_DT + assign core_r_d0 = '{default:'0} ; + assign core_r_d1 = '{default:'0} ; + assign core_r_d2 = '{default:'0} ; + assign core_r_d3 = '{default:'0} ; + end + + +///// DEBUG OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_OUT == 1) begin : OUT_DB + ///// PS_CLOCK Debug Signals + assign ps_debug_do[31:28] = {IF_s_axireg.axi_arready, IF_s_axireg.axi_rready, IF_s_axireg.axi_awready, IF_s_axireg.axi_wready}; + assign ps_debug_do[27:24] = {IF_s_axireg.axi_arvalid, IF_s_axireg.axi_rvalid, IF_s_axireg.axi_awvalid, IF_s_axireg.axi_wvalid}; + assign ps_debug_do[23:12] = {IF_s_axireg.axi_araddr[5:0], IF_s_axireg.axi_awaddr[5:0]}; + assign ps_debug_do[11 :0] = {IF_s_axireg.axi_rdata[5:0], IF_s_axireg.axi_wdata[5:0]}; + + ///// T_CLOCK Debug Signals + assign t_debug_do[31:16] = t_fifo_ds; + assign t_debug_do[15:12] = 4'd0; + assign t_debug_do[11:10] = { time_rst, time_en }; + assign t_debug_do[ 9: 3] = ctrl_t_ds; + assign t_debug_do[ 2: 0] = { time_st_ds[2:0] }; + + assign t_fifo_do = fifo_dt_ds ; + + ///// C_CLOCK Debug Signals + assign c_time_usr_do = c_time_usr ; + + assign c_debug_do[31:16] = c_fifo_ds; + assign c_debug_do[15:14] = { some_fifo_full, all_fifo_full } ; + assign c_debug_do[13:12] = { 2'd0 } ; + assign c_debug_do[11:10] = { core_rst, core_en } ; + assign c_debug_do[ 9: 3] = ctrl_c_ds; + assign c_debug_do[ 2: 0] = { core_st_ds[2:0] }; + + assign c_time_ref_do = c_time_ref_dt ; + + assign c_port_do[31:28] = out_port_data.p_addr[3:0] ; + assign c_port_do[27:16] = out_port_data.p_data[11:0]; + assign c_port_do[15: 0] = out_port_data.p_time[15:0]; + + assign c_proc_do[31:30] = { flag_c0, |port_dt_new } ; + assign c_proc_do[29:18] = sreg_status[11:0]; + assign c_proc_do[17:11] = core0_ctrl[6:0] ; + assign c_proc_do[10: 8] = core0_src_dt[2:0] ; + assign c_proc_do[ 7: 2] = { int_flag_r, axi_flag_r, int_flag_clr, int_flag_set, axi_flag_clr, axi_flag_set } ; + assign c_proc_do[ 1: 0] = { time_ref_inc, time_ref_set } ; + + assign c_core_do = core_ds ; + + assign time_ref_set = ( int_time_pen & core_usr_operation[2]) ; + assign time_ref_inc = ( int_time_pen & core_usr_operation[3]) ; + + end else begin + // DEBUG OUT + assign ps_debug_do = 0 ; + assign t_debug_do = 0 ; + assign t_fifo_do = 0 ; + assign c_time_usr_do = 0 ; + assign c_debug_do = 0 ; + assign c_time_ref_do = 0 ; + assign c_port_do = 0 ; + assign c_proc_do = 0 ; + assign c_core_do = 0 ; + end +endgenerate + + +endmodule + diff --git a/firmware/ip/qick_processor/src/qick_processor.xdc b/firmware/ip/qick_processor/src/qick_processor.xdc new file mode 100644 index 000000000..360b83b21 --- /dev/null +++ b/firmware/ip/qick_processor/src/qick_processor.xdc @@ -0,0 +1,43 @@ +#--------------------------- +# QICK_PROCESSOR False Paths +#--------------------------- + +# General Synchronizers +set_false_path -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name=~*_cdc_reg*}]] + +# Specific Paths +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/c_time_ref_o_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg*}]] +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/offset_dt_r_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/time_updt_dt_reg*}]] +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/tproc_cfg_sync_reg[9]}]] -to [get_clocks -of_objects [get_ports -filter {name =~ t_clk_i}]] +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg*}]] + +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_xREG/QPROC_xREG/slv_*_reg*}]] -to [get_clocks -of_objects [get_ports -filter {name =~ c_clk_i}]] + +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/IN_PORT_REG/*.port_dt_r_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/xreg_TPROC_R_DT_reg*}]] + +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/xreg_TPROC_R_DT_reg*}]] + +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/CORE_*/CORE_CPU/reg_bank/LFSR_YES.lfsr/reg_lfsr_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/xreg_TPROC_R_DT_reg*}]] + +set_false_path -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/qp?_dt_r_reg*}]] -to [get_clocks -of_objects [get_ports -filter {name =~ ps_clk_i}]] + +# Doesn't exist if parameter QNET = 0 +set_false_path -quiet -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/qnet_dt_r_reg*}]] -to [get_clocks -of_objects [get_ports -filter {name =~ ps_clk_i}]] + +# Doesn't exist if parameter QCOM = 0 +set_false_path -quiet -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/qcom_dt_r_reg*}]] -to [get_clocks -of_objects [get_ports -filter {name =~ ps_clk_i}]] + +# Doesn't exist if parameter DIVIDER = 0 +set_false_path -quiet -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPER_DIV.div_*_r_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/xreg_TPROC_R_DT_reg*}]] + +# Doesn't exist if parameter ARITH = 0 +set_false_path -quiet -from [get_pins -filter {REF_PIN_NAME =~ CLK} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPER_ARITH.ARITH/ARITH_DSP*i_primitive*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/xreg_TPROC_R_DT_reg*}]] + +# Doesn't exist if parameter TIME_READ = 0 +set_false_path -quiet -from [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/*t_time_abs_r_reg*}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/QPROC_CTRL/*c_time_abs_r_reg*}]] + +# Doesn't exist if parameter DEBUG = 0 +set_false_path -quiet -from [get_clocks -of_objects [get_ports -filter {name =~ t_clk_i}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/AXI_DB.xreg_TPROC_DEBUG_reg*}]] +set_false_path -quiet -from [get_clocks -of_objects [get_ports -filter {name =~ t_clk_i}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/AXI_DB.xreg_TPROC_STATUS_reg*}]] +set_false_path -quiet -from [get_clocks -of_objects [get_ports -filter {name =~ c_clk_i}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/AXI_DB.xreg_TPROC_DEBUG_reg*}]] +set_false_path -quiet -from [get_clocks -of_objects [get_ports -filter {name =~ c_clk_i}]] -to [get_pins -filter {REF_PIN_NAME =~ D} -of_objects [get_cells -hier -filter {name =~ *QPROC/AXI_DB.xreg_TPROC_STATUS_reg*}]] diff --git a/firmware/ip/qick_processor/src/qick_processor_ooc.xdc b/firmware/ip/qick_processor/src/qick_processor_ooc.xdc new file mode 100644 index 000000000..75bf6bfe1 --- /dev/null +++ b/firmware/ip/qick_processor/src/qick_processor_ooc.xdc @@ -0,0 +1,3 @@ +create_clock -period 10.000 -name ps_clk_i -waveform {0.000 5.000} [get_ports ps_clk_i] +create_clock -period 1.620 -name t_clk_i -waveform {0.000 0.810} [get_ports t_clk_i] +create_clock -period 5.000 -name c_clk_i -waveform {0.000 2.500} [get_ports c_clk_i] diff --git a/firmware/ip/qick_processor/src/qproc_axi_reg.sv b/firmware/ip/qick_processor/src/qproc_axi_reg.sv new file mode 100644 index 000000000..9662a029d --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_axi_reg.sv @@ -0,0 +1,65 @@ +`include "_qproc_defines.svh" + +// TPROC REG +///////////////////////////////////////////////// +module qproc_axi_reg( + input wire ps_aclk , + input wire ps_aresetn , + TYPE_IF_AXI_REG.slave IF_s_axireg , + output logic [15:0] TPROC_CTRL , + output logic [15:0] TPROC_CFG , + output logic [15:0] MEM_ADDR , + output logic [15:0] MEM_LEN , + output logic [31:0] MEM_DT_I , + output logic [31:0] TPROC_W_DT1 , + output logic [31:0] TPROC_W_DT2 , + output logic [7:0] CORE_CFG , + output logic [7:0] READ_SEL , + input wire [31:0] MEM_DT_O , + input wire [31:0] TPROC_R_DT1 , + input wire [31:0] TPROC_R_DT2 , + input wire [31:0] TIME_USR , + input wire [31:0] TPROC_STATUS , + input wire [31:0] TPROC_DEBUG +); + +// AXI Slave. +axi_slv_qproc QPROC_xREG ( + .aclk ( ps_aclk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( IF_s_axireg.axi_awaddr [5:0] ) , + .awprot ( IF_s_axireg.axi_awprot ) , + .awvalid ( IF_s_axireg.axi_awvalid ) , + .awready ( IF_s_axireg.axi_awready ) , + .wdata ( IF_s_axireg.axi_wdata ) , + .wstrb ( IF_s_axireg.axi_wstrb ) , + .wvalid ( IF_s_axireg.axi_wvalid ) , + .wready ( IF_s_axireg.axi_wready ) , + .bresp ( IF_s_axireg.axi_bresp ) , + .bvalid ( IF_s_axireg.axi_bvalid ) , + .bready ( IF_s_axireg.axi_bready ) , + .araddr ( IF_s_axireg.axi_araddr ) , + .arprot ( IF_s_axireg.axi_arprot ) , + .arvalid ( IF_s_axireg.axi_arvalid ) , + .arready ( IF_s_axireg.axi_arready ) , + .rdata ( IF_s_axireg.axi_rdata ) , + .rresp ( IF_s_axireg.axi_rresp ) , + .rvalid ( IF_s_axireg.axi_rvalid ) , + .rready ( IF_s_axireg.axi_rready ) , + .TPROC_CTRL ( TPROC_CTRL ) , + .TPROC_CFG ( TPROC_CFG ) , + .MEM_ADDR ( MEM_ADDR ) , + .MEM_LEN ( MEM_LEN ) , + .MEM_DT_I ( MEM_DT_I ) , + .TPROC_W_DT1 ( TPROC_W_DT1 ) , + .TPROC_W_DT2 ( TPROC_W_DT2 ) , + .CORE_CFG ( CORE_CFG ) , + .READ_SEL ( READ_SEL ) , + .MEM_DT_O ( MEM_DT_O ) , + .TPROC_R_DT1 ( TPROC_R_DT1 ) , + .TPROC_R_DT2 ( TPROC_R_DT2 ) , + .TIME_USR ( TIME_USR ) , + .TPROC_STATUS ( TPROC_STATUS ) , + .TPROC_DEBUG ( TPROC_DEBUG ) ); + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_core.sv b/firmware/ip/qick_processor/src/qproc_core.sv new file mode 100644 index 000000000..8a19cf2da --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_core.sv @@ -0,0 +1,169 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qproc_core # ( + parameter LFSR = 1, + parameter IN_PORT_QTY = 1, + parameter PMEM_AW = 8, + parameter DMEM_AW = 8, + parameter WMEM_AW = 8, + parameter REG_AW = 4 +)( + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + input wire en_i , + input wire restart_i , +// CORE CTRL + input wire [1:0] lfsr_cfg_i , + output wire [31:0] core_status_o , + output wire [31:0] core_debug_o , + output wire [31:0] lfsr_o , +// AXI Registers + input wire [63:0] port_dt_i [ IN_PORT_QTY ] , + input wire flag_i , +// Special Function Registers + output wire [7 :0] sreg_cfg_o , + output wire [7 :0] sreg_ctrl_o , + input wire [31:0] sreg_arith_i , + input wire [31:0] sreg_div_i[2] , + input wire [31:0] sreg_status_i , + input wire [31:0] sreg_core_r_dt_i[2] , + input wire [31:0] sreg_time_dt_i , + output wire [31:0] sreg_core_w_dt_o[2] , +// Peripherals + output wire usr_en_o , + output wire [7:0] usr_ctrl_o , + output wire [31:0] usr_dt_a_o , + output wire [31:0] usr_dt_b_o , + output wire [31:0] usr_dt_c_o , + output wire [31:0] usr_dt_d_o , + +// Memory + input wire [ 1:0] ps_mem_sel_i , + input wire ps_mem_we_i , + input wire [ 15:0] ps_mem_addr_i , + input wire [167:0] ps_mem_w_dt_i , + output wire [167:0] ps_mem_r_dt_o , +//Port + output wire port_we_o , + output PORT_DT port_o , +//Debug + output wire [31:0] core_do ); + + +wire [PMEM_AW-1:0] pmem_addr ; +wire pmem_en ; +wire [71:0] pmem_dt ; +wire dmem_we ; +wire [DMEM_AW-1:0] dmem_addr ; +wire [31:0] dmem_w_dt ; +wire [31:0] dmem_r_dt ; +wire wmem_we ; +wire [WMEM_AW-1:0] wmem_addr ; +wire [167:0] wmem_w_dt ; +wire [167:0] wmem_r_dt ; + +wire port_re; + + + + +qcore_cpu # ( + .LFSR ( LFSR ) , + .PMEM_AW ( PMEM_AW ) , + .DMEM_AW ( DMEM_AW ) , + .WMEM_AW ( WMEM_AW ) , + .REG_AW ( REG_AW ) +) CORE_CPU ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .restart_i ( restart_i ) , + .en_i ( en_i ) , + .lfsr_cfg_i ( lfsr_cfg_i ) , + .lfsr_o ( lfsr_o ) , + .flag_i ( flag_i ) , // External Condition + .sreg_cfg_o ( sreg_cfg_o ) , + .sreg_ctrl_o ( sreg_ctrl_o ) , + .sreg_arith_i ( sreg_arith_i ) , // Arith Input + .sreg_div_i ( sreg_div_i ) , // Div Input + .sreg_status_i ( sreg_status_i ) , + .sreg_core_r_dt_i ( sreg_core_r_dt_i ) , + .sreg_port_dt_i ( {in_port_dt_r[31:0], in_port_dt_r[63:32] } ) , + .sreg_time_dt_i ( sreg_time_dt_i ) , + .sreg_core_w_dt_o ( sreg_core_w_dt_o ) , + .usr_ctrl_o ( usr_ctrl_o ) , + .usr_en_o ( usr_en_o ) , + .usr_dt_a_o ( usr_dt_a_o ) , + .usr_dt_b_o ( usr_dt_b_o ) , + .usr_dt_c_o ( usr_dt_c_o ) , + .usr_dt_d_o ( usr_dt_d_o ) , + .pmem_addr_o ( pmem_addr ) , + .pmem_en_o ( pmem_en ) , + .pmem_dt_i ( pmem_dt ) , + .dmem_we_o ( dmem_we ) , + .dmem_addr_o ( dmem_addr ) , + .dmem_w_dt_o ( dmem_w_dt ) , + .dmem_r_dt_i ( dmem_r_dt ) , + .wmem_we_o ( wmem_we ) , + .wmem_addr_o ( wmem_addr ) , + .wmem_w_dt_o ( wmem_w_dt ) , + .wmem_r_dt_i ( wmem_r_dt ) , + .port_we_o ( port_we_o ) , + .port_re_o ( port_re ) , + .port_o ( port_o ) , + .core_do ( core_do ) ); + + +reg [63:0 ] in_port_dt_r; +// PORT READ +/////////////////////////////////////////////////////////////////////////////// +always_ff @(posedge c_clk_i) begin + if ( restart_i ) in_port_dt_r <= 0 ; + else if ( port_re ) in_port_dt_r <= port_dt_i[port_o.p_addr[3:0]]; +end + + +qcore_mem # ( + .PMEM_AW ( PMEM_AW ) , + .DMEM_AW ( DMEM_AW ) , + .WMEM_AW ( WMEM_AW ) +) CORE_MEM ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .ps_sel_i ( ps_mem_sel_i ) , + .ps_we_i ( ps_mem_we_i ) , + .ps_addr_i ( ps_mem_addr_i ) , + .ps_w_dt_i ( ps_mem_w_dt_i ) , + .ps_r_dt_o ( ps_mem_r_dt_o ) , + .c_pmem_en_i ( pmem_en ) , + .c_pmem_addr_i ( pmem_addr ) , + .c_pmem_r_dt_o ( pmem_dt ) , + .c_dmem_we_i ( dmem_we ) , + .c_dmem_addr_i ( dmem_addr ) , + .c_dmem_w_dt_i ( dmem_w_dt ) , + .c_dmem_r_dt_o ( dmem_r_dt ) , + .c_wmem_we_i ( wmem_we ) , + .c_wmem_addr_i ( wmem_addr ) , + .c_wmem_w_dt_i ( wmem_w_dt ) , + .c_wmem_r_dt_o ( wmem_r_dt ) ); + +assign core_status_o = 0; +assign core_debug_o =0; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qproc_ctrl.sv b/firmware/ip/qick_processor/src/qproc_ctrl.sv new file mode 100644 index 000000000..91ea1297e --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_ctrl.sv @@ -0,0 +1,355 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2024 +// Version : 4 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// +module qproc_ctrl # ( + parameter TIME_READ = 1 +)( +// Time, Core and AXI CLK & RST. + input wire t_clk_i , + input wire t_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , +// External Control + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_updt_i , + input wire [31:0] time_updt_dt_i , +// Core Control + input wire int_time_en , //int_time_pen + input wire [3:0] int_time_cmd , //core_usr_operation + input wire [31:0] int_time_dt , //core_usr_operation +// AXI Control + input wire [15:0] PS_TPROC_CTRL, + input wire [11:9] PS_TPROC_CFG, + // input wire [15:0] xreg_TPROC_CTRL , + // input wire [15:0] xreg_TPROC_CFG , + input wire [31:0] xreg_TPROC_W_DT , +// QPROC_STATE + input wire all_fifo_full_i , + input wire some_fifo_full_i , +// CORE ST + output reg core_rst_o , + output reg core_en_o , +// TIME ST + output reg time_rst_o , + output reg time_en_o , + output wire [47:0] time_abs_o , + output reg [47:0] c_time_ref_o , + output wire [31:0] c_time_usr_o , // User time "current_user_time" +// DEBUG + output reg [ 2:0] time_st_do , + output reg [ 2:0] core_st_do , + output reg [ 6:0] t_debug_do , + output reg [ 6:0] c_debug_do +); + +//------------------------------------------------------- +// Code moved from qproc_axi_reg due to issue #33 +(* ASYNC_REG = "TRUE" *) logic [15:0] tproc_ctrl_cdc, tproc_ctrl_sync; +logic [15:0] tproc_ctrl_2r; +logic [15:0] xreg_TPROC_CTRL; + +(* ASYNC_REG = "TRUE" *) logic [11:9] tproc_cfg_cdc, tproc_cfg_sync; +logic [11:9] xreg_TPROC_CFG; + +// From PS_CLK to C_CLK +always_ff @(posedge c_clk_i) begin + if (!c_rst_ni) begin + tproc_ctrl_cdc <= 0 ; + tproc_ctrl_sync <= 0 ; + tproc_ctrl_2r <= 0 ; + tproc_cfg_cdc <= 0 ; + end else begin + tproc_ctrl_cdc <= PS_TPROC_CTRL ; + tproc_ctrl_sync <= tproc_ctrl_cdc ; + tproc_ctrl_2r <= tproc_ctrl_sync ; + tproc_cfg_cdc <= PS_TPROC_CFG ; + tproc_cfg_sync <= tproc_cfg_cdc ; + end +end + +// The C_TPROC_CTRL is only ONE clock. +assign xreg_TPROC_CTRL = tproc_ctrl_sync & ~tproc_ctrl_2r ; +assign xreg_TPROC_CFG = tproc_cfg_sync; +//------------------------------------------------------- + + +// Control +reg t_core_rst_prev_net; // NET Request to RESET the Processor and go to previous state +reg [31:0] time_updt_dt ; // New incremental time value + +/////////////////////////////////////////////////////////////////////////////// +// CONTROL Signals +/////////////////////////////////////////////////////////////////////////////// +// wire fifo_ok; +// assign fifo_ok = ~(some_fifo_full_i) | xreg_TPROC_CFG[11] ; // With 1 in TPROC_CFG[11] Continue +// assign core_en = core_en_s & fifo_ok; + + +/// IO CTRL +assign proc_start_io = proc_start_i & xreg_TPROC_CFG[10] ; +assign proc_stop_io = proc_stop_i & xreg_TPROC_CFG[10] ; + +/// PYTHON +assign time_stop_p = xreg_TPROC_CTRL[3] | xreg_TPROC_CTRL[9] | proc_stop_io ; // STOP | P_FREEZE +assign time_run_p = xreg_TPROC_CTRL[7] | xreg_TPROC_CTRL[8] ; // RUN | P_PAUSE +assign time_rst_stop_p = xreg_TPROC_CTRL[6] ; //T_RST | START | P_RST +assign time_rst_run_p = xreg_TPROC_CTRL[0] | xreg_TPROC_CTRL[2] | proc_start_io ; // START | T_RST +assign time_update_p = xreg_TPROC_CTRL[1] ; +assign time_step_p = xreg_TPROC_CTRL[10] | xreg_TPROC_CTRL[12] ; + +assign core_stop_p = xreg_TPROC_CTRL[3] | xreg_TPROC_CTRL[5] | xreg_TPROC_CTRL[8] | proc_stop_io; // STOP | C_STOP | P_PAUSE +assign core_run_p = xreg_TPROC_CTRL[7] | xreg_TPROC_CTRL[9] ; // RUN | P_FREEZE +assign core_rst_stop_p = xreg_TPROC_CTRL[6] ; // P_RST +assign core_rst_run_p = xreg_TPROC_CTRL[2] | xreg_TPROC_CTRL[4] | proc_start_io ; // START | C_START +assign core_rst_prev_p = xreg_TPROC_CTRL[0] ; // T_RST +assign core_step_p = xreg_TPROC_CTRL[10] | xreg_TPROC_CTRL[11] ; + +/// QPROC-CORE +assign time_rst_core = ( int_time_en & int_time_cmd[0]) ; +assign time_updt_core = ( int_time_en & int_time_cmd[1]) ; +assign time_ref_set = ( int_time_en & int_time_cmd[2]) ; +assign time_ref_inc = ( int_time_en & int_time_cmd[3]) ; + +/// NET CTRL +assign time_rst_net = time_rst_i & ~xreg_TPROC_CFG[9] ; +assign time_updt_net = time_updt_i & ~xreg_TPROC_CFG[9] ; +assign core_start_net = core_start_i & ~xreg_TPROC_CFG[9] ; +assign core_stop_net = core_stop_i & ~xreg_TPROC_CFG[9] ; + +assign c_time_rst_run = time_rst_run_p | time_rst_core ; +assign c_time_updt = time_update_p | time_updt_core ; + + + +/////////////////////////////////////////////////////////////////////////////// +// CORE CONTROL +/////////////////////////////////////////////////////////////////////////////// + +// Store Time_Update_Data from PROCESSOR or PYTHON in offset_dt_r +reg [31:0] offset_dt_r; +always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + offset_dt_r <= 0; + end else begin + if ( time_updt_core ) offset_dt_r <= int_time_dt ; // Update from CORE + else if ( time_update_p ) offset_dt_r <= xreg_TPROC_W_DT ; // Update from PYTHON + end + +assign ctrl_c_rst_stop = core_rst_stop_p ; +assign ctrl_c_rst_run = core_start_net | core_rst_run_p ; +assign ctrl_c_stop = core_stop_net | core_stop_p ; +assign ctrl_c_run = core_run_p; +assign ctrl_c_step = core_step_p ; + + +// Core Control State Machine +/////////////////////////////////////////////////////////////////////////////// +enum {C_RST_STOP=0, C_RST_STOP_WAIT=1, C_RST_RUN=2, C_RST_RUN_WAIT=3, C_STOP=4, C_RUN=5, C_STEP=6, C_END_STEP=7} core_st_nxt, core_st; + +// Sequential Stante Machine +always_ff @(posedge c_clk_i) + if (!c_rst_ni) core_st <= C_RST_STOP; + else core_st <= core_st_nxt; + +// State change and Out +always_comb begin + core_en_o = 0; + core_rst_o = 0; + core_st_nxt = core_st; + //COMMON TRANSITIONS + if ( ctrl_c_stop ) core_st_nxt = C_STOP; + else if ( ctrl_c_run ) core_st_nxt = C_RUN; + else if ( ctrl_c_rst_run ) core_st_nxt = C_RST_RUN; + else if ( ctrl_c_rst_stop) core_st_nxt = C_RST_STOP; + else if ( ctrl_c_step ) core_st_nxt = C_STEP; + //State Transitions and Out + case (core_st) + C_RST_RUN : begin + core_rst_o = 1; + if (all_fifo_full_i) core_st_nxt = C_RST_RUN_WAIT; + end + C_RST_RUN_WAIT : + if (!all_fifo_full_i) core_st_nxt = C_RUN; + C_RST_STOP : begin + core_rst_o = 1; + if (all_fifo_full_i) core_st_nxt = C_RST_STOP_WAIT; + end + C_RST_STOP_WAIT : + if (!all_fifo_full_i) core_st_nxt = C_STOP; + C_RUN: begin + core_en_o = 1; + end + C_STOP: begin + end + C_STEP: begin + core_en_o = 1; + core_st_nxt = C_END_STEP; + end + C_END_STEP: begin + if (!ctrl_c_step) core_st_nxt = C_STOP; + end + default:; + endcase + // Pause Core on Dispatcher FIFO full; with 1 in TPROC_CFG[11] continue + if (some_fifo_full_i & ~(xreg_TPROC_CFG[11])) begin + core_en_o = 0; + end +end + +/////////////////////////////////////////////////////////////////////////////// +// TIME CONTROL +/////////////////////////////////////////////////////////////////////////////// + +// T_CLK DOMAIN Synchronization +/////////////////////////////////////////////////////////////////////////////// +sync_reg # (.DW ( 7 ) ) sync_ctrl_ps_t ( + .dt_i ( {core_rst_o, time_rst_stop_p, c_time_rst_run, c_time_updt, time_stop_p, time_run_p, time_step_p} ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( {core_rst_ack, t_time_rst_stop, t_time_rst_run, t_time_update, t_time_stop, t_time_run, t_time_step} ) ); + + +always_ff @(posedge t_clk_i) + if (!t_rst_ni) begin + t_core_rst_prev_net <= 1'b0 ; // NET Request to RESET the Processor + time_updt_dt <= 32'd0; // Store Time_Update_Data from offset_dt_r(CORE, PYTHON) OR time_updt_dt_i (NET) + end else begin + if ( t_time_update ) + time_updt_dt <= offset_dt_r; + else + time_updt_dt <= time_updt_dt_i; + if ( time_rst_net ) t_core_rst_prev_net <= 1'b1; + else if ( core_rst_ack ) t_core_rst_prev_net <= 1'b0; + end + +assign ctrl_t_rst_stop = t_time_rst_stop ; +assign ctrl_t_rst_run = time_rst_net | t_time_rst_run ; +assign ctrl_t_updt = time_updt_net | t_time_update ; +assign ctrl_t_run = t_time_run ; +assign ctrl_t_stop = t_time_stop; +assign ctrl_t_step = t_time_step ; + +// Time Control State Machine +/////////////////////////////////////////////////////////////////////////////// +enum {T_RST_STOP=0, T_RST_RUN=1, T_UPDT=2, T_RUN=3, T_STOP=4, T_STEP=5} time_st_nxt, time_st; +// Sequential Stante Machine +always_ff @(posedge t_clk_i) + if (!t_rst_ni) time_st <= T_RST_STOP; + else time_st <= time_st_nxt; +// State change and Out +reg time_updt ; +always_comb begin + time_en_o = 0; + time_rst_o = 0; + time_updt = 0; + time_st_nxt = time_st; + //COMMON TRANSITIONS + if ( ctrl_t_rst_stop ) time_st_nxt = T_RST_STOP ; + if ( ctrl_t_rst_run ) time_st_nxt = T_RST_RUN ; + else if ( ctrl_t_updt ) time_st_nxt = T_UPDT ; + else if ( ctrl_t_run ) time_st_nxt = T_RUN ; + else if ( ctrl_t_stop ) time_st_nxt = T_STOP ; + else if ( ctrl_t_step ) time_st_nxt = T_STEP ; + case (time_st) + T_RST_STOP : begin + time_en_o = 1; + time_rst_o = 1; + time_st_nxt = T_STOP ; + end + T_RST_RUN : begin + time_en_o = 1; + time_rst_o = 1; + time_st_nxt = T_RUN ; + end + T_UPDT : begin + time_en_o = 1; + time_updt = 1; + time_st_nxt = T_RUN ; + end + T_RUN: begin + time_en_o = 1; + end + T_STEP: begin + time_en_o = 1; + time_st_nxt = T_STOP ; + end + default:; + endcase +end + + +// Time REF +/////////////////////////////////////////////////////////////////////////////// +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) c_time_ref_o <= '{default:'0} ; + else if (core_rst_o) c_time_ref_o <= '{default:'0} ; + else if (time_ref_set ) c_time_ref_o <= {16'd0, int_time_dt} ; + else if (time_ref_inc ) c_time_ref_o <= c_time_ref_o + {16'd0, int_time_dt} ; +end + +// Time ABS +/////////////////////////////////////////////////////////////////////////////// +qproc_time_ctrl QTIME_CTRL ( + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_rst_ni ) , + .time_en_i ( time_en_o ) , + .time_rst_i ( time_rst_o ) , + .time_init_i ( 1'b0 ) , + .time_updt_i ( time_updt ) , + .updt_dt_i ( time_updt_dt ) , + .time_abs_o ( time_abs_o ) ); + +assign c_debug_do = { 2'b00, ctrl_c_step, ctrl_c_stop, ctrl_c_run, ctrl_c_rst_run, ctrl_c_rst_stop } ; +assign t_debug_do = { ctrl_t_updt, 1'b0, ctrl_t_step, ctrl_t_stop, ctrl_t_run, ctrl_t_rst_run, ctrl_t_rst_stop } ; + +/////////////////////////////////////////////////////////////////////////////// +// TIME READ +(* ASYNC_REG = "TRUE" *) reg [47:0] c_time_abs_r ; // Absolute Time Counter Value "Registered" +reg [47:0] t_time_abs_r; + +generate + if ( TIME_READ == 1) begin : QPER_TIME_READ + sync_ab_en sync_ab_en_inst ( + .clk_a_i ( c_clk_i ) , + .rst_a_ni ( c_rst_ni ) , + .clk_b_i ( t_clk_i ) , + .rst_b_ni ( t_rst_ni ) , + .a_en_o ( c_time_en ) , + .b_en_o ( t_time_en ) ); + + // Register TIME_ABS + /////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge t_clk_i) begin + if ( !t_rst_ni ) t_time_abs_r <= 0; + else if ( t_time_en ) t_time_abs_r <= time_abs_o; + end + + always_ff @(posedge c_clk_i) begin + if ( !c_rst_ni ) c_time_abs_r <= 0; + else if ( c_time_en ) c_time_abs_r <= t_time_abs_r; + end + + assign c_time_usr_o = (c_time_abs_r - c_time_ref_o); + + end else begin : TIME_READ_NO + assign c_time_usr_o = 0; + end +endgenerate + +assign time_st_do = { time_st[2:0] }; +assign core_st_do = { core_st[2:0] }; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_dispatcher.sv b/firmware/ip/qick_processor/src/qproc_dispatcher.sv new file mode 100644 index 000000000..ae03a59e4 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_dispatcher.sv @@ -0,0 +1,414 @@ +`include "_qproc_defines.svh" + +module qproc_dispatcher # ( + parameter FIFO_DEPTH = 8 , + parameter IN_PORT_QTY = 1 , + parameter OUT_TRIG_QTY = 1 , + parameter OUT_DPORT_QTY = 1 , + parameter OUT_DPORT_DW = 4 , + parameter OUT_WPORT_QTY = 1 +)( + input wire c_clk_i , + input wire c_rst_ni , + input wire t_clk_i , + input wire t_rst_ni , + //Port + input wire core_en , + input wire core_rst , + input wire time_en , + input wire time_rst , + input wire [47:0] c_time_ref_dt , + input wire [47:0] time_abs_i , + input wire port_we , + input PORT_DT out_port_data , + output wire all_fifo_full , + output wire some_fifo_full , + // TRIGGERS + output wire port_trig_o [OUT_TRIG_QTY] , + // DATA OUTPUT INTERFACE + output wire port_tvalid_o[OUT_DPORT_QTY] , + output wire [OUT_DPORT_DW-1:0] port_tdata_o [OUT_DPORT_QTY] , + // WAVE OUTPUT INTERFACE + output wire [167:0] m_axis_tdata [OUT_WPORT_QTY] , + output wire m_axis_tvalid [OUT_WPORT_QTY] , + input wire m_axis_tready [OUT_WPORT_QTY] , + // DEBUG outputs + output wire [31:0] fifo_dt_do , + output wire [31:0] axi_fifo_do , + output wire [15:0] c_fifo_do , + output wire [15:0] t_fifo_do +); + + +// FIFOS & DISPATCHER + +// .p_type > Select between WAVE or DATA (TRIG is DATA with high address) +// .p_addr > Select Port Addr (Bit 3 select between DATA and TRIGGER (Addr 0 to 7 are Data, Addr 8 to 15 are Trigger) +// .p_time > c_fifo_time_in_r +// .p_data > c_fifo_data_in_r +reg [ 47:0] time_abs_r ; + +reg [ 47:0] c_fifo_time_in_r ; // TIME from the CORE > To the FIFOs +reg [167:0] c_fifo_data_in_r ; // DATA from the CORE > To the FIFOs + +wire [47:0] t_fifo_wave_time [OUT_WPORT_QTY-1:0]; // TIME from the FIFO > To the Comparator +wire [167:0] t_fifo_wave_dt [OUT_WPORT_QTY-1:0]; // DATA from the FIFO > TO the WPORT +reg [OUT_WPORT_QTY-1:0] wave_t_gr_r; // Abs Time greater than Time from W FIFO +reg [OUT_WPORT_QTY-1:0] c_fifo_wave_push, c_fifo_wave_push_r, c_fifo_wave_push_s; +reg [OUT_WPORT_QTY-1:0] wave_pop, wave_pop_prev; +reg [OUT_WPORT_QTY-1:0] wave_pop_r, wave_pop_r2; + +wire [47:0] t_fifo_data_time [OUT_DPORT_QTY-1:0]; // TIME from the FIFO > To the Comparator +wire [OUT_DPORT_DW-1 :0] t_fifo_data_dt [OUT_DPORT_QTY-1:0]; // DATA from the FIFO > TO the DPORT +reg [OUT_DPORT_QTY-1:0] data_t_gr_r; // Abs Time greater than Time from D FIFO +reg [OUT_DPORT_QTY-1:0] c_fifo_data_push, c_fifo_data_push_r, c_fifo_data_push_s ; +reg data_pop[OUT_DPORT_QTY], data_pop_prev[OUT_DPORT_QTY]; +reg data_pop_r[OUT_DPORT_QTY], data_pop_r2[OUT_DPORT_QTY]; + +wire [47:0] t_fifo_trig_time [OUT_TRIG_QTY]; // TIME from the FIFO > To the Comparator +wire t_fifo_trig_dt [OUT_TRIG_QTY]; // DATA from the FIFO > TO the WPORT +reg [OUT_TRIG_QTY-1:0] trig_t_gr_r; // Abs Time greater than Time from T FIFO +reg [OUT_TRIG_QTY-1:0] c_fifo_trig_push, c_fifo_trig_push_r, c_fifo_trig_push_s ; +reg trig_pop[OUT_TRIG_QTY], trig_pop_prev[OUT_TRIG_QTY]; +reg trig_pop_r[OUT_TRIG_QTY], trig_pop_r2[OUT_TRIG_QTY]; + +(* ASYNC_REG = "TRUE" *) reg [OUT_TRIG_QTY-1:0] fifo_trig_empty_cdc; +(* ASYNC_REG = "TRUE" *) reg [OUT_TRIG_QTY-1:0] c_fifo_trig_empty ; +wire [OUT_TRIG_QTY-1:0] t_fifo_trig_empty, c_fifo_trig_full ; +reg [OUT_TRIG_QTY-1:0] t_fifo_trig_empty_r; + +(* ASYNC_REG = "TRUE" *) reg [OUT_DPORT_QTY-1:0] fifo_data_empty_cdc; +(* ASYNC_REG = "TRUE" *) reg [OUT_DPORT_QTY-1:0] c_fifo_data_empty ; +wire [OUT_DPORT_QTY-1:0] t_fifo_data_empty, c_fifo_data_full ; +reg [OUT_DPORT_QTY-1:0] t_fifo_data_empty_r; + +(* ASYNC_REG = "TRUE" *) reg [OUT_WPORT_QTY-1:0] fifo_wave_empty_cdc; +(* ASYNC_REG = "TRUE" *) reg [OUT_WPORT_QTY-1:0] c_fifo_wave_empty; +wire [OUT_WPORT_QTY-1:0] t_fifo_wave_empty , c_fifo_wave_full ; +reg [OUT_WPORT_QTY-1:0] t_fifo_wave_empty_r; + +wire dfifo_full, wfifo_full; + +/////////////////////////////////////////////////////////////////////////////// +/// FIFO & DISPATCHER +/////////////////////////////////////////////////////////////////////////////// +assign all_tfifo_empty = &c_fifo_trig_empty ; +assign all_dfifo_empty = &c_fifo_data_empty ; +assign all_wfifo_empty = &c_fifo_wave_empty ; +assign all_fifo_empty = all_tfifo_empty & all_dfifo_empty & all_wfifo_empty ; + +assign all_tfifo_full = &c_fifo_trig_full ; +assign all_dfifo_full = &c_fifo_data_full ; +assign all_wfifo_full = &c_fifo_wave_full ; +assign all_fifo_full = all_dfifo_full & all_wfifo_full & all_tfifo_full; + +assign tfifo_full = |c_fifo_trig_full ; +assign dfifo_full = |c_fifo_data_full ; +assign wfifo_full = |c_fifo_wave_full ; +assign some_fifo_full = tfifo_full | dfifo_full | wfifo_full ; + +// CLOCK DOMAIN CHANGE +always_ff @(posedge c_clk_i) begin + fifo_trig_empty_cdc <= t_fifo_trig_empty; + fifo_data_empty_cdc <= t_fifo_data_empty; + fifo_wave_empty_cdc <= t_fifo_wave_empty; + c_fifo_trig_empty <= fifo_trig_empty_cdc; + c_fifo_data_empty <= fifo_data_empty_cdc; + c_fifo_wave_empty <= fifo_wave_empty_cdc; +end + +// (* ASYNC_REG = "TRUE" *) logic time_en_cdc, time_rst_cdc; +logic time_en_r, time_rst_r; +always_ff @(posedge t_clk_i) begin + // time_en_cdc <= time_en; + // time_rst_cdc <= time_rst; + time_en_r <= time_en; + time_rst_r <= time_rst; +end + +/////////////////////////////////////////////////////////////////////////////// +/// FIFO CTRL-REG +always_comb begin + c_fifo_wave_push = 0; + c_fifo_data_push = 0; + c_fifo_trig_push = 0; + if (port_we) + if (out_port_data.p_type) + if ( out_port_data.p_addr[5] == 1'b1 ) //TRIGGER Selection Bit + c_fifo_trig_push [out_port_data.p_addr[4:0] ] = 1'b1 ; //32 Possible Port Address + else // DATA + c_fifo_data_push [out_port_data.p_addr[4:0] ] = 1'b1 ; //32 Possible Port Address + else + c_fifo_wave_push [out_port_data.p_addr] = 1'b1 ; + if (core_en) begin + c_fifo_trig_push_s = c_fifo_trig_push_r; + c_fifo_data_push_s = c_fifo_data_push_r; + c_fifo_wave_push_s = c_fifo_wave_push_r; + end else begin + c_fifo_trig_push_s = '{default:'0} ; + c_fifo_data_push_s = '{default:'0} ; + c_fifo_wave_push_s = '{default:'0} ; + end +end + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + c_fifo_data_in_r <= '{default:'0} ; + c_fifo_time_in_r <= '{default:'0} ; + c_fifo_trig_push_r <= '{default:'0} ; + c_fifo_data_push_r <= '{default:'0} ; + c_fifo_wave_push_r <= '{default:'0} ; + end else if (core_en) begin + c_fifo_trig_push_r <= c_fifo_trig_push ; + c_fifo_data_push_r <= c_fifo_data_push ; + c_fifo_wave_push_r <= c_fifo_wave_push ; + if (c_fifo_trig_push | c_fifo_data_push | c_fifo_wave_push) begin + c_fifo_data_in_r <= out_port_data.p_data ; + //c_fifo_time_in_r <= {16'd0, out_port_data.p_time} + c_time_ref_dt; + c_fifo_time_in_r <= { {16{out_port_data.p_time[31]}} , out_port_data.p_time} + c_time_ref_dt; + end + end +end + + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) begin + time_abs_r <= '{default:'0} ; + trig_pop_r <= '{default:'0} ; + trig_pop_r2 <= '{default:'0} ; + data_pop_r <= '{default:'0} ; + data_pop_r2 <= '{default:'0} ; + wave_pop_r <= '{default:'0} ; + wave_pop_r2 <= '{default:'0} ; + t_fifo_trig_empty_r <= '{default:'0} ; + t_fifo_data_empty_r <= '{default:'0} ; + t_fifo_wave_empty_r <= '{default:'0} ; + end else begin + time_abs_r <= time_abs_i; + trig_pop_r <= trig_pop; + trig_pop_r2 <= trig_pop_r; + data_pop_r <= data_pop; + data_pop_r2 <= data_pop_r; + wave_pop_r <= wave_pop; + wave_pop_r2 <= wave_pop_r; + t_fifo_trig_empty_r <= t_fifo_trig_empty; + t_fifo_data_empty_r <= t_fifo_data_empty; + t_fifo_wave_empty_r <= t_fifo_wave_empty; + end +end + + +/////////////////////////////////////////////////////////////////////////////// +/// TRIGGER PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_tfifo; +generate + for (ind_tfifo=0; ind_tfifo < OUT_TRIG_QTY; ind_tfifo=ind_tfifo+1) begin: TRIG_PORT + // TRIGGER FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (1+48) , + .FIFO_AW (FIFO_DEPTH) + ) trig_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_trig_push_s[ind_tfifo] ) , + .data_i ( {c_fifo_data_in_r[0],c_fifo_time_in_r} ) , + .flush_i ( core_rst ), + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en_r ) , + .pop_i ( trig_pop_r [ind_tfifo] ) , + .data_o ( {t_fifo_trig_dt[ind_tfifo], t_fifo_trig_time[ind_tfifo]} ) , + .async_empty_o ( t_fifo_trig_empty [ind_tfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_trig_full [ind_tfifo] ) // SYNC with WR_CLK + ); + // Time Comparator + always @(posedge t_clk_i) begin + trig_t_gr_r[ind_tfifo] <= $signed({1'b0,time_abs_r}) > $signed({1'b0,t_fifo_trig_time[ind_tfifo]}); + end + // POP Generator + always_comb begin : TRIG_DISPATCHER + trig_pop[ind_tfifo] = 0; + trig_pop_prev[ind_tfifo] = |({trig_pop_r[ind_tfifo], trig_pop_r2[ind_tfifo]}); + if (time_en_r & ~t_fifo_trig_empty_r[ind_tfifo] ) + if ( trig_t_gr_r[ind_tfifo] & ~trig_pop_prev[ind_tfifo] ) + trig_pop [ind_tfifo] = 1'b1 ; + end //ALWAYS + end //FOR +endgenerate + + +/////////////////////////////////////////////////////////////////////////////// +/// WAVE PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_wfifo; +generate + for (ind_wfifo=0; ind_wfifo < OUT_WPORT_QTY; ind_wfifo=ind_wfifo+1) begin: WAVE_PORT + // WaveForm FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (168+48) , + .FIFO_AW (FIFO_DEPTH) + ) wave_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_wave_push_s [ind_wfifo] ) , + .data_i ( {c_fifo_data_in_r,c_fifo_time_in_r} ) , + .flush_i ( core_rst ), + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en_r ) , + .pop_i ( wave_pop_r [ind_wfifo] ) , + .data_o ( {t_fifo_wave_dt[ind_wfifo],t_fifo_wave_time[ind_wfifo]} ) , + .async_empty_o ( t_fifo_wave_empty [ind_wfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_wave_full [ind_wfifo] ) // SYNC with WR_CLK + ); + // Time Comparator + always @(posedge t_clk_i) begin + wave_t_gr_r[ind_wfifo] <= $signed({1'b0,time_abs_r}) > $signed({1'b0,t_fifo_wave_time[ind_wfifo]}); + end + // POP Generator + always_comb begin : WAVE_DISPATCHER + wave_pop[ind_wfifo] = 0; + wave_pop_prev[ind_wfifo] = |({wave_pop_r[ind_wfifo], wave_pop_r2[ind_wfifo]}); + if (time_en & ~t_fifo_wave_empty_r[ind_wfifo]) + if ( wave_t_gr_r[ind_wfifo] & ~wave_pop_prev[ind_wfifo] ) + wave_pop [ind_wfifo] = m_axis_tready[ind_wfifo] ; + end //ALWAYS + end // FOR +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +/// DATA PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_dfifo; +generate + for (ind_dfifo=0; ind_dfifo < OUT_DPORT_QTY; ind_dfifo=ind_dfifo+1) begin: DATA_PORT + // DATA FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (OUT_DPORT_DW+48) , + .FIFO_AW (FIFO_DEPTH) + ) data_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_data_push_s[ind_dfifo] ) , + .data_i ( {c_fifo_data_in_r[OUT_DPORT_DW-1:0],c_fifo_time_in_r} ) , + .flush_i ( core_rst ), + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en_r ) , + .pop_i ( data_pop_r [ind_dfifo] ) , + .data_o ( {t_fifo_data_dt[ind_dfifo], t_fifo_data_time[ind_dfifo]} ) , + .async_empty_o ( t_fifo_data_empty [ind_dfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_data_full [ind_dfifo] ) // SYNC with WR_CLK + ); + // Time Comparator + always @(posedge t_clk_i) begin + data_t_gr_r[ind_dfifo] <= $signed({1'b0,time_abs_r}) > $signed({1'b0,t_fifo_data_time[ind_dfifo]}); + end + // POP Generator + always_comb begin : DATA_DISPATCHER + data_pop[ind_dfifo] = 0; + data_pop_prev[ind_dfifo] = |({data_pop_r[ind_dfifo], data_pop_r2[ind_dfifo]}); + if (time_en_r & ~t_fifo_data_empty_r[ind_dfifo] ) + if ( data_t_gr_r[ind_dfifo] & ~data_pop_prev[ind_dfifo] ) + data_pop [ind_dfifo] = 1'b1 ; + end //ALWAYS + end //FOR +endgenerate + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// OUT TRIGGERS +reg port_trig_r [OUT_TRIG_QTY]; +integer ind_tport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_tport=0; ind_tport < OUT_TRIG_QTY; ind_tport=ind_tport+1) begin: OUT_TRIG_PORT + if (!t_rst_ni) + port_trig_r[ind_tport] <= 1'b0; + else if (time_rst_r) + port_trig_r[ind_tport] <= 1'b0; + else + if (trig_pop[ind_tport]) + port_trig_r[ind_tport] <= t_fifo_trig_dt[ind_tport] ; + end +end +assign port_trig_o = port_trig_r; + +/////////////////////////////////////////////////////////////////////////////// +// OUT DATA +reg [OUT_DPORT_DW-1:0] port_dt_r [OUT_DPORT_QTY]; +integer ind_dport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_dport=0; ind_dport < OUT_DPORT_QTY; ind_dport=ind_dport+1) begin: OUT_DATA_PORT + if (!t_rst_ni) + port_dt_r[ind_dport] <= '{default:'0} ; + else if (time_rst_r) + port_dt_r[ind_dport] <= '{default:'0} ; + else + if (data_pop[ind_dport]) + port_dt_r[ind_dport] <= t_fifo_data_dt[ind_dport] ; + end +end +assign port_tvalid_o = data_pop_r; +assign port_tdata_o = port_dt_r; + + +/////////////////////////////////////////////////////////////////////////////// +// OUT WAVES +// REGISTERED OUTPUT +reg m_axis_tvalid_r [ OUT_WPORT_QTY] ; +reg [167:0] m_axis_tdata_r [ OUT_WPORT_QTY] ; +integer ind_wport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_wport=0; ind_wport < OUT_WPORT_QTY; ind_wport=ind_wport+1) begin: OUT_WAVE_PORT + if (!t_rst_ni) begin + m_axis_tvalid_r[ind_wport] <= 1'b0 ; + m_axis_tdata_r [ind_wport] <= '{default:'0} ; + end else if (time_rst_r) begin + m_axis_tvalid_r[ind_wport] <= 1'b0 ; + m_axis_tdata_r [ind_wport] <= '{default:'0} ; + end else begin + if (wave_pop[ind_wport]) begin + m_axis_tvalid_r[ind_wport] <= 1'b1; + end + else if (m_axis_tready[ind_wport]) begin + m_axis_tvalid_r[ind_wport] <= 1'b0; + end + m_axis_tdata_r[ind_wport] <= t_fifo_wave_dt [ind_wport] ; + end + end +end + +assign m_axis_tvalid = m_axis_tvalid_r ; +assign m_axis_tdata = m_axis_tdata_r ; + +///// DEBUG + assign fifo_dt_do = {t_fifo_data_time[0][27:0], t_fifo_data_dt[0][3:0]} ; + + assign axi_fifo_do[31:28] = t_fifo_data_dt[0][3:0] ; + assign axi_fifo_do[27:12] = t_fifo_data_time[0][15:0] ; + assign axi_fifo_do[11: 8] = { some_fifo_full , wfifo_full , dfifo_full , tfifo_full }; + assign axi_fifo_do[ 7: 4] = { all_fifo_full , all_wfifo_full , all_dfifo_full, all_tfifo_full }; + assign axi_fifo_do[ 3: 0] = { all_fifo_empty, all_wfifo_empty, all_dfifo_empty, all_tfifo_empty }; + + assign c_fifo_do[15:11] = { c_fifo_wave_push_s[0],c_fifo_data_push_s[1],c_fifo_data_push_s[0],c_fifo_trig_push_s[1],c_fifo_trig_push_s[0]}; + assign c_fifo_do[10: 9] = { c_fifo_wave_full[1], c_fifo_wave_full[0] }; + assign c_fifo_do[ 8: 7] = { c_fifo_data_full[1], c_fifo_data_full[0] }; + assign c_fifo_do[ 6: 5] = { c_fifo_trig_full[1], c_fifo_trig_full[0] }; + assign c_fifo_do[ 4: 0] = { all_fifo_full, all_wfifo_full, all_dfifo_full, all_tfifo_full, 1'b0 }; + + assign t_fifo_do[15:11] = { wave_pop_r[0], data_pop_r[1], data_pop_r[0], trig_pop_r[1], trig_pop_r[0] } ; + assign t_fifo_do[10: 9] = { c_fifo_wave_empty[1], c_fifo_wave_empty[0] }; + assign t_fifo_do[ 8: 7] = { c_fifo_data_empty[1], c_fifo_data_empty[0] }; + assign t_fifo_do[ 6: 5] = { c_fifo_trig_empty[1], c_fifo_trig_empty[0] }; + assign t_fifo_do[ 4: 0] = { all_fifo_empty, all_wfifo_empty, all_dfifo_empty, all_tfifo_empty, 1'b0 }; +endmodule + diff --git a/firmware/ip/qick_processor/src/qproc_inport_reg.sv b/firmware/ip/qick_processor/src/qproc_inport_reg.sv new file mode 100644 index 000000000..534c2821b --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_inport_reg.sv @@ -0,0 +1,60 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 11-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + This block register the input of the sAxi. + Indicates the arrival of new data in port_tnew_o +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qproc_inport_reg # ( + parameter PORT_QTY = 2 +)( +// CLK & RST. + input wire c_clk_i , + input wire c_rst_ni , + input wire c_clear , +// DATA INPUT INTERFACE + input wire port_tvalid_i [ PORT_QTY ] , + input wire [63:0] port_tdata_i [ PORT_QTY ] , +// DATA OUTPUT INTERFACE + output wire [15:0 ] port_tnew_o , + output wire [63:0] port_tdata_o [ PORT_QTY ] + ); + +localparam ZFP = 16 - PORT_QTY; // Zero Fill for Input Port + + +// REGISTR INPUTS +reg [63:0] port_dt_r [PORT_QTY] ; +reg [PORT_QTY-1:0] port_dt_new ; + +genvar ind; +generate + for (ind=0; ind < PORT_QTY; ind=ind+1) begin + always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + port_dt_r[ind] <= 0 ; + port_dt_new[ind] <= 0 ; + end else begin + if ( port_tvalid_i[ind] ) begin + port_dt_r[ind] <= port_tdata_i[ind]; + port_dt_new[ind] <= 1'b1; + end else if (c_clear) + port_dt_new[ind] <= 0 ; + end + end +endgenerate + +assign port_tnew_o = { {ZFP{1'b0}} , port_dt_new }; + +assign port_tdata_o = port_dt_r ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_mem_ctrl.v b/firmware/ip/qick_processor/src/qproc_mem_ctrl.v new file mode 100644 index 000000000..109524fd6 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_mem_ctrl.v @@ -0,0 +1,224 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +// Assembled memory access module. Three modes of accessing the memory: +// +// * Single access using the in/out ports. It's only available when busy_o = 0. +// +// * AXIS read: this mode allows to send data using m_axis_* interface, using +// ADDR_REG as the starting address and LEN_REG to indicate the number of +// samples to be transferred. The last sample will assert m_axis_tlast_o to +// indicate the external block transaction is done. Similar to AXIS write +// mode, the user needs to set START_REG = 1 to start the process. +// +// * AXIS write: this mode receives data from s_axis_* interface and writes +// into the memory using ADDR_REG as the starting address. The user must also +// provide the START_REG = 1 to allow starting receiving data. The block will +// rely on s_axis_tlast_i = 1 to finish the writing process. +// +// When not performing any AXIS transaction, the block will grant access to +// the memory using the single access interface. This is a very basic +// handshake interface to allow external blocks to easily communicate and +// perform single-access transaction. +// +// Once a AXIS transaction is done, the user must set START_REG = 0 and back +// to 1 if a new AXIS transaction needs to be executed. START_REG = 1 steady +// will not allow further AXIS transactions, and will only allow +// single-access. +// +// Registers: +// +// MODE_REG : indicates the type of the next AXIS transaction. +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// START_REG : starts execution of indicated AXIS transaction. +// * 0 : Stop. +// * 1 : Execute Operation. +// +// ADDR_REG : starting memory address for either AXIS read or write. +// +// LEN_REG : number of samples to be transferred in AXIS read mode. +// +*/ +////////////////////////////////////////////////////////////////////////////// + +module qproc_mem_ctrl # ( + parameter PMEM_AW = 16 , + parameter DMEM_AW = 16 , + parameter WMEM_AW = 16 +)( + // CLK & RST. + input wire ps_clk_i , + input wire ps_rst_ni , +// EXTERNAL MEMORY ACCESS + output wire [1:0] ext_core_sel_o , + output wire [1:0] ext_mem_sel_o , //00-NONE 01-PMEM 10-DMEM 11-WMEM + output wire ext_mem_we_o , + output wire [15:0] ext_mem_addr_o , + output wire [167:0] ext_mem_w_dt_o , + input wire [167:0] ext_mem_r_dt_i , +// AXIS Slave + input wire [255:0] s_axis_tdata_i , + input wire s_axis_tlast_i , + input wire s_axis_tvalid_i, + output wire s_axis_tready_o, +// AXIS Master for sending data. + output wire [255:0] m_axis_tdata_o , + output wire m_axis_tlast_o , + output wire m_axis_tvalid_o, + input wire m_axis_tready_i, +//Control Regiters + input wire [6 :0] MEM_CTRL , + input wire [15:0] MEM_ADDR , + input wire [15:0] MEM_LEN , + input wire [31:0] MEM_DT_I , + output wire [31:0] MEM_DT_O , + output wire [31:0] DEBUG_O ); + +// SIGNALS +wire ar_exec, ar_end ; +wire aw_exec, aw_end ; +wire mem_start, mem_op, mem_source ; +wire [1:0] mem_sel ; +wire mem_we_single, mem_we_axis; +wire [31:0] mem_w_dt_single; +wire [255:0] mem_w_dt_axis; +wire [15:0] mem_w_addr_axis, mem_r_addr_axis ; +wire [15:0] axis_addr, mem_addr_single, ext_mem_addr; +wire [1:0] core_sel; + +assign mem_start = MEM_CTRL[ 0 ] ; // 1-Start Go to 0 For Next +assign mem_op = MEM_CTRL[ 1 ] ; // 0-READ , 1-WRITE +assign mem_sel = MEM_CTRL[3:2] ; // 01-Pmem , 10-Dmem , 11-Wmem +assign mem_source = MEM_CTRL[ 4 ] ; // 0-AXIS, 1-REGISTERS (Single) +assign core_sel = MEM_CTRL[6:5] ; // Core Selection + +wire start_single; +assign start_axis = mem_start & ~mem_source ; +assign start_single = mem_start & mem_source ; + +assign axis_addr = mem_op ? mem_w_addr_axis : mem_r_addr_axis ; +assign ext_mem_addr = mem_source ? mem_addr_single : axis_addr ; + +// Registe-READ ONLY with DMEM +assign dmem_we_single = mem_we_single & mem_sel == 2'b10; + + +// Data AXI-Read Format (From ext_mem_r_dt_i to mem_r_dt_axis ) +wire [255:0] mem_r_dt_axis; + +assign mem_r_dt_axis = (mem_sel == 2'b01)? {184'd0, ext_mem_r_dt_i } : //PMEM + (mem_sel == 2'b10)? {224'd0, ext_mem_r_dt_i }: //DMEM + (mem_sel == 2'b11)? { 80'd0, ext_mem_r_dt_i[167:88],8'd0, ext_mem_r_dt_i[87:0]}: // WMEM + 0; + +// Data AXI-Write Format ( From mem_w_dt_axis TO ext_mem_w_dt_o ) +wire [71 :0] ext_pmem_w_dt; +wire [31 :0] ext_dmem_w_dt; +wire [167:0] ext_wmem_w_dt; + +wire [31 :0] freq, phase, env, gain, lenght, conf; +assign freq = mem_w_dt_axis[ 31 : 0] ; // 32-bit FREQ +assign phase = mem_w_dt_axis[ 63 : 32] ; // 32-bit PHASE +assign env = mem_w_dt_axis[ 95 : 64] ; // 32-bit ENV +assign gain = mem_w_dt_axis[127 : 96] ; // 32-bit GAIN +assign lenght = mem_w_dt_axis[159 :128] ; // 32-bit LENGHT +assign conf = mem_w_dt_axis[191 :160] ; // 32-bit CONF + + +assign ext_pmem_w_dt = mem_w_dt_axis[71:0]; +assign ext_dmem_w_dt = mem_source ? mem_w_dt_single : mem_w_dt_axis[31:0] ; +assign ext_wmem_w_dt = {conf[15:0], lenght, gain, env[23:0], phase, freq} ; + +assign ext_mem_w_dt_o = (mem_sel == 2'b01)? ext_pmem_w_dt : + (mem_sel == 2'b10)? ext_dmem_w_dt : + (mem_sel == 2'b11)? ext_wmem_w_dt : + 0; + + +// OUTPUTS +assign ext_core_sel_o = core_sel; +assign ext_mem_sel_o = mem_sel; +assign ext_mem_we_o = dmem_we_single | mem_we_axis ; +assign ext_mem_addr_o = ext_mem_addr; + + +data_mem_ctrl #( + .N(16) + ) data_mem_ctrl_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .sel_o ( ) , + .ar_exec_o ( ar_exec ) , + .ar_exec_ack_i ( ar_end ) , + .aw_exec_o ( aw_exec ) , + .aw_exec_ack_i ( aw_end ) , + .busy_o ( busy_o ) , + .mem_op_i ( mem_op ) , + .mem_start_i ( start_axis ) ); + +mem_rw #( + .N( 16 ), + .B( 32 ) +) mem_rw_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .rw_i ( mem_op ) , + .exec_i ( start_single ) , + .exec_ack_o ( end_single_o ) , + .addr_i ( MEM_ADDR ) , + .di_i ( MEM_DT_I ) , + .do_o ( MEM_DT_O ) , + .mem_we_o ( mem_we_single ) , + .mem_di_o ( mem_w_dt_single ) , + .mem_do_i ( ext_mem_r_dt_i[31:0] ) , + .mem_addr_o ( mem_addr_single ) ); + +axis_read #( + .N( 16 ), + .B( 256 ) +) axis_read_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .addr_i ( MEM_ADDR ) , + .len_i ( MEM_LEN ) , + .exec_i ( ar_exec ) , + .exec_ack_o ( ar_end ) , + .mem_we_o ( ) , + .mem_addr_o ( mem_r_addr_axis ) , + .mem_do_i ( mem_r_dt_axis ) , + .m_axis_tready_i ( m_axis_tready_i ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) ); + +axis_write #( + .N( 16 ), + .B( 256 ) +) axis_write_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .s_axis_tdata_i ( s_axis_tdata_i ) , + .s_axis_tlast_i ( s_axis_tlast_i ) , + .s_axis_tvalid_i ( s_axis_tvalid_i ) , + .s_axis_tready_o ( s_axis_tready_o ) , + .mem_we_o ( mem_we_axis ) , + .mem_di_o ( mem_w_dt_axis ) , + .mem_addr_o ( mem_w_addr_axis ) , + .exec_i ( aw_exec ) , + .exec_ack_o ( aw_end ) , + .addr_i ( MEM_ADDR ) ); + +assign DEBUG_O[31:24] = 8'd0; +assign DEBUG_O[23:16] = {mem_op, core_sel, mem_source,mem_sel, ar_exec, aw_exec} ; +assign DEBUG_O[15:8] = ext_mem_addr [7:0] ; +assign DEBUG_O[7:0] = ext_mem_w_dt_o[7:0] ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_time_ctrl.sv b/firmware/ip/qick_processor/src/qproc_time_ctrl.sv new file mode 100644 index 000000000..ee24bb5c6 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_time_ctrl.sv @@ -0,0 +1,127 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 11-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + Controls the Time Counter. time_abs_o +*/ +////////////////////////////////////////////////////////////////////////////// + +module qproc_time_ctrl ( + input wire t_clk_i , + input wire t_rst_ni , + input wire time_en_i , // Time RUNS + input wire time_rst_i , // Set Time to 0 + input wire time_init_i , // Set Time to current OFFSET + input wire time_updt_i , // Increment Time updt_dt_i + input wire [31:0] updt_dt_i , + output wire [47:0] time_abs_o ); + +// Time ABS +/////////////////////////////////////////////////////////////////////////////// +(* use_dsp = "yes" *) reg [47:0] time_abs; + +wire[47:0] time_update_dt; +assign time_update_dt = { { 16{updt_dt_i[31]} } ,updt_dt_i}; //Sign Extend updt_dt_i + + +enum {ST_IDLE, ST_RESET, ST_INIT, ST_LOAD_OFFSET, ST_INCREMENT, ST_UPDATE } ctrl_time_st, ctrl_time_st_nxt; + +////////// Sequential Logic +always @ (posedge t_clk_i) begin : CTRL_SYNC_PROC + if (!t_rst_ni) ctrl_time_st <= ST_IDLE; + else ctrl_time_st <= ctrl_time_st_nxt; +end + +////////// Comb Logic - Outputs and State +reg [47:0] time_inc; +reg [47:0] initial_offset; +wire [47:0] updated_offset ; +reg time_cnt_en, time_c_in; + +wire time_cnt_rst; +assign time_cnt_rst = time_rst_i | time_init_i ; + + +always_comb begin : CTRL_ST_AND_OUTPUT_DECODE + time_cnt_en = 1'b0; + time_inc = 48'd0; + time_c_in = 1'b0; + + ctrl_time_st_nxt = ctrl_time_st; // Default Current State + case (ctrl_time_st) + ST_IDLE : begin + if ( time_rst_i ) ctrl_time_st_nxt = ST_RESET; + else if ( time_init_i ) ctrl_time_st_nxt = ST_INIT; + else if ( time_updt_i ) ctrl_time_st_nxt = ST_UPDATE; + else if ( time_en_i ) ctrl_time_st_nxt = ST_INCREMENT; + end + ST_RESET : begin + if ( time_en_i ) + ctrl_time_st_nxt = ST_INCREMENT; + else + ctrl_time_st_nxt = ST_IDLE; + end + ST_INIT : begin + time_cnt_en = 1'b1; + ctrl_time_st_nxt = ST_LOAD_OFFSET; + end + ST_LOAD_OFFSET : begin + time_cnt_en = 1'b1; + time_inc = updt_dt_i ; + ctrl_time_st_nxt = ST_INCREMENT; + end + ST_INCREMENT : begin + time_cnt_en = 1'b1; + time_inc = 48'd1 ; + if ( time_rst_i ) ctrl_time_st_nxt = ST_RESET; + else if ( time_init_i ) ctrl_time_st_nxt = ST_INIT; + else if ( time_updt_i ) ctrl_time_st_nxt = ST_UPDATE; + else if ( !time_en_i ) ctrl_time_st_nxt = ST_IDLE; + end + ST_UPDATE : begin + time_cnt_en = 1'b1; + time_inc = time_update_dt ; + time_c_in = 1'b1; + ctrl_time_st_nxt = ST_INCREMENT; + end + default:; + endcase +end + + // Time Operation + ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY ( 1 ), // Desired clock cycle latency, 0-2 + .WIDTH ( 48 ) // Input / output bus width, 1-48 + ) TIME_ADDER ( + .CARRYOUT ( ), // 1-bit carry-out output signal + .RESULT ( time_abs ), // Add/sub result output, width defined by WIDTH parameter + .B ( time_abs ), // Input A bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b1 ), // 1-bit add/sub input, high selects add, low selects subtract + .A ( time_inc ), // Input B bus, width defined by WIDTH parameter + .CARRYIN ( time_c_in ), // 1-bit carry-in input + .CE ( time_cnt_en | time_cnt_rst ), // 1-bit clock enable input + .CLK ( t_clk_i ), // 1-bit clock input + .RST ( time_cnt_rst ) // 1-bit active high synchronous reset + ); + +//// Time Operation +// NOTE: code to infer the DSP, although not sure if it does exactly the same +//always @ (posedge t_clk_i) begin +// if (time_cnt_rst) begin +// time_abs <= 'd0; +// end +// else if (time_cnt_en) begin +// time_abs <= $signed({1'b0,time_abs}) + $signed(time_inc); +// end +//end + +assign time_abs_o = time_abs; + +endmodule + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo new file mode 100644 index 000000000..5653a7928 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho new file mode 100644 index 000000000..4ca178885 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci new file mode 100644 index 000000000..156d86e66 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": 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] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "address_spaces": { + "Master_AXI": { + "range": "4294967296", + "width": "32" + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xml b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xml new file mode 100644 index 000000000..70dc7a1c4 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4743 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + 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+ 0 + + + + + + true + + + + + + m_axi_buser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_bvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_bready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arid + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_araddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arlock + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arregion + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.h + systemCSource + true + + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.h + systemCSource + true + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.h + systemCSource + true + axi_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/qick_processor/src/tb/dmem_issue35.mem b/firmware/ip/qick_processor/src/tb/dmem_issue35.mem new file mode 100644 index 000000000..5b9462ddc --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/dmem_issue35.mem @@ -0,0 +1,2 @@ +// DMEM content +00000000 diff --git a/firmware/ip/qick_processor/src/tb/prog.bin b/firmware/ip/qick_processor/src/tb/prog.bin new file mode 100644 index 000000000..7c3e52190 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/prog.bin @@ -0,0 +1,32 @@ +// TPROC Program Memory File +//H_ADF__CND__S_T_F_WR_OP___| immAddr/rsA0__Port/rsA1_| rsD0__ rsD1__ ImmData__| rDest +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +100_011__000__11__0_00_00______00000000000__000000__________00000000000000001111111111000010__0000001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000001011010000__0100001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000000000110000__0000010 //REG_WR +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +100_010__000__00__0__1100______00000000000__000000____0_0000001_____000000000000000000000000__0101110 //REG_WR +010_001__000___010___0000___00000___000000__000000____0_0101110__0_0100001__0000000000000000__0000000 //ARITH +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +100_010__000__00__0__1010______00000000000__000000____0_0000011_____000000000000000000000000__0101111 //REG_WR +101_001__000__0_0_0_00_00___00000___100000__000000____0_0101111__0_0000000__0000000000000000__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000000101_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_111__000__10__0_00_00_______00000011010_000000__________00000000000000000000000000000000__0000000 //CALL +100_011__000__11__0_00_00______00000000000__000000__________00000000000000001111111111100001__0000001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000001011010000__0100001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000000000110000__0000010 //REG_WR +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +100_010__000__00__0__0100______00000000000__000000____0_0000001_____000000000111111111111111__0101110 //REG_WR +010_001__000___010___0000___00000___000000__000000____0_0101110__0_0100001__0000000000000000__0000000 //ARITH +001_111__110__00__0_00_00_______00000010110_000000__________00000000000000000000000000000000__0000000 //JUMP +101_010__000__0_0_0_00_11___00000___100000__000000____0_0000011_____000000000000000000001111__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000010100_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_111__000__00__0_00_00_______00000011001_000000__________00000000000000000000000000000000__0000000 //JUMP +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +101_011__000__0_1_0_00_00___00000___100000__000000__________00000000000000000000000000000000__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000011011_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_011__000__11__0_00_00_______00000000000_000000__________00000000000000000000000000000000__0000000 //RET diff --git a/firmware/ip/qick_processor/src/tb/prog_issue35.mem b/firmware/ip/qick_processor/src/tb/prog_issue35.mem new file mode 100644 index 000000000..335f88c93 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/prog_issue35.mem @@ -0,0 +1,36 @@ +// PMEM content +000000000000000000 +8c600000000000000c +8c600000000000000e +dcc001040000000000 +4c080000000000c000 +8c6000000000000020 +8c600000000000398e +dd8000300000000000 +dd8000348000000000 +dd8000350000000000 +88000000070000050e +dd8000100000000000 +dd8000148000000000 +dd8000150000000000 +8c600000000000000e +dcc000000000000000 +dcc000200000000000 +dcc000400000000000 +8c6000000000004d0e +dcc000600000000000 +8c600000000000998e +dcc000800000000000 +8c600000000000e68e +dcc000a00000000000 +dcc000c00000000000 +dcc000e00000000000 +8c600000000001330e +dcc000600000000000 +08110000058001a180 +39110380058001a180 +4c0800000000020680 +88000000060000008c +081100001000000000 +398800c010000000a0 +3c0004400000000000 diff --git a/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv b/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv new file mode 100644 index 000000000..2fa530d7b --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv @@ -0,0 +1,1018 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +Test Bench for Qick Processor Testing +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + + + +//`define T_TCLK 1.953125 // Half Clock Period for Simulation +`define T_TCLK 1.302 // Half Clock Period for Simulation +`define T_CCLK 2.5 // Half Clock Period for Simulation +`define T_SCLK 5 // Half Clock Period for Simulation + + +`define GEN_SYNC 1 +`define DUAL_CORE 0 +`define IO_CTRL 0 +`define DEBUG 3 +`define TNET 0 +`define QCOM 0 +`define CUSTOM_PERIPH 1 +`define LFSR 1 +`define DIVIDER 1 +`define ARITH 1 +`define TIME_READ 1 +`define FIFO_DEPTH 9 +`define PMEM_AW 8 +`define DMEM_AW 10 +`define WMEM_AW 4 +`define REG_AW 4 +`define IN_PORT_QTY 2 +`define OUT_TRIG_QTY 8 +`define OUT_DPORT_QTY 1 +`define OUT_DPORT_DW 4 +`define OUT_WPORT_QTY 3 + + +module tb_axis_qick_processor (); + +/////////////////////////////////////////////////////////////////////////////// + + + +//wire [31:0] port_data_o [`OUT_WPORT_QTY] ; +//wire m_axis_tvalid [`OUT_WPORT_QTY] ; +//wire m_axis_tdata [`OUT_WPORT_QTY] ; + + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +xil_axi_resp_t resp; +//AXI-LITE +//wire s_axi_aclk ; +wire s_ps_dma_aresetn ; +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +reg c_clk, t_clk, s_ps_dma_aclk, rst_ni; + +initial begin + t_clk = 1'b0; + forever # (`T_TCLK) t_clk = ~t_clk; +end + +initial begin + c_clk = 1'b0; + forever # (`T_CCLK) c_clk = ~c_clk; +end + +initial begin + s_ps_dma_aclk = 1'b0; + #0.5 + forever # (`T_SCLK) s_ps_dma_aclk = ~s_ps_dma_aclk; +end + + assign s_ps_dma_aresetn = rst_ni; + + + + + +reg [255:0] max_value ; +reg axis_dma_start ; + + + + +reg [255 :0] s_dma_axis_tdata_i ; +reg s_dma_axis_tlast_i ; +reg s_dma_axis_tvalid_i ; +reg m_dma_axis_tready_i ; +wire [63 :0] port_0_dt_i ; +reg [63 :0] port_1_dt_i ; +reg s_axi_aclk ; +reg s_axi_aresetn ; + + + +reg axis_aclk ; +reg axis_aresetn ; +reg m0_axis_tready =0 ; +reg m1_axis_tready =0 ; +reg m2_axis_tready =0 ; +reg m3_axis_tready =0 ; +reg m4_axis_tready =0 ; +reg m5_axis_tready =0 ; +reg m6_axis_tready =0 ; +reg m7_axis_tready =0 ; + +wire s_dma_axis_tready_o ; +wire [255 :0] m_dma_axis_tdata_o ; +wire m_dma_axis_tlast_o ; +wire m_dma_axis_tvalid_o ; + +wire [167:0] m0_axis_tdata ; +wire m0_axis_tvalid ; +wire [167:0] m1_axis_tdata ; +wire m1_axis_tvalid ; +wire [167:0] m2_axis_tdata ; +wire m2_axis_tvalid ; +wire [167:0] m3_axis_tdata ; +wire m3_axis_tvalid ; +wire [167:0] m4_axis_tdata ; +wire m4_axis_tvalid ; +wire [167:0] m5_axis_tdata ; +wire m5_axis_tvalid ; +wire [167:0] m6_axis_tdata ; +wire m6_axis_tvalid ; +wire [167:0] m7_axis_tdata ; +wire m7_axis_tvalid ; +wire [`OUT_DPORT_DW-1:0] port_0_dt_o, port_1_dt_o, port_2_dt_o, port_3_dt_o ; + +wire qnet_en_o ; +wire [4 :0] qnet_op_o ; +wire [31:0] qnet_a_dt_o ; +wire [31:0] qnet_b_dt_o ; +wire [31:0] qnet_c_dt_o ; +wire [31:0] qnet_d_dt_o ; +reg qnet_rdy_i ; +reg [31 :0] qnet_dt_i [2] ; +reg [31 :0] qcom_dt_i [2] ; +reg [31 :0] qp1_dt_i [2] ; +reg [31 :0] qp2_dt_i [2] ; + +wire periph_en_o ; +wire [4 :0] periph_op_o ; +wire [31:0] periph_a_dt_o ; +wire [31:0] periph_b_dt_o ; +wire [31:0] periph_c_dt_o ; +wire [31:0] periph_d_dt_o ; +reg periph_rdy_i ; +reg [31 :0] periph_dt_i [2] ; + + +reg s0_axis_tvalid , s1_axis_tvalid ; +reg [15:0] waves, wtime; +reg [31:0] axi_dt; + + +int val_A, val_B, val_C, val_D, result ; +reg [31:0] result_r, result_2r, result_3r ; + +always_ff @ (posedge c_clk) begin + result_r <= result; + result_2r <= result_r; + result_3r <= result_2r; +end + +// Register ADDRESS +parameter REG_TPROC_CTRL = 0 * 4 ; +parameter REG_TPROC_CFG = 1 * 4 ; +parameter REG_MEM_ADDR = 2 * 4 ; +parameter REG_MEM_LEN = 3 * 4 ; +parameter REG_MEM_DT_I = 4 * 4 ; +parameter REG_AXI_W_DT1 = 5 * 4 ; +parameter REG_AXI_W_DT2 = 6 * 4 ; +parameter REG_CORE_CFG = 7 * 4 ; +parameter REG_AXI_DT_SRC = 8 * 4 ; +parameter REG_MEM_DT_O = 10 * 4 ; +parameter REG_AXI_R_DT1 = 11 * 4 ; +parameter REG_AXI_R_DT2 = 12 * 4 ; +parameter REG_TIME_USR = 13 * 4 ; +parameter REG_TPROC_STATUS = 14 * 4 ; +parameter REG_TPROC_DEBUG = 15 * 4 ; + + + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_ps_dma_aclk ), + .aresetn (s_ps_dma_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + +reg proc_start_i, proc_stop_i ; +reg core_start_i, core_stop_i ; +reg time_rst_i, time_init_i, time_updt_i; + +reg [47:0] offset_dt_i ; +wire [47:0] t_time_abs_o ; +reg time_updt_i; + +wire [31:0] ps_debug_do; + +reg qp1_en_r; +reg [31:0] qp1_a_dt_r, qp1_b_dt_r; +wire [31:0] qp1_a_dt_o, qp1_b_dt_o, qp1_c_dt_o, qp1_d_dt_o; +always_ff @ (posedge c_clk) begin + qp1_en_r <= qp1_en_o; + qp1_a_dt_r <= qp1_a_dt_o; + qp1_b_dt_r <= qp1_b_dt_o; +end + +assign qp1_rdy_i = ~qp1_en_r; +assign qp1_dt_i[0] = qp1_a_dt_r; +assign qp1_dt_i[1] = qp1_b_dt_r; +assign qp1_vld_i = qp1_en_r ; + + +axis_qick_processor # ( + .DUAL_CORE ( `DUAL_CORE ) , + .GEN_SYNC ( `GEN_SYNC ) , + .IO_CTRL ( `IO_CTRL ) , + .DEBUG ( `DEBUG ) , + .TNET ( `TNET ) , + .QCOM ( `QCOM ) , + .CUSTOM_PERIPH ( `CUSTOM_PERIPH ) , + .LFSR ( `LFSR ) , + .DIVIDER ( `DIVIDER ) , + .ARITH ( `ARITH ) , + .TIME_READ ( `TIME_READ ) , + .FIFO_DEPTH ( `FIFO_DEPTH ) , + .PMEM_AW ( `PMEM_AW ) , + .DMEM_AW ( `DMEM_AW ) , + .WMEM_AW ( `WMEM_AW ) , + .REG_AW ( `REG_AW ) , + .IN_PORT_QTY ( `IN_PORT_QTY ) , + .OUT_TRIG_QTY ( `OUT_TRIG_QTY ) , + .OUT_DPORT_QTY ( `OUT_DPORT_QTY ) , + .OUT_DPORT_DW ( `OUT_DPORT_DW ) , + .OUT_WPORT_QTY ( `OUT_WPORT_QTY ) +) AXIS_QPROC ( + .t_clk_i ( t_clk ) , + .t_resetn ( rst_ni ) , + .c_clk_i ( c_clk ) , + .c_resetn ( rst_ni ) , + .ps_clk_i ( s_ps_dma_aclk ) , + .ps_resetn ( s_ps_dma_aresetn ) , + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_i ) , + .proc_stop_i ( proc_stop_i ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_dt_i ( offset_dt_i ) , + .t_time_abs_o ( t_time_abs_o ) , + .ps_debug_do ( ps_debug_do ) , + + .qnet_en_o ( qnet_en_o ) , + .qnet_op_o ( qnet_op_o ) , + .qnet_a_dt_o ( qnet_a_dt_o ) , + .qnet_b_dt_o ( qnet_b_dt_o ) , + .qnet_c_dt_o ( qnet_c_dt_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt1_i ( qnet_dt_i[0] ) , + .qnet_dt2_i ( qnet_dt_i[1] ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + + .qcom_en_o ( qcom_en_o ) , + .qcom_op_o ( qcom_op_o ) , + .qcom_dt_o ( qcom_dt_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt1_i ( qcom_dt_i[0] ) , + .qcom_dt2_i ( qcom_dt_i[1] ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + + .qp1_en_o ( qp1_en_o ) , + .qp1_op_o ( qp1_op_o ) , + .qp1_a_dt_o ( qp1_a_dt_o ) , + .qp1_b_dt_o ( qp1_b_dt_o ) , + .qp1_c_dt_o ( qp1_c_dt_o ) , + .qp1_d_dt_o ( qp1_d_dt_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt1_i ( qp1_dt_i[0] ) , + .qp1_dt2_i ( qp1_dt_i[1] ) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + + .qp2_en_o ( qp2_en_o ) , + .qp2_op_o ( qp2_op_o ) , + .qp2_a_dt_o ( qp2_a_dt_o ) , + .qp2_b_dt_o ( qp2_b_dt_o ) , + .qp2_c_dt_o ( qp2_c_dt_o ) , + .qp2_d_dt_o ( qp2_d_dt_o ) , + .qp2_rdy_i ( qpb_rdy_i ) , + .qp2_dt1_i ( qp2_dt_i[0] ) , + .qp2_dt2_i ( qp2_dt_i[1] ) , + .qp2_vld_i ( qp2_vld_i ) , + + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , + .s0_axis_tdata ( port_0_dt_i ) , + .s0_axis_tvalid ( port_0_vld ) , + .s1_axis_tdata ( port_1_dt_i ) , + .s1_axis_tvalid ( s1_axis_tvalid ) , + .s2_axis_tdata ( 64'd2 ) , + .s2_axis_tvalid ( 1'b0 ) , + .s3_axis_tdata ( 64'd3 ) , + .s3_axis_tvalid ( 1'b0 ) , + .s4_axis_tdata ( 64'd4 ) , + .s4_axis_tvalid ( 1'b0 ) , + .s5_axis_tdata ( 64'd5 ) , + .s5_axis_tvalid ( 1'b0 ) , + .s6_axis_tdata ( 64'd6 ) , + .s6_axis_tvalid ( 1'b0 ) , + .s7_axis_tdata ( 64'd7 ) , + .s7_axis_tvalid ( 1'b0 ) , + .s_axi_awaddr ( s_axi_awaddr[7:0] ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr[7:0] ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .m0_axis_tdata ( m0_axis_tdata ) , + .m0_axis_tvalid ( m0_axis_tvalid ) , + .m0_axis_tready ( m0_axis_tready ) , + .m1_axis_tdata ( m1_axis_tdata ) , + .m1_axis_tvalid ( m1_axis_tvalid ) , + .m1_axis_tready ( m1_axis_tready ) , + .m2_axis_tdata ( m2_axis_tdata ) , + .m2_axis_tvalid ( m2_axis_tvalid ) , + .m2_axis_tready ( m2_axis_tready ) , + .m3_axis_tdata ( m3_axis_tdata ) , + .m3_axis_tvalid ( m3_axis_tvalid ) , + .m3_axis_tready ( m3_axis_tready ) , + .m4_axis_tdata ( m4_axis_tdata ) , + .m4_axis_tvalid ( m4_axis_tvalid ) , + .m4_axis_tready ( m4_axis_tready ) , + .m5_axis_tdata ( m5_axis_tdata ) , + .m5_axis_tvalid ( m5_axis_tvalid ) , + .m5_axis_tready ( m5_axis_tready ) , + .m6_axis_tdata ( m6_axis_tdata ) , + .m6_axis_tvalid ( m6_axis_tvalid ) , + .m6_axis_tready ( m6_axis_tready ) , + .m7_axis_tdata ( m7_axis_tdata ) , + .m7_axis_tvalid ( m7_axis_tvalid ) , + .m7_axis_tready ( m7_axis_tready ) , + .port_0_dt_o ( port_0_dt_o ) , + .port_1_dt_o ( port_1_dt_o ) , + .port_2_dt_o ( port_2_dt_o ) , + .port_3_dt_o ( port_3_dt_o ) ); + +wire port_0_vld, qnet_vld_i, qnet_flag_i, periph_flag_i, ext_flag_i; +assign port_0_dt_i = port_1_dt_o; +assign port_0_vld = port_0_dt_o[0]; +assign qnet_vld_i = t_time_abs_o[3]&t_time_abs_o[2]&t_time_abs_o[1] ; +assign qnet_flag_i = ~t_time_abs_o[5] & ~t_time_abs_o[4] & t_time_abs_o[3] ; +assign periph_flag_i = ~t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; +assign ext_flag_i = t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; + +reg periph_vld_i ; +reg qcom_rdy_i, qpb_rdy_i; + +initial begin + + $display("*** Start Test ***"); + + $display("AXI_WDATA_WIDTH %d", `AXI_WDATA_WIDTH); + + $display("LFSR %d", `LFSR); + $display("DIVIDER %d", `DIVIDER); + $display("ARITH %d", `ARITH); + $display("TIME_READ %d", `TIME_READ); + + $display("DMEM_AW %d", `DMEM_AW); + $display("WMEM_AW %d", `WMEM_AW); + $display("REG_AW %d", `REG_AW); + $display("IN_PORT_QTY %d", `IN_PORT_QTY); + $display("OUT_DPORT_QTY %d", `OUT_DPORT_QTY); + $display("OUT_WPORT_QTY %d", `OUT_WPORT_QTY); + + + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + //AXIS_QPROC.QPROC.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + //AXIS_QPROC.QPROC.WAVE_FIFO[1].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[2].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[3].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[4].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.DATA_FIFO[1].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + + //$readmemb("/home/mdifeder/repos/qick-spin/firmware/ip/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/repos/qick-spin/firmware/ip/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); +// $readmemb("/home/mdifeder/IPs/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + $readmemb("prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/IPs/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemb("wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_axis_qick_processor.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + + +// INITIAL VALUES + + qnet_dt_i = '{default:'0} ; + rst_ni = 1'b0; + axi_dt = 0 ; + axis_dma_start = 1'b0; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + qcom_rdy_i = 0 ; + qpb_rdy_i = 0 ; + periph_dt_i = {0,0} ; + qnet_rdy_i = 0 ; + qnet_dt_i [2] = {0,0} ; + proc_start_i = 1'b0; + proc_stop_i = 1'b0; + core_start_i = 1'b0; + core_stop_i = 1'b0; + time_rst_i = 1'b0; + time_init_i = 1'b0; + time_updt_i = 1'b0; + offset_dt_i = 0 ; + periph_vld_i = 1'b0; + + m_dma_axis_tready_i = 1'b1; + max_value = 0; + #10; + repeat(16) @ (posedge s_ps_dma_aclk); #0.1; + rst_ni = 1'b1; + #10; + + + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN + #900; + + force tb_axis_qick_processor.AXIS_QPROC.QPROC.DISPATCHER.some_fifo_full = 1'b1; + #100ns; + force tb_axis_qick_processor.AXIS_QPROC.QPROC.DISPATCHER.some_fifo_full = 1'b0; + + #1000; + + +// TEST_AXI (); + //TEST_SINGLE_READ_AXI(); + // TEST_DMA_AXI (); + //TEST_SINGLE_READ_AXI(); + +// WRITE_AXI( REG_TPROC_CFG , 512); //DISABLE NET CTRL NOTHING HAPPENS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 0); //DISABLE NET CTRL ONLY NET COMMANDS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 1536); //ENABLE IO ONLY IO COMMANDS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 1024); //ENABLE IO ENABLE NET +// TEST_STATES(); + +// WRITE_AXI( REG_CORE_CFG , 2); //LFSR CHange when READ + + +// //#100; +// //@ (posedge t_clk); #0.1; +//// proc_start_i = 1'b1; +//// @ (posedge t_clk); #0.1; +//// proc_start_i = 1'b0; + +// WRITE_AXI( REG_TPROC_CFG, 1024); //ENABLE EXTERNAL CONTROL + + +// #100; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + + +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG + +// #1000; + +/* +// CONFIGURE LFSR + @ (posedge s_ps_dma_aclk); #0.1; + WRITE_AXI( REG_TPROC_W_DT1 , 4); // + WRITE_AXI( REG_TPROC_W_DT2 , 10); // + WRITE_AXI( REG_CORE_CFG, 1); //LFSR FREE RUN + WRITE_AXI( REG_CORE_CFG, 2); //LFSR LAST + WRITE_AXI( REG_TPROC_CTRL , 4); //START + + + WRITE_AXI( REG_READ_SEL, 0); //SELECT READ + WRITE_AXI( REG_READ_SEL, 1); //SELECT READ + WRITE_AXI( REG_READ_SEL, 2); //SELECT READ + WRITE_AXI( REG_READ_SEL, 3); //SELECT READ + WRITE_AXI( REG_READ_SEL, 4); //SELECT READ + WRITE_AXI( REG_READ_SEL, 5); //SELECT READ + WRITE_AXI( REG_READ_SEL, 6); //SELECT READ + WRITE_AXI( REG_READ_SEL, 7); //SELECT READ + WRITE_AXI( REG_READ_SEL, 8); //SELECT READ + WRITE_AXI( REG_READ_SEL, 1); //SELECT READ + + #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //STOP + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + + //WRITE_AXI( REG_TPROC_CFG , 6144); //CONTINUE IF FULL + // PROCESSOR START + WRITE_AXI( REG_TPROC_W_DT1 , 4); // + WRITE_AXI( REG_TPROC_W_DT2 , 10); // + WRITE_AXI( REG_TPROC_CTRL , 8192); //COND_SET +// PORT DATA IN + @ (posedge c_clk); #0.1; + s1_axis_tvalid = 1'b1 ; + port_1_dt_i = 13; + @ (posedge c_clk); #0.1; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + #25; +*/ + + + $display("*** End Test ***"); + $finish(); +end + + +integer DATA_RD; + +/// DMA SIMULATOR +always_ff @(posedge s_ps_dma_aclk) begin + if (axis_dma_start) begin + if (s_dma_axis_tdata_i < axis_dma_len ) begin + s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; + s_dma_axis_tvalid_i <= 1; + end else if (s_dma_axis_tdata_i == axis_dma_len ) begin + s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; + s_dma_axis_tlast_i <= 1'b1; + s_dma_axis_tvalid_i <= 1'b1; + end else begin + s_dma_axis_tdata_i <= 0 ; + s_dma_axis_tlast_i <= 0 ; + s_dma_axis_tvalid_i <= 0 ; + end + end else begin + s_dma_axis_tdata_i <= 0 ; + s_dma_axis_tlast_i <= 0 ; + s_dma_axis_tvalid_i <= 0 ; + end +end + + +reg [15:0] axis_dma_len; +task TEST_SINGLE_READ_AXI (); begin + $display("Running TEST_SINGLE_READ_AXI Task"); + + //DATA MEMORY READ + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + //PROGRAM MEMORY WRITE + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + // DATA + data_wr = 127; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_01_1_1; // '00'_CORE0 - '1'_SINGLE - '01'_PMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + //DATA MEMORY WRITE + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + // DATA + data_wr = 255; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_1_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY READ + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + +end +endtask + +task TEST_DMA_AXI (); begin + $display("Running TEST_DMA_AXI Task"); + + //PROGRAM MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_01_1_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //PROGRAM MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 25; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 25; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_01_0_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_10_1_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_10_0_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + /* + //WAVE MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 15; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_11_1_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + */ + + //WAVE MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 15; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_11_0_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + +end +endtask + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + $display("Running WRITE_AXI() Task"); + //$display("PORT %d", PORT_AXI); + //$display("DATA %d", DATA_AXI); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task READ_AXI(integer ADDR_AXI); begin + $display("Running READ_AXI() Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_READ_BURST(ADDR_AXI, 0, DATA_RD, resp); + $display("READ AXI_DATA %d", DATA_RD); + end +endtask + +task COND_CLEAR; begin + $display("Running COND CLEAR Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 2048, resp); + end +endtask + +task COND_SET; begin + $display("Running COND SET Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 20481024, resp); + end +endtask + + +integer cnt ; +integer axi_addr ; +integer num; + +task TEST_STATES; begin + $display("Running TPROC TEST_STATES Task"); + +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; +// PROCESSOR STOP + #1000; + @ (posedge c_clk); #0.1; + proc_stop_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_stop_i = 1'b0; +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; + +// CORE STOP + #1000; + @ (posedge c_clk); #0.1; + core_stop_i = 1'b1; + @ (posedge c_clk); #0.1; + core_stop_i = 1'b0; +// CORE START + #1000; + @ (posedge c_clk); #0.1; + core_start_i = 1'b1; + @ (posedge c_clk); #0.1; + core_start_i = 1'b0; + +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; + +// CORE START + #1000; + @ (posedge c_clk); #0.1; + core_start_i = 1'b1; + @ (posedge c_clk); #0.1; + core_start_i = 1'b0; + +// TIME RESET + #1000; + @ (posedge t_clk); #0.1; + time_rst_i = 1'b1; + @ (posedge t_clk); #0.1; + time_rst_i = 1'b0; +// TIME INIT + #1000; + @ (posedge t_clk); #0.1; + time_init_i = 1'b1; + offset_dt_i = 100; + @ (posedge t_clk); #0.1; + time_init_i = 1'b0; +// TIME UPDATE + #1000; + @ (posedge t_clk); #0.1; + time_updt_i = 1'b1; + offset_dt_i = 50; + @ (posedge t_clk); #0.1; + time_updt_i = 1'b0; + + @ (posedge c_clk); #0.1; + + + end +endtask + + +task TEST_AXI (); begin + $display("Running TEST_AXI Task"); + WRITE_AXI( REG_TPROC_CTRL , 1); //TIME_RST + #1000; + WRITE_AXI( REG_TPROC_CTRL , 2); //TIME_UPDT + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 32); //CORE_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 64); //PROC_RST + #1000; + WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN + #1000; + WRITE_AXI( REG_TPROC_CTRL , 256); //PROC_PAUSE + #1000; + WRITE_AXI( REG_TPROC_CTRL , 512); //PROC_FREEZE + #1000; + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 1024); //PROC_STEP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 2048); //CORE_STEP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4096); //TIME_STEP + + #100; + WRITE_AXI( REG_TPROC_CTRL , 8192); //PROC_START + WRITE_AXI( REG_TPROC_CTRL , 16384); //PROC_RST + #100; + + +end +endtask + + +/* +always @(posedge t_clk) + if (!rst_ni) + count_bin_i <= 0; + else + count_bin_i <= count_bin_i + 1'b1; + +reg [31:0] count_gray, count_bin_i, count_bin_o; +bin_2_gray bin_2_gray_inst (count_bin_i , count_gray ); +gray_2_bin gray_2_bin_inst (count_gray , count_bin_o ); +*/ + +endmodule diff --git a/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv b/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv new file mode 100644 index 000000000..1dc6da359 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv @@ -0,0 +1,923 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +Test Bench for Qick Processor Testing +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + + + +//`define T_TCLK 1.953125 // Half Clock Period for Simulation +`define T_TCLK 1.302 // Half Clock Period for Simulation +`define T_CCLK 2.5 // Half Clock Period for Simulation +`define T_SCLK 5 // Half Clock Period for Simulation + + +`define GEN_SYNC 1 +`define DUAL_CORE 0 +`define IO_CTRL 1 +`define DEBUG 3 +`define TNET 0 +`define QCOM 0 +`define CUSTOM_PERIPH 1 +`define LFSR 1 +`define DIVIDER 1 +`define ARITH 1 +`define TIME_READ 1 +`define FIFO_DEPTH 8 +`define PMEM_AW 12 +`define DMEM_AW 14 +`define WMEM_AW 10 +`define REG_AW 4 +`define IN_PORT_QTY 2 +`define OUT_TRIG_QTY 8 +`define OUT_DPORT_QTY 2 +`define OUT_DPORT_DW 8 +`define OUT_WPORT_QTY 3 + +module tb_qick_processor_issue35 (); + + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +xil_axi_resp_t resp; +//AXI-LITE +//wire s_axi_aclk ; +wire s_ps_dma_aresetn ; +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +reg c_clk, t_clk, s_ps_dma_aclk, rst_ni; + +initial begin + t_clk = 1'b0; + forever # (`T_TCLK) t_clk = ~t_clk; +end + +initial begin + c_clk = 1'b0; + forever # (`T_CCLK) c_clk = ~c_clk; +end + +initial begin + s_ps_dma_aclk = 1'b0; + #0.5 + forever # (`T_SCLK) s_ps_dma_aclk = ~s_ps_dma_aclk; +end + + assign s_ps_dma_aresetn = rst_ni; + + + + + +reg [255:0] max_value ; +reg axis_dma_start ; + + + + +reg [255 :0] s_dma_axis_tdata_i ; +reg s_dma_axis_tlast_i ; +reg s_dma_axis_tvalid_i ; +reg m_dma_axis_tready_i ; +wire [63 :0] port_0_dt_i ; +reg [63 :0] port_1_dt_i ; +reg s_axi_aclk ; +reg s_axi_aresetn ; + + + +reg axis_aclk ; +reg axis_aresetn ; +reg m0_axis_tready =1 ; +reg m1_axis_tready =0 ; +reg m2_axis_tready =0 ; +reg m3_axis_tready =0 ; +reg m4_axis_tready =0 ; +reg m5_axis_tready =0 ; +reg m6_axis_tready =0 ; +reg m7_axis_tready =0 ; + +wire s_dma_axis_tready_o ; +wire [255 :0] m_dma_axis_tdata_o ; +wire m_dma_axis_tlast_o ; +wire m_dma_axis_tvalid_o ; + +wire [167:0] m0_axis_tdata ; +wire m0_axis_tvalid ; +wire [167:0] m1_axis_tdata ; +wire m1_axis_tvalid ; +wire [167:0] m2_axis_tdata ; +wire m2_axis_tvalid ; +wire [167:0] m3_axis_tdata ; +wire m3_axis_tvalid ; +wire [167:0] m4_axis_tdata ; +wire m4_axis_tvalid ; +wire [167:0] m5_axis_tdata ; +wire m5_axis_tvalid ; +wire [167:0] m6_axis_tdata ; +wire m6_axis_tvalid ; +wire [167:0] m7_axis_tdata ; +wire m7_axis_tvalid ; +wire [`OUT_DPORT_DW-1:0] port_0_dt_o, port_1_dt_o, port_2_dt_o, port_3_dt_o ; + +wire qnet_en_o ; +wire [4 :0] qnet_op_o ; +wire [31:0] qnet_a_dt_o ; +wire [31:0] qnet_b_dt_o ; +wire [31:0] qnet_c_dt_o ; +wire [31:0] qnet_d_dt_o ; +reg qnet_rdy_i ; +reg [31 :0] qnet_dt_i [2] ; +reg [31 :0] qcom_dt_i [2] ; +reg [31 :0] qp1_dt_i [2] ; +reg [31 :0] qp2_dt_i [2] ; + +wire periph_en_o ; +wire [4 :0] periph_op_o ; +wire [31:0] periph_a_dt_o ; +wire [31:0] periph_b_dt_o ; +wire [31:0] periph_c_dt_o ; +wire [31:0] periph_d_dt_o ; +reg periph_rdy_i ; +reg [31 :0] periph_dt_i [2] ; + + +reg s0_axis_tvalid , s1_axis_tvalid ; +reg [15:0] waves, wtime; +reg [31:0] axi_dt; + + +int val_A, val_B, val_C, val_D, result ; +reg [31:0] result_r, result_2r, result_3r ; + +always_ff @ (posedge c_clk) begin + result_r <= result; + result_2r <= result_r; + result_3r <= result_2r; +end + +// Register ADDRESS +parameter REG_TPROC_CTRL = 0 * 4 ; +parameter REG_TPROC_CFG = 1 * 4 ; +parameter REG_MEM_ADDR = 2 * 4 ; +parameter REG_MEM_LEN = 3 * 4 ; +parameter REG_MEM_DT_I = 4 * 4 ; +parameter REG_AXI_W_DT1 = 5 * 4 ; +parameter REG_AXI_W_DT2 = 6 * 4 ; +parameter REG_CORE_CFG = 7 * 4 ; +parameter REG_AXI_DT_SRC = 8 * 4 ; +parameter REG_MEM_DT_O = 10 * 4 ; +parameter REG_AXI_R_DT1 = 11 * 4 ; +parameter REG_AXI_R_DT2 = 12 * 4 ; +parameter REG_TIME_USR = 13 * 4 ; +parameter REG_TPROC_STATUS = 14 * 4 ; +parameter REG_TPROC_DEBUG = 15 * 4 ; + + + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_ps_dma_aclk ), + .aresetn (s_ps_dma_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + +reg proc_start_i, proc_stop_i ; +reg core_start_i, core_stop_i ; +reg time_rst_i, time_init_i, time_updt_i; + +reg [47:0] offset_dt_i ; +wire [47:0] t_time_abs_o ; +reg time_updt_i; + +wire [31:0] ps_debug_do; + +reg qp1_en_r; +reg [31:0] qp1_a_dt_r, qp1_b_dt_r; +wire [31:0] qp1_a_dt_o, qp1_b_dt_o, qp1_c_dt_o, qp1_d_dt_o; +always_ff @ (posedge c_clk) begin + qp1_en_r <= qp1_en_o; + qp1_a_dt_r <= qp1_a_dt_o; + qp1_b_dt_r <= qp1_b_dt_o; +end + +assign qp1_rdy_i = ~qp1_en_r; +assign qp1_dt_i[0] = qp1_a_dt_r; +assign qp1_dt_i[1] = qp1_b_dt_r; +assign qp1_vld_i = qp1_en_r ; + + +axis_qick_processor # ( + .DUAL_CORE ( `DUAL_CORE ) , + .GEN_SYNC ( `GEN_SYNC ) , + .IO_CTRL ( `IO_CTRL ) , + .DEBUG ( `DEBUG ) , + .TNET ( `TNET ) , + .QCOM ( `QCOM ) , + .CUSTOM_PERIPH ( `CUSTOM_PERIPH ) , + .LFSR ( `LFSR ) , + .DIVIDER ( `DIVIDER ) , + .ARITH ( `ARITH ) , + .TIME_READ ( `TIME_READ ) , + .FIFO_DEPTH ( `FIFO_DEPTH ) , + .PMEM_AW ( `PMEM_AW ) , + .DMEM_AW ( `DMEM_AW ) , + .WMEM_AW ( `WMEM_AW ) , + .REG_AW ( `REG_AW ) , + .IN_PORT_QTY ( `IN_PORT_QTY ) , + .OUT_TRIG_QTY ( `OUT_TRIG_QTY ) , + .OUT_DPORT_QTY ( `OUT_DPORT_QTY ) , + .OUT_DPORT_DW ( `OUT_DPORT_DW ) , + .OUT_WPORT_QTY ( `OUT_WPORT_QTY ) +) AXIS_QPROC ( + .t_clk_i ( t_clk ) , + .t_resetn ( rst_ni ) , + .c_clk_i ( c_clk ) , + .c_resetn ( rst_ni ) , + .ps_clk_i ( s_ps_dma_aclk ) , + .ps_resetn ( s_ps_dma_aresetn ) , + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_i ) , + .proc_stop_i ( proc_stop_i ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_dt_i ( offset_dt_i ) , + .t_time_abs_o ( t_time_abs_o ) , + .ps_debug_do ( ps_debug_do ) , + + .qnet_en_o ( qnet_en_o ) , + .qnet_op_o ( qnet_op_o ) , + .qnet_a_dt_o ( qnet_a_dt_o ) , + .qnet_b_dt_o ( qnet_b_dt_o ) , + .qnet_c_dt_o ( qnet_c_dt_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt1_i ( qnet_dt_i[0] ) , + .qnet_dt2_i ( qnet_dt_i[1] ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + + .qcom_en_o ( qcom_en_o ) , + .qcom_op_o ( qcom_op_o ) , + .qcom_dt_o ( qcom_dt_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt1_i ( qcom_dt_i[0] ) , + .qcom_dt2_i ( qcom_dt_i[1] ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + + .qp1_en_o ( qp1_en_o ) , + .qp1_op_o ( qp1_op_o ) , + .qp1_a_dt_o ( qp1_a_dt_o ) , + .qp1_b_dt_o ( qp1_b_dt_o ) , + .qp1_c_dt_o ( qp1_c_dt_o ) , + .qp1_d_dt_o ( qp1_d_dt_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt1_i ( qp1_dt_i[0] ) , + .qp1_dt2_i ( qp1_dt_i[1] ) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + + .qp2_en_o ( qp2_en_o ) , + .qp2_op_o ( qp2_op_o ) , + .qp2_a_dt_o ( qp2_a_dt_o ) , + .qp2_b_dt_o ( qp2_b_dt_o ) , + .qp2_c_dt_o ( qp2_c_dt_o ) , + .qp2_d_dt_o ( qp2_d_dt_o ) , + .qp2_rdy_i ( qpb_rdy_i ) , + .qp2_dt1_i ( qp2_dt_i[0] ) , + .qp2_dt2_i ( qp2_dt_i[1] ) , + .qp2_vld_i ( qp2_vld_i ) , + + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , + .s0_axis_tdata ( port_0_dt_i ) , + .s0_axis_tvalid ( port_0_vld ) , + .s1_axis_tdata ( port_1_dt_i ) , + .s1_axis_tvalid ( s1_axis_tvalid ) , + .s2_axis_tdata ( 64'd2 ) , + .s2_axis_tvalid ( 1'b0 ) , + .s3_axis_tdata ( 64'd3 ) , + .s3_axis_tvalid ( 1'b0 ) , + .s4_axis_tdata ( 64'd4 ) , + .s4_axis_tvalid ( 1'b0 ) , + .s5_axis_tdata ( 64'd5 ) , + .s5_axis_tvalid ( 1'b0 ) , + .s6_axis_tdata ( 64'd6 ) , + .s6_axis_tvalid ( 1'b0 ) , + .s7_axis_tdata ( 64'd7 ) , + .s7_axis_tvalid ( 1'b0 ) , + .s_axi_awaddr ( s_axi_awaddr[7:0] ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr[7:0] ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .m0_axis_tdata ( m0_axis_tdata ) , + .m0_axis_tvalid ( m0_axis_tvalid ) , + .m0_axis_tready ( m0_axis_tready ) , + .m1_axis_tdata ( m1_axis_tdata ) , + .m1_axis_tvalid ( m1_axis_tvalid ) , + .m1_axis_tready ( m1_axis_tready ) , + .m2_axis_tdata ( m2_axis_tdata ) , + .m2_axis_tvalid ( m2_axis_tvalid ) , + .m2_axis_tready ( m2_axis_tready ) , + .m3_axis_tdata ( m3_axis_tdata ) , + .m3_axis_tvalid ( m3_axis_tvalid ) , + .m3_axis_tready ( m3_axis_tready ) , + .m4_axis_tdata ( m4_axis_tdata ) , + .m4_axis_tvalid ( m4_axis_tvalid ) , + .m4_axis_tready ( m4_axis_tready ) , + .m5_axis_tdata ( m5_axis_tdata ) , + .m5_axis_tvalid ( m5_axis_tvalid ) , + .m5_axis_tready ( m5_axis_tready ) , + .m6_axis_tdata ( m6_axis_tdata ) , + .m6_axis_tvalid ( m6_axis_tvalid ) , + .m6_axis_tready ( m6_axis_tready ) , + .m7_axis_tdata ( m7_axis_tdata ) , + .m7_axis_tvalid ( m7_axis_tvalid ) , + .m7_axis_tready ( m7_axis_tready ) , + .port_0_dt_o ( port_0_dt_o ) , + .port_1_dt_o ( port_1_dt_o ) , + .port_2_dt_o ( port_2_dt_o ) , + .port_3_dt_o ( port_3_dt_o ) ); + +wire port_0_vld, qnet_vld_i, qnet_flag_i, periph_flag_i, ext_flag_i; +assign port_0_dt_i = port_1_dt_o; +assign port_0_vld = port_0_dt_o[0]; +assign qnet_vld_i = t_time_abs_o[3]&t_time_abs_o[2]&t_time_abs_o[1] ; +assign qnet_flag_i = ~t_time_abs_o[5] & ~t_time_abs_o[4] & t_time_abs_o[3] ; +assign periph_flag_i = ~t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; +assign ext_flag_i = t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; + +reg periph_vld_i ; +reg qcom_rdy_i, qpb_rdy_i; + +initial begin + + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qick_processor_issue35.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + + + $display("*** Start Test ***"); + + $display("AXI_WDATA_WIDTH %d", `AXI_WDATA_WIDTH); + + $display("LFSR %d", `LFSR); + $display("DIVIDER %d", `DIVIDER); + $display("ARITH %d", `ARITH); + $display("TIME_READ %d", `TIME_READ); + + $display("DMEM_AW %d", `DMEM_AW); + $display("WMEM_AW %d", `WMEM_AW); + $display("REG_AW %d", `REG_AW); + $display("IN_PORT_QTY %d", `IN_PORT_QTY); + $display("OUT_DPORT_QTY %d", `OUT_DPORT_QTY); + $display("OUT_WPORT_QTY %d", `OUT_WPORT_QTY); + + + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM = '{default:'0} ; + +// AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[1].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + +// for (int i=0; i < 1 /*`OUT_TRIG_QTY*/; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[i].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// for (int i=0; i < `OUT_DPORT_QTY; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[i].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// for (int i=0; i < `OUT_WPORT_QTY; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[i].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + // Load Memories + +// $readmemb("/home/mdifeder/IPs/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); +// $readmemb("prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + $readmemh("prog_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/IPs/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemh("wave_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemh("dmem_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM); + + +// INITIAL VALUES + + qnet_dt_i = '{default:'0} ; + rst_ni = 1'b0; + axi_dt = 0 ; + axis_dma_start = 1'b0; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + qcom_rdy_i = 0 ; + qpb_rdy_i = 0 ; + periph_dt_i = {0,0} ; + qnet_rdy_i = 0 ; + qnet_dt_i [2] = {0,0} ; + proc_start_i = 1'b0; + proc_stop_i = 1'b0; + core_start_i = 1'b0; + core_stop_i = 1'b0; + time_rst_i = 1'b0; + time_init_i = 1'b0; + time_updt_i = 1'b0; + offset_dt_i = 0 ; + periph_vld_i = 1'b0; + + m_dma_axis_tready_i = 1'b1; + max_value = 0; + + #0.5us; + + repeat(16) @ (posedge s_ps_dma_aclk); #0.1; + rst_ni = 1'b1; + + #0.5us; + + WRITE_AXI( REG_TPROC_CFG , 32'h0001_0000); // prev_mask_dbg + + + repeat (2) begin + + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + + #5us; + + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + + #5us; + end + + + $display("*** End Test ***"); + $finish(); +end + + +//integer DATA_RD; + +///// DMA SIMULATOR +//always_ff @(posedge s_ps_dma_aclk) begin +// if (axis_dma_start) begin +// if (s_dma_axis_tdata_i < axis_dma_len ) begin +// s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; +// s_dma_axis_tvalid_i <= 1; +// end else if (s_dma_axis_tdata_i == axis_dma_len ) begin +// s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; +// s_dma_axis_tlast_i <= 1'b1; +// s_dma_axis_tvalid_i <= 1'b1; +// end else begin +// s_dma_axis_tdata_i <= 0 ; +// s_dma_axis_tlast_i <= 0 ; +// s_dma_axis_tvalid_i <= 0 ; +// end +// end else begin +// s_dma_axis_tdata_i <= 0 ; +// s_dma_axis_tlast_i <= 0 ; +// s_dma_axis_tvalid_i <= 0 ; +// end +//end + + +//reg [15:0] axis_dma_len; +//task TEST_SINGLE_READ_AXI (); begin +// $display("Running TEST_SINGLE_READ_AXI Task"); + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +// //PROGRAM MEMORY WRITE +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// // DATA +// data_wr = 127; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_01_1_1; // '00'_CORE0 - '1'_SINGLE - '01'_PMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// //DATA MEMORY WRITE +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// // DATA +// data_wr = 255; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_1_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +//end +//endtask + +//task TEST_DMA_AXI (); begin +// $display("Running TEST_DMA_AXI Task"); + +// //PROGRAM MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_01_1_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //PROGRAM MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 25; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 25; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_01_0_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 10; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_10_1_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_10_0_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +// /* +// //WAVE MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 15; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_11_1_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// */ + +// //WAVE MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 15; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_11_0_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + + +//end +//endtask + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + $display("Running WRITE_AXI() Task"); + //$display("PORT %d", PORT_AXI); + //$display("DATA %d", DATA_AXI); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +//task READ_AXI(integer ADDR_AXI); begin +// $display("Running READ_AXI() Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_READ_BURST(ADDR_AXI, 0, DATA_RD, resp); +// $display("READ AXI_DATA %d", DATA_RD); +// end +//endtask + +//task COND_CLEAR; begin +// $display("Running COND CLEAR Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 2048, resp); +// end +//endtask + +//task COND_SET; begin +// $display("Running COND SET Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 20481024, resp); +// end +//endtask + + +//integer cnt ; +//integer axi_addr ; +//integer num; + +//task TEST_STATES; begin +// $display("Running TPROC TEST_STATES Task"); + +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; +//// PROCESSOR STOP +// #1000; +// @ (posedge c_clk); #0.1; +// proc_stop_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_stop_i = 1'b0; +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + +//// CORE STOP +// #1000; +// @ (posedge c_clk); #0.1; +// core_stop_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_stop_i = 1'b0; +//// CORE START +// #1000; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b0; + +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + +//// CORE START +// #1000; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b0; + +//// TIME RESET +// #1000; +// @ (posedge t_clk); #0.1; +// time_rst_i = 1'b1; +// @ (posedge t_clk); #0.1; +// time_rst_i = 1'b0; +//// TIME INIT +// #1000; +// @ (posedge t_clk); #0.1; +// time_init_i = 1'b1; +// offset_dt_i = 100; +// @ (posedge t_clk); #0.1; +// time_init_i = 1'b0; +//// TIME UPDATE +// #1000; +// @ (posedge t_clk); #0.1; +// time_updt_i = 1'b1; +// offset_dt_i = 50; +// @ (posedge t_clk); #0.1; +// time_updt_i = 1'b0; + +// @ (posedge c_clk); #0.1; + + +// end +//endtask + + +//task TEST_AXI (); begin +// $display("Running TEST_AXI Task"); +// WRITE_AXI( REG_TPROC_CTRL , 1); //TIME_RST +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 2); //TIME_UPDT +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 32); //CORE_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 64); //PROC_RST +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 256); //PROC_PAUSE +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 512); //PROC_FREEZE +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 1024); //PROC_STEP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 2048); //CORE_STEP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 4096); //TIME_STEP + +// #100; +// WRITE_AXI( REG_TPROC_CTRL , 8192); //PROC_START +// WRITE_AXI( REG_TPROC_CTRL , 16384); //PROC_RST +// #100; + + +//end +//endtask + + +///* +//always @(posedge t_clk) +// if (!rst_ni) +// count_bin_i <= 0; +// else +// count_bin_i <= count_bin_i + 1'b1; + +//reg [31:0] count_gray, count_bin_i, count_bin_o; +//bin_2_gray bin_2_gray_inst (count_bin_i , count_gray ); +//gray_2_bin gray_2_bin_inst (count_gray , count_bin_o ); +//*/ + +endmodule diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg new file mode 100644 index 000000000..45fc5e326 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg @@ -0,0 +1,605 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk_i + ps_clk_i + + + proc_start_i + proc_start_i + + + proc_stop_i + proc_stop_i + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + time_rst_i + time_rst_i + + + time_updt_i + time_updt_i + + + time_updt_dt_i[31:0] + time_updt_dt_i[31:0] + + + int_time_en + int_time_en + + + int_time_cmd[3:0] + int_time_cmd[3:0] + + + int_time_dt[31:0] + int_time_dt[31:0] + + + TPROC_CTRL[15:0] + TPROC_CTRL[15:0] + + + xreg_TPROC_CTRL[15:0] + xreg_TPROC_CTRL[15:0] + UNSIGNEDDECRADIX + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + xreg_TPROC_W_DT[31:0] + xreg_TPROC_W_DT[31:0] + + + c_clk_i + c_clk_i + + + all_fifo_full + all_fifo_full + + + all_fifo_full_i + all_fifo_full_i + + + some_fifo_full + some_fifo_full + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + c_pmem_addr_i[7:0] + c_pmem_addr_i[7:0] + + + t_clk_i + t_clk_i + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + t_core_rst_prev_net + t_core_rst_prev_net + + + core_rst_run_p + core_rst_run_p + + + core_rst_stop_p + core_rst_stop_p + + + core_rst_prev_p + core_rst_prev_p + + + core_run_p + core_run_p + + + core_stop_p + core_stop_p + + + time_stop_p + time_stop_p + + + time_run_p + time_run_p + + + time_rst_stop_p + time_rst_stop_p + + + time_rst_run_p + time_rst_run_p + + + time_update_p + time_update_p + + + core_step_p + core_step_p + + + time_step_p + time_step_p + + + RAM[0:255][71:0] + RAM[0:255][71:0] + + + QPROC_CTRL + label + + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + some_fifo_full + some_fifo_full + + + fifo_ok + fifo_ok + + + core_en + core_en + + + en_i + en_i + + + halt + halt + + + fetch_en + fetch_en + + + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + we_a_i + we_a_i + + + addr_a_i[7:0] + addr_a_i[7:0] + + + dt_a_i[71:0] + dt_a_i[71:0] + + + dt_a_o[71:0] + dt_a_o[71:0] + + + c_fifo_trig_full[7:0] + c_fifo_trig_full[7:0] + + + c_fifo_data_full[0:0] + c_fifo_data_full[0:0] + + + c_fifo_wave_full[2:0] + c_fifo_wave_full[2:0] + + + pulse_sync_o + pulse_sync_o + + + CORE_P_MEM + label + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + we_a_i + we_a_i + + + addr_a_i[7:0] + addr_a_i[7:0] + + + dt_a_i[71:0] + dt_a_i[71:0] + + + dt_a_o[71:0] + dt_a_o[71:0] + + + rDest + label + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + if_op_code[15:0] + if_op_code[15:0] + + + if_op_data[55:0] + if_op_data[55:0] + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + PC_prev[7:0] + PC_prev[7:0] + + + PC_curr[7:0] + PC_curr[7:0] + + + PC_nxt[7:0] + PC_nxt[7:0] + + + TRIG_FIFO_0 + label + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[48:0] + data_i[48:0] + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[48:0] + data_o[48:0] + + + flush_i + flush_i + + + async_empty_o + async_empty_o + + + async_full_o + async_full_o + + + + cfg_pc_nxt[2:0] + cfg_pc_nxt[2:0] + + + id_branch_cond_ok + id_branch_cond_ok + + + id_ret + id_ret + + + id_AI + id_AI + + + id_type_br + id_type_br + + + id_exec_ok + id_exec_ok + + + id_cond_ok + id_cond_ok + + + id_cond_used + id_cond_used + + + id_COND[2:0] + id_COND[2:0] + + + alu_fZ_r + alu_fZ_r + + + x1_alu_fZ + x1_alu_fZ + + + .flag_we + .flag_we + + + AB_alu + label + + Z_o + Z_o + + + C_o + C_o + + + S_o + S_o + + + alu_result_o[31:0] + alu_result_o[31:0] + + + clk_i + clk_i + + + A_i[31:0] + A_i[31:0] + + + B_i[31:0] + B_i[31:0] + + + alu_op_i[3:0] + alu_op_i[3:0] + + + + [0][31:0] + [0][31:0] + + + [0][31:0] + [0][31:0] + + + [0][31:0] + [0][31:0] + + + [0] + [0] + + + [0] + [0] + + + .src[1:0] + .src[1:0] + + + .src[1:0] + .src[1:0] + + + [0][31:0] + [0][31:0] + + + m_axis_tdata[0:2][167:0] + m_axis_tdata[0:2][167:0] + + + m_axis_tvalid[0:2] + m_axis_tvalid[0:2] + + + clk_i + clk_i + + + rst_ni + rst_ni + + + restart_i + restart_i + + + en_i + en_i + + + x1_ctrl + x1_ctrl + + + x2_ctrl + x2_ctrl + + + wmem_we_o + wmem_we_o + + + wmem_addr_o[3:0] + wmem_addr_o[3:0] + + + wmem_w_dt_o[167:0] + wmem_w_dt_o[167:0] + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + + diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg new file mode 100644 index 000000000..864795af8 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg @@ -0,0 +1,658 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + t_resetn + t_resetn + + + c_resetn + c_resetn + + + ps_resetn + ps_resetn + + + QPROC_CTRL + label + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + + pulse_sync_o + pulse_sync_o + #FFA500 + true + + + DEBUG_OUT + label + + ps_debug_do[31:0] + ps_debug_do[31:0] + + + c_core_do[31:0] + c_core_do[31:0] + + + c_debug_do[31:0] + c_debug_do[31:0] + + + c_time_usr_do[31:0] + c_time_usr_do[31:0] + SIGNEDDECRADIX + + + c_time_ref_do[31:0] + c_time_ref_do[31:0] + UNSIGNEDDECRADIX + + + c_port_do[31:0] + c_port_do[31:0] + + + t_debug_do[31:0] + t_debug_do[31:0] + + + t_fifo_do[31:0] + t_fifo_do[31:0] + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + + CORE_PMEM + label + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + addr_a_i[11:0] + addr_a_i[11:0] + UNSIGNEDDECRADIX + + + dt_a_o[71:0] + dt_a_o[71:0] + HEXRADIX + + + + CORE_WMEM + label + + wmem_addr_o[9:0] + wmem_addr_o[9:0] + UNSIGNEDDECRADIX + #FFA500 + true + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + #FFA500 + true + + + wmem_data + label + #FFA500 + true + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + + CORE_PIPELINE + label + + CPU_STAGE_1 + label + + r_mem_rst + r_mem_rst + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + CPU_STAGE_2 + label + + PC_curr[11:0] + PC_curr[11:0] + UNSIGNEDDECRADIX + + + PC_prev[11:0] + PC_prev[11:0] + UNSIGNEDDECRADIX + + + + CPU_STAGE_3 + label + + rd_ctrl + rd_ctrl + + + rd_reg + rd_reg + + + + CPU_STAGE_4 + label + + x1_ctrl + x1_ctrl + + + + CPU_STAGE_5 + label + + x2_ctrl + x2_ctrl + + + + + HAZARD_CTRL + label + + clk_i + clk_i + + + rst_ni + rst_ni + + + halt_i + halt_i + + + rs_A_addr_i[0:1][5:0] + rs_A_addr_i[0:1][5:0] + + + rs_A_dt_i[0:1][31:0] + rs_A_dt_i[0:1][31:0] + + + rs_D_addr_i[0:1][6:0] + rs_D_addr_i[0:1][6:0] + + + rs_D_dt_i[0:1][31:0] + rs_D_dt_i[0:1][31:0] + + + id_reg_i + id_reg_i + + + rd_reg_i + rd_reg_i + + + x1_reg_i + x1_reg_i + + + x2_reg_i + x2_reg_i + + + wr_reg_i + wr_reg_i + + + rd_periph_use + rd_periph_use + + + x1_periph_use + x1_periph_use + + + x2_periph_use + x2_periph_use + + + id_wmem_we + id_wmem_we + + + id_flag_used + id_flag_used + + + flag_we + flag_we + + + id_jmp_i + id_jmp_i + + + x1_alu_dt_i[31:0] + x1_alu_dt_i[31:0] + + + x2_alu_dt_i[31:0] + x2_alu_dt_i[31:0] + + + x2_dmem_dt_i[31:0] + x2_dmem_dt_i[31:0] + + + rd_imm_dt_i[31:0] + rd_imm_dt_i[31:0] + + + x1_imm_dt_i[31:0] + x1_imm_dt_i[31:0] + + + x2_imm_dt_i[31:0] + x2_imm_dt_i[31:0] + + + reg_A_dt_o[0:1][31:0] + reg_A_dt_o[0:1][31:0] + + + reg_D_dt_o[0:1][31:0] + reg_D_dt_o[0:1][31:0] + + + bubble_id_o + bubble_id_o + + + bubble_rd_o + bubble_rd_o + + + + FullPathName + [0][47:0] + [0][47:0] + UNSIGNEDDECRADIX + #00FFFF + true + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + [14][31:0] + [14][31:0] + UNSIGNEDDECRADIX + + + core_en + core_en + #00FFFF + true + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + time_abs_i[47:0] + time_abs_i[47:0] + HEXRADIX + #FFFF00 + true + + + DISPATCHER_WAVE_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[215:0] + data_i[215:0] + + + flush_i + flush_i + + + async_full_o + async_full_o + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[215:0] + data_o[215:0] + + + async_empty_o + async_empty_o + + + + FullPathName + [0] + [0] + + + DISPATCHER_TRIG_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[48:0] + data_i[48:0] + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[48:0] + data_o[48:0] + + + flush_i + flush_i + + + async_empty_o + async_empty_o + + + async_full_o + async_full_o + + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + TPROC_OUTPUTS + label + + + trig_0_o + trig_0_o + #00FFFF + true + + + port_0_dt_o[7:0] + port_0_dt_o[7:0] + #00FFFF + true + + + m0_axis_tdata[167:0] + m0_axis_tdata[167:0] + #00FFFF + true + + + m0_axis_tvalid + m0_axis_tvalid + #00FFFF + true + + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + xreg_TPROC_DBG[15:0] + xreg_TPROC_DBG[15:0] + + diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg new file mode 100644 index 000000000..22b685079 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg @@ -0,0 +1,853 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk_i + ps_clk_i + + + proc_start_i + proc_start_i + + + proc_stop_i + proc_stop_i + + + xreg_TPROC_CTRL[15:0] + xreg_TPROC_CTRL[15:0] + UNSIGNEDDECRADIX + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + c_clk_i + c_clk_i + + + some_fifo_full + some_fifo_full + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + c_pmem_addr_i[11:0] + c_pmem_addr_i[11:0] + + + t_clk_i + t_clk_i + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + t_core_rst_prev_net + t_core_rst_prev_net + + + core_rst_run_p + core_rst_run_p + + + time_rst_run_p + time_rst_run_p + + + RAM[0:4095][71:0] + RAM[0:4095][71:0] + HEXRADIX + + + QPROC_CTRL + label + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + some_fifo_full + some_fifo_full + + + fifo_ok + fifo_ok + + + core_en + core_en + + + en_i + en_i + + + halt + halt + + + fetch_en + fetch_en + + + + pulse_sync_o + pulse_sync_o + #FFA500 + true + + + out_port_data + out_port_data + + + + DEBUG_OUT + label + + ps_debug_do[31:0] + ps_debug_do[31:0] + + + c_core_do[31:0] + c_core_do[31:0] + + + c_debug_do[31:0] + c_debug_do[31:0] + + + c_time_usr_do[31:0] + c_time_usr_do[31:0] + SIGNEDDECRADIX + + + c_time_ref_do[31:0] + c_time_ref_do[31:0] + UNSIGNEDDECRADIX + + + c_port_do[31:0] + c_port_do[31:0] + + + t_debug_do[31:0] + t_debug_do[31:0] + + + t_fifo_do[31:0] + t_fifo_do[31:0] + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + + some_fifo_full + some_fifo_full + #00FFFF + true + + + core_en + core_en + #00FFFF + true + + + halt + halt + #00FFFF + true + + + stall + stall + + + port_we + port_we + + + port_o + port_o + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + label + [0][167:0] + [0][167:0] + m_axis_tdata[0][167:0] + #FF00FF + true + + + label + [0] + [0] + m_axis_tvalid[0] + #FF00FF + true + + + DISPATCHER_WAVE_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[215:0] + data_i[215:0] + + + time + label + UNSIGNEDDECRADIX + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + data_i + label + + [59] + [59] + + + [58] + [58] + + + [57] + [57] + + + [56] + [56] + + + [55] + [55] + + + [54] + [54] + + + [53] + [53] + + + [52] + [52] + + + [51] + [51] + + + [50] + [50] + + + [49] + [49] + + + [48] + [48] + + + + async_full_o + async_full_o + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[215:0] + data_o[215:0] + + + async_empty_o + async_empty_o + + + flush_i + flush_i + + + + CORE_PMEM + label + + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + addr_a_i[11:0] + addr_a_i[11:0] + UNSIGNEDDECRADIX + + + dt_a_o[71:0] + dt_a_o[71:0] + HEXRADIX + + + + CORE_WMEM + label + + + wmem_addr_o[9:0] + wmem_addr_o[9:0] + UNSIGNEDDECRADIX + #FFA500 + true + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + #FFA500 + true + + + wmem_data + label + #FFA500 + true + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + + label + [0] + [0] + c_fifo_wave_push[0] + + + label + [0] + [0] + c_fifo_wave_push_r[0] + #00FF00 + true + + + label + [0] + [0] + c_fifo_wave_push_s[0] + #FFFF00 + true + + + c_fifo_data_in_r[167:0] + c_fifo_data_in_r[167:0] + #FFFF00 + true + + + x1_rsA0_dt[31:0] + x1_rsA0_dt[31:0] + + + .cfg_addr_imm + .cfg_addr_imm + + + r_rd_imm_addr[10:0] + r_rd_imm_addr[10:0] + + + [0][31:0] + [0][31:0] + + + CPU_STAGE_1 + label + + r_mem_rst + r_mem_rst + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + CPU_STAGE_2 + label + + PC_curr[11:0] + PC_curr[11:0] + UNSIGNEDDECRADIX + + + PC_prev[11:0] + PC_prev[11:0] + UNSIGNEDDECRADIX + + + + CPU_STAGE_3 + label + + rd_ctrl + rd_ctrl + + + rd_reg + rd_reg + + + + CPU_STAGE_4 + label + + x1_ctrl + x1_ctrl + + + + CPU_STAGE_5 + label + + x2_ctrl + x2_ctrl + + + + HAZARD_CTRL + label + + + clk_i + clk_i + + + rst_ni + rst_ni + + + halt_i + halt_i + + + rs_A_addr_i[0:1][5:0] + rs_A_addr_i[0:1][5:0] + + + rs_A_dt_i[0:1][31:0] + rs_A_dt_i[0:1][31:0] + + + rs_D_addr_i[0:1][6:0] + rs_D_addr_i[0:1][6:0] + + + rs_D_dt_i[0:1][31:0] + rs_D_dt_i[0:1][31:0] + + + id_reg_i + id_reg_i + + + rd_reg_i + rd_reg_i + + + x1_reg_i + x1_reg_i + + + x2_reg_i + x2_reg_i + + + wr_reg_i + wr_reg_i + + + rd_periph_use + rd_periph_use + + + x1_periph_use + x1_periph_use + + + x2_periph_use + x2_periph_use + + + id_wmem_we + id_wmem_we + + + id_flag_used + id_flag_used + + + flag_we + flag_we + + + id_jmp_i + id_jmp_i + + + x1_alu_dt_i[31:0] + x1_alu_dt_i[31:0] + + + x2_alu_dt_i[31:0] + x2_alu_dt_i[31:0] + + + x2_dmem_dt_i[31:0] + x2_dmem_dt_i[31:0] + + + rd_imm_dt_i[31:0] + rd_imm_dt_i[31:0] + + + x1_imm_dt_i[31:0] + x1_imm_dt_i[31:0] + + + x2_imm_dt_i[31:0] + x2_imm_dt_i[31:0] + + + reg_A_dt_o[0:1][31:0] + reg_A_dt_o[0:1][31:0] + + + reg_D_dt_o[0:1][31:0] + reg_D_dt_o[0:1][31:0] + + + bubble_id_o + bubble_id_o + + + bubble_rd_o + bubble_rd_o + + + + id_type_wp + id_type_wp + + + port_we + port_we + + + stall_id_wp + stall_id_wp + + + [0][31:0] + [0][31:0] + + + [0][167:0] + [0][167:0] + + + [0][71:0] + [0][71:0] + + diff --git a/firmware/ip/qick_processor/src/tb/wave.bin b/firmware/ip/qick_processor/src/tb/wave.bin new file mode 100644 index 000000000..ed64e2027 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/wave.bin @@ -0,0 +1,16 @@ +// WAVE Memory File +// CONFIG_16 _ LENGHT 32 _ GAIN_32 _ ENV_24 _ PHASE_32 _ FREQ_32 +_0000000000100000_00000000000000000000000000010000_00000000000000000000000000001000_000000000000000000000100_00000000000000000000000000000010_00000000000000000000000000000001 +_1111111111111111_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000001_00000000000000000000000000000001 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000010_00000000000000000000000000000010 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000011_00000000000000000000000000000011 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000100_00000000000000000000000000000100 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000101_00000000000000000000000000000101 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000110_00000000000000000000000000000110 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000111_00000000000000000000000000000111 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001000_00000000000000000000000000001000 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001001_00000000000000000000000000001001 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001010_00000000000000000000000000001010 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001011_00000000000000000000000000001011 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001100_00000000000000000000000000001100 + diff --git a/firmware/ip/qick_processor/src/tb/wave_issue35.mem b/firmware/ip/qick_processor/src/tb/wave_issue35.mem new file mode 100644 index 000000000..847b5cce8 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/wave_issue35.mem @@ -0,0 +1,10 @@ +// WMEM content +080000002600007ffe000000000000000014d55556 +090000002600003fff000000000000000014d55556 +080000002600007ffe000000260000000014d55556 +080000004c00007ffe000000000000000014d55556 +090000004d00007ffe000000000000000014d55556 +080000002600007ffe000000004000000014d55556 +090000002600003fff000000004000000014d55556 +080000002600007ffe000000264000000014d55556 +0800000003000000000000000000000000e0bfffff diff --git a/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl b/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl new file mode 100644 index 000000000..132bedb2b --- /dev/null +++ b/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl @@ -0,0 +1,443 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_static_text $IPINST -name "Introduction" -parent ${Page_0} -text {Values for Memory size, port quantity, and register amount can be modified in order to make a smaller and faster processor} + #Adding Group + set Process [ipgui::add_group $IPINST -name "Process" -parent ${Page_0} -display_name {Processor Options}] + set_property tooltip {Process} ${Process} + ipgui::add_param $IPINST -name "REG_AW" -parent ${Process} + ipgui::add_static_text $IPINST -name "dreg" -parent ${Process} -text {User can define the amount of 32-bits General Purpouse Data registers. This value impacts on the max freq of the processor.} + #Adding Group + set Memory_Configuration [ipgui::add_group $IPINST -name "Memory Configuration" -parent ${Process} -display_name {Core Memory}] + ipgui::add_param $IPINST -name "PMEM_AW" -parent ${Memory_Configuration} + set DMEM_AW [ipgui::add_param $IPINST -name "DMEM_AW" -parent ${Memory_Configuration}] + set_property tooltip {DmemAw} ${DMEM_AW} + ipgui::add_param $IPINST -name "WMEM_AW" -parent ${Memory_Configuration} + + #Adding Group + set IN_Port_Configuration [ipgui::add_group $IPINST -name "IN Port Configuration" -parent ${Process} -display_name {IN Configuration} -layout horizontal] + #Adding Group + set QICK_PORTS [ipgui::add_group $IPINST -name "QICK PORTS" -parent ${IN_Port_Configuration}] + set_property tooltip {G_PORTS} ${QICK_PORTS} + ipgui::add_param $IPINST -name "IN_PORT_QTY" -parent ${QICK_PORTS} + ipgui::add_param $IPINST -name "EXT_FLAG" -parent ${QICK_PORTS} -widget checkBox + + #Adding Group + set QICK_CONTROL [ipgui::add_group $IPINST -name "QICK CONTROL" -parent ${IN_Port_Configuration}] + set_property tooltip {GCTRL} ${QICK_CONTROL} + set IO_CTRL [ipgui::add_param $IPINST -name "IO_CTRL" -parent ${QICK_CONTROL} -widget checkBox] + set_property tooltip {External Inputs Qick Control Pins} ${IO_CTRL} + ipgui::add_param $IPINST -name "TIME_CTRL" -parent ${QICK_CONTROL} -widget checkBox + ipgui::add_param $IPINST -name "CORE_CTRL" -parent ${QICK_CONTROL} -widget checkBox + + + #Adding Group + set OUT_Port_Configuration [ipgui::add_group $IPINST -name "OUT Port Configuration" -parent ${Process} -display_name {OUT Configuration} -layout horizontal] + set_property tooltip {OUT Configuration} ${OUT_Port_Configuration} + #Adding Group + set GROUP1 [ipgui::add_group $IPINST -name "GROUP1" -parent ${OUT_Port_Configuration} -display_name {QICK PORTS}] + set_property tooltip {G_PORTS} ${GROUP1} + ipgui::add_param $IPINST -name "OUT_TRIG_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_WPORT_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_DPORT_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_DPORT_DW" -parent ${GROUP1} + ipgui::add_param $IPINST -name "FIFO_DEPTH" -parent ${GROUP1} -widget comboBox + + #Adding Group + set GROUP [ipgui::add_group $IPINST -name "GROUP" -parent ${OUT_Port_Configuration} -display_name {QICK SIGNALS}] + set_property tooltip {G_SIGNALS} ${GROUP} + ipgui::add_param $IPINST -name "OUT_TIME" -parent ${GROUP} -widget checkBox + ipgui::add_param $IPINST -name "GEN_SYNC" -parent ${GROUP} -widget checkBox + + + #Adding Group + set Options [ipgui::add_group $IPINST -name "Options" -parent ${Process} -display_name {Internal Peripherals} -layout horizontal] + set LFSR [ipgui::add_param $IPINST -name "LFSR" -parent ${Options} -widget checkBox] + set_property tooltip {Linear Feedback Shit Register} ${LFSR} + ipgui::add_param $IPINST -name "ARITH" -parent ${Options} -widget checkBox + set DIVIDER [ipgui::add_param $IPINST -name "DIVIDER" -parent ${Options} -widget checkBox] + set_property tooltip {32-bit Integer Divider (Quotient - Reminder)} ${DIVIDER} + ipgui::add_param $IPINST -name "TIME_READ" -parent ${Options} -widget checkBox + + #Adding Group + set External_Peripherals [ipgui::add_group $IPINST -name "External Peripherals" -parent ${Process} -display_name {External Peripherals Interfaces}] + ipgui::add_param $IPINST -name "QNET" -parent ${External_Peripherals} -widget checkBox + ipgui::add_param $IPINST -name "QCOM" -parent ${External_Peripherals} -widget checkBox + ipgui::add_param $IPINST -name "CUSTOM_PERIPH" -parent ${External_Peripherals} -widget comboBox + + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ARITH { PARAM_VALUE.ARITH } { + # Procedure called to update ARITH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARITH { PARAM_VALUE.ARITH } { + # Procedure called to validate ARITH + return true +} + +proc update_PARAM_VALUE.CALL_DEPTH { PARAM_VALUE.CALL_DEPTH } { + # Procedure called to update CALL_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CALL_DEPTH { PARAM_VALUE.CALL_DEPTH } { + # Procedure called to validate CALL_DEPTH + return true +} + +proc update_PARAM_VALUE.CORE_CTRL { PARAM_VALUE.CORE_CTRL } { + # Procedure called to update CORE_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CORE_CTRL { PARAM_VALUE.CORE_CTRL } { + # Procedure called to validate CORE_CTRL + return true +} + +proc update_PARAM_VALUE.CUSTOM_PERIPH { PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to update CUSTOM_PERIPH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CUSTOM_PERIPH { PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to validate CUSTOM_PERIPH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.DIVIDER { PARAM_VALUE.DIVIDER } { + # Procedure called to update DIVIDER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIVIDER { PARAM_VALUE.DIVIDER } { + # Procedure called to validate DIVIDER + return true +} + +proc update_PARAM_VALUE.DMEM_AW { PARAM_VALUE.DMEM_AW } { + # Procedure called to update DMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMEM_AW { PARAM_VALUE.DMEM_AW } { + # Procedure called to validate DMEM_AW + return true +} + +proc update_PARAM_VALUE.DUAL_CORE { PARAM_VALUE.DUAL_CORE } { + # Procedure called to update DUAL_CORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DUAL_CORE { PARAM_VALUE.DUAL_CORE } { + # Procedure called to validate DUAL_CORE + return true +} + +proc update_PARAM_VALUE.EXT_FLAG { PARAM_VALUE.EXT_FLAG } { + # Procedure called to update EXT_FLAG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_FLAG { PARAM_VALUE.EXT_FLAG } { + # Procedure called to validate EXT_FLAG + return true +} + +proc update_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to update FIFO_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to validate FIFO_DEPTH + return true +} + +proc update_PARAM_VALUE.GEN_SYNC { PARAM_VALUE.GEN_SYNC } { + # Procedure called to update GEN_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.GEN_SYNC { PARAM_VALUE.GEN_SYNC } { + # Procedure called to validate GEN_SYNC + return true +} + +proc update_PARAM_VALUE.IN_PORT_QTY { PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to update IN_PORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_PORT_QTY { PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to validate IN_PORT_QTY + return true +} + +proc update_PARAM_VALUE.IO_CTRL { PARAM_VALUE.IO_CTRL } { + # Procedure called to update IO_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_CTRL { PARAM_VALUE.IO_CTRL } { + # Procedure called to validate IO_CTRL + return true +} + +proc update_PARAM_VALUE.LFSR { PARAM_VALUE.LFSR } { + # Procedure called to update LFSR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LFSR { PARAM_VALUE.LFSR } { + # Procedure called to validate LFSR + return true +} + +proc update_PARAM_VALUE.OUT_DPORT_DW { PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to update OUT_DPORT_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_DPORT_DW { PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to validate OUT_DPORT_DW + return true +} + +proc update_PARAM_VALUE.OUT_DPORT_QTY { PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to update OUT_DPORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_DPORT_QTY { PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to validate OUT_DPORT_QTY + return true +} + +proc update_PARAM_VALUE.OUT_TIME { PARAM_VALUE.OUT_TIME } { + # Procedure called to update OUT_TIME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TIME { PARAM_VALUE.OUT_TIME } { + # Procedure called to validate OUT_TIME + return true +} + +proc update_PARAM_VALUE.OUT_TRIG_QTY { PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to update OUT_TRIG_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TRIG_QTY { PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to validate OUT_TRIG_QTY + return true +} + +proc update_PARAM_VALUE.OUT_WPORT_QTY { PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to update OUT_WPORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_WPORT_QTY { PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to validate OUT_WPORT_QTY + return true +} + +proc update_PARAM_VALUE.PMEM_AW { PARAM_VALUE.PMEM_AW } { + # Procedure called to update PMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PMEM_AW { PARAM_VALUE.PMEM_AW } { + # Procedure called to validate PMEM_AW + return true +} + +proc update_PARAM_VALUE.QCOM { PARAM_VALUE.QCOM } { + # Procedure called to update QCOM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QCOM { PARAM_VALUE.QCOM } { + # Procedure called to validate QCOM + return true +} + +proc update_PARAM_VALUE.QNET { PARAM_VALUE.QNET } { + # Procedure called to update QNET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QNET { PARAM_VALUE.QNET } { + # Procedure called to validate QNET + return true +} + +proc update_PARAM_VALUE.REG_AW { PARAM_VALUE.REG_AW } { + # Procedure called to update REG_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.REG_AW { PARAM_VALUE.REG_AW } { + # Procedure called to validate REG_AW + return true +} + +proc update_PARAM_VALUE.TIME_CTRL { PARAM_VALUE.TIME_CTRL } { + # Procedure called to update TIME_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TIME_CTRL { PARAM_VALUE.TIME_CTRL } { + # Procedure called to validate TIME_CTRL + return true +} + +proc update_PARAM_VALUE.TIME_READ { PARAM_VALUE.TIME_READ } { + # Procedure called to update TIME_READ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TIME_READ { PARAM_VALUE.TIME_READ } { + # Procedure called to validate TIME_READ + return true +} + +proc update_PARAM_VALUE.WMEM_AW { PARAM_VALUE.WMEM_AW } { + # Procedure called to update WMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WMEM_AW { PARAM_VALUE.WMEM_AW } { + # Procedure called to validate WMEM_AW + return true +} + + +proc update_MODELPARAM_VALUE.PMEM_AW { MODELPARAM_VALUE.PMEM_AW PARAM_VALUE.PMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PMEM_AW}] ${MODELPARAM_VALUE.PMEM_AW} +} + +proc update_MODELPARAM_VALUE.DMEM_AW { MODELPARAM_VALUE.DMEM_AW PARAM_VALUE.DMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMEM_AW}] ${MODELPARAM_VALUE.DMEM_AW} +} + +proc update_MODELPARAM_VALUE.WMEM_AW { MODELPARAM_VALUE.WMEM_AW PARAM_VALUE.WMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WMEM_AW}] ${MODELPARAM_VALUE.WMEM_AW} +} + +proc update_MODELPARAM_VALUE.REG_AW { MODELPARAM_VALUE.REG_AW PARAM_VALUE.REG_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REG_AW}] ${MODELPARAM_VALUE.REG_AW} +} + +proc update_MODELPARAM_VALUE.IN_PORT_QTY { MODELPARAM_VALUE.IN_PORT_QTY PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_PORT_QTY}] ${MODELPARAM_VALUE.IN_PORT_QTY} +} + +proc update_MODELPARAM_VALUE.OUT_DPORT_QTY { MODELPARAM_VALUE.OUT_DPORT_QTY PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_DPORT_QTY}] ${MODELPARAM_VALUE.OUT_DPORT_QTY} +} + +proc update_MODELPARAM_VALUE.OUT_WPORT_QTY { MODELPARAM_VALUE.OUT_WPORT_QTY PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_WPORT_QTY}] ${MODELPARAM_VALUE.OUT_WPORT_QTY} +} + +proc update_MODELPARAM_VALUE.LFSR { MODELPARAM_VALUE.LFSR PARAM_VALUE.LFSR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LFSR}] ${MODELPARAM_VALUE.LFSR} +} + +proc update_MODELPARAM_VALUE.DIVIDER { MODELPARAM_VALUE.DIVIDER PARAM_VALUE.DIVIDER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIVIDER}] ${MODELPARAM_VALUE.DIVIDER} +} + +proc update_MODELPARAM_VALUE.ARITH { MODELPARAM_VALUE.ARITH PARAM_VALUE.ARITH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARITH}] ${MODELPARAM_VALUE.ARITH} +} + +proc update_MODELPARAM_VALUE.TIME_READ { MODELPARAM_VALUE.TIME_READ PARAM_VALUE.TIME_READ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TIME_READ}] ${MODELPARAM_VALUE.TIME_READ} +} + +proc update_MODELPARAM_VALUE.DUAL_CORE { MODELPARAM_VALUE.DUAL_CORE PARAM_VALUE.DUAL_CORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DUAL_CORE}] ${MODELPARAM_VALUE.DUAL_CORE} +} + +proc update_MODELPARAM_VALUE.IO_CTRL { MODELPARAM_VALUE.IO_CTRL PARAM_VALUE.IO_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_CTRL}] ${MODELPARAM_VALUE.IO_CTRL} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.CUSTOM_PERIPH { MODELPARAM_VALUE.CUSTOM_PERIPH PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CUSTOM_PERIPH}] ${MODELPARAM_VALUE.CUSTOM_PERIPH} +} + +proc update_MODELPARAM_VALUE.OUT_DPORT_DW { MODELPARAM_VALUE.OUT_DPORT_DW PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_DPORT_DW}] ${MODELPARAM_VALUE.OUT_DPORT_DW} +} + +proc update_MODELPARAM_VALUE.OUT_TRIG_QTY { MODELPARAM_VALUE.OUT_TRIG_QTY PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TRIG_QTY}] ${MODELPARAM_VALUE.OUT_TRIG_QTY} +} + +proc update_MODELPARAM_VALUE.FIFO_DEPTH { MODELPARAM_VALUE.FIFO_DEPTH PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_DEPTH}] ${MODELPARAM_VALUE.FIFO_DEPTH} +} + +proc update_MODELPARAM_VALUE.EXT_FLAG { MODELPARAM_VALUE.EXT_FLAG PARAM_VALUE.EXT_FLAG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_FLAG}] ${MODELPARAM_VALUE.EXT_FLAG} +} + +proc update_MODELPARAM_VALUE.QCOM { MODELPARAM_VALUE.QCOM PARAM_VALUE.QCOM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QCOM}] ${MODELPARAM_VALUE.QCOM} +} + +proc update_MODELPARAM_VALUE.CALL_DEPTH { MODELPARAM_VALUE.CALL_DEPTH PARAM_VALUE.CALL_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CALL_DEPTH}] ${MODELPARAM_VALUE.CALL_DEPTH} +} + +proc update_MODELPARAM_VALUE.OUT_TIME { MODELPARAM_VALUE.OUT_TIME PARAM_VALUE.OUT_TIME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TIME}] ${MODELPARAM_VALUE.OUT_TIME} +} + +proc update_MODELPARAM_VALUE.QNET { MODELPARAM_VALUE.QNET PARAM_VALUE.QNET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QNET}] ${MODELPARAM_VALUE.QNET} +} + +proc update_MODELPARAM_VALUE.TIME_CTRL { MODELPARAM_VALUE.TIME_CTRL PARAM_VALUE.TIME_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TIME_CTRL}] ${MODELPARAM_VALUE.TIME_CTRL} +} + +proc update_MODELPARAM_VALUE.CORE_CTRL { MODELPARAM_VALUE.CORE_CTRL PARAM_VALUE.CORE_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CORE_CTRL}] ${MODELPARAM_VALUE.CORE_CTRL} +} + +proc update_MODELPARAM_VALUE.GEN_SYNC { MODELPARAM_VALUE.GEN_SYNC PARAM_VALUE.GEN_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.GEN_SYNC}] ${MODELPARAM_VALUE.GEN_SYNC} +} + diff --git a/firmware/ip/qick_sg_translator/component.xml b/firmware/ip/qick_sg_translator/component.xml new file mode 100644 index 000000000..a4a212f08 --- /dev/null +++ b/firmware/ip/qick_sg_translator/component.xml @@ -0,0 +1,759 @@ + + + QICK + QICK + sg_translator + 1.0 + + + m_int4_axis + + + + + + + TDATA + + + m_int4_axis_tdata + + + + + TVALID + + + m_int4_axis_tvalid + + + + + TREADY + + + m_int4_axis_tready + + + + + + + false + + + + + + m_mux4_axis + + + + + + + TDATA + + + m_mux4_axis_tdata + + + + + TVALID + + + m_mux4_axis_tvalid + + + + + TREADY + + + m_mux4_axis_tready + + + + + + + false + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_int4_axis:m_mux4_axis:s_tproc_axis:m_gen_v6_axis:m_readout_v3_axis + + + ASSOCIATED_RESET + aresetn + + + + + m_gen_v6_axis + + + + true + + + + TDATA + + + m_gen_v6_axis_tdata + + + + + TVALID + + + m_gen_v6_axis_tvalid + + + + + TREADY + + + m_gen_v6_axis_tready + + + + + + NUM_READ_OUTSTANDING + + + + NUM_WRITE_OUTSTANDING + + + + + + + true + + + + + + s_tproc_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + m_readout_v3_axis + + + + true + + + + TVALID + + + m_readout_axis_tvalid + + + + + TREADY + + + m_readout_axis_tready + + + + + TDATA + + + m_readout_axis_tdata + + + + + + + false + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + sg_translator + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ef542ab9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + sg_translator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ef542ab9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 7315fcc5 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 167 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tdata + + out + + 159 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tdata + + out + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_mux4_axis_tdata + + out + + 39 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_mux4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_mux4_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_readout_axis_tdata + + out + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_readout_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_readout_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + OUT_TYPE + Out Type + 0 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_ea9dd076 + 0 + 1 + 2 + 3 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/sg_translator.v + verilogSource + CHECKSUM_ef542ab9 + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/sg_translator.v + verilogSource + IMPORTED_FILE + + + + xilinx_xpgui_view_fileset + + xgui/sg_translator_v1_0.tcl + tclSource + CHECKSUM_7315fcc5 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + qick_sg_translator + + + OUT_TYPE + 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a/firmware/ip/qick_sg_translator/src/sg_translator.v b/firmware/ip/qick_sg_translator/src/sg_translator.v new file mode 100644 index 000000000..4e2faff87 --- /dev/null +++ b/firmware/ip/qick_sg_translator/src/sg_translator.v @@ -0,0 +1,152 @@ +/* +TRANSLATE from tProc_v2 to diferente Signals Souorces. + +// tProc-v2 OUT +// |-----------|-----------|-----------|-----------|-----------|-----------| +// | 167..152 | 151..120 | 119..88 | 87..64 | 63..32 | 31..0 | +// |-----------|-----------|-----------|-----------|-----------|-----------| +// | CONF | LENGHT | GAIN | ENV | PHASE | FREQ | +// | 16-bit | 32-bit | 32-bit | 24-bit | 32-bit | 32-bit | +// |-----------|-----------|-----------|-----------|-----------|-----------| + + +*/ +module sg_translator # ( + OUT_TYPE = 0 // (0:gen_v6, 1:int4_v1, 2:mux4_v1, 3:readout) +) ( + // Reset and clock. + input wire aresetn , + input wire aclk , + // IN WAVE PORT + input wire [167:0] s_axis_tdata , + input wire s_axis_tvalid , + output wire s_axis_tready , + // OUT DATA gen_v6 (SEL:0) + output wire [159:0] m_gen_v6_axis_tdata , + output wire m_gen_v6_axis_tvalid , + input wire m_gen_v6_axis_tready , + // OUT DATA int4_v1 (SEL:1) + output wire [87:0] m_int4_axis_tdata , + output wire m_int4_axis_tvalid , + input wire m_int4_axis_tready , + // OUT DATA mux4_v1 (SEL:2) + output wire [39:0] m_mux4_axis_tdata , + output wire m_mux4_axis_tvalid , + input wire m_mux4_axis_tready , + // OUT DATA readout_v3 (SEL:3) + output wire [87:0] m_readout_axis_tdata , + output wire m_readout_axis_tvalid , + input wire m_readout_axis_tready +); + +// GET Data from tPtoc_v2 +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] freq, phase, gain, nsamp ; +wire [23:0] addr ; +wire [23:0] conf ; + +wire [1:0] outsel ; +wire mode, stdysel, phrst; + +assign conf = s_axis_tdata[167:152] ; +assign nsamp = s_axis_tdata[151:120] ; +assign gain = s_axis_tdata[119: 88] ; +assign addr = s_axis_tdata[ 87: 64] ; +assign phase = s_axis_tdata[ 63: 32] ; +assign freq = s_axis_tdata[ 31: 0] ; + +assign phrst = conf[4] ; +assign stdysel = conf[3] ; +assign mode = conf[2] ; +assign outsel = conf[1:0] ; + + +assign gen_v6_en = (OUT_TYPE == 0) ; +assign int4_en = (OUT_TYPE == 1) ; +assign mux4_en = (OUT_TYPE == 2) ; +assign readout_en = (OUT_TYPE == 3) ; + +// OUTPUTS + +/////////////////////////////////////////////////////////////////////////////// +assign s_axis_tready = ( gen_v6_en ) ? m_gen_v6_axis_tready : ( + ( int4_en ) ? m_int4_axis_tready : ( + ( mux4_en ) ? m_mux4_axis_tready : ( + ( readout_en ) ? m_readout_axis_tready : 0 ))); +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// axis_signal_gen_v6 +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +assign m_gen_v6_axis_tdata[159:149] = 0 ; +assign m_gen_v6_axis_tdata[148] = phrst ; +assign m_gen_v6_axis_tdata[147] = stdysel ; +assign m_gen_v6_axis_tdata[146] = mode ; +assign m_gen_v6_axis_tdata[145:144] = outsel ; +assign m_gen_v6_axis_tdata[143:128] = nsamp [15:0] ; +assign m_gen_v6_axis_tdata[127:112] = 0 ; +assign m_gen_v6_axis_tdata[111: 96] = gain [15:0] ; +assign m_gen_v6_axis_tdata[ 95: 80] = 0 ; +assign m_gen_v6_axis_tdata[ 79: 64] = addr [15:0] ; +assign m_gen_v6_axis_tdata[ 63: 32] = phase [31:0] ; +assign m_gen_v6_axis_tdata[ 31: 0] = freq [31:0] ; + +assign m_gen_v6_axis_tvalid = gen_v6_en ? s_axis_tvalid : 0 ; + + +/////////////////////////////////////////////////////////////////////////////// +// axis_sg_int4_v1 +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 48 | 47 .. 32 | 31 .. 16 | 15 .. 0 | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | phrst | stdysel | mode | outsel | nsamp | gain | addr | phase | freq | +// | 1-bit | 1-bit | 1-bit| 2-bit | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit| +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +assign m_int4_axis_tdata[87:85] = 0 ; +assign m_int4_axis_tdata[84] = phrst ; +assign m_int4_axis_tdata[83] = stdysel ; +assign m_int4_axis_tdata[82] = mode ; +assign m_int4_axis_tdata[81:80] = outsel ; +assign m_int4_axis_tdata[79:64] = nsamp [15:0] ; +assign m_int4_axis_tdata[63:48] = gain [15:0] ; +assign m_int4_axis_tdata[47:32] = addr [15:0] ; +assign m_int4_axis_tdata[31:16] = phase [15:0] ; +assign m_int4_axis_tdata[15:0 ] = freq [15:0] ; + +assign m_int4_axis_tvalid = int4_en ? s_axis_tvalid : 0 ; + +/////////////////////////////////////////////////////////////////////////////// +// axis_sg_mux_4_v1 +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +assign m_mux4_axis_tdata[39:32] = conf [7: 0] ; +assign m_mux4_axis_tdata[31:0] = nsamp [31:0] ; + +assign m_mux4_axis_tvalid = mux4_en ? s_axis_tvalid : 0 ; + +/////////////////////////////////////////////////////////////////////////////// +// axis_readout_v3 +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +assign m_readout_axis_tdata[87:84] = 0 ; +assign m_readout_axis_tdata[83] = phrst ; +assign m_readout_axis_tdata[82] = mode ; +assign m_readout_axis_tdata[81:80] = outsel ; +assign m_readout_axis_tdata[79:64 ] = nsamp [15:0] ; +assign m_readout_axis_tdata[ 63: 32] = phase [31:0] ; +assign m_readout_axis_tdata[ 31: 0] = freq [31:0] ; + +assign m_readout_axis_tvalid = readout_en ? s_axis_tvalid : 0 ; + +endmodule diff --git a/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl b/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl new file mode 100644 index 000000000..9b06bbc9d --- /dev/null +++ b/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl @@ -0,0 +1,22 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "OUT_TYPE" + +} + +proc update_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to update OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to validate OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.OUT_TYPE { MODELPARAM_VALUE.OUT_TYPE PARAM_VALUE.OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TYPE}] ${MODELPARAM_VALUE.OUT_TYPE} +} + diff --git a/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl b/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl new file mode 100644 index 000000000..9b06bbc9d --- /dev/null +++ b/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl @@ -0,0 +1,22 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "OUT_TYPE" + +} + +proc update_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to update OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to validate OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.OUT_TYPE { MODELPARAM_VALUE.OUT_TYPE PARAM_VALUE.OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TYPE}] ${MODELPARAM_VALUE.OUT_TYPE} +} + diff --git a/firmware/ip/qick_time_tagger/component.xml b/firmware/ip/qick_time_tagger/component.xml new file mode 100644 index 000000000..3f56ab9c6 --- /dev/null +++ b/firmware/ip/qick_time_tagger/component.xml @@ -0,0 +1,1970 @@ + + + QICK + QICK + qick_time_tagger + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + adc_aresetn + + + + + + + RST + + + adc_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_aresetn + + + ASSOCIATED_BUSIF + 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Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_qick_time_tagger + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 52ef8718 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb_qtt_cmp + + xilinx_testbench_view_fileset + + + + viewChecksum + 642ce9cc + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c492f711 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + c_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + c_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_aresetn + + in + + + wire + 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dma_m_axis_tvalid_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tdata_o + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tlast_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qtt_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + CMP_SLOPE + Cmp Slope + 0 + + + CMP_INTER + Cmp Inter + 4 + + + TAG_FIFO_AW + Tag Fifo Aw + 16 + + + SMP_DW + Smp Dw + 16 + + + SMP_CK + Smp Ck + 8 + + + SMP_STORE + Smp Store + 0 + + + SMP_FIFO_AW + Smp Fifo Aw + 18 + + + DEBUG + Debug + 1 + + + ADC_QTY + Adc Qty + 1 + + + ARM_STORE + Arm Store + 1 + + + ARM_FIFO_AW + Arm Fifo Aw + 10 + + + EXT_ARM + Ext Arm + 0 + + + + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_pairs_2501fc2f + 0 + 1 + 2 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qtt_dma.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/_qtt_ips.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/_qtt_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qtt_cmd.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qtt_tag_calc.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/smp_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/tag_gen.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/tag_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/axi_slv_qtt.vhd + vhdlSource + IMPORTED_FILE + + + src/axi_qick_time_tagger.sv + systemVerilogSource + CHECKSUM_0bd61aa1 + IMPORTED_FILE + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qtt_dma.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/_qtt_ips.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/_qtt_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qtt_cmd.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/qtt_tag_calc.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/smp_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/tag_gen.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/tag_mem.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + src/axi_slv_qtt.vhd + vhdlSource + IMPORTED_FILE + + + src/axi_qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + xil_defaultlib + + + + xilinx_testbench_view_fileset + + src/TB/tb_tag_fifo.wcfg + unknown + + + src/TB/tb_qtag_behav.wcfg + unknown + + + src/TB/tb_fifo_dma_behav.wcfg + unknown + + + src/TB/tb_smp_fifo.wcfg + unknown + + + src/TB/thr_cmp.sv + systemVerilogSource + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + xil_defaultlib + + + src/axi_mst_0/axi_mst_0.xci + xci + + + src/TB/tb_qtag.sv + systemVerilogSource + xil_defaultlib + + + src/TB/tb_qtt_cmp.sv + systemVerilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + xil_defaultlib + + + src/TB/tb_tag_fifo.sv + systemVerilogSource + xil_defaultlib + + + src/TB/tb_fifo_dma.sv + systemVerilogSource + xil_defaultlib + + + src/TB/tb_smp_fifo.sv + systemVerilogSource + xil_defaultlib + + + src/TB/tb_qtt_cmp_behav.wcfg + unknown + + + + xilinx_xpgui_view_fileset + + xgui/qick_time_tagger_v1_0.tcl + tclSource + CHECKSUM_c492f711 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + image + LOGO + + + + qick_time_tagger + + + CMP_SLOPE + Compare with Slope (Constant Fraction Discrimination) + 0 + + + CMP_INTER + Interpolation bits (0 No interpolation) + 4 + + + TAG_FIFO_AW + TAG FIFO Address width + 16 + + + SMP_DW + Smp Dw + 16 + + + SMP_CK + Smp Ck + 8 + + + SMP_STORE + Store Samples + 0 + + + SMP_FIFO_AW + Sample FIFO Address Width + 18 + + + DEBUG + Debug + 1 + + + Component_Name + axi_qick_time_tagger_v1_0 + + + ADC_QTY + Number of ADCs + 1 + + + ARM_STORE + Store Number of Triggers per ARM in ADC0 + 1 + + + ARM_FIFO_AW + ARM Triggers FIFO Address Width + 10 + + + EXT_ARM + IO ARM Control + 0 + + + + + + /QICK/QICK_Peripheral + + qick_time_tagger + level_2 + package_project + + XPM_CDC + + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 29 + 2025-11-10T19:12:39Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv new file mode 100644 index 000000000..83fd54db1 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv @@ -0,0 +1,308 @@ +//////4///////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define HP_CLK 3 // Half Clock Period for Simulation +`define HP_CCLK 2 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_fifo_dma(); + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i, ready; +reg rst_ni; + +// CLK Generation +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`HP_CCLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`HP_CCLK) rd_clk_i = ~rd_clk_i; +end +initial begin + ready = 1'b0; + forever begin + #(1) + //#(16) + //#(24) + //#(34) + //#(37) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + + +parameter DW = 32 ; +parameter AW = 16 ; + +reg rst_ni; + + +wire [2:0] trig_inter; +reg [DW-1:0] data_i; +wire [DW-1:0] data_0; +wire [20:0] dma_qty_o, rd_qty_o; +/* +FIFO_SC_DMA # ( + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dma ( + .clk_i ( wr_clk_i ) , + .rst_ni ( rst_ni ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .rd_pop_i ( rd_pop_i ) , + .rd_pop_o ( rd_pop_o ) , + .rd_qty_o ( rd_qty_o ) , + .rd_empty_o ( ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_qty_o ( dma_qty_o ) , + .dma_empty_o ( async_empty_o ) , + .dt_o ( ) , + .full_o ( async_full_o ) ); +*/ + +reg push_i, rd_pop_i, dma_pop_i; +reg flush_i; +/* +FIFO_DC_DMA # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dc_dma ( + .wr_clk_i ( wr_clk_i ) , + .wr_rst_ni ( rst_ni ) , + .rd_clk_i ( rd_clk_i ) , + .rd_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .rd_pop_i ( rd_pop_i ) , + .rd_pop_o ( ) , + .rd_qty_o ( ) , + .rd_empty_o ( ) , + .dma_pop_i ( fifo_pop_o ) , + .dma_pop_o ( fifo_pop_i ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( fifo_dt_o ) , + .full_o ( ) ); + +FIFO_DC_DMA_2 # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dc_dma_2 ( + .wr_clk_i ( wr_clk_i ) , + .wr_rst_ni ( rst_ni ) , + .rd_clk_i ( rd_clk_i ) , + .rd_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .proc_pop_i ( rd_pop_i ) , + .proc_pop_o ( ) , + .proc_qty_o ( ) , + .proc_empty_o ( ) , + .dma_pop_i ( fifo_pop_o ) , + .dma_pop_o ( ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( ) , + .full_o ( ) ); +*/ +TAG_FIFO_TC # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( 32 ) , + .FIFO_AW ( AW ) +) tag_mem ( + .dma_clk_i ( rd_clk_i ) , + .dma_rst_ni ( rst_ni ) , + .c_clk_i ( rd_clk_i ) , + .c_rst_ni ( rst_ni ) , + .adc_clk_i ( wr_clk_i ) , + .adc_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .adc_push_i ( push_i ) , + .adc_data_i ( data_i ) , + .c_pop_i ( rd_pop_i ) , + .c_pop_o ( ) , + .c_qty_o ( ) , + .c_empty_o ( ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( fifo_dt_o ) , + .full_o ( ) ); + +wire [DW-1:0] fifo_dt_o; +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .fifo_pop_o ( dma_pop_i ) , + .fifo_pop_i ( dma_pop_o ) , + .fifo_dt_i ( fifo_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + + +initial begin + START_SIMULATION(); + FIFO_PUSH(); // Write 20 + #50; + FIFO_RD(); //Read 5 + #50; + FIFO_DMA(); //Read 10 + #50; + FIFO_BOTH(); //Read 10 and 10 + #50; + FIFO_PUSH(); // Write 20 + #50; + FIFO_BOTH(); //Read 10 and 10 + #50; + FIFO_RD_BOTH_WR(); //Read 10 and 10writes 10 +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + rd_pop_i = 1'b0; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 10; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t; + + +task FIFO_PUSH(); begin + $display("PUSH DATA"); + for (t=0; t<32; t=t+1) begin + data_i = t; + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + @ (posedge wr_clk_i); #0.1; + end + push_i = 1'b0; +end +endtask + +task FIFO_RD(); begin + $display("RD DATA"); + for (t=0; t<5; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + end + #10; +end +endtask + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + +task FIFO_BOTH(); begin + $display("RD and DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + + for (t=0; t<10; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + end + #10; + wait ( dma_ack_o == 1'b0); + #10; + #10; +end +endtask + +task FIFO_RD_BOTH_WR(); begin + $display("RD and DMA DATA and PUSH"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + + for (t=0; t<10; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + + #10; + @ (posedge wr_clk_i); #0.1; + data_i = t; + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + + end + #10; + + wait ( dma_ack_o == 1'b0); + #10; + #10; +end +endtask +endmodule + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg new file mode 100644 index 000000000..740b0cb07 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_push_i + adc_push_i + #D2691E + true + + + c_pop_i + c_pop_i + #D2691E + true + + + dma_pop_i + dma_pop_i + #D2691E + true + + + flush_i + flush_i + #D2691E + true + + + do_dma_pop + do_dma_pop + #D2691E + true + + + do_proc_pop + do_proc_pop + #D2691E + true + + + do_push + do_push + #D2691E + true + + + c_pop_o + c_pop_o + #D2691E + true + + + dma_pop_o + dma_pop_o + #D2691E + true + + + dt_o[31:0] + dt_o[31:0] + #D2691E + true + UNSIGNEDDECRADIX + + + m_axis_tready_i + m_axis_tready_i + #0000FF + true + + + m_axis_tdata_o[31:0] + m_axis_tdata_o[31:0] + #0000FF + true + UNSIGNEDDECRADIX + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + dma_rd_st[31:0] + dma_rd_st[31:0] + + + len_cnt[15:0] + len_cnt[15:0] + UNSIGNEDDECRADIX + + + len_cnt_en + len_cnt_en + + + lp_cnt[3:0] + lp_cnt[3:0] + UNSIGNEDDECRADIX + + + lp_cnt_en + lp_cnt_en + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv b/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv new file mode 100644 index 000000000..88ef5559b --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv @@ -0,0 +1,434 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_PS_CLK 11 // Half Clock Period for Simulation +`define T_C_CLK 3 // 1.66 // Half Clock Period for Simulation +`define T_ADC_CLK 2 // 1.66 // Half Clock Period for Simulation + +`define ADC_QTY 1 +`define DMA_RD 1 +`define PROC_RD 0 +`define CMP_SLOPE 0 +`define CMP_INTER 4 +`define ARM_STORE 1 +`define SMP_STORE 1 +`define TAG_FIFO_AW 19 +`define ARM_FIFO_AW 5 +`define SMP_FIFO_AW 15 +`define SMP_DW 16 +`define SMP_CK 8 +`define DEBUG 1 + +module tb_qtag(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, adc_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +integer t; +real x [`SMP_CK]; +reg [`SMP_DW-1:0] y [`SMP_CK]; +reg [`SMP_DW*`SMP_CK-1:0] adc_dt ; +wire [`SMP_DW*`SMP_CK-1:0] adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i, adc3_s_axis_tdata_i ; + + +assign adc0_s_axis_tdata_i = adc_dt; +assign adc1_s_axis_tdata_i = adc_dt; +assign adc2_s_axis_tdata_i = adc_dt; +assign adc3_s_axis_tdata_i = adc_dt; + + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + adc_clk = 1'b0; + forever # (`T_ADC_CLK) adc_clk = ~adc_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end + +reg arm_i; +reg qtag_en_i ; +reg [4 :0] qtag_op_i ; +reg [31:0] qtag_dt1_i, qtag_dt2_i, qtag_dt3_i, qtag_dt4_i ; + +wire qtag_rdy_o, qtag_vld_o, qtag_flag_o ; +wire [31:0] qtag_dt1_o, qtag_dt2_o; + +//reg [15:0] threshold; +//wire[31:0] time_ck_s0 , time_ck_s1 , time_ck_s2 , time_ck_s3 ; +//wire[2:0] time_adc_s0, time_adc_s1, time_adc_s2, time_adc_s3; +//wire[3:0] time_int_s0, time_int_s1, time_int_s2, time_int_s3; + + +// Register ADDRESS +parameter QTT_CTRL = 0 * 4 ; +parameter QTT_CFG = 1 * 4 ; +parameter DMA_CFG = 2 * 4 ; +parameter AXI_DT1 = 3 * 4 ; +parameter PROC_DT = 5 * 4 ; +parameter PROC_QTY = 6 * 4 ; +parameter TAG0_QTY = 7 * 4 ; +parameter TAG1_QTY = 8 * 4 ; +parameter TAG2_QTY = 9 * 4 ; +parameter TAG3_QTY = 10* 4 ; +parameter SMP_QTY = 11* 4 ; +parameter ARM_QTY = 12* 4 ; + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk ( ps_clk ), + .aresetn ( rst_ni ), + .m_axi_araddr ( s_axi_araddr ), + .m_axi_arprot ( s_axi_arprot ), + .m_axi_arready ( s_axi_arready ), + .m_axi_arvalid ( s_axi_arvalid ), + .m_axi_awaddr ( s_axi_awaddr ), + .m_axi_awprot ( s_axi_awprot ), + .m_axi_awready ( s_axi_awready ), + .m_axi_awvalid ( s_axi_awvalid ), + .m_axi_bready ( s_axi_bready ), + .m_axi_bresp ( s_axi_bresp ), + .m_axi_bvalid ( s_axi_bvalid ), + .m_axi_rdata ( s_axi_rdata ), + .m_axi_rready ( s_axi_rready ), + .m_axi_rresp ( s_axi_rresp ), + .m_axi_rvalid ( s_axi_rvalid ), + .m_axi_wdata ( s_axi_wdata ), + .m_axi_wready ( s_axi_wready ), + .m_axi_wstrb ( s_axi_wstrb ), + .m_axi_wvalid ( s_axi_wvalid )); + +axi_qick_time_tagger # ( + .ADC_QTY ( `ADC_QTY ) , +// .DMA_RD ( `DMA_RD ) , +// .PROC_RD ( `PROC_RD ) , + .CMP_SLOPE ( `CMP_SLOPE ) , + .CMP_INTER ( `CMP_INTER ) , + .ARM_STORE ( `ARM_STORE ) , + .SMP_STORE ( `SMP_STORE ) , + .TAG_FIFO_AW ( `TAG_FIFO_AW ) , + .ARM_FIFO_AW ( `ARM_FIFO_AW ) , + .SMP_FIFO_AW ( `SMP_FIFO_AW ) , + .SMP_DW ( `SMP_DW ) , + .SMP_CK ( `SMP_CK ) , + .DEBUG ( `DEBUG ) +) axi_qick_time_tagger ( +// Core and AXI CLK & RST + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .adc_clk ( adc_clk ) , + .adc_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .arm_i ( arm_i ) , + .qtag_en_i ( qtag_en_i ) , + .qtag_op_i ( qtag_op_i ) , + .qtag_dt1_i ( qtag_dt1_i ) , + .qtag_dt2_i ( qtag_dt2_i ) , + .qtag_dt3_i ( qtag_dt3_i ) , + .qtag_dt4_i ( qtag_dt4_i ) , + .qtag_rdy_o ( qtag_rdy_o ) , + .qtag_dt1_o ( qtag_dt1_o ) , + .qtag_dt2_o ( qtag_dt2_o ) , + .qtag_vld_o ( qtag_vld_o ) , + .qtag_flag_o ( qtag_flag_o ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .adc0_s_axis_tvalid_i ( adc0_s_axis_tvalid_i ) , + .adc0_s_axis_tdata_i ( adc0_s_axis_tdata_i ) , + .adc0_s_axis_tready_o ( adc0_s_axis_tready_o ) , + .adc1_s_axis_tvalid_i ( adc1_s_axis_tvalid_i ) , + .adc1_s_axis_tdata_i ( adc1_s_axis_tdata_i ) , + .adc1_s_axis_tready_o ( adc1_s_axis_tready_o ) , + .adc2_s_axis_tvalid_i ( adc2_s_axis_tvalid_i ) , + .adc2_s_axis_tdata_i ( adc2_s_axis_tdata_i ) , + .adc2_s_axis_tready_o ( adc2_s_axis_tready_o ) , + .adc3_s_axis_tvalid_i ( adc3_s_axis_tvalid_i ) , + .adc3_s_axis_tdata_i ( adc3_s_axis_tdata_i ) , + .adc3_s_axis_tready_o ( adc3_s_axis_tready_o ) , + .dma_m_axis_tready_i ( dma_m_axis_tready_i ) , + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ) , + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ) , + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ) , + .qtt_do ( qtt_do ) +); + +integer FILTER, SLOPE, INTER, SMP_NUM, rand_mult, tmp; +reg p_start; + + +initial begin + rand_mult = 0; + START_SIMULATION(); + arm_i = 1'b1; + #10000; + arm_i = 1'b0; + CMD_DISARM(); + CMD_POP_DT(); + WRITE_AXI( AXI_DT1 , 3950); + CMD_SET_THR(); + WRITE_AXI( AXI_DT1 , 50); + CMD_SET_DEAD_TIME(); + + CMD_RST(); + FILTER = 1; + SLOPE = 0; + INTER = 4; + SMP_NUM = 6; + WRITE_AXI( QTT_CFG , 1* FILTER+ 2* SLOPE + 4*INTER + 32* SMP_NUM); // NO FILTER + + CMD_ARM(); + AMP = 24; + SIM_SINE(); + SIM_SINE(); + CMD_DISARM(); + WRITE_AXI( DMA_CFG , 16*3); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + WRITE_AXI( DMA_CFG , 16*2); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + WRITE_AXI( DMA_CFG , 16*1); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + + + //CMD_DMA_RD(); + + CMD_SMP_RD (); + #10000; + + for (INTER=0; INTER<=4; INTER=INTER+1) begin + CMD_DISARM(); + WRITE_AXI( QTT_CFG , 1* FILTER+ 2* SLOPE + 4*INTER + 32* SMP_NUM ); // NO FILTER INVERT INPUT + CMD_ARM(); + for (AMP=2; AMP<=32; AMP=AMP*2) begin + SIM_RANDOM(); + SIM_PULSES(); + end + CMD_SMP_RD (); + #10000; + end + SIM_RANDOM(); + CMD_DISARM(); + WRITE_AXI( DMA_CFG , 0+16*1); + WRITE_AXI( QTT_CTRL , 32); + #10000; + WRITE_AXI( DMA_CFG , 0+16*2); + WRITE_AXI( QTT_CTRL , 32); + #10000; + WRITE_AXI( DMA_CFG , 0+16*3); + WRITE_AXI( QTT_CTRL , 32); + #10000; + +//Micro POP + @ (posedge c_clk); #0.1; + qtag_en_i = 1; + qtag_op_i = 2; + @ (posedge c_clk); #0.1; + qtag_en_i = 0; + qtag_op_i = 2; + + @ (posedge c_clk); #0.1; + CMD_POP_DT(); + CMD_POP_DT(); + +end +reg adc0_s_axis_tvalid_i, adc1_s_axis_tvalid_i, adc2_s_axis_tvalid_i, adc3_s_axis_tvalid_i; +reg dma_m_axis_tready_i; + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qtag.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + dma_m_axis_tready_i = 1'b1; + adc0_s_axis_tvalid_i = 1'b1; + adc1_s_axis_tvalid_i = 1'b1; + adc2_s_axis_tvalid_i = 1'b1; + adc3_s_axis_tvalid_i = 1'b1; + + arm_i = 1'b0; + qtag_en_i = 0; + qtag_op_i = 0; + qtag_dt1_i = 0; + qtag_dt2_i = 0; + qtag_dt3_i = 0; + qtag_dt4_i = 0; + p_start = 0; + adc_dt = 0; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + @ (posedge adc_clk); #0.1; + p_start = 1; + @ (posedge adc_clk); #0.1; + p_start = 0; + + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task CMD_DISARM (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 0); +endtask +task CMD_ARM (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 1); +endtask +task CMD_POP_DT (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 2); +endtask +task CMD_SET_THR (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 4); +endtask +task CMD_SET_DEAD_TIME (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 5); +endtask +task CMD_RST (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 7); +endtask + +task CMD_DMA_RD (); + WRITE_AXI( DMA_CFG , 16*5); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); +endtask + +task CMD_SMP_RD (); + WRITE_AXI( DMA_CFG , 5+16*SMP_NUM*`SMP_CK*4); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + +endtask + + +integer AMP; +integer i; + +task SIM_SINE(); begin +//50t per sinewave + for (t=0; t<84000; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t) + i ) / (`SMP_CK*100.0) * (44.0 / 7.0); + y[i] = $sin(x[i])*1000*AMP ; + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + adc_dt = 0; +end +endtask + +task SIM_PULSES(); begin + for (t=0; t<5; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t)+i ) * (22.0/7.0) / 10/8 ; + y[i] = $sin(x[i])*1000*AMP+($random %10)*rand_mult; + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + for (t=0; t<25; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t)+i ) * (22.0/7.0) / 50/8 ; + y[i] = $cos(x[i])*1000*AMP+($random %10); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + for (t=0; t<20; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + y[i] = ($random %100); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + adc_dt = 0; +end +endtask + + +task SIM_RANDOM(); begin + for (t=0; t<50; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + y[i] = ($random %100); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end +end +endtask + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg new file mode 100644 index 000000000..810203bb4 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + time_trig_st[31:0] + time_trig_st[31:0] + UNSIGNEDDECRADIX + #FF00FF + true + + + time_cnt[28:0] + time_cnt[28:0] + + + CMD + label + + adc_clk + adc_clk + + + arm_i + arm_i + + + ext_arm_t01 + ext_arm_t01 + + + ext_arm_t10 + ext_arm_t10 + + + qtt_arm + qtt_arm + + + cmd_req + cmd_req + + + p_en_i + p_en_i + + + p_op_i[4:0] + p_op_i[4:0] + + + p_dt_i[31:0] + p_dt_i[31:0] + UNSIGNEDDECRADIX + + + cmd_dt[31:0] + cmd_dt[31:0] + UNSIGNEDDECRADIX + + + cmd_disarm + cmd_disarm + + + cmd_arm + cmd_arm + + + cmd_pop + cmd_pop + + + cmd_set_th + cmd_set_th + + + cmd_set_inh + cmd_set_inh + + + cmd_reset + cmd_reset + + + + qtt_cmp_inh[7:0] + qtt_cmp_inh[7:0] + #FFFF00 + true + UNSIGNEDDECRADIX + + + cfg_filter_i + cfg_filter_i + + + cfg_slope_i + cfg_slope_i + + + cfg_inter_i[2:0] + cfg_inter_i[2:0] + + + cfg_smp_wr_qty_i[4:0] + cfg_smp_wr_qty_i[4:0] + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + ftr_smp[7:0][16:0] + ftr_smp[7:0][16:0] + SIGNEDDECRADIX + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + trig_cal_st[31:0] + trig_cal_st[31:0] + #FF00FF + true + + + [0][15:0] + [0][15:0] + STYLE_ANALOG + 100 + SIGNEDDECRADIX + ANALOG_YRANGETYPE_FIXED + -32000.000000 + 32000.000000 + ANALOG_INTERPOLATION_LINEAR + ANALOG_OFFSCALE_HIDE + 0.000000 + + + adc_rst_ni + adc_rst_ni + + + tag_gen_en + tag_gen_en + + + trig_event + trig_event + + + trig_o + trig_o + #0000FF + true + + + cmp_o + cmp_o + #0000FF + true + + + \ARM.trig_cnt [31:0] + \ARM.trig_cnt [31:0] + UNSIGNEDDECRADIX + + + mem[0:31][31:0] + mem[0:31][31:0] + + + [0][31:0] + [0][31:0] + UNSIGNEDDECRADIX + + + [1][31:0] + [1][31:0] + UNSIGNEDDECRADIX + + + [2][31:0] + [2][31:0] + UNSIGNEDDECRADIX + + + [3][31:0] + [3][31:0] + UNSIGNEDDECRADIX + + + [4][31:0] + [4][31:0] + UNSIGNEDDECRADIX + + + [5][31:0] + [5][31:0] + UNSIGNEDDECRADIX + + + [6][31:0] + [6][31:0] + UNSIGNEDDECRADIX + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + [0][31:0] + [0][31:0] + + + [1][31:0] + [1][31:0] + + + [2][31:0] + [2][31:0] + + + [3][31:0] + [3][31:0] + + + [4][31:0] + [4][31:0] + + + [5][31:0] + [5][31:0] + + + [6][31:0] + [6][31:0] + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + + dma_len_i[19:0] + dma_len_i[19:0] + UNSIGNEDDECRADIX + + + dma_req_i + dma_req_i + + + pop_req_o + pop_req_o + + + pop_ack_i + pop_ack_i + + + dma_rd_st[31:0] + dma_rd_st[31:0] + #FF00FF + true + + + len_cnt[19:0] + len_cnt[19:0] + UNSIGNEDDECRADIX + + + len_cnt_p1[19:0] + len_cnt_p1[19:0] + UNSIGNEDDECRADIX + + + len_cnt_rst + len_cnt_rst + + + len_cnt_last + len_cnt_last + + + dma_m_axis_tvalid_o + dma_m_axis_tvalid_o + #0000FF + true + + + dma_m_axis_tdata_o[31:0] + dma_m_axis_tdata_o[31:0] + #0000FF + true + UNSIGNEDDECRADIX + + + dma_m_axis_tlast_o + dma_m_axis_tlast_o + #0000FF + true + + + dma_qty_o[0:3][18:0] + dma_qty_o[0:3][18:0] + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv new file mode 100644 index 000000000..8aa81db4c --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv @@ -0,0 +1,547 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_C_CLK 2 // 1.66 // Half Clock Period for Simulation +`define T_ADC_CLK 1 // 1.66 // Half Clock Period for Simulation +`define T_PS_CLK 10 // Half Clock Period for Simulation + +`define DMA_RD 1 +`define PROC_RD 1 +`define CMP_SLOPE 1 +`define CMP_INTER 4 +`define SMP_DW 16 +`define SMP_CK 8 +`define TAG_FIFO_AW 10 +`define SMP_STORE 0 +`define SMP_FIFO_AW 10 +`define DEBUG 2 + + +module tb_qtt_cmp(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, adc_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +integer t; +real x0, x1, x2, x3,x4, x5, x6, x7 ; +reg [`SMP_DW-1:0] y0, y1, y2, y3,y4, y5, y6, y7 ; +reg [`SMP_DW*`SMP_CK-1:0] adc_dt, adc_s_axis_tdata_i ; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + adc_clk = 1'b0; + forever # (`T_ADC_CLK) adc_clk = ~adc_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end + +reg pulse_f; +reg dma_m_axis_tready_i; + + +always @ (posedge ps_clk, negedge rst_ni) begin + if ( !rst_ni ) + dma_m_axis_tready_i = 1'b1; + else + if ( dma_m_axis_tvalid_o) begin + #0.5; + dma_m_axis_tready_i = 0; + #100; + end else begin + #0.5; + dma_m_axis_tready_i = 1'b1; + end +end + +always_ff @ (posedge adc_clk, negedge rst_ni) begin + if ( !rst_ni ) pulse_f <= 1'b0; + else + if ( pulse_f2 | rdy_a) pulse_f <= 1'b1; + if ( pulse_f ) pulse_f <= 1'b0; +end + + +reg qtag_en_i ; +reg [4 :0] qtag_op_i ; +reg [31:0] qtag_dt1_i, qtag_dt2_i, qtag_dt3_i, qtag_dt4_i ; + +wire qtag_rdy_o, qtag_vld_o, qtag_flag_o ; +wire [31:0] qtag_dt1_o, qtag_dt2_o; + +// Register ADDRESS +parameter QTT_CTRL = 0 * 4 ; +parameter QTT_CFG = 1 * 4 ; +parameter QTT_ADDR = 2 * 4 ; +parameter QTT_LEN = 3 * 4 ; +parameter AXI_DT1 = 4 * 4 ; +parameter AXI_DT2 = 5 * 4 ; +parameter AXI_DT3 = 6 * 4 ; +parameter AXI_DT4 = 7 * 4 ; +parameter QTT_DT1 = 9 * 4 ; +parameter QTT_DT2 = 10* 4 ; +parameter QTT_DT3 = 11* 4 ; +parameter QTT_DT4 = 12* 4 ; +parameter QTT_STATUS = 14* 4 ; +parameter QTT_DEBUG = 15* 4 ; + + + +pulse_cdc pulse_f2s ( + .clk_a_i ( adc_clk ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( pulse_f ) , + .rdy_a_o ( rdy_a ) , + .clk_b_i ( ps_clk ) , + .rst_b_ni ( rst_ni ) , + .pulse_b_o ( pulse_slow ) ); + +pulse_cdc pulse_s2f ( + .clk_a_i ( ps_clk ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( pulse_slow ) , + .rdy_a_o ( ) , + .clk_b_i ( adc_clk ) , + .rst_b_ni ( rst_ni ) , + .pulse_b_o ( pulse_f2 ) ); +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk ( ps_clk ), + .aresetn ( rst_ni ), + .m_axi_araddr ( s_axi_araddr ), + .m_axi_arprot ( s_axi_arprot ), + .m_axi_arready ( s_axi_arready ), + .m_axi_arvalid ( s_axi_arvalid ), + .m_axi_awaddr ( s_axi_awaddr ), + .m_axi_awprot ( s_axi_awprot ), + .m_axi_awready ( s_axi_awready ), + .m_axi_awvalid ( s_axi_awvalid ), + .m_axi_bready ( s_axi_bready ), + .m_axi_bresp ( s_axi_bresp ), + .m_axi_bvalid ( s_axi_bvalid ), + .m_axi_rdata ( s_axi_rdata ), + .m_axi_rready ( s_axi_rready ), + .m_axi_rresp ( s_axi_rresp ), + .m_axi_rvalid ( s_axi_rvalid ), + .m_axi_wdata ( s_axi_wdata ), + .m_axi_wready ( s_axi_wready ), + .m_axi_wstrb ( s_axi_wstrb ), + .m_axi_wvalid ( s_axi_wvalid )); + + +axi_qick_time_tagger # ( +// .DMA_RD ( `DMA_RD ) , +// .PROC_RD ( `PROC_RD ) , + .CMP_SLOPE ( `CMP_SLOPE ) , + .CMP_INTER ( `CMP_INTER ) , + .TAG_FIFO_AW ( `TAG_FIFO_AW ) , + .SMP_DW ( `SMP_DW ) , + .SMP_CK ( `SMP_CK ) , + .SMP_STORE ( `SMP_STORE ) , + .SMP_FIFO_AW ( `SMP_FIFO_AW ) , + .DEBUG ( `DEBUG ) +) axi_qick_time_tagger ( + .c_clk ( c_clk ), + .c_aresetn ( rst_ni ), + .adc_clk ( adc_clk ), + .adc_aresetn ( rst_ni ), + .ps_clk ( ps_clk ), + .ps_aresetn ( rst_ni ), + .qtag_en_i ( qtag_en_i ), + .qtag_op_i ( qtag_op_i ), + .qtag_dt1_i ( qtag_dt1_i ), + .qtag_dt2_i ( qtag_dt2_i ), + .qtag_dt3_i ( qtag_dt3_i ), + .qtag_dt4_i ( qtag_dt4_i ), + .qtag_rdy_o ( qtag_rdy_o ), + .qtag_dt1_o ( qtag_dt1_o ), + .qtag_dt2_o ( qtag_dt2_o ), + .qtag_vld_o ( qtag_vld_o ), + .qtag_flag_o ( qtag_flag_o ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .adc0_s_axis_tvalid_i ( adc_s_axis_tvalid_i ), + .adc0_s_axis_tdata_i ( adc_s_axis_tdata_i ), + .adc0_s_axis_tready_o ( adc_s_axis_tready_o ), + .dma_m_axis_tready_i ( dma_m_axis_tready_i ), + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ), + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ), + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ), + .qtt_do ( )); + +reg [15:0] threshold; +wire[31:0] time_ck_s0 , time_ck_s1 , time_ck_s2 , time_ck_s3 ; +wire[2:0] time_adc_s0, time_adc_s1, time_adc_s2, time_adc_s3; +wire[3:0] time_int_s0, time_int_s1, time_int_s2, time_int_s3; + + +thr_cmp CMP_0 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 0 ) , + .cfg_slope_i ( 0 ) , + .cfg_inter_i ( 1 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s0 ) , + .trig_time_adc_o ( time_adc_s0 ) , + .trig_time_int_o ( time_int_s0 ) , + .trig_vld_o ( time_vld_s0 ) ); +thr_cmp CMP_1 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 0 ) , + .cfg_slope_i ( 1 ) , + .cfg_inter_i ( 0 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s1 ) , + .trig_time_adc_o ( time_adc_s1 ) , + .trig_time_int_o ( time_int_s1 ) , + .trig_vld_o ( time_vld_s1 ) ); +thr_cmp CMP_2 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 1 ) , + .cfg_slope_i ( 0 ) , + .cfg_inter_i ( 1 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s2 ) , + .trig_time_adc_o ( time_adc_s2 ) , + .trig_time_int_o ( time_int_s2 ) , + .trig_vld_o ( time_vld_s2 ) ); +thr_cmp CMP_3 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 1 ) , + .cfg_slope_i ( 1 ) , + .cfg_inter_i ( 0 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s3 ) , + .trig_time_adc_o ( time_adc_s3 ) , + .trig_time_int_o ( time_int_s3 ) , + .trig_vld_o ( time_vld_s3 ) ); + +assign adc_s_axis_tvalid_i = 1'b1; +assign adc_s_axis_tdata_i = adc_dt; + +integer INTER, rand_mult, tmp; +reg p_start; + +initial begin + rand_mult = 0; + START_SIMULATION(); + // TEST_AXI () ; + // TEST_CMD (); + WRITE_AXI( QTT_CFG , 5); // SET DEAD TIME + WRITE_AXI( AXI_DT1 , 30); + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 4); // SET THR + WRITE_AXI( AXI_DT1 , 3630); + WRITE_AXI( QTT_CTRL , 1); + + for (tmp=0; tmp<=100; tmp=tmp+1) begin + for (INTER=0; INTER<=7; INTER=INTER+1) begin + //for (AMP=2; AMP<=32; AMP=AMP*2) begin + for (AMP=2; AMP<=32; AMP=AMP+1) begin + WRITE_AXI( QTT_CFG , INTER*32+1); + WRITE_AXI( QTT_CTRL , 1 ); + SIM_RANDOM(); + SIM_PULSES(); + end + //WRITE_AXI( QTT_CFG , 0); // DISARM + //WRITE_AXI( QTT_CTRL , 1); + end + SIM_RANDOM(); + SIM_RANDOM(); + SIM_RANDOM(); + end + WRITE_AXI( QTT_CFG , 0); // DISARM + WRITE_AXI( QTT_CTRL , 1); + +//Micro POP + qtag_en_i = 1; + qtag_op_i = 2; + @ (posedge c_clk); #0.1; + qtag_en_i = 0; + qtag_op_i = 2; + + @ (posedge c_clk); #0.1; + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + #5000; + @ (posedge c_clk); #0.1; + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 1); // ARM + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 7); // RESET + WRITE_AXI( QTT_CTRL , 1); + +end + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qtt_cmp.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + qtag_en_i = 0; + qtag_op_i = 0; + qtag_dt1_i = 0; + qtag_dt2_i = 0; + qtag_dt3_i = 0; + qtag_dt4_i = 0; + p_start = 0; + adc_dt = 0; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + @ (posedge adc_clk); #0.1; + p_start = 1; + @ (posedge adc_clk); #0.1; + p_start = 0; + + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QTT_CTRL , 1); + WRITE_AXI( QTT_CFG , 2); + WRITE_AXI( QTT_ADDR , 3); + WRITE_AXI( QTT_LEN , 4); + WRITE_AXI( AXI_DT1 , 5); + WRITE_AXI( AXI_DT2 , 6); + WRITE_AXI( AXI_DT3 , 7); + WRITE_AXI( AXI_DT4 , 8); +end +endtask + +task TEST_CMD (); begin + $display("-----Writting AXI "); + WRITE_AXI( QTT_CTRL , 1); // RST + + WRITE_AXI( QTT_CFG , 1); // ARM + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 2); // DISARM + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 8); // SET_THR + WRITE_AXI( AXI_DT1 , 456); + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 9); // SET_DEAD_TIME + WRITE_AXI( AXI_DT1 , 123); + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_ADDR , 3); + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + WRITE_AXI( QTT_CTRL , 8); // SMP READ +end +endtask + +task SIM_QTT(); begin + $display("SIM TAGGER"); + for (t=0; t<=360; t=t+1) begin + @ (posedge adc_clk); #0.1; + x0 = ( (8*t)+0 ) * (22.0/7.0) / 180/4; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 180/4; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 180/4; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 180/4; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 180/4; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 180/4; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 180/4; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 180/4; + y0 = 255*$sin(0.5*x0) + 255*$sin(3*x0) + 511*$sin(2*x0); + y1 = 255*$sin(0.5*x1) + 255*$sin(3*x1) + 511*$sin(2*x1); + y2 = 255*$sin(0.5*x2) + 255*$sin(3*x2) + 511*$sin(2*x2); + y3 = 255*$sin(0.5*x3) + 255*$sin(3*x3) + 511*$sin(2*x3); + y4 = 255*$sin(0.5*x4) + 255*$sin(3*x4) + 511*$sin(2*x4); + y5 = 255*$sin(0.5*x5) + 255*$sin(3*x5) + 511*$sin(2*x5); + y6 = 255*$sin(0.5*x6) + 255*$sin(3*x6) + 511*$sin(2*x6); + y7 = 255*$sin(0.5*x7) + 255*$sin(3*x7) + 511*$sin(2*x7); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end +end +endtask + +integer AMP; + + +task SIM_PULSES(); begin + for (t=0; t<5; t=t+1) begin + @ (posedge adc_clk); #0.1; + //x = (t)* (22.0/7.0)/20; + //y = $sin(x) ; + //yd = y *1000*AMP+($random %100); + x0 = ( (8*t)+0 ) * (22.0/7.0) / 10/8; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 10/8; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 10/8; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 10/8; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 10/8; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 10/8; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 10/8; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 10/8; + y0 = $sin(x0)*1000*AMP+($random %10)*rand_mult; + y1 = $sin(x1)*1000*AMP+($random %10)*rand_mult; + y2 = $sin(x2)*1000*AMP+($random %10)*rand_mult; + y3 = $sin(x3)*1000*AMP+($random %10)*rand_mult; + y4 = $sin(x4)*1000*AMP+($random %10)*rand_mult; + y5 = $sin(x5)*1000*AMP+($random %10)*rand_mult; + y6 = $sin(x6)*1000*AMP+($random %10)*rand_mult; + y7 = $sin(x7)*1000*AMP+($random %10)*rand_mult; + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + + end + for (t=0; t<25; t=t+1) begin + @ (posedge adc_clk); #0.1; + //x = (t)* (22.0/7.0)/100; + //y = $cos(x); + //yd = y *1000*AMP+($random %100); + x0 = ( (8*t)+0 ) * (22.0/7.0) / 50/8; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 50/8; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 50/8; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 50/8; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 50/8; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 50/8; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 50/8; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 50/8; + y0 = $cos(x0)*1000*AMP+($random %10); + y1 = $cos(x1)*1000*AMP+($random %10); + y2 = $cos(x2)*1000*AMP+($random %10); + y3 = $cos(x3)*1000*AMP+($random %10); + y4 = $cos(x4)*1000*AMP+($random %10); + y5 = $cos(x5)*1000*AMP+($random %10); + y6 = $cos(x6)*1000*AMP+($random %10); + y7 = $cos(x7)*1000*AMP+($random %10); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + for (t=0; t<20; t=t+1) begin + @ (posedge adc_clk); #0.1; + y0 = ($random %100); + y1 = ($random %100); + y2 = ($random %100); + y3 = ($random %100); + y4 = ($random %100); + y5 = ($random %100); + y6 = ($random %100); + y7 = ($random %100); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + adc_dt = 0; +end +endtask + + +task SIM_RANDOM(); begin + for (t=0; t<50; t=t+1) begin + @ (posedge adc_clk); #0.1; + y0 = ($random %100); + y1 = ($random %100); + y2 = ($random %100); + y3 = ($random %100); + y4 = ($random %100); + y5 = ($random %100); + y6 = ($random %100); + y7 = ($random %100); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end +end +endtask + +endmodule + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp_behav.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp_behav.wcfg new file mode 100644 index 000000000..5c75c0ddc --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp_behav.wcfg @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + time_trig_st[31:0] + time_trig_st[31:0] + UNSIGNEDDECRADIX + #FF00FF + true + + + time_cnt[28:0] + time_cnt[28:0] + + + CMD + label + + adc_clk + adc_clk + + + arm_i + arm_i + + + ext_arm_t01 + ext_arm_t01 + + + ext_arm_t10 + ext_arm_t10 + + + qtt_arm + qtt_arm + + + cmd_req + cmd_req + + + p_en_i + p_en_i + + + p_op_i[4:0] + p_op_i[4:0] + + + p_dt_i[31:0] + p_dt_i[31:0] + UNSIGNEDDECRADIX + + + cmd_dt[31:0] + cmd_dt[31:0] + UNSIGNEDDECRADIX + + + cmd_disarm + cmd_disarm + + + cmd_arm + cmd_arm + + + cmd_pop + cmd_pop + + + cmd_set_th + cmd_set_th + + + cmd_set_inh + cmd_set_inh + + + cmd_reset + cmd_reset + + + + qtt_cmp_inh[7:0] + qtt_cmp_inh[7:0] + #FFFF00 + true + UNSIGNEDDECRADIX + + + cfg_filter_i + cfg_filter_i + + + cfg_slope_i + cfg_slope_i + + + cfg_inter_i[2:0] + cfg_inter_i[2:0] + + + cfg_smp_wr_qty_i[4:0] + cfg_smp_wr_qty_i[4:0] + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + ftr_smp[7:0][16:0] + ftr_smp[7:0][16:0] + SIGNEDDECRADIX + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + trig_cal_st[31:0] + trig_cal_st[31:0] + #FF00FF + true + + + [0][15:0] + [0][15:0] + STYLE_ANALOG + 100 + SIGNEDDECRADIX + ANALOG_YRANGETYPE_FIXED + -32000.000000 + 32000.000000 + ANALOG_INTERPOLATION_LINEAR + ANALOG_OFFSCALE_HIDE + 0.000000 + + + adc_rst_ni + adc_rst_ni + + + tag_gen_en + tag_gen_en + + + trig_event + trig_event + + + trig_o + trig_o + #0000FF + true + + + cmp_o + cmp_o + #0000FF + true + + + \ARM.trig_cnt [31:0] + \ARM.trig_cnt [31:0] + UNSIGNEDDECRADIX + + + mem[0:31][31:0] + mem[0:31][31:0] + + + [0][31:0] + [0][31:0] + UNSIGNEDDECRADIX + + + [1][31:0] + [1][31:0] + UNSIGNEDDECRADIX + + + [2][31:0] + [2][31:0] + UNSIGNEDDECRADIX + + + [3][31:0] + [3][31:0] + UNSIGNEDDECRADIX + + + [4][31:0] + [4][31:0] + UNSIGNEDDECRADIX + + + [5][31:0] + [5][31:0] + UNSIGNEDDECRADIX + + + [6][31:0] + [6][31:0] + UNSIGNEDDECRADIX + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + [0][31:0] + [0][31:0] + + + [1][31:0] + [1][31:0] + + + [2][31:0] + [2][31:0] + + + [3][31:0] + [3][31:0] + + + [4][31:0] + [4][31:0] + + + [5][31:0] + [5][31:0] + + + [6][31:0] + [6][31:0] + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + + dma_len_i[19:0] + dma_len_i[19:0] + UNSIGNEDDECRADIX + + + dma_req_i + dma_req_i + + + pop_req_o + pop_req_o + + + pop_ack_i + pop_ack_i + + + dma_rd_st[31:0] + dma_rd_st[31:0] + #FF00FF + true + + + len_cnt[19:0] + len_cnt[19:0] + UNSIGNEDDECRADIX + + + len_cnt_p1[19:0] + len_cnt_p1[19:0] + UNSIGNEDDECRADIX + + + len_cnt_rst + len_cnt_rst + + + len_cnt_last + len_cnt_last + + + dma_m_axis_tvalid_o + dma_m_axis_tvalid_o + #0000FF + true + + + dma_m_axis_tdata_o[31:0] + dma_m_axis_tdata_o[31:0] + #0000FF + true + UNSIGNEDDECRADIX + + + dma_m_axis_tlast_o + dma_m_axis_tlast_o + #0000FF + true + + + dma_qty_o[0:3][18:0] + dma_qty_o[0:3][18:0] + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv new file mode 100644 index 000000000..17d688882 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv @@ -0,0 +1,185 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 1 +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define WR_CLK 3 // Half Clock Period for Simulation +`define RD_CLK 11 // Half Clock Period for Simulation + +module tb_smp_fifo(); + +parameter DW = 16 ; +parameter AW = 8 ; +parameter SMP_CK = 8 ; + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i; +reg rst_ni, ready; + +// CLK +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`WR_CLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`RD_CLK) rd_clk_i = ~rd_clk_i; +end + +// READY +////////////////////////////////////////////////////////////////////////// +initial begin + ready = 1'b0; + forever begin + //#(1) + #(15*`RD_CLK*2) + //#(16) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + +reg [DW-1:0] data_i; +wire [AW-1:0] dma_qty ; +reg push_i, dma_pop_i; +reg flush_i; + +reg [SMP_CK*DW-1:0] adc_dt ; + +smp_mem # ( + .SMP_DW ( DW ) , // Samples WIDTH + .SMP_CK ( SMP_CK ) , // Samples per Clock + .SMP_FIFO_AW ( AW ) // Size of SAMPLES FIFO Memory +) SMP_MEM ( +// Core and AXI CLK & RST + .dma_clk_i ( rd_clk_i ) , + .dma_rst_ni ( rst_ni ) , + .adc_clk_i ( wr_clk_i ) , + .adc_rst_ni ( rst_ni ) , + .qtt_rst_req_i ( flush_i ) , + .qtt_rst_ack_o ( flush_o ) , + .cfg_smp_wr_qty_i ( 4'd5 ) , + .tag_wr_i ( push_i ) , + .adc_dt_i ( adc_dt ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_dt_o ( dma_dt_o ) , + .dma_qty_o ( dma_qty ) , + .smp_empty_o ( ) , + .smp_full_o ( ) , + .smp_debug_o ( ) ); + +wire [DW-1:0] dma_dt_o; +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .pop_req_o ( dma_pop_i ) , + .pop_ack_i ( dma_pop_o ) , + .fifo_dt_i ( dma_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + + +initial begin + START_SIMULATION(); + FIFO_PUSH(); // Write 20 + #5000; + dma_len_i = 22; + FIFO_DMA(); + #50; + dma_len_i = 5; + FIFO_DMA(); + #50; +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 0; + adc_dt = 0 ; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t, x, y; +integer x0, x1, x2, x3,x4, x5, x6, x7 ; +reg [DW-1:0] y0, y1, y2, y3,y4, y5, y6, y7 ; + + +task FIFO_PUSH(); begin + $display("PUSH DATA"); + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + @ (posedge wr_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge wr_clk_i); #0.1; + x0 = ( (8*t)+0 ) ; + x1 = ( (8*t)+1 ) ; + x2 = ( (8*t)+2 ) ; + x3 = ( (8*t)+3 ) ; + x4 = ( (8*t)+4 ) ; + x5 = ( (8*t)+5 ) ; + x6 = ( (8*t)+6 ) ; + x7 = ( (8*t)+7 ) ; + y0 = x0 ; + y1 = x1 ; + y2 = x2 ; + y3 = x3 ; + y4 = x4 ; + y5 = x5 ; + y6 = x6 ; + y7 = x7 ; + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + push_i = 1'b0; +end + +endtask + + + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg new file mode 100644 index 000000000..d78e27cc3 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg @@ -0,0 +1,149 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_clk_i + adc_clk_i + + + dma_pop_i + dma_pop_i + + + smp_wr_st[31:0] + smp_wr_st[31:0] + + + smp_wr_cnt[7:0] + smp_wr_cnt[7:0] + + + tag_wr_i + tag_wr_i + + + adc_dt_i[127:0] + adc_dt_i[127:0] + + + smp_wr_dt[127:0] + smp_wr_dt[127:0] + + + data_i[127:0] + data_i[127:0] + + + push_i + push_i + + + mem[0:255][15:0] + mem[0:255][15:0] + UNSIGNEDDECRADIX + + + smp_empty_o + smp_empty_o + + + smp_full_o + smp_full_o + + + wr_push + wr_push + + + we_a_i + we_a_i + + + dt_a_i[15:0] + dt_a_i[15:0] + + + dma_clk_i + dma_clk_i + + + dma_pop_o + dma_pop_o + + + dma_dt_o[31:0] + dma_dt_o[31:0] + UNSIGNEDDECRADIX + + + dma_qty_o[7:0] + dma_qty_o[7:0] + UNSIGNEDDECRADIX + + + m_axis_tdata_o[15:0] + m_axis_tdata_o[15:0] + UNSIGNEDDECRADIX + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + addr_a_i[7:0] + addr_a_i[7:0] + #FFFF00 + true + + + we_a_i + we_a_i + #FFFF00 + true + + + dt_a_i[15:0] + dt_a_i[15:0] + #FFFF00 + true + + + addr_b_i[7:0] + addr_b_i[7:0] + UNSIGNEDDECRADIX + + + dt_b_o[15:0] + dt_b_o[15:0] + UNSIGNEDDECRADIX + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv new file mode 100644 index 000000000..bb688118d --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv @@ -0,0 +1,239 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 1 +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define WR_CLK 3 // Half Clock Period for Simulation +`define RD_CLK 11 // Half Clock Period for Simulation +`define CORE_CLK 5 // Half Clock Period for Simulation + +module tb_tag_fifo(); + + +parameter MEM_QTY = 4 ; +parameter DW = 32 ; +parameter AW = 16 ; +//parameter SMP_CK = 8 ; + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i, core_clk_i; +reg rst_ni, ready; + +// CLK +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`WR_CLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`RD_CLK) rd_clk_i = ~rd_clk_i; +end +initial begin + core_clk_i = 1'b0; + forever # (`CORE_CLK) core_clk_i = ~core_clk_i; +end + +// READY +////////////////////////////////////////////////////////////////////////// +initial begin + ready = 1'b0; + forever begin + //#(1) + #(15*`RD_CLK*2) + //#(16) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + +reg [DW-1:0] data_i; +reg push_i, dma_pop_i; +reg flush_i; + +reg [MEM_QTY-1:0] tag_wr_i; +reg [31:0] tag_dt_i [MEM_QTY] ; +reg [AW-1:0] dma_qty_o[MEM_QTY] ; +wire [DW-1:0] dma_dt_o; + +reg [32-1:0] tag_debug_o ; +reg [AW-1:0] proc_qty_o ; +reg qtt_pop_req; +reg [DW-1:0] m_axis_tdata_o ; + + +tag_mem # ( + .MEM_QTY ( MEM_QTY ), // Amount of Memories +// .DMA_RD ( 1 ), // TAG FIFO Read from DMA +// .PROC_RD ( 0 ), // TAG FIFO Read from tProcessor + .TAG_FIFO_AW ( AW ), // Size of TAG FIFO Memory + .DEBUG ( 0 ) +) TAG_MEM ( + .dma_clk_i ( rd_clk_i ), + .dma_rst_ni ( rst_ni ), + .c_clk_i ( core_clk_i ), + .c_rst_ni ( rst_ni ), + .adc_clk_i ( wr_clk_i ), + .adc_rst_ni ( rst_ni ), + .qtt_pop_req_i ( qtt_pop_req ), + .qtt_rst_req_i ( flush_i ), + .qtt_rst_ack_o ( qtt_rst_ack_o ), + .tag_wr_i ( tag_wr_i ), + .tag_dt_i ( tag_dt_i ), + .dma_qty_o ( dma_qty_o ), + .proc_qty_o ( proc_qty_o ), + .empty_o ( tag_empty_o ), + .full_o ( tag_full_o ), + .dma_sel_i ( dma_sel_i ), + .dma_pop_i ( dma_pop_i ), + .dma_pop_o ( dma_pop_o ), + .dma_dt_o ( dma_dt_o ), + .debug_do ( tag_debug_o ) +); + +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .pop_req_o ( dma_pop_i ) , + .pop_ack_i ( dma_pop_o ) , + .fifo_dt_i ( dma_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + +reg [3:0] tag_wr_sel; +reg [1:0] dma_sel_i; +initial begin + START_SIMULATION(); + #1000; + tag_wr_sel = 4'b0001; + TAG_WR(); + tag_wr_sel = 4'b0010; + TAG_WR(); + tag_wr_sel = 4'b0100; + TAG_WR(); + tag_wr_sel = 4'b1000; + TAG_WR(); + tag_wr_sel = 4'b1010; + TAG_WR(); + tag_wr_sel = 4'b0101; + TAG_WR(); + tag_wr_sel = 4'b1111; + TAG_WR(); + #1000; + +// @ (posedge wr_clk_i); #0.1; +// flush_i = 1'b1; +// @ (posedge wr_clk_i); #0.1; +// @ (posedge wr_clk_i); #0.1; +// flush_i = 1'b0; +// #1000; + + TAG_POP(); + TAG_POP(); + TAG_POP(); + + #1000; + dma_len_i = 22; + dma_sel_i = 2'b00; + FIFO_DMA(); + #1000; + dma_len_i = 5; + dma_sel_i = 2'b01; + FIFO_DMA(); + #1000; + dma_sel_i = 2'b10; + FIFO_DMA(); + #1000; + dma_sel_i = 2'b11; + FIFO_DMA(); + #1000; +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + dma_sel_i = 2'b00; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 0; + qtt_pop_req = 0; + tag_wr_i = '{default:'0} ; + tag_dt_i = '{default:'0} ; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t, ind; +task TAG_WR(); begin + $display("PUSH DATA"); + @ (posedge wr_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge wr_clk_i); #0.1; + for (ind=0; ind<=MEM_QTY; ind=ind+1) begin + tag_dt_i[ind] = ((ind+1)*t+ind+1); + tag_wr_i[ind] = tag_wr_sel[ind]; + @ (posedge wr_clk_i); #0.1; + tag_wr_i = '{default:'0}; + end + end + push_i = 1'b0; +end + +endtask + +task TAG_POP(); begin + $display("POP TAGS"); + @ (posedge core_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge core_clk_i); #0.1; + qtt_pop_req = 1; + @ (posedge core_clk_i); #0.1; + qtt_pop_req = 0; + #200; + end +end + +endtask + + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg new file mode 100644 index 000000000..1b87106cb --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg @@ -0,0 +1,84 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_clk_i + adc_clk_i + + + tag_dt_i[0:3][31:0] + tag_dt_i[0:3][31:0] + UNSIGNEDDECRADIX + + + + tag_wr_i[0:3] + tag_wr_i[0:3] + UNSIGNEDDECRADIX + + + + dma_clk_i + dma_clk_i + + + dma_sel_i[1:0] + dma_sel_i[1:0] + + + dma_dt_o[31:0] + dma_dt_o[31:0] + + + dma_req_i + dma_req_i + + + dma_ack_o + dma_ack_o + + + m_axis_tdata_o[15:0] + m_axis_tdata_o[15:0] + UNSIGNEDDECRADIX + #0000FF + true + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + dma_qty_o[0:3][7:0] + dma_qty_o[0:3][7:0] + UNSIGNEDDECRADIX + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/thr_cmp.sv b/firmware/ip/qick_time_tagger/src/TB/thr_cmp.sv new file mode 100644 index 000000000..2e3685ccb --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/thr_cmp.sv @@ -0,0 +1,181 @@ +module thr_cmp # ( + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 1 , // Interpolate SAMPLES + parameter SMP_DW = 16 , //Sample Data width + parameter SMP_CK = 8 // Samples per Clock +) ( + input wire clk_i , + input wire rst_ni , + input wire en_i , + input wire cfg_filter_i , + input wire [2:0] cfg_inter_i , + input wire cfg_slope_i , + input wire [28:0] time_ck_i , + input wire [SMP_DW-1:0] th_i , + input wire [SMP_CK*SMP_DW-1:0] dt_i , + output wire [28:0] trig_time_ck_o , + output wire [2:0] trig_time_adc_o , + output wire [6:0] trig_time_int_o , + output wire trig_inter_end_o , + output wire trig_vld_o ); + +reg [15:0] adc_smp [SMP_CK-1:0]; +reg [15:0] adc_prev_smp [SMP_CK-1:0]; +reg [15:0] adc_2prev_smp [SMP_CK-1:0]; +reg [15:0] ftr_smp [SMP_CK-1:0]; +reg [15:0] ftr_prev_smp [SMP_CK-1:0]; +reg [15:0] cmp_smp [SMP_CK-1:0]; +reg [15:0] cmp_prev_smp [SMP_CK-1:0]; +reg [15:0] cmp_rslt [SMP_CK-1:0]; + +wire [SMP_CK-1:0] cmp_s ; +wire [2:0] enc_s, enc_m1; +wire [15:0] triggered_sample; + +reg [SMP_DW-1:0] adc_prev_smp_0, adc_2prev_smp_0; +reg [15:0] adc_smp_r [SMP_CK-1:0] ; +reg [15:0] adc_smp_2r [SMP_CK-1:0]; +reg adc_prev_smp_r, adc_prev_smp_2r; + +reg [28:0] time_ck_r, time_ck_2r; +wire [28:0] time_ck_s; + +wire [ 2:0] time_adc_s; +wire [ 6:0] time_inter_s; + +reg [28:0] trig_time_ck_r; +reg [2:0] trig_time_adc_r; +reg [CMP_INTER-1:0] trig_time_inter_r; + +wire[CMP_INTER-1:0] thr_inter_smp; +wire x_inter_end; + +// TYPE +/////////////////////////////////////////////////////////////////////////////// + +// Store las Sample of current, for prev next. +always_ff @(posedge clk_i) begin + if ( !rst_ni ) begin + adc_prev_smp_0 <= 0; + adc_2prev_smp_0 <= 0; + adc_prev_smp_r <= 0; + adc_smp_r <= '{default:'0}; + adc_prev_smp_2r <= 0; + adc_smp_2r <= '{default:'0}; + time_ck_r <= 0; + time_ck_2r <= 0; + end else begin + adc_prev_smp_0 <= adc_smp[SMP_CK-1]; + adc_2prev_smp_0 <= adc_smp[SMP_CK-2]; + adc_prev_smp_r <= adc_prev_smp_0[SMP_CK-1]; + adc_smp_r <= adc_smp; + adc_prev_smp_2r <= adc_prev_smp_r; + adc_smp_2r <= adc_smp_r; + time_ck_r <= time_ck_i; + time_ck_2r <= time_ck_r; + end +end + +genvar i; +generate + for (i=0; i 0 ) begin: INTER + x_inter #( + .DW ( SMP_DW ) , + .IW ( CMP_INTER ) + ) x_inter ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .start_i ( trigger_cmp ) , + .cfg_inter_i( cfg_inter_i ) , + .thr_i ( th_i ) , + .curr_i ( ftr_smp[enc_s] ) , + .prev_i ( ftr_prev_smp[enc_s] ) , + .end_o ( x_inter_end ) , + .ready_o ( ) , + .x_int_o ( thr_inter_smp ) ); + end else begin + assign x_inter_end = trigger_cmp; + assign thr_inter_smp = 7'b0; + end +endgenerate +localparam zfp = 6-CMP_INTER; +assign trig_inter_end_o = x_inter_end; +assign trig_time_ck_o = trig_time_ck_r; +assign trig_time_adc_o = trig_time_adc_r; +assign trig_time_int_o = {{ zfp {1'b0}}, trig_time_inter_r}; +assign trig_vld_o = trigger_cmp_s; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/_qtt_dma.sv b/firmware/ip/qick_time_tagger/src/_qtt_dma.sv new file mode 100644 index 000000000..3786567f3 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_dma.sv @@ -0,0 +1,184 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module dma_fifo_rd # ( + parameter MEM_AW = 16 , // Memory Address Width + parameter MEM_DW = 8 , // Memory Data Width + parameter DMA_DW = 8 // DMA Data Width +) ( + input wire clk_i , + input wire rst_ni , + input wire dma_req_i , + output wire dma_ack_o , + input wire [MEM_AW-1:0] dma_len_i , + output wire pop_req_o , //fifo_pop_o , + input wire pop_ack_i , //fifo_pop_i , + input wire [MEM_DW-1:0] fifo_dt_i , + input wire m_axis_tready_i , + output wire [DMA_DW-1:0] m_axis_tdata_o , + output wire m_axis_tvalid_o , + output wire m_axis_tlast_o , + output wire [15:0] dma_do , + output wire [25:0] dma_reg_do + ); + +///// Signals +/////////////////////////////////////////////////////////////////////////////// +reg [MEM_AW-1:0] len_cnt ; +wire [MEM_AW-1:0] len_cnt_p1 ; +reg len_cnt_rst, dma_rd_ack ; +reg fifo_rd ; // Reading FIFO for streaming +reg dt_bf ; // Data received when not Ready. Should Buffer +reg dt_vld ; // Data Valid on input. +reg dt_last ; // Last Data of Stream +reg dt_tx ; // Transmitting Data +reg dt_w ; // Data Buffered is is waiting for rdy + +reg [3:0] lp_cnt ; // Last FIFO REQ Pulse +wire [3:0] lp_cnt_p1 ; // Last FIFO REQ Pulse +reg lp_cnt_en ; // Last FIFO REQ Pulse + + +assign len_dma_one = (dma_len_i == 1) ; +assign len_cnt_last = (len_cnt_p1 == dma_len_i) ; +assign last_rd_addr = len_cnt_last & m_axis_tvalid_o ; + +///// DMA STATE +/////////////////////////////////////////////////////////////////////////////// +typedef enum { ST_IDLE, ST_TXING, ST_LAST, ST_END } TYPE_DMA_RD_ST; +(* fsm_encoding = "sequential" *) TYPE_DMA_RD_ST dma_rd_st; +TYPE_DMA_RD_ST dma_rd_st_nxt; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) dma_rd_st <= ST_IDLE; + else dma_rd_st <= dma_rd_st_nxt; +end + +always_comb begin + dma_rd_st_nxt = dma_rd_st; + dma_rd_ack = 1'b1; + len_cnt_rst = 1'b0; + fifo_rd = 1'b0; + dt_bf = 1'b0; + dt_vld = 1'b0; + dt_last = 1'b0; + dt_tx = 1'b0; + lp_cnt_en = 1'b0; + case (dma_rd_st) + ST_IDLE: begin + dma_rd_ack = 1'b0; + len_cnt_rst = 1'b1; + if (dma_req_i) + if (len_dma_one) dma_rd_st_nxt = ST_LAST; + else dma_rd_st_nxt = ST_TXING; + end + ST_TXING : begin + dt_bf = pop_ack_i & !m_axis_tready_i ; + fifo_rd = ~dt_bf; // Read From FIFO if no data is waiting for READY + dt_tx = 1'b1; + dt_vld = pop_ack_i ; + //if (len_cnt_last & len_cnt_en) + if (len_cnt_last & m_axis_tvalid_o) + dma_rd_st_nxt = ST_LAST; + end + ST_LAST : begin + lp_cnt_en = m_axis_tready_i; + fifo_rd = &lp_cnt; //Read from FIFO, every 8 READY (IN CASE TPROC has read ) + dt_bf = pop_ack_i & !m_axis_tready_i ; + dt_vld = pop_ack_i ; + dt_last = 1'b1; + dt_tx = 1'b1; + if ( m_axis_tvalid_o & m_axis_tready_i) dma_rd_st_nxt = ST_END; + end + ST_END : begin + if (!dma_req_i & m_axis_tready_i) dma_rd_st_nxt = ST_IDLE; + end + endcase +end + +// Len Count +assign len_cnt_p1 = len_cnt + 1'b1; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) + len_cnt <= 0; + else begin + if ( len_cnt_rst ) + len_cnt <= 1; + else if ( m_axis_tvalid_o ) + len_cnt <= len_cnt_p1; + end +end + +// Last Pulse Count +assign lp_cnt_p1 = lp_cnt + 1'b1; +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) lp_cnt <= 0; + else if ( lp_cnt_en ) lp_cnt <= lp_cnt_p1; + else lp_cnt <= 0; +end + + +// OUT Buffer +reg [MEM_DW-1:0] dt_r ; +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + dt_r <= 0; + dt_w <= 0; + end else if ( dt_bf ) begin + dt_w <= 1'b1; + dt_r <= fifo_dt_i; + end else if ( dt_w & m_axis_tready_i) begin + dt_w <= 1'b0; + end +end + + +// Assign outputs. +reg [3:0] cnt_fifo_rd, cnt_vld; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + cnt_fifo_rd <= 0; + cnt_vld <= 0; + end else begin + if ( dt_vld ) cnt_fifo_rd <= cnt_fifo_rd + 1'b1; + else if ( m_axis_tvalid_o ) cnt_vld <= cnt_vld + 1'b1; + end +end + +// ILA Debug 16 Bits +assign dma_do[0] = dma_req_i ; +assign dma_do[1] = dma_rd_ack ; +assign dma_do[2] = pop_req_o ; +assign dma_do[3] = pop_ack_i ; +assign dma_do[4] = fifo_rd ; +assign dma_do[5] = dt_tx ; +assign dma_do[6] = dt_w ; +assign dma_do[7] = dt_vld ; +assign dma_do[8] = dt_bf ; +assign dma_do[9] = lp_cnt_en ; +assign dma_do[11:10] = len_cnt[1:0]; +assign dma_do[13:12] = cnt_fifo_rd[1:0]; +assign dma_do[15:14] = cnt_vld[1:0]; + +// Register Debug 24 Bits +assign dma_reg_do[9:0] = dma_do[9:0]; +assign dma_reg_do[15:10] = len_cnt[5:0]; +assign dma_reg_do[19:16] = cnt_fifo_rd; +assign dma_reg_do[23:20] = cnt_vld ; +assign dma_reg_do[25:24] = dma_rd_st[1:0] ; + +assign pop_req_o = fifo_rd & m_axis_tready_i ; +assign m_axis_tvalid_o = dt_tx & (dt_w | dt_vld) & m_axis_tready_i ; +assign m_axis_tdata_o = dt_w ? dt_r : fifo_dt_i ; +assign m_axis_tlast_o = dt_last & m_axis_tvalid_o;; +assign dma_ack_o = dma_rd_ack ; + +endmodule + + diff --git a/firmware/ip/qick_time_tagger/src/_qtt_ips.sv b/firmware/ip/qick_time_tagger/src/_qtt_ips.sv new file mode 100644 index 000000000..76bdd66f5 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_ips.sv @@ -0,0 +1,385 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +/// Clock Domain Register Change +/////////////////////////////////////////////////////////////////////////////// +/* +sync_reg # ( + .DW ( ) +) sync_tx_i ( + .dt_i ( ) , + .clk_i ( ) , + .rst_ni ( ) , + .dt_o ( ) ); +*/ + +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_rcd, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_rcd <= 0; + data_r <= 0; + end else begin + data_rcd <= dt_i; + data_r <= data_rcd; + end +assign dt_o = data_r ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +/// Priority Encoder +/////////////////////////////////////////////////////////////////////////////// +module priority_encoder # ( + parameter DW = 5 , + parameter OUT = "NO_REG" +)( + input wire clk_i , + input wire rst_ni , + input wire [2**DW-1:0] one_hot_dt_i , + output reg [DW-1:0] bin_dt_o , + output reg vld_o ); + +localparam ONE_HOT_DW = 2**DW; + +integer i ; +reg valid; +reg [DW-1 : 0] bin_dt ; + +always_comb begin + valid = 1'b0; + bin_dt = 0; + for (i = 0 ; i < ONE_HOT_DW; i=i+1) + if (!valid & one_hot_dt_i[i]) begin + valid = 1'b1; + bin_dt = i; + end +end + +generate + if (OUT == "NO_REG") begin: no_output_register // 1 clock cycle read + assign vld_o = valid ; + assign bin_dt_o = bin_dt ; + end else begin: output_register // 2 clock cycle read + reg vld_r = {DW{1'b0}}; + reg [DW-1:0] bin_dt_r = {DW{1'b0}}; + always @(posedge clk_i) vld_r <= valid; + always @(posedge clk_i) bin_dt_r <= bin_dt; + assign vld_o = vld_r ; + assign bin_dt_o = bin_dt_r ; + end +endgenerate + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +/// Sincronice Chain of Pulses +/////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +/* +sync_pulse # ( + .QUEUE_AW ( ) + .BLOCK ( ) +) sync_p_i ( + .a_clk_i ( ) , + .a_rst_ni ( ) , + .a_pulse_i ( ) , + .b_clk_i ( ) , + .b_rst_ni ( ) , + .b_pulse_o ( ) , + .pulse_full ( ) ); +*/ +module sync_pulse # ( + parameter QUEUE_AW = 4 , + parameter BLOCK = 0 +) ( + input wire a_clk_i , + input wire a_rst_ni , + input wire a_pulse_i , + input wire b_clk_i , + input wire b_rst_ni , + input wire b_en_i , + output reg b_pulse_o , + output wire pulse_full ); + +wire [QUEUE_AW-1:0] wr_gptr_p1, rd_gptr_p1 ; +wire [QUEUE_AW-1:0] wr_gptr, rd_gptr ; + +// Pulse Counters +reg [QUEUE_AW-1:0] wr_gptr_cdc, wr_gptr_r; +always_ff @(posedge b_clk_i) begin + wr_gptr_cdc <= wr_gptr; + wr_gptr_r <= wr_gptr_cdc; +end + +//Check for Out Pulses +assign pulse_empty = (rd_gptr == wr_gptr_r) ; + + +///// DEBUG +generate + if (BLOCK) begin + // BLOCK IF QUEUE FULL + reg [QUEUE_AW-1:0] rd_gptr_rcd, rd_gptr_r; + always_ff @(posedge a_clk_i) begin + rd_gptr_rcd <= rd_gptr; + rd_gptr_r <= rd_gptr_rcd; + end + assign pulse_full = (rd_gptr_r == wr_gptr_p1) ; + end else begin + assign pulse_full = 1'b0; + end +endgenerate + +always @(posedge b_clk_i) begin + if ( !b_rst_ni ) b_pulse_o <= 1'b0; + else if ( b_pulse_o ) b_pulse_o <= 1'b0; + else if ( !pulse_empty & b_en_i) b_pulse_o <= 1'b1; +end + +//Gray Code Counters +gcc #( + .DW ( QUEUE_AW ) +) gcc_wr_ptr ( + .clk_i ( a_clk_i ) , + .rst_ni ( a_rst_ni ) , + .async_clear_i ( 1'b0 ) , + .clear_o ( ) , + .cnt_en_i ( a_pulse_i & ~pulse_full ) , + .count_bin_o ( ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( QUEUE_AW ) +) gcc_rd_ptr ( + .clk_i ( b_clk_i ) , + .rst_ni ( b_rst_ni ) , + .async_clear_i ( 1'b0 ) , + .clear_o ( ) , + .cnt_en_i ( b_pulse_o ) , + .count_bin_o ( ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +endmodule + +/* +pulse_cdc pulse_cdc_inst ( + .clk_a_i ( ) , + .rst_a_ni ( ) , + .pulse_a_i ( ) , + .rdy_a_o ( ) , + .clk_b_i ( ) , + .rst_b_ni ( ) , + .pulse_b_o ( ) ); +*/ +module pulse_cdc ( + input wire clk_a_i , + input wire rst_a_ni , + input wire pulse_a_i , + output wire rdy_a_o , + input wire clk_b_i , + input wire rst_b_ni , + output wire pulse_b_o ); + +/// REQ +/////////////////////////////////////////////////////////////////////////////// +reg a_pulse_req; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + a_pulse_req <= 1'b0; + end else + if ( pulse_a_i ) a_pulse_req <= 1'b1; + else if ( a_pulse_ack ) a_pulse_req <= 1'b0; +end + +(* ASYNC_REG = "TRUE" *) reg pulse_req_cdc, b_pulse_req ; +reg pulse_b_req_r, pulse_b; +always_ff @(posedge clk_b_i, negedge rst_b_ni) + if(!rst_b_ni) begin + pulse_req_cdc <= 0; + b_pulse_req <= 0; + pulse_b_req_r <= 0; + pulse_b <= 0; + end else begin + pulse_req_cdc <= a_pulse_req; + b_pulse_req <= pulse_req_cdc; + pulse_b_req_r <= b_pulse_req; + pulse_b <= b_pulse_req & !pulse_b_req_r; + end + +/// ACK +/////////////////////////////////////////////////////////////////////////////// +reg b_pulse_ack; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + b_pulse_ack <= 1'b0; + end else + if ( b_pulse_req ) b_pulse_ack <= 1'b1; + else if ( !b_pulse_req ) b_pulse_ack <= 1'b0; +end + +(* ASYNC_REG = "TRUE" *) reg pulse_ack_cdc, a_pulse_ack ; +always_ff @(posedge clk_a_i, negedge rst_a_ni) + if(!rst_a_ni) begin + pulse_ack_cdc <= 0; + a_pulse_ack <= 0; + end else begin + pulse_ack_cdc <= b_pulse_ack; + a_pulse_ack <= pulse_ack_cdc; + end + +assign pulse_b_o = pulse_b; +assign rdy_a_o = !(a_pulse_req | a_pulse_ack); + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// X-Interpolator +/////////////////////////////////////////////////////////////////////////////// +module x_inter #( + parameter DW = 16 , + parameter IW = 4 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [2:0] cfg_inter_i , + input wire [DW-1:0] curr_i , + input wire [DW-1:0] prev_i , + input wire [DW-1:0] thr_i , + output wire end_o , + output wire ready_o , + output wire [IW-1:0] x_int_o ); + +// Registers +reg [IW+DW-1:0] sub_temp, r_temp, r_temp_nxt; +reg [DW-1:0] inB ; +reg [IW-1:0] q_temp; +reg [2:0] ind_bit; +reg working, qtb; + +wire [2:0] ind_bit_m1 ; + +assign ind_bit_m1 = ind_bit - 1'b1; +assign div_start = start_i; +assign div_end = (ind_bit==0) ; + + +// State Machine +/////////////////////////////////////////////////////////////////////////// +enum {IDLE, WORKING} div_st, div_st_nxt; +always_ff @(posedge clk_i) + if (!rst_ni) div_st <= IDLE; + else div_st <= div_st_nxt; + +always_comb begin + div_st_nxt = div_st; + working = 1'b0; + case (div_st) + IDLE: begin + if ( div_start ) div_st_nxt = WORKING; + end + WORKING: begin + working = 1'b1; + if ( div_end ) begin + div_st_nxt = IDLE; + end + end + endcase +end + +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + ind_bit <= -1; + q_temp <= 0 ; + r_temp <= 0 ; + inB <= 0 ; + end else if (div_start) begin + ind_bit <= cfg_inter_i; + q_temp <= 0 ; + r_temp <= ( (thr_i - prev_i) << cfg_inter_i); + inB <= ( curr_i - prev_i ); + end else if (working) begin + ind_bit <= ind_bit_m1; + r_temp <= r_temp_nxt ; + q_temp[ind_bit_m1] <= qtb ; + end +end + +/////////////////////////////////////////////////////////////////////////// +always_comb begin + qtb = 1'b0; + r_temp_nxt = r_temp ; + sub_temp = inB << ind_bit_m1 ; + if (r_temp >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt = r_temp - sub_temp ; + end else + r_temp_nxt = r_temp; +end + +/* +// In case wnat to use a DSP +wire [IW+DW-1:0] d_sub_a; +reg [IW+DW-1:0] r_temp_nxt_dsp, sub_temp_dsp; +ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY (0), // Desired clock cycle latency, 0-2 + .WIDTH (IW+DW) // Input / output bus width, 1-48 + ) ADDSUB_MACRO_inst ( + .CARRYOUT ( ), // 1-bit carry-out output signal + .RESULT ( d_sub_a ),// Add/sub result output, width defined by WIDTH parameter + .A ( r_temp ),// Input A bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b0 ),// 1-bit add/sub input, high selects add, low selects subtract + .B ( sub_temp_dsp ),// Input B bus, width defined by WIDTH parameter + .CARRYIN ( 1'b0 ),// 1-bit carry-in input + .CE ( 1'b1 ),// 1-bit clock enable input + .CLK ( clk_i ),// 1-bit clock input + .RST ( ~rst_ni) // 1-bit active high synchronous reset +); + +always_comb begin + qtb = 1'b0; + sub_temp_dsp = inB << ind_bit_m1 ; + if (d_sub_a[IW+DW-1] == r_temp[IW+DW-1]) begin // (r_temp >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt_dsp = d_sub_a ; + end else + r_temp_nxt_dsp = r_temp; +end +*/ + +/////////////////////////////////////////////////////////////////////////// +// OUT REG +//always_ff @ (posedge clk_i) begin +// if (!rst_ni) x_int_o <= 0; +// else if (div_end) x_int_o <= q_temp; +//end + +assign x_int_o = q_temp; +assign ready_o = ~working; +assign end_o = div_end; + + + +endmodule + diff --git a/firmware/ip/qick_time_tagger/src/_qtt_mem.sv b/firmware/ip/qick_time_tagger/src/_qtt_mem.sv new file mode 100644 index 000000000..fbf4a01c3 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_mem.sv @@ -0,0 +1,311 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 2 +/////////////////////////////////////////////////////////////////////////////// +// BRAM_DP_DC_EN +// gcc +// FIFO_DC +// BRAM_SC +// TAG_FIFO_TC + +////////////////////////////////////////////////////////////////////////////// +// BRAM +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +module BRAM_DP_DC_EN # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REG" // Select "NO_REG" or "REG" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] mem [RAM_SIZE]; +reg [MEM_DW-1:0] mem_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] mem_dt_b = {MEM_DW{1'b0}}; + +always @(posedge clk_a_i) + if (en_a_i) begin + mem_dt_a <= mem[addr_a_i] ; + if (we_a_i) + mem[addr_a_i] <= dt_a_i; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + mem[addr_b_i] <= dt_b_i; + else + mem_dt_b <= mem[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REG") begin: no_output_register // 1 clock cycle read + assign dt_a_o = mem_dt_a ; + assign dt_b_o = mem_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] mem_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] mem_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) if (en_a_i) mem_dt_a_r <= mem_dt_a; + always @(posedge clk_b_i) if (en_b_i) mem_dt_b_r <= mem_dt_b; + assign dt_a_o = mem_dt_a_r ; + assign dt_b_o = mem_dt_b_r ; + end +endgenerate + +endmodule + + + + + + +//GRAY CODE COUNTER +////////////////////////////////////////////////////////////////////////////// +module gcc # ( + parameter DW = 32 +)( + input wire clk_i , + input wire rst_ni , + input wire async_clear_i , + output wire clear_o , + input wire cnt_en_i , + output wire [DW-1:0] count_bin_o , + output wire [DW-1:0] count_gray_o , + output wire [DW-1:0] count_bin_p1_o , + output wire [DW-1:0] count_gray_p1_o); + +reg [DW-1:0] count_bin ; // count turned into binary number +wire [DW-1:0] count_bin_p1; // count_bin+1 + +reg [DW-1:0] count_bin_r, count_gray_r; + +integer ind; +always_comb begin + count_bin[DW-1] = count_gray_r[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin[ind] = count_bin[ind+1]^count_gray_r[ind]; + end +end + +reg clear_rcd, clear_r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + clear_rcd <= 0; + clear_r <= 0; + end else begin + clear_rcd <= async_clear_i; + clear_r <= clear_rcd; + end + +assign count_bin_p1 = count_bin + 1'b1 ; + +reg [DW-1:0] count_bin_2r, count_gray_2r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else begin + if (clear_r) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else if (cnt_en_i) begin + count_gray_r <= count_bin_p1 ^ {1'b0,count_bin_p1[DW-1:1]}; + count_bin_r <= count_bin_p1; + count_gray_2r <= count_gray_r; + count_bin_2r <= count_bin_r; + + end + end + +assign clear_o = clear_r ; +assign count_bin_o = count_bin_2r ; +assign count_gray_o = count_gray_2r ; +assign count_bin_p1_o = count_bin_r ; +assign count_gray_p1_o = count_gray_r ; + +endmodule + +////////////////////////////////////////////////////////////////////////////// +module FIFO_DC # ( + parameter FIFO_DW = 32 , + parameter FIFO_AW = 18 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + output wire [FIFO_DW - 1:0] data_o , + input wire flush_i , + output wire async_empty_o , + output wire async_full_o ); + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value +wire [FIFO_AW-1:0] rd_gptr_p1 ; +wire [FIFO_AW-1:0] wr_gptr_p1 ; +wire [FIFO_AW-1:0] rd_ptr, wr_ptr, rd_gptr, wr_gptr ; +wire clr_wr, clr_rd; + +// Sample Pointers +reg [FIFO_AW-1:0] wr_gptr_rcd, wr_gptr_r; +always_ff @(posedge rd_clk_i) begin + wr_gptr_rcd <= wr_gptr; + wr_gptr_r <= wr_gptr_rcd; +end + +reg [FIFO_AW-1:0] rd_gptr_rcd, rd_gptr_r; +always_ff @(posedge wr_clk_i) begin + rd_gptr_rcd <= rd_gptr; + rd_gptr_r <= rd_gptr_rcd; +end + + +reg clr_fifo_req, clr_fifo_ack; +reg clr_rd_rdc, clr_rd_r; +always_ff @(posedge wr_clk_i, negedge wr_rst_ni) begin + if (!wr_rst_ni) begin + clr_fifo_req <= 0 ; + clr_fifo_ack <= 0 ; + clr_rd_rdc <= 0 ; + clr_rd_r <= 0 ; + end else begin + clr_rd_rdc <= clr_rd; + clr_rd_r <= clr_rd_rdc; + if ( flush_i ) clr_fifo_req <= 1 ; + else if ( clr_fifo_ack ) clr_fifo_req <= 0 ; + if ( clear_all ) clr_fifo_ack <= 1 ; + else if ( clr_fifo_ack & clear_none) clr_fifo_ack <= 0 ; + end +end + +assign clear_all = clr_rd_r & clr_wr; +assign clear_none = !clr_rd_r & !clr_wr; + +wire busy; +assign busy = clr_fifo_ack | clr_fifo_req ; + +wire [FIFO_DW - 1:0] mem_dt; + +wire async_empty, async_full; + +//SYNC with POP (RD_CLK) +assign async_empty = (rd_gptr == wr_gptr_r) ; + +//SYNC with PUSH (WR_CLK) +assign async_full = (rd_gptr_r == wr_gptr_p1) ; + +wire do_pop, do_push; +assign do_pop = pop_i & !async_empty; +assign do_push = push_i & !async_full; + +assign async_empty_o = async_empty | busy; // While RESETTING, Shows EMPTY +assign async_full_o = async_full | busy; +assign data_o = mem_dt; + +//Gray Code Counters +gcc #( + .DW ( FIFO_AW ) +) gcc_wr_ptr ( + .clk_i ( wr_clk_i ) , + .rst_ni ( wr_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_wr ) , + .cnt_en_i ( do_push ) , + .count_bin_o ( wr_ptr ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( FIFO_AW ) +) gcc_rd_ptr ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rd_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_rd ) , + .cnt_en_i ( do_pop ) , + .count_bin_o ( rd_ptr ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +// Data +BRAM_DP_DC_EN # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( FIFO_DW ) , + .RAM_OUT ( "NO_REG" ) // Select "NO_REG" or "REG" +) fifo_mem ( + .clk_a_i ( wr_clk_i ) , + .en_a_i ( wr_en_i ) , + .we_a_i ( do_push ) , + .addr_a_i ( wr_ptr ) , + .dt_a_i ( data_i ) , + .dt_a_o ( ) , + .clk_b_i ( rd_clk_i ) , + .en_b_i ( rd_en_i ) , + .we_b_i ( 1'b0 ) , + .addr_b_i ( rd_ptr ) , + .dt_b_i ( ) , + .dt_b_o ( mem_dt ) ); + +endmodule + +////////////////////////////////////////////////////////////////////////////// +module BRAM_SC # ( + parameter MEM_AW = 18 , + parameter MEM_DW = 32 +) ( + input wire clk_i , + input wire we_a_i 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FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_7_24 +// Version : 13 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Time Tagger +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_time_tagger # ( + parameter EXT_ARM = 0 , // External ARM Control + parameter ADC_QTY = 1 , // Number of ADC Inputs + parameter CMP_INTER = 4 , // Max Number of Interpolation bits + parameter ARM_STORE = 1 , // Store NUmber of Triggers on each ARM + parameter SMP_STORE = 0 , // Store Sample Values + parameter TAG_FIFO_AW = 16 , // Size of TAG FIFO Memory + parameter ARM_FIFO_AW = 10 , // Size of ARM FIFO Memory + parameter SMP_FIFO_AW = 18 , // Size of SAMPLE FIFO Memory + parameter CMP_SLOPE = 0 , // Compare with SLOPE Option + parameter SMP_DW = 16 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter DEBUG = 1 +) ( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire adc_clk , + input wire adc_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// EXTERNAL INTERFACE + input wire arm_i , + output wire trig_o , + output wire cmp_o , +// PROCESSOR INTERFACE + input wire qtag_en_i , + input wire [ 4:0] qtag_op_i , + input wire [31:0] qtag_dt1_i , + input wire [31:0] qtag_dt2_i , + input wire [31:0] qtag_dt3_i , + input wire [31:0] qtag_dt4_i , + output reg qtag_rdy_o , + output reg [31:0] qtag_dt1_o , + output reg [31:0] qtag_dt2_o , + output reg qtag_vld_o , + output reg qtag_flag_o , +// AXI INTERFACE + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// ADC DATA + input wire adc0_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc0_s_axis_tdata_i , + output wire adc0_s_axis_tready_o , + input wire adc1_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc1_s_axis_tdata_i , + output wire adc1_s_axis_tready_o , + input wire adc2_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc2_s_axis_tdata_i , + output wire adc2_s_axis_tready_o , + input wire adc3_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc3_s_axis_tdata_i , + output wire adc3_s_axis_tready_o , +///// DATA DMA + input wire dma_m_axis_tready_i , + output wire dma_m_axis_tvalid_o , + output wire [31:0] dma_m_axis_tdata_o , + output wire dma_m_axis_tlast_o , +///// DEBUG + output wire [31:0] qtt_do + ); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// + + +wire [31:0] tag_dt ; +wire [TAG_FIFO_AW-1:0] dma_qty [4] ; +wire [TAG_FIFO_AW-1:0] proc_qty ; +wire [SMP_FIFO_AW-1:0] smp_qty ; +wire [ARM_FIFO_AW-1:0] arm_qty ; + + +wire [2:0] cfg_inter; +wire [4:0] qtt_op; + +wire [ 2:0] dma_mem_sel; +wire [19:0] dma_len; +wire [4:0] cfg_smp_wr_qty; + +// PERIPHERAL +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qtt_reg_debug_s, qtt_debug_s; + +wire [ 7:0] axi_reg_CTRL; +wire [10:0] axi_reg_CFG; +wire [23:0] axi_reg_DMA_CFG ; +wire [31:0] axi_reg_AXI_DT1 ; +wire [31:0] axi_reg_PROC_DT ; +wire [31:0] axi_reg_PROC_QTY, axi_reg_TAG0_QTY ; +wire [31:0] axi_reg_TAG1_QTY, axi_reg_TAG2_QTY, axi_reg_TAG3_QTY ; +wire [31:0] axi_reg_SMP_QTY, axi_reg_ARM_QTY ; +wire [31:0] axi_reg_THR_INH , axi_reg_QTT_STATUS, axi_reg_QTT_DEBUG; + +wire [SMP_DW-1:0] qtt_cmp_th; +wire[7:0] qtt_cmp_inh; +wire [23:0]qtt_reg_status_s; + +wire [SMP_CK*SMP_DW-1:0] adc_dt [ADC_QTY]; + +generate + if (ADC_QTY == 1 ) begin: ONE_ADC + assign adc_dt = '{adc0_s_axis_tdata_i}; + end else if (ADC_QTY == 2) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i}; + end else if (ADC_QTY == 3) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i}; + end else if (ADC_QTY == 4) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i, adc3_s_axis_tdata_i}; + end +endgenerate +generate + +endgenerate + +qick_time_tagger # ( + .ADC_QTY ( ADC_QTY ) , + .CMP_SLOPE ( CMP_SLOPE ) , + .CMP_INTER ( CMP_INTER ) , + .ARM_STORE ( ARM_STORE ) , + .SMP_STORE ( SMP_STORE ) , + .TAG_FIFO_AW ( TAG_FIFO_AW ) , + .ARM_FIFO_AW ( ARM_FIFO_AW ) , + .SMP_FIFO_AW ( SMP_FIFO_AW ) , + .SMP_DW ( SMP_DW ) , + .SMP_CK ( SMP_CK ) , + .DEBUG ( DEBUG ) +) QTT ( + .ps_clk_i ( ps_clk ) , + .ps_rst_ni ( ps_aresetn ) , + .c_clk_i ( c_clk ) , + .c_rst_ni ( c_aresetn ) , + .adc_clk_i ( adc_clk ) , + .adc_rst_ni ( adc_aresetn ) , + .qtt_pop_req_i ( qtt_pop_req ) , + .qtt_rst_req_i ( qtt_rst_req ) , + .qtt_rst_ack_o ( qtt_rst_ack ) , + .cfg_invert_i ( cfg_invert ), + .cfg_filter_i ( cfg_filter ), + .cfg_slope_i ( cfg_slope ), + .cfg_inter_i ( cfg_inter ), + .cfg_smp_wr_qty_i ( cfg_smp_wr_qty ) , + .arm_i ( qtt_arm ) , // Arm Trigger (ONE works) + .cmp_th_i ( qtt_cmp_th ) , // Threhold Data + .cmp_inh_i ( qtt_cmp_inh ) , // Inhibit Clock Pulses + .adc_dt_i ( adc_dt ) , +// DMA + .dma_req_i ( dma_rd ) , + .dma_mem_sel_i ( dma_mem_sel ) , + .dma_len_i ( dma_len ) , + .dma_ack_o ( ) , + .dma_m_axis_tready_i ( dma_m_axis_tready_i ) , + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ) , + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ) , + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ) , +//PROC + .tag_dt_o ( tag_dt ) , + .tag_vld_o ( qtt_tag_vld ) , + .trig_o ( trig_o ) , + .cmp_o ( cmp_o ) , +//DATA + .proc_qty_o ( proc_qty ) , + .dma_qty_o ( dma_qty ) , + .smp_qty_o ( smp_qty ) , + .arm_qty_o ( arm_qty ) , + .qtt_debug_o ( qtt_debug_s ) , + .qtt_reg_status_o ( qtt_reg_status_s ) , + .qtt_reg_debug_o ( qtt_reg_debug_s ) ); + +wire[7:0] cmd_cnt_do; +qtt_cmd CMD ( + .clk_i ( adc_clk ) , + .rst_ni ( adc_aresetn ) , + .c_clk_i ( c_clk ) , + .c_rst_ni ( c_aresetn ) , + .ext_arm_i ( arm_i ) , + .c_en_i ( qtag_en_i ) , + .c_op_i ( qtag_op_i ) , + .c_dt_i ( qtag_dt1_i ) , + .p_en_i ( qtt_cmd_en ) , + .p_op_i ( qtt_op ) , + .p_dt_i ( axi_reg_AXI_DT1 ) , + .pop_req_o ( qtt_pop_req ) , +// .pop_ack_i ( qtt_pop_ack ) , + .rst_req_o ( qtt_rst_req ) , + .rst_ack_i ( qtt_rst_ack ) , + .peek_o ( cmd_peek ) , + .qtt_arm_o ( qtt_arm ) , + .qtt_cmp_th_o ( qtt_cmp_th ) , + .qtt_cmp_inh_o ( qtt_cmp_inh ) , + .cmd_cnt_do ( cmd_cnt_do ) ); + + + +assign qtt_cmd_en = axi_reg_CTRL[0]; +assign qtt_op = {1'b0,axi_reg_CTRL[4:1]}; +assign dma_rd = axi_reg_CTRL[5]; + +assign cfg_filter = axi_reg_CFG[0]; +assign cfg_slope = axi_reg_CFG[1]; +assign cfg_inter = axi_reg_CFG[4:2]; +assign cfg_smp_wr_qty = axi_reg_CFG[9:5]; +assign cfg_invert = axi_reg_CFG[10]; + +assign dma_mem_sel = axi_reg_DMA_CFG[ 2:0]; +assign dma_len = axi_reg_DMA_CFG[23:4]; + +// AXI REGISTER ASSIGNMENT +/////////////////////////////////////////////////////////////////////////////// +localparam zf_taw = 20-TAG_FIFO_AW; +localparam zf_saw = 20-SMP_FIFO_AW; +localparam zf_aaw = 20-ARM_FIFO_AW; +localparam zf_th = 16-SMP_DW; + +assign axi_reg_PROC_DT = tag_dt; +assign axi_reg_PROC_QTY = { 12'd0, {zf_taw{1'b0}}, proc_qty }; +assign axi_reg_TAG0_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[0] }; +assign axi_reg_TAG1_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[1] }; +assign axi_reg_TAG2_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[2] }; +assign axi_reg_TAG3_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[3] }; +assign axi_reg_SMP_QTY = { 12'd0, {zf_saw{1'b0}}, smp_qty }; +assign axi_reg_ARM_QTY = { 12'd0, {zf_aaw{1'b0}}, arm_qty }; +assign axi_reg_THR_INH = { 8'd0, qtt_cmp_inh, {zf_th{1'b0}}, qtt_cmp_th }; +assign axi_reg_QTT_STATUS = { qtt_reg_status_s , cmd_cnt_do } ; + +///// DATA PROC + +/////////////////////////////////////////////////////////////////////////////// +// AXI Registers +/////////////////////////////////////////////////////////////////////////////// +axi_slv_qtt AXI_REG ( + .aclk ( ps_clk ), + .aresetn ( ps_aresetn ), + .awaddr ( s_axi_awaddr[5:0] ), + .awprot ( s_axi_awprot ), + .awvalid ( s_axi_awvalid ), + .awready ( s_axi_awready ), + .wdata ( s_axi_wdata ), + .wstrb ( s_axi_wstrb ), + .wvalid ( s_axi_wvalid ), + .wready ( s_axi_wready ), + .bresp ( s_axi_bresp ), + .bvalid ( s_axi_bvalid ), + .bready ( s_axi_bready ), + .araddr ( s_axi_araddr ), + .arprot ( s_axi_arprot ), + .arvalid ( s_axi_arvalid ), + .arready ( s_axi_arready ), + .rdata ( s_axi_rdata ), + .rresp ( s_axi_rresp ), + .rvalid ( s_axi_rvalid ), + .rready ( s_axi_rready ), +// Registers + .CTRL (axi_reg_CTRL ), + .CFG (axi_reg_CFG ), + .DMA_CFG (axi_reg_DMA_CFG ), + .AXI_DT1 (axi_reg_AXI_DT1 ), + .PROC_DT (axi_reg_PROC_DT ), + .PROC_QTY (axi_reg_PROC_QTY ), + .TAG0_QTY (axi_reg_TAG0_QTY ), + .TAG1_QTY (axi_reg_TAG1_QTY ), + .TAG2_QTY (axi_reg_TAG2_QTY ), + .TAG3_QTY (axi_reg_TAG3_QTY ), + .SMP_QTY (axi_reg_SMP_QTY ), + .ARM_QTY (axi_reg_ARM_QTY ), + .THR_INH (axi_reg_THR_INH ), + .QTT_STATUS (axi_reg_QTT_STATUS ), + .QTT_DEBUG (axi_reg_QTT_DEBUG ) +); + + + +/////////////////////////////////////////////////////////////////////////////// +// OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// +assign adc0_s_axis_tready_o = 1'b1; +assign adc1_s_axis_tready_o = 1'b1; +assign adc2_s_axis_tready_o = 1'b1; +assign adc3_s_axis_tready_o = 1'b1; + +assign qtag_rdy_o = 1; +assign qtag_dt1_o = tag_dt; +//assign qtag_dt2_o = axi_reg_PROC_QTY; +assign qtag_vld_o = qtt_tag_vld | cmd_peek; +assign qtag_flag_o = 0; + +sync_reg # ( + .DW ( 32 ) +) sync_dt2 ( + .dt_i ( axi_reg_PROC_QTY ) , + .clk_i ( c_clk ) , + .rst_ni ( c_aresetn ) , + .dt_o ( qtag_dt2_o ) ); + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +generate + if (DEBUG == 0 ) begin: DEBUG_NO + assign axi_reg_QTT_DEBUG = 0; + assign qtt_do = 0; + end else if (DEBUG == 1) begin: DEBUG_REG + assign axi_reg_QTT_DEBUG = qtt_reg_debug_s; + assign qtt_do = 0; + end else if (DEBUG == 2) begin: DEBUG_OUT + assign axi_reg_QTT_DEBUG = qtt_reg_debug_s; + assign qtt_do = qtt_debug_s; + end +endgenerate + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd b/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd new file mode 100644 index 000000000..5f37aea03 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd @@ -0,0 +1,521 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qtt is + Generic ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6); + Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + CTRL : out std_logic_vector ( 7 downto 0) ; + CFG : out std_logic_vector (10 downto 0) ; + DMA_CFG : out std_logic_vector (23 downto 0) ; + AXI_DT1 : out std_logic_vector (31 downto 0) ; + PROC_DT : in std_logic_vector (31 downto 0) ; + PROC_QTY : in std_logic_vector (31 downto 0) ; + TAG0_QTY : in std_logic_vector (31 downto 0) ; + TAG1_QTY : in std_logic_vector (31 downto 0) ; + TAG2_QTY : in std_logic_vector (31 downto 0) ; + TAG3_QTY : in std_logic_vector (31 downto 0) ; + SMP_QTY : in std_logic_vector (31 downto 0) ; + ARM_QTY : in std_logic_vector (31 downto 0) ; + THR_INH : in std_logic_vector (31 downto 0) ; + QTT_STATUS : in std_logic_vector (31 downto 0) ; + QTT_DEBUG : in std_logic_vector (31 downto 0) ); +end axi_slv_qtt; + +architecture rtl of axi_slv_qtt is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= PROC_DT; + when b"0110" => + reg_data_out <= PROC_QTY; + when b"0111" => + reg_data_out <= TAG0_QTY; + when b"1000" => + reg_data_out <= TAG1_QTY; + when b"1001" => + reg_data_out <= TAG2_QTY; + when b"1010" => + reg_data_out <= TAG3_QTY; + when b"1011" => + reg_data_out <= SMP_QTY; + when b"1100" => + reg_data_out <= ARM_QTY; + when b"1101" => + reg_data_out <= THR_INH; + when b"1110" => + reg_data_out <= QTT_STATUS; + when b"1111" => + reg_data_out <= QTT_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +CTRL <= slv_reg0( 7 downto 0); +CFG <= slv_reg1(10 downto 0); +DMA_CFG <= slv_reg2(23 downto 0); +AXI_DT1 <= slv_reg3(31 downto 0); + +end rtl; diff --git a/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv b/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv new file mode 100644 index 000000000..c09b0e248 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv @@ -0,0 +1,362 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-6-21 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qick_time_tagger # ( + parameter ADC_QTY = 4 , // Number of ADC Inputs + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 4 , // Max Number of Interpolation bits + parameter ARM_STORE = 1 , // Store NUmber of Triggers on each ARM + parameter SMP_STORE = 1 , // Store Sample Values + parameter TAG_FIFO_AW = 19 , // Size of TAG FIFO Memory + parameter ARM_FIFO_AW = 10 , // Size of ARM FIFO Memory + parameter SMP_FIFO_AW = 10 , // Size of SAMPLE FIFO Memory + parameter SMP_DW = 19 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter DEBUG = 1 +) ( +// Core and AXI CLK & RST + input wire ps_clk_i , + input wire ps_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire adc_clk_i , + input wire adc_rst_ni , + input wire qtt_pop_req_i , + input wire qtt_rst_req_i , // reset from qtt_cmd, on ADC clock + output wire qtt_rst_ack_o , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire cfg_slope_i , + input wire [2:0] cfg_inter_i , + input wire [4:0] cfg_smp_wr_qty_i , + input wire arm_i , // Arm Trigger (ONE works) + input wire [SMP_DW-1:0] cmp_th_i , // Threhold Data + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i[ADC_QTY] , +///// DATA DMA + input wire dma_req_i , + input wire [2:0] dma_mem_sel_i , + input wire [19:0] dma_len_i , + output wire dma_ack_o , + input wire dma_m_axis_tready_i , + output wire dma_m_axis_tvalid_o , + output wire [31:0] dma_m_axis_tdata_o , + output wire dma_m_axis_tlast_o , +///// DATA PROC + output wire [31:0] tag_dt_o , + output wire tag_vld_o , + output wire trig_o , + output wire cmp_o , + +///// DATA OUT + output wire [TAG_FIFO_AW-1:0] proc_qty_o , + output wire [TAG_FIFO_AW-1:0] dma_qty_o [4] , + output wire [SMP_FIFO_AW-1:0] smp_qty_o , + output wire [ARM_FIFO_AW-1:0] arm_qty_o , +///// STATUS & DEBUG + output wire [31:0] qtt_debug_o , + output wire [23:0] qtt_reg_status_o , + output wire [31:0] qtt_reg_debug_o + ); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// +wire [15:0] dma_ds; +wire [25:0] dma_reg_ds; + +wire [31:0] tag_fifo_dt, arm_fifo_dt, smp_fifo_dt; +wire tag_dma_pop_req, tag_dma_pop_ack ; +wire arm_dma_pop_req, arm_dma_pop_ack ; +wire smp_dma_pop_req, smp_dma_pop_ack ; + +wire [ADC_QTY-1:0] tag_vld_s ; +wire [31:0] tag_dt_s [ADC_QTY]; + +wire trig_event; +wire [TAG_FIFO_AW-1:0] dma_qty_s [4]; + + +// Synchronize Input Signals +////////////////////////////////////////////////////////////////////////// + +sync_reg # ( + .DW ( 1 ) +) sync_arm ( + .dt_i ( arm_i ), + .clk_i ( adc_clk_i ), + .rst_ni ( adc_rst_ni ), + .dt_o ( arm_s ) +); + +// Control State Machine +////////////////////////////////////////////////////////////////////////// +typedef enum { ST_RST, ST_IDLE, ST_ARMED } TYPE_TRIG_ST; +(* fsm_encoding = "one_hot" *) TYPE_TRIG_ST time_trig_st; +TYPE_TRIG_ST time_trig_st_nxt; + +always_ff @ (posedge adc_clk_i, negedge adc_rst_ni) begin + if ( !adc_rst_ni ) time_trig_st <= ST_IDLE; + else time_trig_st <= time_trig_st_nxt; +end + +reg inhibit, tag_gen_en, qtt_rst; +; +always_comb begin + time_trig_st_nxt = time_trig_st; + tag_gen_en = 1'b0; + qtt_rst = 1'b0; + case (time_trig_st) + ST_RST: begin + qtt_rst = 1'b1; + if ( !qtt_rst_req_i ) time_trig_st_nxt = ST_IDLE; + end + ST_IDLE: begin + if ( qtt_rst_req_i ) time_trig_st_nxt = ST_RST; + else if ( arm_s ) time_trig_st_nxt = ST_ARMED; + end + ST_ARMED: begin + tag_gen_en = 1'b1; + if (!arm_s) + time_trig_st_nxt = ST_IDLE; + end + endcase +end + +// Time Counter +////////////////////////////////////////////////////////////////////////// +reg [28:0] time_cnt; +always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) time_cnt <= 0; + else + if (tag_gen_en) time_cnt <= time_cnt + 1'b1; + else time_cnt <= 0; +end + +assign tag_mem_sel = (dma_mem_sel_i[2] == 1'b0); +assign arm_mem_sel = (dma_mem_sel_i == 3'b100); +assign smp_mem_sel = (dma_mem_sel_i == 3'b101); + +assign tag_dma_pop_req = dma_pop_req & tag_mem_sel ; +assign arm_dma_pop_req = dma_pop_req & arm_mem_sel ; +assign smp_dma_pop_req = dma_pop_req & smp_mem_sel ; + +assign dma_pop_ack = tag_mem_sel & tag_dma_pop_ack | arm_mem_sel & arm_dma_pop_ack | smp_mem_sel & smp_dma_pop_ack ; + +reg [31:0] dma_fifo_dt ; +always_comb + case (dma_mem_sel_i) + 3'b000: dma_fifo_dt = tag_fifo_dt; // tag0_dt + 3'b001: dma_fifo_dt = tag_fifo_dt; // tag1_dt + 3'b010: dma_fifo_dt = tag_fifo_dt; // tag2_dt + 3'b011: dma_fifo_dt = tag_fifo_dt; // tag3_dt + 3'b100: dma_fifo_dt = arm_fifo_dt; + 3'b101: dma_fifo_dt = smp_fifo_dt; + default: dma_fifo_dt = tag_fifo_dt; + endcase + +// Instances +////////////////////////////////////////////////////////////////////////// +tag_gen #( + .ADC_QTY ( ADC_QTY ), + .CMP_SLOPE ( CMP_SLOPE ), + .CMP_INTER ( CMP_INTER ), + .SMP_DW ( SMP_DW ), + .SMP_CK ( SMP_CK ) +) TAG_GEN ( + .clk_i ( adc_clk_i ), + .rst_ni ( adc_rst_ni ), + .cfg_invert_i ( cfg_invert_i ), + .cfg_filter_i ( cfg_filter_i ), + .cfg_slope_i ( cfg_slope_i ), + .cfg_inter_i ( cfg_inter_i ), + .time_ck_i ( time_cnt ), + .cmp_th_i ( cmp_th_i ), + .cmp_inh_i ( cmp_inh_i ), + .en_i ( tag_gen_en ), + .adc_dt_i ( adc_dt_i ), + .trig_o ( trig_event ), + .cmp_o ( cmp_s ) , + .tag_vld_o ( tag_vld_s ), + .tag_dt_o ( tag_dt_s ) +); + +tag_mem # ( + .MEM_QTY ( ADC_QTY ), // Amount of Memories + .TAG_FIFO_AW ( TAG_FIFO_AW ), // Size of TAG FIFO Memory + .DEBUG ( DEBUG ) +) TAG_MEM ( + .dma_clk_i ( ps_clk_i ), + .dma_rst_ni ( ps_rst_ni ), + .c_clk_i ( c_clk_i ), + .c_rst_ni ( c_rst_ni ), + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .qtt_pop_req_i ( qtt_pop_req_i ), + .qtt_pop_ack_o ( qtt_pop_ack ), + .qtt_rst_req_i ( qtt_rst_req_i ), + .qtt_rst_ack_o ( ), + .tag_wr_i ( tag_vld_s ), + .tag_dt_i ( tag_dt_s ), + .dma_qty_o ( dma_qty_o ), + .proc_qty_o ( proc_qty_o ), + .empty_o ( tag_empty_o ), + .full_o ( tag_full_o ), + .dma_sel_i ( dma_mem_sel_i[1:0]), + .dma_pop_i ( tag_dma_pop_req ), + .dma_pop_o ( tag_dma_pop_ack ), + .dma_dt_o ( tag_fifo_dt ), + .debug_do ( tag_debug_o ) +); + +dma_fifo_rd # ( + .MEM_AW ( 20 ), // Memory Address Width + .MEM_DW ( 32 ), // Memory Data Width + .DMA_DW ( 32 ) // DMA Data Width +) DMA ( + .clk_i ( ps_clk_i ), + .rst_ni ( ps_rst_ni ), + .dma_req_i ( dma_req_i ), + .dma_ack_o ( dma_ack_o ), + .dma_len_i ( dma_len_i ), + .pop_req_o ( dma_pop_req ), + .pop_ack_i ( dma_pop_ack ), + .fifo_dt_i ( dma_fifo_dt ), + .m_axis_tready_i ( dma_m_axis_tready_i ), + .m_axis_tdata_o ( dma_m_axis_tdata_o ), + .m_axis_tvalid_o ( dma_m_axis_tvalid_o ), + .m_axis_tlast_o ( dma_m_axis_tlast_o ), + .dma_do ( dma_ds ), + .dma_reg_do ( dma_reg_ds ) +); + +generate + if (SMP_STORE == 1 ) begin: SMP + smp_mem # ( + .SMP_DW ( SMP_DW ) , // Samples WIDTH + .SMP_CK ( SMP_CK ) , // Samples per Clock + .SMP_FIFO_AW ( SMP_FIFO_AW ) // Size of SAMPLES FIFO Memory + ) SMP_MEM ( + // Core and AXI CLK & RST + .dma_clk_i ( ps_clk_i ) , + .dma_rst_ni ( ps_rst_ni ) , + .adc_clk_i ( adc_clk_i ) , + .adc_rst_ni ( adc_rst_ni ) , + .qtt_rst_req_i ( qtt_rst_req_i ) , + .qtt_rst_ack_o ( ) , + .cfg_smp_wr_qty_i ( cfg_smp_wr_qty_i ) , + .tag_wr_i ( trig_event ) , + .adc_dt_i ( adc_dt_i[0] ) , + .dma_pop_i ( smp_dma_pop_req ) , + .dma_pop_o ( smp_dma_pop_ack ) , + .dma_dt_o ( smp_fifo_dt ) , + .dma_qty_o ( smp_qty_o ) , + .smp_empty_o ( smp_empty ) , + .smp_full_o ( smp_full ) , + .debug_do ( smp_debug ) + ); + end else begin + assign smp_dma_pop_ack = 0; + assign smp_fifo_dt = 0; + assign smp_qty_o = 0; + assign smp_empty = 1; + assign smp_full = 0; + assign smp_debug = 0; + end + + if (ARM_STORE ==1 ) begin: ARM + wire arm_t10; + reg arm_r; + // ARM signal + ////////////////////////////////////////////////////////////////////////// + always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) arm_r <= 0; + else arm_r <= arm_s; + end + + assign arm_t10 = arm_r & !arm_s ; + + // Trig Counter + ////////////////////////////////////////////////////////////////////////// + reg [31:0] trig_cnt; + always_ff @(posedge adc_clk_i) begin + if ( !adc_rst_ni ) trig_cnt <= 0; + else if ( !tag_gen_en ) trig_cnt <= 0; + else if ( trig_event ) trig_cnt <= trig_cnt + 1'b1; + end + + TAG_FIFO_DC # ( + .FIFO_AW ( ARM_FIFO_AW ) + ) ARM_MEM ( + .dma_clk_i ( ps_clk_i ), + .dma_rst_ni ( ps_rst_ni ), + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .flush_i ( qtt_rst_req_i ), + .flush_o ( ), + .adc_push_i ( arm_t10 ), + .adc_data_i ( trig_cnt ), + .dma_pop_i ( arm_dma_pop_req ), + .dma_pop_o ( arm_dma_pop_ack ), + .dma_qty_o ( arm_qty_o ), + .dma_dt_o ( arm_fifo_dt ), + .empty_o ( arm_empty ), + .full_o ( arm_full ), + .debug_do ( ) + ); + end else begin + assign arm_dma_pop_ack = 0; + assign arm_fifo_dt = 0; + assign arm_qty_o = 0; + assign arm_empty = 1; + assign arm_full = 0; + end +endgenerate + + +// STATUS +/////////////////////////////////////////////////////////////////////////////// +assign qtt_reg_status_o[7:0] = time_trig_st[7:0]; +assign qtt_reg_status_o[9:8] = dma_reg_ds[25:24]; +assign qtt_reg_status_o[23:10] = 0; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + +assign qtt_debug_o[31:16] = dma_ds; +assign qtt_reg_debug_o[5:4] = 2'b00; +assign qtt_reg_debug_o[31:6] = dma_reg_ds; + + +/////////////////////////////////////////////////////////////////////////////// +// OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// +pulse_cdc tag_vld_sync ( + .clk_a_i ( ps_clk_i ) , + .rst_a_ni ( ps_rst_ni ) , + .pulse_a_i ( qtt_pop_ack ) , + .rdy_a_o ( ) , + .clk_b_i ( c_clk_i ) , + .rst_b_ni ( c_rst_ni ) , + .pulse_b_o ( tadg_vld ) +); + +reg [31:0] tag_dt_r; +always_ff @(posedge c_clk_i) begin + if ( !c_rst_ni ) tag_dt_r <= 0; + else if ( qtt_pop_ack ) tag_dt_r <= tag_fifo_dt; +end + +assign qtt_rst_ack_o = qtt_rst; + + +assign tag_dt_o = tag_dt_r; +assign tag_vld_o = tadg_vld; +assign trig_o = trig_event; +assign cmp_o = cmp_s; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/qtt_cmd.sv b/firmware/ip/qick_time_tagger/src/qtt_cmd.sv new file mode 100644 index 000000000..ef184669b --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qtt_cmd.sv @@ -0,0 +1,221 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + + +module qtt_cmd ( + input wire clk_i , // ADC clock + input wire rst_ni , // reset on ADC clock + input wire c_clk_i , // tProc core clock + input wire c_rst_ni , // reset on tProc core clock + input wire ext_arm_i , // external arm signal (typ. on ADC clock) + input wire c_en_i , // command enable, from tProc core (core clock is assumed to be slower than ADC clock) + input wire [4:0] c_op_i , // command opcode, from tProc core + input wire [31:0] c_dt_i , // command data, from tProc core + input wire p_en_i , // command enable, from AXI registers + input wire [4:0] p_op_i , // command opcode, from AXI registers + input wire [31:0] p_dt_i , // command data, from AXI registers + output wire pop_req_o , // pop, to time tagger + output wire rst_req_o , // reset, to time tagger + input wire rst_ack_i , // reset acknowledge, from time tagger + output wire peek_o , // peek (data-valid), to tProc core + output wire qtt_arm_o , // arm signal, to time tagger and AXI register + output wire [15:0] qtt_cmp_th_o , // threshold, to time tagger and AXI register + output wire [7 :0] qtt_cmp_inh_o , // deadtime, to time tagger and AXI register + output wire [7 :0] cmd_cnt_do ); // command count, to AXI register + + +// Sincronization +/////////////////////////////////////////////////////////////////////////////// +wire p_en_r, p_en_r_t01; +wire ext_arm_r, ext_arm_t01, ext_arm_t10; +wire [4:0] p_op_r; +reg ext_arm_2r, p_en_2r; + +sync_reg # ( + .DW ( 7 ) +) sync_cmd ( + .dt_i ( {ext_arm_i, p_en_i, p_op_i} ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( {ext_arm_r, p_en_r, p_op_r} ) ); + +reg c_en_r; +reg [4:0] c_op_r; +reg [31:0] c_dt_r; +wire cdc_ack; + +always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + c_en_r <= 0; + c_op_r <= 5'd0; + c_dt_r <= 32'd0; + end else begin + c_op_r <= c_op_i; + c_dt_r <= c_dt_i; + if (cdc_ack) begin + c_en_r <= 0; + end else if (c_en_i) begin + c_en_r <= c_en_i; + end + end +wire c_en_2r; +wire [4:0] c_op_2r; +wire [31:0] c_dt_2r; + +xpm_cdc_handshake #( + .DEST_EXT_HSK(0), // DECIMAL; 0=internal handshake, 1=external handshake + .DEST_SYNC_FF(2), // DECIMAL; range: 2-10 + .INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_SYNC_FF(2), // DECIMAL; range: 2-10 + .WIDTH(37) // DECIMAL; range: 1-1024 +) +xpm_cdc_handshake_core ( + .dest_out({c_op_2r, c_dt_2r}), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain. + .dest_req(c_en_2r), // When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus is valid. This output is registered. + .src_rcv(cdc_ack), // 1-bit output: Acknowledgement from destination logic that src_in has been received. + .dest_ack(), // 1-bit input: optional; required when DEST_EXT_HSK = 1 + .dest_clk(clk_i), // 1-bit input: Destination clock. + .src_clk(c_clk_i), // 1-bit input: Source clock. + .src_in({c_op_r, c_dt_r}), // WIDTH-bit input: Input bus that will be synchronized to the destination clock domain. + .src_send(c_en_r) // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to the destination clock domain. +); + +assign p_en_r_t01 = !p_en_2r & p_en_r; +assign ext_arm_t01 = !ext_arm_2r & ext_arm_r; +assign ext_arm_t10 = ext_arm_2r & !ext_arm_r; + +// COMMAND OPERATON +reg cmd_req; +reg [ 4:0] cmd_op; +reg [31:0] cmd_dt; +reg [ 3:0] p_cmd_cnt, c_cmd_cnt; + +always_ff @(posedge clk_i) + if (!rst_ni) begin + cmd_req <= 1'b0; + cmd_op <= 5'd0; + cmd_dt <= 0; + p_cmd_cnt <= 3'd0; + c_cmd_cnt <= 3'd0; + end else begin + p_en_2r <= p_en_r; + ext_arm_2r <= ext_arm_r; + // Python Command + if (p_en_r_t01) begin + cmd_req <= 1'b1; + cmd_op <= p_op_r ; + cmd_dt <= p_dt_i ; + p_cmd_cnt <= p_cmd_cnt + 1'b1; + // Processor Command + end else if (c_en_2r) begin + cmd_req <= 1'b1; + cmd_op <= c_op_2r ; + cmd_dt <= c_dt_2r ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + //External ARM + end else if (ext_arm_t01) begin + cmd_req <= 1'b1; + cmd_op <= 5'b00001 ; + cmd_dt <= 0 ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + //External DISARM + end else if (ext_arm_t10) begin + cmd_req <= 1'b1; + cmd_op <= 5'b00000 ; + cmd_dt <= 0 ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + + end else + if ( cmd_req ) cmd_req <= 1'b0; + end + +// Command Decoding +/////////////////////////////////////////////////////////////////////////////// + +assign ext_arm_t01 = !ext_arm_2r & ext_arm_r; +assign ext_arm_t10 = ext_arm_2r & !ext_arm_r; + +assign cmd_disarm = cmd_req & ( cmd_op==5'b00000 ); +assign cmd_arm = cmd_req & ( cmd_op==5'b00001 ); +assign cmd_pop = cmd_req & ( cmd_op==5'b00010 ); +assign cmd_peek = cmd_req & ( cmd_op==5'b00011 ); +assign cmd_set_th = cmd_req & ( cmd_op==5'b00100 ); +assign cmd_set_inh = cmd_req & ( cmd_op==5'b00101 ); + +assign cmd_reset = cmd_req & ( cmd_op==5'b00111 ); + + + +// Command Processing +/////////////////////////////////////////////////////////////////////////////// +reg qtt_arm, qtt_rst, qtt_pop; +reg[15:0] qtt_cmp_th; +reg[ 7:0] qtt_cmp_inh; +reg core_peek; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + qtt_arm <= 0; + qtt_cmp_th <= 0; + qtt_cmp_inh <= 0; + qtt_rst <= 0; + qtt_pop <= 0; + core_peek <= 0; + + end + else if ( cmd_arm ) qtt_arm <= 1'b1; + else if ( cmd_disarm ) qtt_arm <= 1'b0; + else if ( cmd_reset ) qtt_rst <= 1'b1; + else if ( rst_ack_i ) qtt_rst <= 1'b0; + else if ( cmd_pop ) qtt_pop <= 1'b1; + else if ( qtt_pop ) qtt_pop <= 1'b0; + else if ( cmd_peek ) core_peek <= 1'b1; + else if ( core_peek ) core_peek <= 1'b0; + + else if ( cmd_set_th ) qtt_cmp_th <= cmd_dt[15:0]; + else if ( cmd_set_inh ) qtt_cmp_inh <= cmd_dt[7:0]; +end + +/* +pulse_cdc peek_sync ( + .clk_a_i ( clk_i ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( core_peek) , + .rdy_a_o ( ) , + .clk_b_i ( c_clk_i ) , + .rst_b_ni ( c_rst_ni ) , + .pulse_b_o ( peek_o ) +); +*/ + +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) peek_sync ( + .a_clk_i ( clk_i ) , + .a_rst_ni ( rst_ni ) , + .a_pulse_i ( core_peek ) , + .b_clk_i ( c_clk_i ) , + .b_rst_ni ( c_rst_ni) , + .b_pulse_o ( peek_o ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +assign pop_req_o = qtt_pop ; +assign rst_req_o = qtt_rst; +assign qtt_arm_o = qtt_arm ; +assign qtt_cmp_th_o = qtt_cmp_th ; +assign qtt_cmp_inh_o = qtt_cmp_inh ; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign cmd_cnt_do ={ c_cmd_cnt, p_cmd_cnt }; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv b/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv new file mode 100644 index 000000000..093cf8a78 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv @@ -0,0 +1,259 @@ +module qtt_tag_calc # ( + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 1 , // Interpolate SAMPLES + parameter SMP_DW = 16 , //Sample Data width + parameter SMP_CK = 8 // Samples per Clock +) ( + input wire clk_i , + input wire rst_ni , + input wire arm_i , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire [2:0] cfg_inter_i , + input wire cfg_slope_i , + input wire [28:0] time_ck_i , + input wire [SMP_DW-1:0] cmp_th_i , + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire [SMP_CK*SMP_DW-1:0] dt_i , + output wire trig_o , + output wire cmp_o , + output wire tag_vld_o , + output wire [31:0] tag_dt_o , + output wire [7:0] debug_do +); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// +reg signed [SMP_DW-1:0] adc_smp [SMP_CK-1:0] ; +reg signed [SMP_DW-1:0] adc_prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW-1:0] adc_prev_smp_0 ; +reg signed [SMP_DW-1:0] adc_2prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW-1:0] adc_2prev_smp_0; +reg signed [SMP_DW:0] ftr_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] ftr_prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] cmp_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] cmp_prev_smp [SMP_CK-1:0]; + +reg [SMP_CK-1:0] cmp_s ; +wire [ 2:0] enc_s, enc_m1; +reg [28:0] time_ck_r, time_ck_2r; +wire [28:0] time_ck_s; +wire [ 2:0] time_adc_s; +wire [ 6:0] time_inter_s; +reg [28:0] trig_time_ck_r; +reg [ 2:0] trig_time_adc_r; +reg [CMP_INTER-1:0] trig_time_inter_r; +wire [CMP_INTER-1:0] thr_inter_smp; +wire x_inter_end; + +// Signed comparison values. +wire signed [SMP_DW:0] cmp_smp_s [SMP_CK-1:0]; +wire signed [SMP_DW:0] cmp_thr_s ; +wire [SMP_CK-1:0] cmp_flg ; +assign cmp_thr_s = {cmp_th_i, 1'b0}; + +// Control State Machine +////////////////////////////////////////////////////////////////////////// +typedef enum { ST_IDLE, ST_ARMED, ST_INTER, ST_INHIBIT } TYPE_TRIG_ST; +(* fsm_encoding = "one_hot" *) TYPE_TRIG_ST trig_cal_st; +TYPE_TRIG_ST trig_calc_st_nxt; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) trig_cal_st <= ST_IDLE; + else trig_cal_st <= trig_calc_st_nxt; +end + +reg inhibit; +always_comb begin + trig_calc_st_nxt = trig_cal_st; + inhibit = 1'b1; + case (trig_cal_st) + ST_IDLE: begin + if (arm_i) trig_calc_st_nxt = ST_ARMED; + end + ST_ARMED: begin + inhibit = 1'b0; + if (!arm_i) trig_calc_st_nxt = ST_IDLE; + else if (trigger_cmp_s) begin + if (|cfg_inter_i ) trig_calc_st_nxt = ST_INTER; + else trig_calc_st_nxt = ST_INHIBIT; + end + end + ST_INTER: begin + if (x_inter_end) trig_calc_st_nxt = ST_INHIBIT; // IF INHIBIT IS SHORTER, TAKES MORE TIME + end + ST_INHIBIT : begin + if (inhibit_end) trig_calc_st_nxt = ST_ARMED; + end + endcase +end + +// Inhibit Counter +////////////////////////////////////////////////////////////////////////// +reg [7:0] inhibit_cnt, inhibit_cnt_p1 ; +assign inhibit_cnt_p1 = inhibit_cnt + 1'b1; + +always_ff @(posedge clk_i) begin + if (!rst_ni) inhibit_cnt <= 0; + else + if (arm_i & inhibit) inhibit_cnt <= inhibit_cnt_p1; + else inhibit_cnt <= 0; +end + +assign inhibit_end = ( inhibit_cnt == cmp_inh_i ) ; + +assign trigger_cmp = !inhibit & trigger_cmp_s ; + + + + + +// Samples Processing +/////////////////////////////////////////////////////////////////////////////// + +// Store las Sample of current, for prev next. +always_ff @(posedge clk_i) begin + if ( !rst_ni ) begin + adc_prev_smp_0 <= 0; + adc_2prev_smp_0 <= 0; + time_ck_r <= 0; + time_ck_2r <= 0; + end else begin + adc_prev_smp_0 <= adc_smp[SMP_CK-1]; + adc_2prev_smp_0 <= adc_smp[SMP_CK-2]; + time_ck_r <= time_ck_i; + time_ck_2r <= time_ck_r; + end +end + + +genvar i; +generate + for (i=0; i cmp_thr_s); + always_ff @(posedge clk_i) cmp_s[i] = cmp_flg[i]; + end +endgenerate + + + +// Time Tag +/////////////////////////////////////////////////////////////////////////////// + +assign enc_zero = ~|enc_s ; +assign enc_m1 = enc_s - 1'b1 ; +assign time_ck_s = (cfg_inter_i & enc_zero) ? time_ck_2r : time_ck_r; +assign time_adc_s = cfg_inter_i ? enc_m1 : enc_s ; +assign time_inter_s = cfg_inter_i ? thr_inter_smp : 0 ; + +always_ff @(posedge clk_i) begin + if ( !rst_ni ) begin + trig_time_ck_r <= 0; + trig_time_adc_r <= 0; + trig_time_inter_r <= 0; + end else begin + if (trigger_cmp) begin + trig_time_ck_r <= time_ck_s; + trig_time_adc_r <= time_adc_s; + end + if (x_inter_end) + trig_time_inter_r <= time_inter_s; + end +end + + + +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// +priority_encoder # ( + .DW ( 3 ) , + .OUT ("TNO_REG") +) ENCODER ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .one_hot_dt_i ( cmp_s ) , + .bin_dt_o ( enc_s ) , + .vld_o ( trigger_cmp_s ) +); + +generate + if (CMP_INTER > 0 ) begin: INTER + x_inter #( + .DW ( SMP_DW ) , + .IW ( CMP_INTER ) + ) INTERPOLATOR ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .start_i ( trigger_cmp ) , + .cfg_inter_i( cfg_inter_i ) , + .thr_i ( cmp_th_i ) , + .curr_i ( ftr_smp[enc_s] ) , + .prev_i ( ftr_prev_smp[enc_s] ) , + .end_o ( x_inter_end ) , + .ready_o ( ) , + .x_int_o ( thr_inter_smp ) ); + end else begin + assign x_inter_end = trigger_cmp; + assign thr_inter_smp = 7'b0; + end +endgenerate + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do = 0; + +// OUT +/////////////////////////////////////////////////////////////////////////////// +wire[6:0] trig_time_inter_s; + +localparam zfp = 6-CMP_INTER; +assign trig_time_inter_s = {{ zfp {1'b0}}, trig_time_inter_r}; + +assign tag_dt_o = ( cfg_inter_i ) == 3'b000 ? { trig_time_ck_r[28:0], trig_time_adc_r } : // No Interpolation + ( cfg_inter_i ) == 3'b001 ? { trig_time_ck_r[27:0], trig_time_adc_r, trig_time_inter_s[0] } : // Interpolation of 1 bit + ( cfg_inter_i ) == 3'b010 ? { trig_time_ck_r[26:0], trig_time_adc_r, trig_time_inter_s[1:0] } : // Interpolation of 2 bit + ( cfg_inter_i ) == 3'b011 ? { trig_time_ck_r[25:0], trig_time_adc_r, trig_time_inter_s[2:0] } : // Interpolation of 3 bit + ( cfg_inter_i ) == 3'b100 ? { trig_time_ck_r[24:0], trig_time_adc_r, trig_time_inter_s[3:0] } : // Interpolation of 4 bit + ( cfg_inter_i ) == 3'b101 ? { trig_time_ck_r[23:0], trig_time_adc_r, trig_time_inter_s[4:0] } : // Interpolation of 5 bit + ( cfg_inter_i ) == 3'b110 ? { trig_time_ck_r[22:0], trig_time_adc_r, trig_time_inter_s[5:0] } : // Interpolation of 6 bit + { trig_time_ck_r[21:0], trig_time_adc_r, trig_time_inter_s[6:0] } ; // Interpolation of 7 bit +assign tag_vld_o = arm_i & x_inter_end; +assign trig_o = trigger_cmp; +assign cmp_o = trigger_cmp_s; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/smp_mem.sv b/firmware/ip/qick_time_tagger/src/smp_mem.sv new file mode 100644 index 000000000..ed1dafe11 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/smp_mem.sv @@ -0,0 +1,349 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module smp_mem # ( + parameter SMP_DW = 16 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter SMP_FIFO_AW = 10 // Size of SAMPLES FIFO Memory +) ( +// Core and AXI CLK & RST + input wire dma_clk_i , + input wire dma_rst_ni , + input wire adc_clk_i , + input wire adc_rst_ni , + input wire qtt_rst_req_i , //flush_i + output wire qtt_rst_ack_o , //flush_o +// Configuration + input wire [4:0] cfg_smp_wr_qty_i , +///// ADC TRIG + input wire tag_wr_i , + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i , +///// DATA DMA + input wire dma_pop_i , + output wire dma_pop_o , + output wire [31:0] dma_dt_o , + output wire [SMP_FIFO_AW-1:0] dma_qty_o , + output wire smp_empty_o , + output wire smp_full_o , +///// STATUS & DEBUG + output wire [7:0] debug_do +); + +////////////////////////////////////////////////////////////////////////// +// SMP STORE +////////////////////////////////////////////////////////////////////////// +wire [SMP_DW-1:0] smp_fifo_dt; + + reg [SMP_CK*SMP_DW-1:0] smp_wr_dt, smp_wr_dt_r, smp_wr_dt_2r, smp_wr_dt_3r ; + reg [4:0] smp_wr_cnt ; + wire[4:0] smp_wr_cnt_p1 ; + // Control State Machine + ////////////////////////////////////////////////////////////////////////// + typedef enum { ST_SMP_IDLE, ST_SMP_WR } TYPE_SMP_WR_ST; + (* fsm_encoding = "one_hot" *) TYPE_SMP_WR_ST smp_wr_st; + TYPE_SMP_WR_ST smp_wr_st_nxt; + + always_ff @ (posedge adc_clk_i, negedge adc_rst_ni) begin + if ( !adc_rst_ni ) smp_wr_st <= ST_SMP_IDLE; + else smp_wr_st <= smp_wr_st_nxt; + end + reg smp_wr; + always_comb begin + smp_wr_st_nxt = smp_wr_st; + smp_wr = 1'b0; + case (smp_wr_st) + ST_SMP_IDLE: begin + if (tag_wr_i) smp_wr_st_nxt = ST_SMP_WR; + end + ST_SMP_WR : begin + smp_wr = 1'b1; + if (smp_wr_end) smp_wr_st_nxt = ST_SMP_IDLE; + end + endcase + end + // Number of Samples to Store + ////////////////////////////////////////////////////////////////////////// + always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) smp_wr_cnt <= 0; + else + if (smp_wr) smp_wr_cnt <= smp_wr_cnt_p1; + else smp_wr_cnt <= 0; + end + assign smp_wr_cnt_p1 = smp_wr_cnt + 1'b1; + assign smp_wr_end = ( smp_wr_cnt_p1 == cfg_smp_wr_qty_i ) ; + + always_ff @(posedge adc_clk_i) begin + if ( !adc_rst_ni) begin + smp_wr_dt <= 0; + smp_wr_dt_r <= 0; + end else begin + smp_wr_dt <= adc_dt_i; + smp_wr_dt_r <= smp_wr_dt; + smp_wr_dt_2r <= smp_wr_dt_r; + smp_wr_dt_3r <= smp_wr_dt_2r; + + end + end + SMP_FIFO_DC # ( + .SMP_CK ( SMP_CK ), // Number of Samples in adc_data (MAX 16) + .SMP_DW ( SMP_DW ), // Sample Data Width + .FIFO_AW ( SMP_FIFO_AW ) // Memory bit address Width + ) SMP_FIFO_DC ( + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .dma_clk_i ( dma_clk_i ), + .dma_rst_ni ( dma_rst_ni ), + .flush_i ( qtt_rst_req_i ), + .flush_o ( qtt_rst_ack_o ), + .adc_push_i ( smp_wr ), + .adc_data_i ( smp_wr_dt_3r ), + .dma_pop_i ( dma_pop_i ), + .dma_pop_o ( dma_pop_o ), + .dma_qty_o ( dma_qty_o ), + .dma_empty_o ( smp_empty_o ), + .dt_o ( smp_fifo_dt ), + .full_o ( smp_full_o ), + .debug_do ( )); + + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do = 0; + + +// OUT +/////////////////////////////////////////////////////////////////////////////// +localparam sfp = 32-SMP_DW; +assign dma_dt_o = {{ sfp {smp_fifo_dt[SMP_DW-1]}}, smp_fifo_dt}; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// + +module SMP_FIFO_DC # ( + parameter SMP_CK = 8 , // Number of Samples in adc_data (MAX 16) + parameter SMP_DW = 16 , // Sample Data Width + parameter FIFO_AW = 10 // Memory bit address Width +) ( + input wire adc_clk_i , + input wire adc_rst_ni , + input wire dma_clk_i , + input wire dma_rst_ni , + input wire flush_i , + output wire flush_o , + input wire adc_push_i , + input wire [SMP_CK*SMP_DW-1:0] adc_data_i , + input wire dma_pop_i , + output wire dma_pop_o , + output wire [FIFO_AW-1:0] dma_qty_o , + output wire dma_empty_o , + output wire [SMP_DW - 1:0] dt_o , + output wire full_o , + output wire [15:0] debug_do + ); + +/////////////////////////////////////////////////////////////////////////////// +// Signal Declaration + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value + +reg [FIFO_AW-1:0] rd_dma_ptr , wr_ptr; +wire [FIFO_AW-1:0] rd_dma_ptr_p1, wr_ptr_p1 ; +reg [FIFO_AW-1:0] dma_qty; +wire [FIFO_AW-1:0] addr_b ; +wire dma_empty, dma_full; +wire [SMP_DW - 1:0] data_s, mem_dt; +wire do_dma_pop; +reg do_dma_pop_r ; +wire [SMP_CK*SMP_DW-1:0] wr_smp_data ; +reg [SMP_CK*SMP_DW-1:0] wr_dt_r ; +wire [SMP_DW-1:0] wr_dt ; +wire [SMP_DW-1:0] wr_dt1, wr_dt2, wr_dt3 ; +wire [3:0] wr_cnt_p1 ; +reg [3:0] wr_cnt ; +reg wr_push; +reg wr_smp_pop, wr_smp_push; + +/////////////////////////////////////////////////////////////////////////////// +// WRITE SAMPLE FIFO +/////////////////////////////////////////////////////////////////////////////// +FIFO_DC # ( + .FIFO_DW ( SMP_CK*SMP_DW ), + .FIFO_AW ( 8 ) +) WR_SMP_FIFO ( + .wr_clk_i ( adc_clk_i ), + .wr_rst_ni ( adc_rst_ni ), + .wr_en_i ( 1'b1 ), + .push_i ( adc_push_i ), + .data_i ( adc_data_i ), + .rd_clk_i ( dma_clk_i ), + .rd_rst_ni ( dma_rst_ni ), + .rd_en_i ( 1'b1 ), + .pop_i ( wr_smp_pop ), + .data_o ( wr_smp_data ), + .flush_i ( flush_i ), + .async_empty_o ( wr_smp_empty), + .async_full_o ( wr_smp_full ) +); + + + +/////////////////////////////////////////////////////////////////////////////// +// WRITE Control state +typedef enum { WR_IDLE, WR_PUSH_DT, WR_POP_DT } TYPE_WR_ST ; +(* fsm_encoding = "sequential" *) TYPE_WR_ST smp_wr_st; +TYPE_WR_ST smp_wr_st_nxt; + +always_ff @ (posedge dma_clk_i) begin + if ( !dma_rst_ni ) smp_wr_st <= WR_IDLE; + else smp_wr_st <= smp_wr_st_nxt; +end + +always_comb begin + smp_wr_st_nxt = smp_wr_st; // Default Current + wr_smp_pop = 1'b0; + wr_smp_push = 1'b0; + case (smp_wr_st) + WR_IDLE : begin + if ( !wr_smp_empty ) + smp_wr_st_nxt = WR_POP_DT; + end + WR_POP_DT : begin + wr_smp_pop = 1'b1; + smp_wr_st_nxt = WR_PUSH_DT; + end + WR_PUSH_DT : begin + wr_smp_push = 1'b1; + if ( wr_last_dt | flush_i ) begin + wr_smp_push = 1'b0; + smp_wr_st_nxt = WR_IDLE; + end + end + endcase +end + +assign wr_cnt_p1 = wr_cnt + 1'b1; +assign wr_last_dt = (wr_cnt_p1 == SMP_CK) ; + + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni ) begin + wr_push <= 1'b0; + wr_dt_r <= 0; + wr_cnt <= 0; + end else begin + // Register DT + if ( wr_smp_pop ) wr_dt_r <= wr_smp_data; + // Increment Counter + if ( wr_push ) wr_cnt <= wr_cnt_p1; + else wr_cnt <= 0; + // Push to OUT FIFO + if ( flush_i ) wr_push <= 1'b0; + else if ( wr_smp_push ) wr_push <= 1'b1; + else wr_push <= 1'b0; + end +end + +assign wr_dt = wr_dt_r[SMP_DW*wr_cnt +: SMP_DW]; + + + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( adc_clk_i ) , + .rst_a_ni ( adc_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( adc_clk_i ) , + .a_rst_ni ( adc_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +/////////////////////////////////////////////////////////////////////////////// +// READ +/////////////////////////////////////////////////////////////////////////////// +assign do_dma_pop = (dma_pop_i & !dma_empty ) | (wr_push & dma_full) ; // POP IF FULL +assign dma_empty = (rd_dma_ptr == wr_ptr) ; +assign dma_full = (rd_dma_ptr == wr_ptr_p1) ; + +// DMA Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) dma_qty <= 0; + else if ( wr_push & !do_dma_pop ) dma_qty <= dma_qty + 1'b1 ; + else if ( !wr_push & do_dma_pop ) dma_qty <= dma_qty - 1'b1 ; +end + + +/////////////////////////////////////////////////////////////////////////////// +// POINTERS +/////////////////////////////////////////////////////////////////////////////// +assign wr_ptr_p1 = wr_ptr + 1'b1 ; +assign rd_dma_ptr_p1 = rd_dma_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + end else begin + if ( wr_push ) wr_ptr <= wr_ptr_p1; + if ( do_dma_pop ) rd_dma_ptr <= rd_dma_ptr_p1; + end +end + +BRAM_SC # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( SMP_DW ) +) SMP_FIFO ( + .clk_i ( dma_clk_i ), + .we_a_i ( wr_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( wr_dt ), + .addr_b_i ( rd_dma_ptr ), + .dt_b_o ( mem_dt )); + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_dma_pop_r <= 0; + end else begin + do_dma_pop_r <= do_dma_pop; + end +end + +assign flush_o = wr_smp_empty & wr_smp_full ; +assign full_o = dma_full; + +assign dma_qty_o = dma_qty; +assign dma_empty_o = dma_empty; // While RESETTING, Shows EMPTY +assign dma_pop_o = do_dma_pop_r; +assign dt_o = mem_dt; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/tag_gen.sv b/firmware/ip/qick_time_tagger/src/tag_gen.sv new file mode 100644 index 000000000..62f72e31d --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/tag_gen.sv @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module tag_gen # ( + parameter ADC_QTY = 1 , // Number of ADC Inputs + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 1 , // Interpolate SAMPLES + parameter SMP_DW = 16 , //Sample Data width + parameter SMP_CK = 8 // Samples per Clock +) ( + input wire clk_i , + input wire rst_ni , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire [2:0] cfg_inter_i , + input wire cfg_slope_i , + input wire [28:0] time_ck_i , + input wire [SMP_DW-1:0] cmp_th_i , + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire en_i , + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i [ADC_QTY], + output wire trig_o , + output wire cmp_o , + output wire [ADC_QTY-1:0] tag_vld_o , + output wire [31:0] tag_dt_o [ADC_QTY] +); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// +wire [ADC_QTY-1:0] trig_s, cmp_s ; + +genvar ind; +generate + for (ind=0; ind Last Empty Value +// READ_POINTER > Last Value + +assign wr_ptr_p1 = wr_ptr + 1'b1 ; +assign rd_ptr_p1 = rd_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_ptr <= 0; + end else begin + if ( do_push ) wr_ptr <= wr_ptr_p1; + if ( do_pop ) rd_ptr <= rd_ptr_p1; + end +end + +assign tag_empty = (rd_ptr == wr_ptr) ; +assign tag_full = (rd_ptr == wr_ptr_p1) ; + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( adc_clk_i ) , + .rst_a_ni ( adc_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( adc_clk_i ) , + .a_rst_ni ( adc_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +// TAG QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) tag_qty <= 0; + else if ( do_push & !do_pop ) tag_qty <= tag_qty + 1'b1 ; + else if ( !do_push & do_pop ) tag_qty <= tag_qty - 1'b1 ; +end + + +BRAM_SC # ( + .MEM_DW ( 32 ) , + .MEM_AW ( FIFO_AW ) +) FIFO_TAG ( + .clk_i ( dma_clk_i ), + .we_a_i ( do_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( data_s ), + .addr_b_i ( rd_ptr ), + .dt_b_o ( mem_dt )); + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do[0] = tag_full ; +assign debug_do[1] = tag_empty; +assign debug_do[2] = push_empty; +assign debug_do[3] = do_push; +assign debug_do[4] = dma_pop_i ; +assign debug_do[5] = do_pop ; +assign debug_do[6] = flush_i; +assign debug_do[7] = flush_o; + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_pop_r <= 0; + end else begin + do_pop_r <= do_pop; + end +end + +assign flush_o = push_empty & push_full ; +assign full_o = tag_full ; +assign empty_o = tag_empty ; + +assign dma_qty_o = tag_qty; +assign dma_pop_o = do_pop_r; +assign dma_dt_o = mem_dt; + +endmodule + +module TAG_FIFO_TC # ( + parameter TAG_DW = 32 , + parameter FIFO_AW = 18 +) ( + input wire tag_clk_i , + input wire tag_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire dma_clk_i , + input wire dma_rst_ni , + input wire flush_i , + output wire flush_o , + input wire tag_push_i , + input wire [TAG_DW - 1:0] tag_data_i , + input wire tag_pop_i , + output wire c_pop_o , + output wire [FIFO_AW-1:0] c_qty_o , + output wire c_empty_o , + input wire dma_pop_i , + output wire dma_pop_o , + output wire [FIFO_AW-1:0] dma_qty_o , + output wire dma_empty_o , + output wire [TAG_DW - 1:0] dt_o , + output wire full_o , + output wire [15:0] debug_do ); + + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value + +wire [FIFO_AW-1:0] wr_ptr_p1 ; +reg [FIFO_AW-1:0] rd_dma_ptr, rd_proc_ptr, wr_ptr; +wire [FIFO_AW-1:0] addr_b ; +wire [TAG_DW-1:0] data_s, mem_dt; +reg [FIFO_AW-1:0] dma_qty, proc_qty; +wire dma_full, proc_full; +wire dma_empty, proc_empty ; +wire do_dma_pop, do_proc_pop; +reg do_dma_pop_r, do_proc_pop_r ; + + +/////////////////////////////////////////////////////////////////////////////// +// WRITE +/////////////////////////////////////////////////////////////////////////////// +reg do_push; + +FIFO_DC # ( + .FIFO_DW ( 32 ), + .FIFO_AW ( 10 ) +) FIFO_PUSH ( + .wr_clk_i ( tag_clk_i ), + .wr_rst_ni ( tag_rst_ni ), + .wr_en_i ( 1'b1 ), + .push_i ( tag_push_i ), + .data_i ( tag_data_i ), + .rd_clk_i ( dma_clk_i ), + .rd_rst_ni ( dma_rst_ni ), + .rd_en_i ( 1'b1 ), + .pop_i ( do_push ), + .data_o ( data_s ), + .flush_i ( flush_i ), + .async_empty_o ( push_empty ), + .async_full_o ( push_full ) +); + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni ) begin + do_push <= 1'b0; + end else begin + if ( flush_i ) do_push <= 1'b0; + else if ( !push_empty & !do_push ) do_push <= 1'b1; + else if ( do_push ) do_push <= 1'b0; + end +end + +/////////////////////////////////////////////////////////////////////////////// +// POINTERS +/////////////////////////////////////////////////////////////////////////////// +assign wr_ptr_p1 = wr_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + rd_proc_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + rd_proc_ptr <= 0; + end else begin + if ( do_push ) wr_ptr <= wr_ptr_p1; + if ( do_proc_pop ) rd_proc_ptr <= rd_proc_ptr + 1'b1 ; + if ( do_dma_pop ) rd_dma_ptr <= rd_dma_ptr + 1'b1 ; + end +end + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( tag_clk_i ) , + .rst_a_ni ( tag_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( tag_clk_i ) , + .a_rst_ni ( tag_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +/////////////////////////////////////////////////////////////////////////////// +// READ (tProc has Priority) +/////////////////////////////////////////////////////////////////////////////// +assign do_dma_pop = (dma_pop_i & !dma_empty & !do_proc_pop) | (do_push & dma_full) ; // POP IF FULL +assign dma_empty = (rd_dma_ptr == wr_ptr) ; +assign dma_full = (rd_dma_ptr == wr_ptr_p1) ; +// DMA Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) dma_qty <= 0; + else if ( do_push & !do_dma_pop ) dma_qty <= dma_qty + 1'b1 ; + else if ( !do_push & do_dma_pop ) dma_qty <= dma_qty - 1'b1 ; +end + +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) sync_p_i ( + .a_clk_i ( tag_clk_i ) , + .a_rst_ni ( tag_rst_ni ) , + .a_pulse_i ( tag_pop_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni) , + .b_pulse_o ( c_pop_s ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); + +assign do_proc_pop = ( c_pop_s & !proc_empty) | (do_push & proc_full); // POP IF FULL +assign proc_empty = ( rd_proc_ptr == wr_ptr) ; +assign proc_full = ( rd_proc_ptr == wr_ptr_p1) ; +// PROC_RD Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) proc_qty <= 0; + else if ( do_push & !do_proc_pop ) proc_qty <= proc_qty + 1'b1 ; + else if ( !do_push & do_proc_pop ) proc_qty <= proc_qty - 1'b1 ; +end + + +assign addr_b = do_proc_pop ? rd_proc_ptr : rd_dma_ptr; + +BRAM_SC # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( TAG_DW ) +) FIFO_TAG ( + .clk_i ( dma_clk_i ), + .we_a_i ( do_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( data_s ), + .addr_b_i ( addr_b ), + .dt_b_o ( mem_dt ) +); + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_proc_pop_r <= 0; + do_dma_pop_r <= 0; + end else begin + do_proc_pop_r <= do_proc_pop; + do_dma_pop_r <= do_dma_pop; + end +end + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do[0] = dma_full ; +assign debug_do[1] = dma_empty; +assign debug_do[2] = proc_full; +assign debug_do[3] = proc_empty; +assign debug_do[4] = do_push; +assign debug_do[5] = dma_pop_i ; +assign debug_do[6] = do_dma_pop ; +assign debug_do[7] = dma_pop_o; +assign debug_do[8] = tag_pop_i; +assign debug_do[9] = do_proc_pop; +assign debug_do[10] = c_pop_o; +assign debug_do[11] = flush_i; +assign debug_do[12] = flush_o; +assign debug_do[13] = full_o; +assign debug_do[15:14] = 0; + + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +assign flush_o = push_empty & push_full ; +assign full_o = proc_full | dma_full; + +assign c_qty_o = proc_qty; +assign c_empty_o = proc_empty ; // While RESETTING, Shows EMPTY +assign c_pop_o = do_proc_pop_r; + +assign dma_qty_o = dma_qty; +assign dma_empty_o = dma_empty; // While RESETTING, Shows EMPTY +assign dma_pop_o = do_dma_pop_r; +assign dt_o = mem_dt; + +endmodule diff --git a/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl b/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl new file mode 100644 index 000000000..c083cb18f --- /dev/null +++ b/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl @@ -0,0 +1,173 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set TAG_FIFO [ipgui::add_group $IPINST -name "TAG FIFO" -parent ${Page_0}] + ipgui::add_param $IPINST -name "TAG_FIFO_AW" -parent ${TAG_FIFO} + + #Adding Group + set Threshold_Comparison [ipgui::add_group $IPINST -name "Threshold Comparison" -parent ${Page_0}] + ipgui::add_param $IPINST -name "CMP_SLOPE" -parent ${Threshold_Comparison} -widget checkBox + ipgui::add_param $IPINST -name "CMP_INTER" -parent ${Threshold_Comparison} + + #Adding Group + set TAG_FIFO_Read_Sources [ipgui::add_group $IPINST -name "TAG FIFO Read Sources" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DMA_RD" -parent ${TAG_FIFO_Read_Sources} -widget checkBox + ipgui::add_param $IPINST -name "PROC_RD" -parent ${TAG_FIFO_Read_Sources} -widget checkBox + + #Adding Group + set Samples_Options [ipgui::add_group $IPINST -name "Samples Options" -parent ${Page_0}] + ipgui::add_param $IPINST -name "SMP_STORE" -parent ${Samples_Options} -widget checkBox + ipgui::add_param $IPINST -name "SMP_FIFO_AW" -parent ${Samples_Options} + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget checkBox + + + +} + +proc update_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to update CMP_INTER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to validate CMP_INTER + return true +} + +proc update_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to update CMP_SLOPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to validate CMP_SLOPE + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.DMA_RD { PARAM_VALUE.DMA_RD } { + # Procedure called to update DMA_RD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_RD { PARAM_VALUE.DMA_RD } { + # Procedure called to validate DMA_RD + return true +} + +proc update_PARAM_VALUE.PROC_RD { PARAM_VALUE.PROC_RD } { + # Procedure called to update PROC_RD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PROC_RD { PARAM_VALUE.PROC_RD } { + # Procedure called to validate PROC_RD + return true +} + +proc update_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to update SMP_CK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to validate SMP_CK + return true +} + +proc update_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to update SMP_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to validate SMP_DW + return true +} + +proc update_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to update SMP_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to validate SMP_FIFO_AW + return true +} + +proc update_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to update SMP_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to validate SMP_STORE + return true +} + +proc update_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to update TAG_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to validate TAG_FIFO_AW + return true +} + + +proc update_MODELPARAM_VALUE.DMA_RD { MODELPARAM_VALUE.DMA_RD PARAM_VALUE.DMA_RD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_RD}] ${MODELPARAM_VALUE.DMA_RD} +} + +proc update_MODELPARAM_VALUE.PROC_RD { MODELPARAM_VALUE.PROC_RD PARAM_VALUE.PROC_RD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PROC_RD}] ${MODELPARAM_VALUE.PROC_RD} +} + +proc update_MODELPARAM_VALUE.CMP_SLOPE { MODELPARAM_VALUE.CMP_SLOPE PARAM_VALUE.CMP_SLOPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_SLOPE}] ${MODELPARAM_VALUE.CMP_SLOPE} +} + +proc update_MODELPARAM_VALUE.CMP_INTER { MODELPARAM_VALUE.CMP_INTER PARAM_VALUE.CMP_INTER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_INTER}] ${MODELPARAM_VALUE.CMP_INTER} +} + +proc update_MODELPARAM_VALUE.TAG_FIFO_AW { MODELPARAM_VALUE.TAG_FIFO_AW PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TAG_FIFO_AW}] ${MODELPARAM_VALUE.TAG_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.SMP_DW { MODELPARAM_VALUE.SMP_DW PARAM_VALUE.SMP_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_DW}] ${MODELPARAM_VALUE.SMP_DW} +} + +proc update_MODELPARAM_VALUE.SMP_CK { MODELPARAM_VALUE.SMP_CK PARAM_VALUE.SMP_CK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_CK}] ${MODELPARAM_VALUE.SMP_CK} +} + +proc update_MODELPARAM_VALUE.SMP_STORE { MODELPARAM_VALUE.SMP_STORE PARAM_VALUE.SMP_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_STORE}] ${MODELPARAM_VALUE.SMP_STORE} +} + +proc update_MODELPARAM_VALUE.SMP_FIFO_AW { MODELPARAM_VALUE.SMP_FIFO_AW PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_FIFO_AW}] ${MODELPARAM_VALUE.SMP_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl b/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl new file mode 100644 index 000000000..1b581eebe --- /dev/null +++ b/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl @@ -0,0 +1,211 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Control [ipgui::add_group $IPINST -name "Control" -parent ${Page_0}] + ipgui::add_static_text $IPINST -name "CtrlText" -parent ${Control} -text {The Time tagger can be controlled from tProcessor and Python} + set EXT_ARM [ipgui::add_param $IPINST -name "EXT_ARM" -parent ${Control} -widget checkBox] + set_property tooltip {External ARM Control} ${EXT_ARM} + + #Adding Group + set TAG_FIFO [ipgui::add_group $IPINST -name "TAG FIFO" -parent ${Page_0} -display_name {ADC Tags}] + ipgui::add_param $IPINST -name "ADC_QTY" -parent ${TAG_FIFO} -widget comboBox + ipgui::add_param $IPINST -name "TAG_FIFO_AW" -parent ${TAG_FIFO} + #Adding Group + set Threshold_Comparison [ipgui::add_group $IPINST -name "Threshold Comparison" -parent ${TAG_FIFO}] + ipgui::add_param $IPINST -name "CMP_SLOPE" -parent ${Threshold_Comparison} -widget checkBox + ipgui::add_param $IPINST -name "CMP_INTER" -parent ${Threshold_Comparison} + + + #Adding Group + set ADC0_Options [ipgui::add_group $IPINST -name "ADC0 Options" -parent ${Page_0}] + #Adding Group + set Samples_Options [ipgui::add_group $IPINST -name "Samples Options" -parent ${ADC0_Options} -display_name {Samples}] + ipgui::add_param $IPINST -name "SMP_STORE" -parent ${Samples_Options} -widget checkBox + ipgui::add_param $IPINST -name "SMP_FIFO_AW" -parent ${Samples_Options} + + #Adding Group + set ARM_Triggers [ipgui::add_group $IPINST -name "ARM Triggers" -parent ${ADC0_Options} -display_name {ARM Info}] + ipgui::add_param $IPINST -name "ARM_STORE" -parent ${ARM_Triggers} -widget checkBox + ipgui::add_param $IPINST -name "ARM_FIFO_AW" -parent ${ARM_Triggers} + + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ADC_QTY { PARAM_VALUE.ADC_QTY } { + # Procedure called to update ADC_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_QTY { PARAM_VALUE.ADC_QTY } { + # Procedure called to validate ADC_QTY + return true +} + +proc update_PARAM_VALUE.ARM_FIFO_AW { PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to update ARM_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARM_FIFO_AW { PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to validate ARM_FIFO_AW + return true +} + +proc update_PARAM_VALUE.ARM_STORE { PARAM_VALUE.ARM_STORE } { + # Procedure called to update ARM_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARM_STORE { PARAM_VALUE.ARM_STORE } { + # Procedure called to validate ARM_STORE + return true +} + +proc update_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to update CMP_INTER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to validate CMP_INTER + return true +} + +proc update_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to update CMP_SLOPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to validate CMP_SLOPE + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.EXT_ARM { PARAM_VALUE.EXT_ARM } { + # Procedure called to update EXT_ARM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_ARM { PARAM_VALUE.EXT_ARM } { + # Procedure called to validate EXT_ARM + return true +} + +proc update_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to update SMP_CK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to validate SMP_CK + return true +} + +proc update_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to update SMP_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to validate SMP_DW + return true +} + +proc update_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to update SMP_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to validate SMP_FIFO_AW + return true +} + +proc update_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to update SMP_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to validate SMP_STORE + return true +} + +proc update_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to update TAG_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to validate TAG_FIFO_AW + return true +} + + +proc update_MODELPARAM_VALUE.CMP_SLOPE { MODELPARAM_VALUE.CMP_SLOPE PARAM_VALUE.CMP_SLOPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_SLOPE}] ${MODELPARAM_VALUE.CMP_SLOPE} +} + +proc update_MODELPARAM_VALUE.CMP_INTER { MODELPARAM_VALUE.CMP_INTER PARAM_VALUE.CMP_INTER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_INTER}] ${MODELPARAM_VALUE.CMP_INTER} +} + +proc update_MODELPARAM_VALUE.TAG_FIFO_AW { MODELPARAM_VALUE.TAG_FIFO_AW PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TAG_FIFO_AW}] ${MODELPARAM_VALUE.TAG_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.SMP_DW { MODELPARAM_VALUE.SMP_DW PARAM_VALUE.SMP_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_DW}] ${MODELPARAM_VALUE.SMP_DW} +} + +proc update_MODELPARAM_VALUE.SMP_CK { MODELPARAM_VALUE.SMP_CK PARAM_VALUE.SMP_CK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_CK}] ${MODELPARAM_VALUE.SMP_CK} +} + +proc update_MODELPARAM_VALUE.SMP_STORE { MODELPARAM_VALUE.SMP_STORE PARAM_VALUE.SMP_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_STORE}] ${MODELPARAM_VALUE.SMP_STORE} +} + +proc update_MODELPARAM_VALUE.SMP_FIFO_AW { MODELPARAM_VALUE.SMP_FIFO_AW PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_FIFO_AW}] ${MODELPARAM_VALUE.SMP_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.ADC_QTY { MODELPARAM_VALUE.ADC_QTY PARAM_VALUE.ADC_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_QTY}] ${MODELPARAM_VALUE.ADC_QTY} +} + +proc update_MODELPARAM_VALUE.ARM_STORE { MODELPARAM_VALUE.ARM_STORE PARAM_VALUE.ARM_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARM_STORE}] ${MODELPARAM_VALUE.ARM_STORE} +} + +proc update_MODELPARAM_VALUE.ARM_FIFO_AW { MODELPARAM_VALUE.ARM_FIFO_AW PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARM_FIFO_AW}] ${MODELPARAM_VALUE.ARM_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.EXT_ARM { MODELPARAM_VALUE.EXT_ARM PARAM_VALUE.EXT_ARM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_ARM}] ${MODELPARAM_VALUE.EXT_ARM} +} + diff --git a/firmware/ip/qick_vec2bit/component.xml b/firmware/ip/qick_vec2bit/component.xml new file mode 100644 index 000000000..96ae1c4c3 --- /dev/null +++ b/firmware/ip/qick_vec2bit/component.xml @@ -0,0 +1,502 @@ + + + QICK + QICK + qick_vec2bit + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + qick_vec2bit + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2255dc03 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + + + viewChecksum + ab23a7c5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f7ada015 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 5fe144f7 + + + + + + + din + + in + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout0 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout1 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout2 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout3 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout4 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout5 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout6 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout7 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout8 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout9 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout10 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout11 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout12 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout13 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout14 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout15 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + IN_DW + In Dw + 16 + + + OUT_QTY + Out Qty + 4 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/qick_vec2bit.v + verilogSource + CHECKSUM_2255dc03 + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/qick_vec2bit_v1_0.tcl + tclSource + CHECKSUM_f7ada015 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + ../../common_ip_files/ip_logos/logoQICK_128x128.png + LOGO + + + + qick_vec2bit + + + IN_DW + In Dw + 16 + + + OUT_QTY + Out Qty + 4 + + + Component_Name + qick_vect2bits_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /QICK/Miscellaneous + + qick_vec2bit + package_project + Quantum Instrumentation Control Kit + https://github.com/openquantumhardware/qick/ + 5 + 2023-06-12T16:47:20Z + + + 2022.1 + + + + + + + diff --git a/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl b/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl new file mode 100644 index 000000000..ccf952fb7 --- /dev/null +++ b/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_OUT_QTY_ENABLEMENT {IN_DW } {expr $IN_DW > 1} diff --git a/firmware/ip/qick_vec2bit/src/qick_vec2bit.v b/firmware/ip/qick_vec2bit/src/qick_vec2bit.v new file mode 100644 index 000000000..20488f817 --- /dev/null +++ b/firmware/ip/qick_vec2bit/src/qick_vec2bit.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +module qick_vec2bit # ( + parameter IN_DW = 16 , + parameter OUT_QTY = 4 +)( + input wire [IN_DW-1:0] din, + output wire dout0 , + output wire dout1 , + output wire dout2 , + output wire dout3 , + output wire dout4 , + output wire dout5 , + output wire dout6 , + output wire dout7 , + output wire dout8 , + output wire dout9 , + output wire dout10 , + output wire dout11 , + output wire dout12 , + output wire dout13 , + output wire dout14 , + output wire dout15 ); + +// OUTPUTS +///////////////////////////////////////////////// + + assign dout0 = din[0]; + assign dout1 = din[1]; + assign dout2 = din[2]; + assign dout3 = din[3]; + assign dout4 = din[4]; + assign dout5 = din[5]; + assign dout6 = din[6]; + assign dout7 = din[7]; + assign dout8 = din[8]; + assign dout9 = din[9]; + assign dout10 = din[10]; + assign dout11 = din[11]; + assign dout12 = din[12]; + assign dout13 = din[13]; + assign dout14 = din[14]; + assign dout15 = din[15]; + +endmodule diff --git a/firmware/ip/qick_vec2bit/src/qick_vect2bits.v b/firmware/ip/qick_vec2bit/src/qick_vect2bits.v new file mode 100644 index 000000000..abc542ef1 --- /dev/null +++ b/firmware/ip/qick_vec2bit/src/qick_vect2bits.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +module qick_vect2bits # ( + parameter IN_DW = 16 , + parameter OUT_QTY = 4 +)( + input wire [IN_DW-1:0] din, + output wire dout0 , + output wire dout1 , + output wire dout2 , + output wire dout3 , + output wire dout4 , + output wire dout5 , + output wire dout6 , + output wire dout7 , + output wire dout8 , + output wire dout9 , + output wire dout10 , + output wire dout11 , + output wire dout12 , + output wire dout13 , + output wire dout14 , + output wire dout15 ); + +// OUTPUTS +///////////////////////////////////////////////// + + assign dout0 = din[0]; + assign dout1 = din[1]; + assign dout2 = din[2]; + assign dout3 = din[3]; + assign dout4 = din[4]; + assign dout5 = din[5]; + assign dout6 = din[6]; + assign dout7 = din[7]; + assign dout8 = din[8]; + assign dout9 = din[9]; + assign dout10 = din[10]; + assign dout11 = din[11]; + assign dout12 = din[12]; + assign dout13 = din[13]; + assign dout14 = din[14]; + assign dout15 = din[15]; + +endmodule diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl new file mode 100644 index 000000000..291a44ecc --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IN_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_QTY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl new file mode 100644 index 000000000..e6fa1df67 --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl @@ -0,0 +1,38 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "IN_DW" + set OUT_QTY [ipgui::add_param $IPINST -name "OUT_QTY"] + set_property tooltip {Number of 1bit Outputs} ${OUT_QTY} + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl new file mode 100644 index 000000000..291a44ecc --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IN_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_QTY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/notebooks/qick_rb/RB_tProc_v1_experiment.ipynb b/firmware/notebooks/qick_rb/RB_tProc_v1_experiment.ipynb new file mode 100644 index 000000000..fd67c079e --- /dev/null +++ b/firmware/notebooks/qick_rb/RB_tProc_v1_experiment.ipynb @@ -0,0 +1,638 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "e369c3a6", + "metadata": {}, + "source": [ + "# Randomized Benchmarking experiment for tProc_v1\n", + "\n", + "This notebook runs the experiment used in the QICK paper for randomized benchmarking (devForLBNL/RB_code_demo/qsystem2_paper_data-Ankur-final.ipynb) ported to run on the current tProc_v1 firmware (original code ran on something called qsystem, previous version of tProc_v1) It was created to measure the runtime of the algorithm and compare it with the implementation on the tProc_v2 firmware." + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "id": "f2d666f1", + "metadata": {}, + "outputs": [ + { + "data": { + "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "data": { + "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "QICK running on ZCU111, software version 0.2.370\n", + "\n", + "Firmware configuration (built Wed Aug 16 13:39:03 2023):\n", + "\n", + "\tGlobal clocks (MHz): tProc dispatcher timing 384.000, RF reference 204.800\n", + "\tGroups of related clocks: [tProc clock, DAC tile 0], [DAC tile 1], [ADC tile 0]\n", + "\n", + "\t7 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 0, blk 0 is DAC228_T0_CH0, or RF board DAC port 0\n", + "\t1:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 0, blk 1 is DAC228_T0_CH1, or RF board DAC port 1\n", + "\t2:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 0, blk 2 is DAC228_T0_CH2, or RF board DAC port 2\n", + "\t3:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 1, blk 0 is DAC229_T1_CH0, or RF board DAC port 4\n", + "\t4:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 1, blk 1 is DAC229_T1_CH1, or RF board DAC port 5\n", + "\t5:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 1, blk 2 is DAC229_T1_CH2, or RF board DAC port 6\n", + "\t6:\taxis_signal_gen_v6 - fs=6144.000 Msps, fabric=384.000 MHz\n", + "\t\tenvelope memory: 65536 complex samples (10.667 us)\n", + "\t\t32-bit DDS, range=6144.000 MHz\n", + "\t\tDAC tile 1, blk 3 is DAC229_T1_CH3, or RF board DAC port 7\n", + "\n", + "\t2 readout channels:\n", + "\t0:\taxis_readout_v2 - configured by PYNQ\n", + "\t\tfs=4096.000 Msps, decimated=512.000 MHz, 32-bit DDS, range=4096.000 MHz\n", + "\t\taxis_avg_buffer v1.0 (no edge counter, no weights)\n", + "\t\tmemory 16384 accumulated, 1024 decimated (2.000 us)\n", + "\t\ttriggered by output 0, pin 14, feedback to tProc input 0\n", + "\t\tADC tile 0, blk 0 is ADC224_T0_CH0, or RF board ADC AC port 0\n", + "\t1:\taxis_readout_v2 - configured by PYNQ\n", + "\t\tfs=4096.000 Msps, decimated=512.000 MHz, 32-bit DDS, range=4096.000 MHz\n", + "\t\taxis_avg_buffer v1.0 (no edge counter, no weights)\n", + "\t\tmemory 16384 accumulated, 1024 decimated (2.000 us)\n", + "\t\ttriggered by output 0, pin 15, feedback to tProc input 1\n", + "\t\tADC tile 0, blk 2 is ADC224_T0_CH1, or RF board ADC AC port 1\n", + "\n", + "\t8 digital output pins:\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: axis_tproc64x32_x8 (\"v1\") rev 4, program memory 8192 words, data memory 4096 words\n", + "\t\texternal start pin: PMOD1_0_LS\n", + "\n", + "\tDDR4 memory buffer: 1073741824 samples (2.097 sec), 256 samples/transfer\n", + "\t\twired to readouts [0, 1]\n", + "\n", + "\tMR buffer: 8192 samples (2.000 us), wired to readouts [0, 1]\n" + ] + } + ], + "source": [ + "%matplotlib inline\n", + "\n", + "import numpy as np\n", + "import matplotlib.pyplot as plt\n", + "import pandas as pd\n", + "from scipy.optimize import curve_fit\n", + "from datetime import datetime\n", + "\n", + "# Import the QICK drivers and auxiliary libraries\n", + "from qick import *\n", + "\n", + "# Load bitstream with custom overlay\n", + "soc = QickSoc()\n", + "soccfg = soc\n", + "print(soccfg)\n" + ] + }, + { + "cell_type": "markdown", + "id": "7a1dc341", + "metadata": {}, + "source": [ + "## RB sequence generator" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "id": "a8e30449", + "metadata": {}, + "outputs": [], + "source": [ + "\"\"\"Writing the sequences in terms of Clifford group algebra\n", + " The Clifford gate set forms a closed group => \n", + " 1. Multiplication of any two gates results in a gate part of the group \n", + " 2. Each gate has an inverse\n", + " 3. The inverse of a product of multiple Clifford gates is unique\n", + "\"\"\"\n", + "def generate_rbsequence(depth):\n", + " \n", + " \"\"\"Single qubit RB program to generate a sequence of 'd' gates followed \n", + " by an inverse gate to bring the qubit back in 'g' state\n", + " \"\"\"\n", + "\n", + " gate_symbol = ['I', 'Z', 'X', 'Y', 'Z/2', 'X/2', 'Y/2', '-Z/2', '-X/2', '-Y/2']\n", + " inverse_gate_symbol = ['I', '-Y/2', 'X/2', 'X', 'Y/2', '-X/2']\n", + "\n", + " \"\"\"Modeled the bloch sphere as 6-node graph, each rotation in the RB sequence is effectively\n", + " exchanging the node label on the bloch sphere.\n", + " For example: Z rotation is doing this: (+Z->+Z, -Z->-Z, +X->+Y, +Y->-X, -X->-Y, -Y->+X)\n", + " \"\"\"\n", + " matrix_ref = {}\n", + " \"\"\"Matrix columns are [Z, X, Y, -Z, -X, -Y]\"\"\"\n", + "\n", + " matrix_ref['0'] = np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 0, 0, 1]])\n", + " matrix_ref['1'] = np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0]])\n", + " matrix_ref['2'] = np.matrix([[0, 0, 0, 1, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 1, 0, 0, 0]])\n", + " matrix_ref['3'] = np.matrix([[0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]])\n", + " matrix_ref['4'] = np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0]])\n", + " matrix_ref['5'] = np.matrix([[0, 0, 1, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0]])\n", + " matrix_ref['6'] = np.matrix([[0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]])\n", + " matrix_ref['7'] = np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0]])\n", + " matrix_ref['8'] = np.matrix([[0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 1, 0, 0]])\n", + " matrix_ref['9'] = np.matrix([[0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]])\n", + " \n", + " \"\"\"Generate a random gate sequence of a certain depth 'd'\"\"\"\n", + " gate_seq = []\n", + " for ii in range(depth):\n", + " gate_seq.append(np.random.randint(0, 9))\n", + " \"\"\"Initial node\"\"\"\n", + " a0 = np.matrix([[1], [0], [0], [0], [0], [0]])\n", + " anow = a0\n", + " for i in gate_seq:\n", + " anow = np.dot(matrix_ref[str(i)], anow)\n", + " anow1 = np.matrix.tolist(anow.T)[0]\n", + " \"\"\"Returns the \"\"\"\n", + " max_index = anow1.index(max(anow1))\n", + " symbol_seq = [gate_symbol[i] for i in gate_seq ]\n", + " symbol_seq.append(inverse_gate_symbol[max_index])\n", + " return symbol_seq" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "id": "cc9aee50", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "['Z/2', 'Y', '-Z/2', 'X']" + ] + }, + "execution_count": 3, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "generate_rbsequence(3)" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "id": "39bf0f0f", + "metadata": {}, + "outputs": [], + "source": [ + "class RBSequenceProgram(AveragerProgram):\n", + " def __init__(self,soccfg, cfg):\n", + " super().__init__(soccfg, cfg)\n", + "\n", + " def initialize(self):\n", + " cfg = self.cfg\n", + "\n", + " self.gate_seq = cfg['gate_seq']\n", + " self.gate_set = cfg['gate_set']\n", + "\n", + "# r_freq=self.sreg(cfg[\"rr_ch\"], \"freq\") #Get frequency register for res_ch\n", + "# f_res=freq2reg(adcfreq(cfg[\"rr_freq\"])) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", + "\n", + "# # rr_freq = self.sreg(self.device_cfg[\"rr_ch\"], self.device_cfg[\"rr_freq\"]) #Get frequency register for res_ch\n", + "# self.cfg[\"adc_lengths\"]=[self.cfg[\"rr_length\"]]*2 #add length of adc acquisition to config\n", + "# self.cfg[\"adc_freqs\"]=[adcfreq(self.cfg[\"rr_freq\"])]*2 #add frequency of adc ddc to config\n", + "# self.f_ge=freq2reg(cfg[\"qubit_freq\"])\n", + "\n", + " pulse_length = self.us2cycles(0.025)\n", + "\n", + " ro_chs = cfg['ro_chs']\n", + " gen_ch = cfg['qubit_ch']\n", + "\n", + " # configure the readout lengths and downconversion frequencies\n", + " for ro_ch in ro_chs:\n", + " self.declare_readout(ch=ro_ch, \n", + " length=self.us2cycles(cfg['rr_length']),\n", + " freq=self.cfg['rr_freq'],\n", + " gen_ch=cfg['rr_ch'])\n", + "\n", + " self.declare_gen(ch=cfg[\"rr_ch\"], nqz=1) #Readout\n", + "\n", + " \"\"\"Add a sequence of fixed number of gates, analytically compute\n", + " the inverse operation after the final gate to bring the qubit back\n", + " to |g> state (minimizes errors due to readout) before reading out the state.\n", + " Repeat this experiment several times with the fixed number of gates.\n", + " \"\"\"\n", + "# self.add_pulse(ch=self.cfg[\"qubit_ch\"], name=\"qubit\", style=\"arb\", idata=gauss(mu=cfg[\"pi_sigma\"]*16*5/2,si=cfg[\"pi_sigma\"]*16, length=5*cfg[\"pi_sigma\"]*16, maxv=32000))\n", + "\n", + " \n", + " \"\"\"This adds the different types of pulses to the pulse library which can be played on demand later\"\"\"\n", + " for name, ginfo in self.gate_set.items():\n", + " self.add_pulse(ch=self.cfg[\"qubit_ch\"], name=name, \n", + " idata=ginfo[\"idata\"],\n", + " qdata=ginfo[\"qdata\"],\n", + " # style=ginfo[\"style\"]\n", + " )\n", + "\n", + "\n", + " # self.add_pulse(ch=self.cfg[\"rr_ch\"], name=\"measure\",\n", + " # # style=\"const\", \n", + " # length=self.cfg[\"rr_length\"]\n", + " # ) #add a constant pulse to the pulse library of res_ch\n", + "\n", + " # \"\"\"Pre-initialze the pulse (not necessary)\"\"\"\n", + " # self.pulse(ch=self.cfg[\"rr_ch\"], name=\"measure\", freq=f_res, \n", + " # phase=self.cfg[\"rr_phase\"], gain=self.cfg[\"rr_gain\"],\n", + " # length=self.cfg['rr_length'] , t=0, play=False) # pre-configure readout pulse\n", + "\n", + " idata = 30000*np.ones(16*cfg[\"rr_length\"])\n", + " self.add_pulse(ch=cfg['rr_ch'], name=\"measure\", idata=idata)\n", + "\n", + " self.set_pulse_registers(ch=cfg[\"rr_ch\"], \n", + " style=\"const\", \n", + " freq=cfg[\"rr_freq\"], \n", + " phase=0, \n", + " gain=cfg[\"rr_gain\"],\n", + " length=cfg[\"rr_length\"])\n", + "\n", + "\n", + " self.sync_all(1000) # give processor some time to configure pulses\n", + " \n", + " def body(self):\n", + " self.phase_ref=0\n", + " for g in self.gate_seq:\n", + " ginfo=self.cfg[\"gate_set\"][g]\n", + " \"\"\"For the Z gates (virtual rotation), we need to advance the phase of all the pulses which follows afterwards\"\"\"\n", + " if g==\"Z\":\n", + " self.phase_ref+=180\n", + " elif g==\"Z/2\":\n", + " self.phase_ref+=90\n", + " elif g==\"-Z/2\":\n", + " self.phase_ref+=-90\n", + " else:\n", + " # self.pulse(ch=self.cfg[\"qubit_ch\"], name=g, phase=deg2reg(self.phase_ref+ginfo[\"phase\"]), gain=ginfo[\"gain\"], play=True)\n", + " pass\n", + " self.setup_and_pulse(ch=self.cfg[\"qubit_ch\"], \n", + " waveform=g, \n", + " phase=self.deg2reg(self.phase_ref+ginfo[\"phase\"]), \n", + " gain=ginfo[\"gain\"], \n", + " style=ginfo[\"style\"],\n", + " freq=self.cfg[\"qubit_freq\"],\n", + " )\n", + "\n", + " self.sync_all(self.us2cycles(0.01)) # align channels and wait 10ns\n", + " # self.trigger_adc(adc1=1, adc2=1, adc_trig_offset=self.cfg[\"adc_trig_offset\"]) # trigger the adc acquisition\n", + " self.trigger(adcs=self.cfg['ro_chs'],\n", + " pins=[0], \n", + " adc_trig_offset=self.cfg[\"adc_trig_offset\"])\n", + " # self.pulse(ch=self.cfg[\"rr_ch\"], length = self.cfg[\"rr_length\"], play=True) # play readout pulse\n", + " self.pulse(ch=self.cfg['rr_ch'], t=0) # play readout pulse\n", + " self.sync_all(self.us2cycles(self.cfg[\"relax_delay\"])) # sync all channels" + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "id": "3da4c2fa", + "metadata": {}, + "outputs": [], + "source": [ + "from qick.helpers import gauss\n", + "\n", + "pi_sigma = 10 # us2cycles(0.025) -> tProc @384MHz -> 10 cycles\n", + "pi_gain = 1\n", + "pi_2_gain = 1\n", + "nu_q_new = 100\n", + "f_res = 100\n", + "rot_angle = 0\n", + "\n", + "qubit_params = {'pi_sigma': pi_sigma, 'pi_gain': pi_gain, 'pi_2_gain': pi_2_gain}\n", + "\n", + "RO_CH = [0,1]\n", + "\n", + "rb_config = {\n", + " \"ro_chs\" : RO_CH, # --Fixed\n", + " 'qubit_freq' : nu_q_new, 'qubit_ch' : 3, \n", + " 'rr_freq' : f_res, 'rr_ch' : 6, \n", + " 'rr_length' : 3, \n", + " 'rr_gain' : 10000,\n", + " 'rr_phase' : rot_angle, \n", + " \"adc_trig_offset\" : 250, 'beta' : 0,\n", + " # 'relax_delay' : 500,\n", + " 'relax_delay' : 1,\n", + " 'reps' : 1000, 'rounds' : 0,\n", + " 'gate_seq' : generate_rbsequence(3), \n", + " 'gate_set' : {\n", + " \"I\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " \n", + " },\n", + " \"X\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":qubit_params['pi_gain'], \"style\":\"arb\",\n", + " },\n", + " \"Y\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"phase\":-90, \"gain\":qubit_params['pi_gain'], \"style\":\"arb\",\n", + " },\n", + " \"Z\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " },\n", + " \"X/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " },\n", + " \"-X/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":180, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " },\n", + "\n", + " \"Y/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":-90, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " },\n", + " \"-Y/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":90, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " },\n", + " \"Z/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " },\n", + " \"-Z/2\": {\n", + " \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000),\n", + " \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,\n", + " length=4*pi_sigma*16,maxv=32000), \n", + " \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " },\n", + "\n", + " } \n", + " }\n", + "\n", + "# \"\"\"Testing if it runs\"\"\"\n", + "# # config['gate_seq'] = generate_rbsequence(10)\n", + "# rb_config['gate_seq'] = ['Y', 'X/2']\n", + "# # rb_config['gate_seq'] = ['Y', 'X/2', 'X/2']\n", + "# rb_config['gate_seq'] = ['X', 'Y/2']\n", + "\n", + "\n", + "# print(rb_config['gate_seq'])\n", + "# rb_config['reps'] = 5000\n", + "# rb=RBSequenceProgram(soccfg, cfg=rb_config)\n", + "# results = rb.acquire(soc, load_pulses=True, progress=True)\n", + "# np.mean(results[3])" + ] + }, + { + "cell_type": "markdown", + "id": "c3ae8bf0", + "metadata": {}, + "source": [ + "## Experiment" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "id": "80e8b05f", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "- Experiment Start Time: 1761678244290016903 ns\n", + " - Depth array 1 - time: 1761678244293387583 ns, elapsed: 3370680 ns\n", + " - Sequence run time: (0): 2091 ms (1): 2051 ms (2): 2051 ms (3): 2051 ms (4): 2051 ms (5): 2050 ms (6): 2050 ms (7): 2053 ms (8): 2054 ms (9): 2050 ms (10): 2051 ms (11): 2050 ms (12): 2052 ms (13): 2050 ms (14): 2052 ms (15): 2050 ms (16): 2051 ms (17): 2051 ms (18): 2051 ms (19): 2051 ms (20): 2051 ms (21): 2050 ms (22): 2052 ms (23): 2051 ms (24): 2051 ms (25): 2050 ms (26): 2052 ms (27): 2051 ms (28): 2051 ms (29): 2050 ms (30): 2051 ms (31): 2050 ms (32): 2055 ms (33): 2051 ms (34): 2051 ms (35): 2050 ms (36): 2051 ms (37): 2050 ms (38): 2054 ms (39): 2052 ms \n", + " - Sequence Total time: 82668 ms (Run time: 82109 ms - Overhead time: 559 ms)\n", + " - Depth array 16 - time: 1761678326961805924 ns, elapsed: 82671789021 ns\n", + " - Sequence run time: (0): 2062 ms (1): 2061 ms (2): 2062 ms (3): 2067 ms (4): 2063 ms (5): 2069 ms (6): 2063 ms (7): 2061 ms (8): 2067 ms (9): 2062 ms (10): 2061 ms (11): 2061 ms (12): 2061 ms (13): 2061 ms (14): 2062 ms (15): 2061 ms (16): 2061 ms (17): 2061 ms (18): 2061 ms (19): 2061 ms (20): 2068 ms (21): 2061 ms (22): 2062 ms (23): 2062 ms (24): 2062 ms (25): 2061 ms (26): 2062 ms (27): 2061 ms (28): 2061 ms (29): 2063 ms (30): 2061 ms (31): 2061 ms (32): 2069 ms (33): 2062 ms (34): 2061 ms (35): 2061 ms (36): 2061 ms (37): 2061 ms (38): 2062 ms (39): 2061 ms \n", + " - Sequence Total time: 83443 ms (Run time: 82512 ms - Overhead time: 930 ms)\n", + " - Depth array 64 - time: 1761678410405049753 ns, elapsed: 166115032850 ns\n", + " - Sequence run time: (0): 2082 ms (1): 2081 ms (2): 2090 ms (3): 2083 ms (4): 2082 ms (5): 2082 ms (6): 2082 ms (7): 2081 ms (8): 2082 ms (9): 2081 ms (10): 2095 ms (11): 2082 ms (12): 2082 ms (13): 2082 ms (14): 2082 ms (15): 2082 ms (16): 2081 ms (17): 2081 ms (18): 2081 ms (19): 2082 ms (20): 2082 ms (21): 2082 ms (22): 2082 ms (23): 2082 ms (24): 2081 ms (25): 2082 ms (26): 2081 ms (27): 2097 ms (28): 2082 ms (29): 2082 ms (30): 2082 ms (31): 2082 ms (32): 2082 ms (33): 2081 ms (34): 2082 ms (35): 2082 ms (36): 2081 ms (37): 2082 ms (38): 2082 ms (39): 2083 ms \n", + " - Sequence Total time: 85603 ms (Run time: 83322 ms - Overhead time: 2280 ms)\n", + " - Depth array 128 - time: 1761678496008335304 ns, elapsed: 251718318401 ns\n", + " - Sequence run time: (0): 2108 ms (1): 2108 ms (2): 2108 ms (3): 2108 ms (4): 2108 ms (5): 2108 ms (6): 2108 ms (7): 2109 ms (8): 2109 ms (9): 2109 ms (10): 2108 ms (11): 2121 ms (12): 2108 ms (13): 2108 ms (14): 2108 ms (15): 2108 ms (16): 2109 ms (17): 2108 ms (18): 2109 ms (19): 2108 ms (20): 2121 ms (21): 2108 ms (22): 2108 ms (23): 2108 ms (24): 2109 ms (25): 2109 ms (26): 2109 ms (27): 2109 ms (28): 2109 ms (29): 2122 ms (30): 2109 ms (31): 2108 ms (32): 2108 ms (33): 2108 ms (34): 2108 ms (35): 2108 ms (36): 2108 ms (37): 2108 ms (38): 2122 ms (39): 2109 ms \n", + " - Sequence Total time: 88518 ms (Run time: 84407 ms - Overhead time: 4111 ms)\n", + " - Depth array 512 - time: 1761678584526531991 ns, elapsed: 340236515088 ns\n", + " - Sequence run time: (0): 2280 ms (1): 2269 ms (2): 2270 ms (3): 2270 ms (4): 2270 ms (5): 2270 ms (6): 2270 ms (7): 2270 ms (8): 2270 ms (9): 2270 ms (10): 2270 ms (11): 2270 ms (12): 2269 ms (13): 2270 ms (14): 2269 ms (15): 2270 ms (16): 2269 ms (17): 2270 ms (18): 2270 ms (19): 2270 ms (20): 2270 ms (21): 2269 ms (22): 2270 ms (23): 2270 ms (24): 2270 ms (25): 2270 ms (26): 2270 ms (27): 2270 ms (28): 2269 ms (29): 2270 ms (30): 2270 ms (31): 2270 ms (32): 2270 ms (33): 2269 ms (34): 2269 ms (35): 2269 ms (36): 2269 ms (37): 2270 ms (38): 2270 ms (39): 2270 ms \n", + " - Sequence Total time: 107704 ms (Run time: 90816 ms - Overhead time: 16887 ms)\n", + " - Depth array 768 - time: 1761678692230818292 ns, elapsed: 447940801389 ns\n", + " - Sequence run time: (0): 2378 ms (1): 2378 ms (2): 2378 ms (3): 2377 ms (4): 2377 ms (5): 2378 ms (6): 2377 ms (7): 2377 ms (8): 2377 ms (9): 2377 ms (10): 3050 ms (11): 2379 ms (12): 2383 ms (13): 2378 ms (14): 2382 ms (15): 2377 ms (16): 2382 ms (17): 2377 ms (18): 2382 ms (19): 2377 ms (20): 2382 ms (21): 2377 ms (22): 2378 ms (23): 2378 ms (24): 2378 ms (25): 2377 ms (26): 2378 ms (27): 2378 ms (28): 2378 ms (29): 2377 ms (30): 2377 ms (31): 2377 ms (32): 2377 ms (33): 2378 ms (34): 2378 ms (35): 2377 ms (36): 2378 ms (37): 2378 ms (38): 2377 ms (39): 2377 ms \n", + " - Sequence Total time: 119178 ms (Run time: 95816 ms - Overhead time: 23362 ms)\n", + " - Depth array 1024 - time: 1761678811409119857 ns, elapsed: 567119102954 ns\n", + " - Sequence run time: (0): 2485 ms (1): 2485 ms (2): 2485 ms (3): 2486 ms (4): 2485 ms (5): 2484 ms (6): 2485 ms (7): 2485 ms (8): 2485 ms (9): 2485 ms (10): 2485 ms (11): 2485 ms (12): 2486 ms (13): 2485 ms (14): 2485 ms (15): 2485 ms (16): 2485 ms (17): 2485 ms (18): 2485 ms (19): 2485 ms (20): 2486 ms (21): 2491 ms (22): 2490 ms (23): 2490 ms (24): 2490 ms (25): 2489 ms (26): 2489 ms (27): 2489 ms (28): 2490 ms (29): 2486 ms (30): 2485 ms (31): 2485 ms (32): 2485 ms (33): 2485 ms (34): 2485 ms (35): 2485 ms (36): 2485 ms (37): 2484 ms (38): 2486 ms (39): 2485 ms \n", + " - Sequence Total time: 131964 ms (Run time: 99462 ms - Overhead time: 32502 ms)\n", + "- End Time: 1761678943374441906 - elapsed: 699084425003\n" + ] + } + ], + "source": [ + "# from datetime import datetime\n", + "import time\n", + "\n", + "I2 = []\n", + "I2_err = []\n", + "\n", + "# Original settings\n", + "depth_array = [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48, 64, 80, 96, 128, 192, \n", + " 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216, 1280, 1344, 1408,\n", + " 1472, 1536, 1600, 1664, 1728, 1750]\n", + "rb_config['reps'] = 4000\n", + "rb_config['rounds'] = 0\n", + "variety = 40\n", + "\n", + "# # Test settings 1\n", + "# rb_config['reps'] = 4000\n", + "# depth_array = [1, 16, 128, 1024]\n", + "# variety = 2\n", + "\n", + "# # Test settings 2\n", + "# rb_config['relax_delay'] = 100\n", + "# rb_config['reps'] = 4000\n", + "# depth_array = [1, 16, 64, 128, 512, 768, 1024]\n", + "# variety = 3\n", + "\n", + "# # Test settings 3\n", + "# rb_config['relax_delay'] = 500 # us\n", + "# depth_array = [1, 1024]\n", + "# rb_config['reps'] = 4000\n", + "# variety = 5\n", + "\n", + "# Test settings 4\n", + "rb_config['relax_delay'] = 500 # us\n", + "depth_array = [1, 16, 64, 128, 512, 768, 1024]\n", + "reps = 4000\n", + "variety = 40\n", + "\n", + "exp_start_time_ns = time.time_ns()\n", + "print('- Experiment Start Time: %0d ns' % (exp_start_time_ns))\n", + "\n", + "th = -30\n", + "\n", + "# Loop for different lengths\n", + "for d in depth_array:\n", + " sequence_time_ns = time.time_ns()\n", + " print(' - Depth array %0d - time: %0d ns, elapsed: %0d ns' % (d,sequence_time_ns,(sequence_time_ns-exp_start_time_ns)) )\n", + " i2_temp = []\n", + " run_time_total_ns = 0\n", + " # Loop for different random sequences\n", + " print(' - Sequence run time: ', end=\" \")\n", + " for jj in range(variety):\n", + " rb_config['gate_seq'] = generate_rbsequence(d)\n", + " # print(rb_config['gate_seq'])\n", + " rb = RBSequenceProgram(soccfg, cfg=rb_config)\n", + " # avgi0, avgq0, avgi1, avgq1 = rb.acquire(soc, load_pulses=True, progress=False, debug=False, single_shot=True)\n", + " run_time_start_ns = time.time_ns()\n", + " adc1, adc2 = rb.acquire(soc, progress=False)\n", + " run_time_end_ns = time.time_ns()\n", + " run_time_total_ns += (run_time_end_ns-run_time_start_ns)\n", + " print(' (%0d): %0d ms' % (jj, (run_time_end_ns-run_time_start_ns)/1e6), end=\" \")\n", + " avgi0 = adc1[0]\n", + " avgq0 = adc1[1]\n", + " avgi1 = adc2[0]\n", + " avgq1 = adc2[1]\n", + " df = pd.DataFrame(avgi1, columns=['data'])\n", + " g = df['data'].apply(lambda x: 0 if x < th else 1).mean()\n", + " i2_temp.append(g) \n", + " print('')\n", + " I2.append(np.mean(i2_temp))\n", + " I2_err.append(np.std(i2_temp)/np.sqrt(variety))\n", + " seq_end_time_ns = time.time_ns()\n", + " print(' - Sequence Total time: %0d ms (Run time: %0d ms - Overhead time: %0d ms)' % ((seq_end_time_ns - sequence_time_ns)/1e6, run_time_total_ns/1e6, (seq_end_time_ns - sequence_time_ns)/1e6 - run_time_total_ns/1e6))\n", + "\n", + "exp_end_time_ns = int(time.time_ns())\n", + "print('- End Time: %0d - elapsed: %0d' % (exp_end_time_ns, (exp_end_time_ns-exp_start_time_ns)))\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "5f90c068", + "metadata": {}, + "outputs": [], + "source": [ + "print(rb)" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/firmware/notebooks/qick_rb/RB_tProc_v2_experiment.ipynb b/firmware/notebooks/qick_rb/RB_tProc_v2_experiment.ipynb new file mode 100644 index 000000000..732d6463d --- /dev/null +++ b/firmware/notebooks/qick_rb/RB_tProc_v2_experiment.ipynb @@ -0,0 +1,1724 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "32982695-822e-40aa-ac5c-9777a4d94fb2", + "metadata": {}, + "source": [ + "## setup" + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "id": "3b5c048a", + "metadata": {}, + "outputs": [], + "source": [ + "# jupyter setup boilerplate\n", + "%matplotlib inline\n", + "import matplotlib.pyplot as plt\n", + "import numpy as np\n", + "\n", + "from qick import *\n", + "\n", + "# for now, all the tProc v2 classes need to be individually imported (can't use qick.*)\n", + "\n", + "# the main program class\n", + "from qick.asm_v2 import AveragerProgramV2\n", + "# for defining sweeps\n", + "from qick.asm_v2 import QickSpan, QickSweep1D" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "id": "ab849bc3", + "metadata": {}, + "outputs": [ + { + "data": { + "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "data": { + "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" + }, + "metadata": {}, + "output_type": "display_data" + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "QICK running on ZCU216, software version 0.2.371\n", + "\n", + "Firmware configuration (built Tue Oct 21 16:43:27 2025):\n", + "\n", + "\tGlobal clocks (MHz): tProc dispatcher timing 430.080, RF reference 245.760\n", + "\tGroups of related clocks: [tProc timing clock, DAC tile 1, DAC tile 2, DAC tile 3], [DAC tile 0], [ADC tile 2]\n", + "\n", + "\t1 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 65536 complex samples (6.838 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 0 is 0_228 on JHC1, or QICK box DAC port 0\n", + "\n", + "\t1 readout channels:\n", + "\t0:\taxis_dyn_readout_v1 - configured by tProc output 4\n", + "\t\tfs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 4096 decimated (13.333 us)\n", + "\t\ttriggered by tport 10, pin 0, feedback to tProc input 0\n", + "\t\tADC tile 2, blk 0 is 0_226 on JHC7, or QICK box ADC port 4\n", + "\n", + "\t8 digital output pins:\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: qick_processor (\"v2\") rev 27, core execution clock 200.000 MHz\n", + "\t\tmemories (words): program 16384, data 16384, waveform 1024\n", + "\t\texternal start pin: None\n", + "\t\texternal stop pin: None\n", + "\n", + "\tDDR4 memory buffer: 1073741824 samples (3.495 sec), 128 samples/transfer\n", + "\t\twired to readouts [0]\n", + "\n", + "\tMR buffer: 8192 samples (3.333 us), wired to readouts [0]\n" + ] + } + ], + "source": [ + "# soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/2025-06-15_216_tprocv2r24_standard/qick_216.bit')\n", + "# soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250828_2/qick_216.bit')\n", + "# soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250829_2/qick_216.bit')\n", + "soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_251021_1/qick_216.bit')\n", + "\n", + "# soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_111_standard_250801_1/qick_111.bit')\n", + "# soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_111_standard_1ch_251020_1/qick_111.bit')\n", + "\n", + "soccfg = soc\n", + "print(soccfg)" + ] + }, + { + "cell_type": "markdown", + "id": "bb1f8b6c-563f-48b5-a864-4e9adac68a7d", + "metadata": {}, + "source": [ + "## Randomized Benchmarking\n", + "RB sequence generator: based on https://github.com/openquantumhardware/devForLBNL/blob/master/RB_code_demo/20220201-3DTransmon-Chacracterization%2BRB.ipynb\n" + ] + }, + { + "cell_type": "code", + "execution_count": 21, + "id": "d6a246e2", + "metadata": {}, + "outputs": [], + "source": [ + "import random, time\n", + "from qick.asm_v2 import AcquireProgramV2, AveragerProgramV2, AsmV2, AsmInst\n", + "from qick.tprocv2_assembler import LFSR\n", + "\n", + "class RBSequenceProgram(AveragerProgramV2):\n", + "\n", + " def _initialize(self, cfg):\n", + "\n", + " t=time.time_ns(); dbg_i=0\n", + "\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + "\n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " self.add_reg(name='lfsr_seed')\n", + " self.add_reg(name='seq_length')\n", + "\n", + "\n", + " self.gates_set = cfg['gates_set']\n", + "\n", + " if cfg['pulse_len_us']:\n", + " self.gauss_len = cfg['pulse_len_us']\n", + " else:\n", + " # If None generate minimum length gaussian pulses\n", + " self.gauss_len = self.cycles2us(3, gen_ch=gen_ch)\n", + " # self.gauss_len = self.cycles2us(100, gen_ch=gen_ch)\n", + " self.add_gauss(ch=gen_ch, name=\"gauss_env\", sigma=self.gauss_len/10, length=self.gauss_len, even_length=False)\n", + " \n", + " \"\"\"This adds the different types of pulses to the pulse library which can be played on demand later\"\"\"\n", + " gates_print = \"\"\n", + " for gate_idx, gate in enumerate(self.gates_set):\n", + " gates_print += \"%0d: %s ; \"%(gate_idx, gate['gate_symbol'])\n", + " # print(\"%0d: %s\"%(gate_idx, gate['gate_symbol']))\n", + " ginfo = gate['gate_pulse']\n", + " self.add_pulse(ch=gen_ch, name=gate['gate_symbol'],\n", + " style = ginfo[\"style\"],\n", + " envelope = ginfo[\"envelope\"],\n", + " freq = ginfo[\"freq\"],\n", + " phase = ginfo[\"phase\"],\n", + " gain = ginfo[\"gain\"],\n", + " )\n", + " if cfg['verbose']:\n", + " print(gates_print)\n", + "\n", + " # Pulse for Readout\n", + " self.add_pulse(ch=gen_ch, name=\"ro_pulse\", ro_ch=ro_ch, \n", + " style = \"const\", \n", + " freq = cfg['freq'], \n", + " # length = 1.0, \n", + " length = 0.1, \n", + " phase = 0,\n", + " gain = 0.2,\n", + " )\n", + "\n", + " # For debug, pulse to signal end of sequence\n", + " self.add_pulse(ch=gen_ch, name=\"end_seq_pulse\", ro_ch=ro_ch, \n", + " style = \"const\", \n", + " freq = cfg['freq'], \n", + " length = 0.1, \n", + " phase = 0,\n", + " gain = 0.2,\n", + " )\n", + "\n", + " # Subroutine to generate random sequence using tProc LFSR\n", + " sub_gen_rnd_seq = AsmV2()\n", + " if sub_gen_rnd_seq and cfg['use_lfsr']:\n", + " # Initialize Seed of LFSR (write s1/s_rand with seed literal)\n", + " sub_gen_rnd_seq.write_reg(dst='s_rand', src='lfsr_seed')\n", + " # Initialize virtual-Z gate phase accumulator (r10)\n", + " sub_gen_rnd_seq.write_reg(dst='r10', src=0)\n", + "\n", + " # Get Random Gate index\n", + " sub_gen_rnd_seq.label('gen_seq_loop')\n", + "\n", + " sub_gen_rnd_seq.cond_jump(label='gen_seq_end', arg1='seq_length', test='Z', op='-', arg2=0)\n", + "\n", + " # Read LFSR (read s1/s_rand) and trunc to 4 lsbs\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r4', 'SRC':'op', 'OP': 's1 AND #h0F'}, addr_inc=1))\n", + " ## Check if index is within Set Range (r4 - arg2(set_size) < 0)\n", + " sub_gen_rnd_seq.cond_jump(label='gen_seq_loop', arg1='r4', test='NS', op='-', arg2=10) # arg2: size of gates set\n", + "\n", + " # Check if Z gate\n", + " sub_gen_rnd_seq.label('gen_seq_checkZ')\n", + " sub_gen_rnd_seq.cond_jump(label='gen_seq_checkZov2', arg1='r4', test='NZ', op='-', arg2=1) # arg2: index of Z in the gates set\n", + " ## Increment Z-phase accumulator r10\n", + " sub_gen_rnd_seq.inc_reg(dst='r10', src='r9')\n", + " sub_gen_rnd_seq.inc_reg(dst='r10', src='r9')\n", + " sub_gen_rnd_seq.jump(label='gen_seq_pulse')\n", + "\n", + " # Check if Z/2 gate\n", + " sub_gen_rnd_seq.label('gen_seq_checkZov2')\n", + " sub_gen_rnd_seq.cond_jump(label='gen_seq_check-Zov2', arg1='r4', test='NZ', op='-', arg2=4) # arg2: index of Z/2 in the gates set\n", + " ## Increment Z-phase accumulator r10\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r10', 'SRC':'op', 'OP': 'r10 + r9'}, addr_inc=1))\n", + " sub_gen_rnd_seq.jump(label='gen_seq_pulse')\n", + "\n", + " # Check if -Z/2 gate\n", + " sub_gen_rnd_seq.label('gen_seq_check-Zov2')\n", + " sub_gen_rnd_seq.cond_jump(label='gen_seq_pulse', arg1='r4', test='NZ', op='-', arg2=7) # arg2: index of -Z/2 in the gates set\n", + " ## Increment Z-phase accumulator r10\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r10', 'SRC':'op', 'OP': 'r10 - r9'}, addr_inc=1))\n", + "\n", + " # Send pulse to Wave Dispatcher\n", + " sub_gen_rnd_seq.label('gen_seq_pulse')\n", + " ## Write r_wave with corresponding waveform from wmem address\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r_wave', 'SRC':'wmem', 'ADDR':'r4'}, addr_inc=1))\n", + " ## Update r_wave phase w1 with Z-phase accumulator\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'w1', 'SRC':'op', 'OP': 'w1 + r10'}, addr_inc=1))\n", + " ## Write r_wave to WPORT\n", + " sub_gen_rnd_seq.append_macro(AsmInst(inst={'CMD':\"WPORT_WR\", 'DST': str(cfg['gen_ch']), 'SRC':'r_wave'}, addr_inc=1))\n", + "\n", + " # Repeat L times\n", + " sub_gen_rnd_seq.label('gen_seq_next_gate')\n", + " sub_gen_rnd_seq.inc_reg(dst='seq_length', src=-1)\n", + " # sub_gen_rnd_seq.cond_jump(label='gen_seq_loop', arg1='seq_length', test='NZ', op='-', arg2=0)\n", + " sub_gen_rnd_seq.jump(label='gen_seq_loop')\n", + "\n", + " sub_gen_rnd_seq.label('gen_seq_end')\n", + "\n", + " # End of subroutine\n", + " self.add_subroutine(\"gen_rnd_seq\", sub_gen_rnd_seq)\n", + "\n", + " # Configure Readout\n", + " self.add_readoutconfig(ch=ro_ch, name=\"measure\", freq=cfg['freq'], gen_ch=gen_ch)\n", + "\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=cfg['ro_ch'], name=\"measure\", t=0.0)\n", + "\n", + " t=time.time_ns(); \n", + " # print(' // DBG RB initialize(): %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + "\n", + " def _body(self, cfg):\n", + " t=time.time_ns(); dbg_i=0\n", + " # print(' // DBG RB body() start: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " ## N_G: number of different gates sequences: e.g.: 5\n", + " N_G = cfg['N_G']\n", + " ## N_L: number of length of the sequences - e.g.: 3\n", + " N_L = cfg['N_L']\n", + " ## l: length of sequences - e.g.: [10, 100, 1000]\n", + " L = cfg['L']\n", + " ## N_E: number of times the same sequence is applied\n", + " N_E = cfg['N_E']\n", + "\n", + " # Initialize total iterations counter (for debug)\n", + " self.write_reg(dst='r8', src=0)\n", + " # Convert 90deg to phase representation value in r9\n", + " self.write_reg(dst='r9', src=self.deg2reg(deg=90, gen_ch=self.cfg[\"gen_ch\"]))\n", + "\n", + " # Wait for 1us from reference_time\n", + " self.delay(1.0)\n", + "\n", + " # Pause tProc until absolute time matches reference time (mainly to align stages in simulation)\n", + " self.wait(0.0)\n", + "\n", + " # Iterate over different sequences\n", + " for n_g in range(0, N_G):\n", + " \n", + " # Iterate over different lengths\n", + " for n_l in range(0, N_L):\n", + " dbg_i=0\n", + " # Generate a random sequence of length l\n", + " if cfg['lfsr_seed']:\n", + " seed = cfg['lfsr_seed']\n", + " else:\n", + " seed = np.random.randint(123456789,987654321)\n", + " # print('Sequence Seed: %0d' % (seed))\n", + "\n", + " t=time.time_ns(); \n", + " if cfg['test_seq']:\n", + " depth = len(cfg['test_seq'])\n", + " self.gate_seq = cfg['test_seq']\n", + " else:\n", + " depth = L[n_l]\n", + " self.gate_seq = self.generate_rbsequence(depth=depth, gates_set=self.gates_set, use_lfsr=cfg['use_lfsr'], lfsr_seed=seed)\n", + " # print(' // DBG generate_rbsequence: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + "\n", + " self.seq_load_time = len(self.gate_seq) * 40 * 0.005\n", + " self.seq_play_time = len(self.gate_seq) * self.gauss_len\n", + "\n", + " # for n_e in range(0, N_E):\n", + " for n_e in range(0, 1):\n", + " # self.open_loop(n=N_E, name='N_E_loop_%0d'%(n_g*N_L+n_l))\n", + " # if (True): # just to indent\n", + "\n", + " if cfg['verbose']:\n", + " print(self.gate_seq) # for debug\n", + " print('Sequence Load Time: %0.3f us'%(self.seq_load_time))\n", + " print('Sequence Play Time: %0.3f us'%(self.seq_play_time))\n", + "\n", + " if cfg['use_lfsr']:\n", + " # Delay start of play sequence\n", + " ## Increase reference_time in delay time (delay should be the estimated time in takes to write the full sequence in the dispatcher)\n", + " self.delay(self.seq_load_time, tag='pre_seq_delay_%0d%0d%0d'%(n_g,n_l,n_e))\n", + " # self.delay(self.seq_load_time, tag='pre_seq_delay_%0d%0d%0d'%(n_g,n_l,0))\n", + "\n", + " if not cfg['use_lfsr']:\n", + " self.phase_ref = 0\n", + " self.write_reg(dst='r10', src=0)\n", + " for gate_symbol in self.gate_seq:\n", + " \"\"\"For the Z gates (virtual rotation), we need to advance the phase of all the pulses which follows afterwards\"\"\"\n", + " if gate_symbol == \"Z\":\n", + " self.phase_ref += 180\n", + " self.inc_reg(dst='r10', src=self.deg2reg(deg=180, gen_ch=self.cfg[\"gen_ch\"]))\n", + " # self.call(\"virt_z\")\n", + " elif gate_symbol == \"Z/2\":\n", + " self.phase_ref += 90\n", + " self.inc_reg(dst='r10', src=self.deg2reg(deg=90, gen_ch=self.cfg[\"gen_ch\"]))\n", + " # self.call(\"virt_z_ov_2\")\n", + " elif gate_symbol == \"-Z/2\":\n", + " self.phase_ref += -90\n", + " self.inc_reg(dst='r10', src=self.deg2reg(deg=-90, gen_ch=self.cfg[\"gen_ch\"]))\n", + " # self.call(\"virt_z_ov_2\")\n", + " else:\n", + " # self.pulse(ch=self.cfg[\"qubit_ch\"], name=gate, phase=deg2reg(self.phase_ref+ginfo[\"phase\"]), gain=ginfo[\"gain\"], play=True)\n", + " # self.pulse(ch=self.cfg[\"gen_ch\"], name=gate, phase=ginfo[\"phase\"]+self.phase_ref, gain=ginfo[\"gain\"])\n", + " # self.pulse(ch=self.cfg[\"gen_ch\"], name=gate, t='auto')\n", + " pass\n", + " # # Execute always even if Z gate to see the same number of pulses as gates\n", + " # self.pulse(ch=self.cfg[\"gen_ch\"], name=gate, t='auto')\n", + " gate_idx = next((idx for idx, gate in enumerate(self.gates_set) if gate['gate_symbol'] == gate_symbol), -1)\n", + " self.write_reg(dst='r4', src=gate_idx)\n", + " ## Write r_wave with corresponding waveform from wmem address\n", + " self.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r_wave', 'SRC':'wmem', 'ADDR':'r4'}, addr_inc=1))\n", + " ## Update r_wave phase w1 with Z-phase accumulator\n", + " self.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'w1', 'SRC':'op', 'OP': 'w1 + r10'}, addr_inc=1))\n", + " ## Write r_wave to WPORT\n", + " self.append_macro(AsmInst(inst={'CMD':\"WPORT_WR\", 'DST': str(cfg['gen_ch']), 'SRC':'r_wave'}, addr_inc=1))\n", + "\n", + " # print(' // DBG RB gate_seq code NO_LFSR: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " else:\n", + " # Initialize tProc LFSR, Configure LFSR seed in lfsr_seed\n", + " self.write_reg(dst='lfsr_seed', src=seed)\n", + " # Configure Random Sequence Length in seq_length\n", + " self.write_reg(dst='seq_length', src=depth-1)\n", + " # Generate Random Sequence - will generate the same sequence as python generate_rbsequence()\n", + " self.call(\"gen_rnd_seq\")\n", + " # Add last gate (taken from the python generated sequence)\n", + " last_gate_idx = next((idx for idx, gate in enumerate(self.gates_set) if gate['gate_symbol'] == self.gate_seq[-1]), -1)\n", + " # gate = self.gate_seq[-1]\n", + " # self.pulse(ch=self.cfg[\"gen_ch\"], name=gate, t=0.0)\n", + " self.write_reg(dst='r4', src=last_gate_idx)\n", + " ## Write r_wave with corresponding waveform from wmem address\n", + " self.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'r_wave', 'SRC':'wmem', 'ADDR':'r4'}, addr_inc=1))\n", + " ## Update r_wave phase w1 with Z-phase accumulator\n", + " self.append_macro(AsmInst(inst={'CMD':\"REG_WR\", 'DST': 'w1', 'SRC':'op', 'OP': 'w1 + r10'}, addr_inc=1))\n", + " ## Write r_wave to WPORT\n", + " self.append_macro(AsmInst(inst={'CMD':\"WPORT_WR\", 'DST': str(cfg['gen_ch']), 'SRC':'r_wave'}, addr_inc=1))\n", + "\n", + " # print(' // DBG RB gate_seq code LFSR: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + "\n", + " if cfg['acquire_mode'] == 'DEC':\n", + " # Generate readout pulse\n", + " # self.send_readoutconfig(ch=cfg['ro_ch'], name=\"measure\", t=0.0)\n", + "\n", + " # Send Readout Pulse\n", + " self.pulse(ch=cfg[\"gen_ch\"], name='ro_pulse', t=0.0)\n", + "\n", + " # Trigger to capture the full sequence before being played\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + "\n", + " # Delay until the sequence is applied (will be proportional to sequence length)\n", + " self.delay(self.seq_play_time, tag='post_seq_delay_%0d%0d%0d'%(n_g,n_l,n_e))\n", + " # self.delay(self.seq_play_time, tag='post_seq_delay_%0d%0d%0d'%(n_g,n_l,0))\n", + "\n", + " if cfg['acquire_mode'] == 'AVG':\n", + " # Generate readout pulse\n", + " # self.send_readoutconfig(ch=cfg['ro_ch'], name=\"measure\", t=0.0)\n", + "\n", + " # Send Readout Pulse\n", + " self.pulse(ch=cfg[\"gen_ch\"], name='ro_pulse', t=0.0)\n", + "\n", + " # Trigger after the sequence has been played\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=0.0, ddr4=False)\n", + "\n", + " # # Add End of Sequence pulse (for debug)\n", + " # self.pulse(ch=cfg[\"gen_ch\"], name='end_seq_pulse', t=0.0)\n", + "\n", + " # Delay some more time to ensure capture has finished\n", + " self.delay(1.0)\n", + "\n", + " # Pause tProc until absolute time matches reference time (mainly to align stages in simulation)\n", + " self.wait(0.0)\n", + "\n", + " # Increment total iterations counter (for debug)\n", + " self.inc_reg(dst='r8', src=1)\n", + "\n", + " # self.close_loop()\n", + "\n", + " # print(' // DBG RB N_E Loop: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " def generate_rbsequence(self, depth, gates_set, use_lfsr=False, lfsr_seed=0):\n", + " \"\"\"Single qubit RB program to generate a sequence of 'd' gates followed \n", + " by an inverse gate to bring the qubit back in 'g' state\n", + " \"\"\"\n", + "\n", + " \"\"\"Writing the sequences in terms of Clifford group algebra\n", + " The Clifford gate set forms a closed group => \n", + " 1. Multiplication of any two gates results in a gate part of the group \n", + " 2. Each gate has an inverse\n", + " 3. The inverse of a product of multiple Clifford gates is unique\n", + " \"\"\"\n", + " # gate_symbol = ['I', 'Z', 'X', 'Y', 'Z/2', 'X/2', 'Y/2', '-Z/2', '-X/2', '-Y/2']\n", + " inverse_gate_symbol = ['I', '-Y/2', 'X/2', 'X', 'Y/2', '-X/2']\n", + "\n", + " # Generate a random gate sequence of a certain depth 'd'\n", + " gates_symbols = [g['gate_symbol'] for g in gates_set]\n", + " gates_set_size = len(gates_set)\n", + " gate_seq_idx = []\n", + " gate_seq = []\n", + " if not use_lfsr:\n", + " gate_seq_idx = np.random.randint(0,gates_set_size,depth-1)\n", + " else:\n", + " lfsr_gen = LFSR()\n", + " lfsr_gen.seed(lfsr_seed)\n", + " idx = lfsr_seed & 0x0F\n", + " for ii in range(depth-1):\n", + " while (idx > gates_set_size-1):\n", + " idx = lfsr_gen.nxt() & 0x0F\n", + " # lfsr_gen.print(debug=True)\n", + " gate_seq_idx.append(idx)\n", + " idx = gates_set_size\n", + " # print(gate_seq_idx)\n", + " # Map indexes to gates symbol\n", + " gate_seq = [gates_set[i]['gate_symbol'] for i in gate_seq_idx]\n", + "\n", + " # Initial node\n", + " a0 = np.matrix([[1], [0], [0], [0], [0], [0]])\n", + " # print('State Initial: ',a0.T)\n", + " anow = a0\n", + " for ii, gate_symbol in enumerate(gate_seq):\n", + " anow = np.dot(gates_set[gates_symbols.index(gate_symbol)]['gate_matrix'], anow)\n", + " # print('State',ii+1,':',anow.T)\n", + "\n", + " # Get the recover gate\n", + " gate_inverse = inverse_gate_symbol[list(anow).index(max(anow))]\n", + " gate_seq.append(gate_inverse)\n", + "\n", + " # Calculate final state for check\n", + " anow = np.dot(gates_set[gates_symbols.index(gate_inverse)]['gate_matrix'], anow)\n", + " # print('State Final:',anow.T)\n", + "\n", + " return gate_seq\n", + "\n" + ] + }, + { + "cell_type": "code", + "execution_count": 22, + "id": "a8b9a691", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "0: I ; 1: Z ; 2: X ; 3: Y ; 4: Z/2 ; 5: X/2 ; 6: Y/2 ; 7: -Z/2 ; 8: -X/2 ; 9: -Y/2 ; \n", + "['X/2', '-X/2']\n", + "Sequence Load Time: 0.400 us\n", + "Sequence Play Time: 0.200 us\n", + "['X/2', 'X/2', '-Z/2', '-Y/2', '-Y/2']\n", + "Sequence Load Time: 1.000 us\n", + "Sequence Play Time: 0.500 us\n", + "['X/2', '-X/2']\n", + "Sequence Load Time: 0.400 us\n", + "Sequence Play Time: 0.200 us\n", + "['X/2', 'X/2', '-Z/2', '-Y/2', '-Y/2']\n", + "Sequence Load Time: 1.000 us\n", + "Sequence Play Time: 0.500 us\n" + ] + }, + { + "data": { + "application/vnd.jupyter.widget-view+json": { + "model_id": "a4b53aea6d7b4601821f95c4216036c8", + "version_major": 2, + "version_minor": 0 + }, + "text/plain": [ + " 0%| | 0/1 [00:00" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "SIM = True\n", + "TRIG_TIME = 0.2\n", + "FREQ = 500\n", + "RO_LEN = 2.0\n", + "USE_LFSR = True\n", + "LFSR_SEED = 123456789\n", + "# LFSR_SEED = None # use None to randomize the seed from python\n", + "ACQUIRE_MODE = 'AVG' # AVG, DEC\n", + "# ACQUIRE_MODE = 'DEC' # AVG, DEC\n", + "\n", + "if SIM:\n", + " GEN_CH = 0 # DAC228_T0_CH0\n", + " RO_CH = 0 # ADC224_T0_CH0\n", + "else:\n", + " GEN_CH = 7 # DAC229_T1_CH3\n", + " RO_CH = 1 # ADC224_T0_CH1\n", + "\n", + "qubit_params = {'pi_gain': 1.0, 'pi_2_gain': 0.5, 'freq': FREQ, 'z_gain': 0.2}\n", + "\n", + "# Define the Gates Set\n", + "\"\"\"Modeled the bloch sphere as 6-node graph, each rotation in the RB sequence is effectively\n", + "exchanging the node label on the bloch sphere.\n", + "For example: Z rotation is doing this: (+Z->+Z, -Z->-Z, +X->+Y, +Y->-X, -X->-Y, -Y->+X)\n", + "\"\"\"\n", + "\"\"\"Matrix columns are [Z, X, Y, -Z, -X, -Y]\"\"\"\n", + "GATES_SET = []\n", + "GATES_SET.append({ 'gate_symbol': 'I',\n", + " 'gate_matrix': np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 0, 0, 1]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": 0.1, \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'Z',\n", + " 'gate_matrix': np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": qubit_params['z_gain'],\n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'X',\n", + " 'gate_matrix': np.matrix([[0, 0, 0, 1, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 1, 0, 0, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":0, \"gain\":qubit_params['pi_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": qubit_params['pi_gain'], \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'Y',\n", + " 'gate_matrix': np.matrix([[0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"phase\":-90, \"gain\":qubit_params['pi_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": -90, \n", + " \"gain\": qubit_params['pi_gain'], \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'Z/2',\n", + " 'gate_matrix': np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": qubit_params['z_gain'],\n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'X/2',\n", + " 'gate_matrix': np.matrix([[0, 0, 1, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":0, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": qubit_params['pi_2_gain'], \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': 'Y/2',\n", + " 'gate_matrix': np.matrix([[0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":-90, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": -90, \n", + " \"gain\": qubit_params['pi_2_gain'], \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': '-Z/2',\n", + " 'gate_matrix': np.matrix([[1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":0, \"gain\":0, \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 0, \n", + " \"gain\": qubit_params['z_gain'],\n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': '-X/2',\n", + " 'gate_matrix': np.matrix([[0, 0, 0, 0, 0, 1],\n", + " [0, 1, 0, 0, 0, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [0, 0, 0, 1, 0, 0]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000),\n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":180, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 180, \n", + " \"gain\": qubit_params['pi_2_gain'], \n", + " }\n", + "})\n", + "GATES_SET.append({ 'gate_symbol': '-Y/2',\n", + " 'gate_matrix': np.matrix([[0, 1, 0, 0, 0, 0],\n", + " [0, 0, 0, 1, 0, 0],\n", + " [0, 0, 1, 0, 0, 0],\n", + " [0, 0, 0, 0, 1, 0],\n", + " [1, 0, 0, 0, 0, 0],\n", + " [0, 0, 0, 0, 0, 1]]\n", + " ),\n", + " 'gate_pulse': {\n", + " # \"idata\": gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"qdata\": 0*gauss(mu=pi_sigma*16*4/2,si=pi_sigma*16,length=4*pi_sigma*16,maxv=32000), \n", + " # \"phase\":90, \"gain\":qubit_params['pi_2_gain'], \"style\":\"arb\",\n", + " \"style\": \"arb\",\n", + " \"envelope\": \"gauss_env\",\n", + " \"freq\": qubit_params['freq'],\n", + " \"phase\": 90, \n", + " \"gain\": qubit_params['pi_2_gain'], \n", + " }\n", + "})\n", + "\n", + "\n", + "# Configure tProc LFSR to step on s1/s_rand read\n", + "soc.tproc.set_lfsr_cfg(2)\n", + "\n", + "rb_config = {\n", + " 'gen_ch' : GEN_CH,\n", + " 'ro_ch' : RO_CH,\n", + " 'ro_len' : RO_LEN,\n", + " 'freq' : FREQ,\n", + " 'trig_time' : TRIG_TIME,\n", + " 'acquire_mode' : ACQUIRE_MODE,\n", + " 'relax_delay' : 1,\n", + " # 'rounds' : 1,\n", + " 'gates_set' : GATES_SET,\n", + " 'pulse_len_us' : 0.01,\n", + " 'test_seq' : None,\n", + " 'use_lfsr' : USE_LFSR,\n", + " 'lfsr_seed' : LFSR_SEED,\n", + " 'N_G' : 1,\n", + " 'N_L' : 3,\n", + " 'L' : np.array([1, 3, 5]).dot(1),\n", + " 'N_E' : 1\n", + " }\n", + "\n", + "\n", + "# # Experiment Settings\n", + "# rb_config['L'] = [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48, 64, 80, 96, 128, 192, \n", + "# 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216, 1280, 1344, 1408,\n", + "# 1472, 1536, 1600, 1664, 1728, 1750]\n", + "# rb_config['N_L'] = len(rb_config['L'])\n", + "# rb_config['N_G'] = 40\n", + "# rb_config['N_E'] = 4000\n", + "\n", + "# # Test settings 1a - Averaged Acquire - NO LSFR\n", + "# rb_config['acquire_mode'] = 'AVG'\n", + "# rb_config['use_lfsr'] = False\n", + "# rb_config['L'] = [1, 16, 64, 128, 512, 768, 1024]\n", + "# # rb_config['L'] = [1, 16, 64]\n", + "# rb_config['L'] = [768, 16, 1]\n", + "# # rb_config['L'] = [2, 3]\n", + "# rb_config['N_L'] = len(rb_config['L'])\n", + "# rb_config['N_G'] = 1 # a.k.a: rounds\n", + "# rb_config['N_E'] = 1 # a.k.a: reps\n", + "# rb_config['verbose'] = True\n", + "\n", + "# # Test settings 1b - Averaged Acquire - LSFR\n", + "# rb_config['acquire_mode'] = 'AVG'\n", + "# rb_config['use_lfsr'] = True\n", + "# rb_config['L'] = [1, 16, 64, 128, 512, 768, 1024]\n", + "# # rb_config['L'] = [1, 16, 64]\n", + "# rb_config['L'] = [768, 16, 1]\n", + "# # rb_config['L'] = [2, 3]\n", + "# rb_config['N_L'] = len(rb_config['L'])\n", + "# rb_config['N_G'] = 1 # a.k.a: rounds\n", + "# rb_config['N_E'] = 1 # a.k.a: reps\n", + "# rb_config['verbose'] = True\n", + "\n", + "# Test settings 2a - Decimation Acquire - NO LFSR\n", + "rb_config['acquire_mode'] = 'DEC'\n", + "rb_config['ro_len'] = 1.0\n", + "rb_config['pulse_len_us'] = 0.1\n", + "rb_config['use_lfsr'] = False\n", + "rb_config['L'] = [2, 5]\n", + "rb_config['N_L'] = len(rb_config['L'])\n", + "rb_config['N_G'] = 2 # a.k.a: rounds\n", + "rb_config['N_E'] = 1 # a.k.a: reps\n", + "rb_config['verbose'] = True\n", + "\n", + "# Test settings 2b - Decimation Acquire - LFSR\n", + "rb_config['acquire_mode'] = 'DEC'\n", + "rb_config['ro_len'] = 1.0\n", + "rb_config['pulse_len_us'] = 0.1\n", + "rb_config['use_lfsr'] = True\n", + "rb_config['L'] = [2, 5]\n", + "rb_config['N_L'] = len(rb_config['L'])\n", + "rb_config['N_G'] = 2 # a.k.a: rounds\n", + "rb_config['N_E'] = 1 # a.k.a: reps\n", + "rb_config['verbose'] = True\n", + "\n", + "\n", + "prog = RBSequenceProgram(soccfg, reps=rb_config['N_E'], final_delay=rb_config['relax_delay'], cfg=rb_config)\n", + "\n", + "\n", + "if (rb_config['acquire_mode'] == 'DEC'):\n", + " iq_list = prog.acquire_decimated(soc, rounds=1)\n", + " t = prog.get_time_axis(ro_index=0)\n", + "\n", + " if rb_config['N_E'] > 1:\n", + " iq_list = iq_list[0]\n", + "\n", + " print(iq_list[0].shape)\n", + "\n", + " plt.figure(figsize=[20,15])\n", + " N = len(iq_list[0])\n", + " for trig, iq in enumerate(iq_list[0]):\n", + " plt.subplot(N,1,trig+1)\n", + " plt.plot(t, iq[:,0], label=\"I value\")\n", + " plt.plot(t, iq[:,1], label=\"Q value\")\n", + " plt.plot(t, np.abs(iq.dot([1,1j])), label=\"magnitude\", ls='--')\n", + " plt.legend()\n", + " plt.ylabel(\"a.u.\")\n", + " plt.xlabel(\"us\")\n", + "\n", + "\n", + "if (rb_config['acquire_mode'] == 'AVG'):\n", + " iq_list = prog.acquire(soc, rounds=1)\n", + " # iq_list = prog.acquire(soc, rounds=rb_config['N_G'])\n", + "\n", + " print(iq_list[0].shape)\n", + "\n", + " plt.figure(figsize=[20,10])\n", + " plt.plot(np.abs(iq_list[0].dot([1,1j])), label=\"magnitude\", ls='--', marker='x')\n", + " plt.legend()\n", + " plt.ylabel(\"a.u.\")\n", + "\n" + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "id": "1512a77e", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='measure', t=0.0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=1, name='reps')\n", + "\tWriteReg(dst='r8', src=0)\n", + "\tWriteReg(dst='r9', src=1073741824)\n", + "\tDelay(t=1.0, auto=False, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tWait(t=0.0, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=2.0, auto=False, tag='pre_seq_delay_000', t_params={'t': }, t_regs={'t': 860})\n", + "\tWriteReg(dst='lfsr_seed', src=123456789)\n", + "\tWriteReg(dst='seq_length', src=9)\n", + "\tCall(label='gen_rnd_seq')\n", + "\tWriteReg(dst='r4', src=2)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r_wave', 'SRC': 'wmem', 'ADDR': 'r4'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'w1', 'SRC': 'op', 'OP': 'w1 + r10'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'WPORT_WR', 'DST': '0', 'SRC': 'r_wave'}, addr_inc=1)\n", + "\tPulse(ch=0, name='ro_pulse', t=0.0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.2, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 86, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tDelay(t=1.0, auto=False, tag='post_seq_delay_000', t_params={'t': }, t_regs={'t': 430})\n", + "\tDelay(t=1.0, auto=False, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tWait(t=0.0, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 0})\n", + "\tIncReg(dst='r8', src=1)\n", + "\tDelay(t=2.0, auto=False, tag='pre_seq_delay_100', t_params={'t': }, t_regs={'t': 860})\n", + "\tWriteReg(dst='lfsr_seed', src=123456789)\n", + "\tWriteReg(dst='seq_length', src=9)\n", + "\tCall(label='gen_rnd_seq')\n", + "\tWriteReg(dst='r4', src=2)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r_wave', 'SRC': 'wmem', 'ADDR': 'r4'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'w1', 'SRC': 'op', 'OP': 'w1 + r10'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'WPORT_WR', 'DST': '0', 'SRC': 'r_wave'}, addr_inc=1)\n", + "\tPulse(ch=0, name='ro_pulse', t=0.0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.2, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 86, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tDelay(t=1.0, auto=False, tag='post_seq_delay_100', t_params={'t': }, t_regs={'t': 430})\n", + "\tDelay(t=1.0, auto=False, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tWait(t=0.0, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 0})\n", + "\tIncReg(dst='r8', src=1)\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "\tLabel(label='gen_rnd_seq')\n", + "\tWriteReg(dst='s_rand', src='lfsr_seed')\n", + "\tWriteReg(dst='r10', src=0)\n", + "\tLabel(label='gen_seq_loop')\n", + "\tCondJump(label='gen_seq_end', arg1='seq_length', test='Z', op='-', arg2=0)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r4', 'SRC': 'op', 'OP': 's1 AND #h0F'}, addr_inc=1)\n", + "\tCondJump(label='gen_seq_loop', arg1='r4', test='NS', op='-', arg2=10)\n", + "\tLabel(label='gen_seq_checkZ')\n", + "\tCondJump(label='gen_seq_checkZov2', arg1='r4', test='NZ', op='-', arg2=1)\n", + "\tIncReg(dst='r10', src='r9')\n", + "\tIncReg(dst='r10', src='r9')\n", + "\tJump(label='gen_seq_pulse')\n", + "\tLabel(label='gen_seq_checkZov2')\n", + "\tCondJump(label='gen_seq_check-Zov2', arg1='r4', test='NZ', op='-', arg2=4)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r10', 'SRC': 'op', 'OP': 'r10 + r9'}, addr_inc=1)\n", + "\tJump(label='gen_seq_pulse')\n", + "\tLabel(label='gen_seq_check-Zov2')\n", + "\tCondJump(label='gen_seq_pulse', arg1='r4', test='NZ', op='-', arg2=7)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r10', 'SRC': 'op', 'OP': 'r10 - r9'}, addr_inc=1)\n", + "\tLabel(label='gen_seq_pulse')\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r_wave', 'SRC': 'wmem', 'ADDR': 'r4'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'w1', 'SRC': 'op', 'OP': 'w1 + r10'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'WPORT_WR', 'DST': '0', 'SRC': 'r_wave'}, addr_inc=1)\n", + "\tLabel(label='gen_seq_next_gate')\n", + "\tIncReg(dst='seq_length', src=-1)\n", + "\tJump(label='gen_seq_loop')\n", + "\tLabel(label='gen_seq_end')\n", + "\tAsmInst(inst={'CMD': 'RET'}, addr_inc=1)\n", + "registers:\n", + "\tlfsr_seed: QickRegisterV2(addr=0, init=None)\n", + "\tseq_length: QickRegisterV2(addr=1, init=None)\n", + "\treps: QickRegisterV2(addr=2, init=None)\n", + "pulses:\n", + "\tI: QickPulse(waveforms=[Waveform(name='I_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=3276, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tZ: QickPulse(waveforms=[Waveform(name='Z_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tX: QickPulse(waveforms=[Waveform(name='X_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tY: QickPulse(waveforms=[Waveform(name='Y_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=-1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tZ/2: QickPulse(waveforms=[Waveform(name='Z/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tX/2: QickPulse(waveforms=[Waveform(name='X/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tY/2: QickPulse(waveforms=[Waveform(name='Y/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=-1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-Z/2: QickPulse(waveforms=[Waveform(name='-Z/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-X/2: QickPulse(waveforms=[Waveform(name='-X/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=2147483648, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-Y/2: QickPulse(waveforms=[Waveform(name='-Y/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tro_pulse: QickPulse(waveforms=[Waveform(name='ro_pulse_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tend_seq_pulse: QickPulse(waveforms=[Waveform(name='end_seq_pulse_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tmeasure: QickPulse(waveforms=[Waveform(name='measure_w0', freq=QickRawParam(par='freq', start=-873813330, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&12] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r2 imm #0 \n", + "\treps:\n", + "\t REG_WR r8 imm #0 \n", + "\t REG_WR r9 imm #1073741824 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s15 imm #10 \n", + "\t WAIT [s15] @0 time \n", + "\t TIME #860 inc_ref \n", + "\t REG_WR r0 imm #123456789 \n", + "\t REG_WR r1 imm #9 \n", + "\t REG_WR s15 label gen_rnd_seq \n", + "\t CALL [s15] \n", + "\t REG_WR r4 imm #2 \n", + "\t REG_WR r_wave wmem [r4] \n", + "\t REG_WR w1 op -op(w1 + r10) \n", + "\t WPORT_WR p0 r_wave \n", + "\t WPORT_WR p0 wmem [&10] @0 \n", + "\t TRIG p0 set @86 \n", + "\t TRIG p9 set @86 \n", + "\t TRIG p10 set @86 \n", + "\t TRIG p0 clr @96 \n", + "\t TRIG p9 clr @96 \n", + "\t TRIG p10 clr @96 \n", + "\t TIME #430 inc_ref \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s15 imm #31 \n", + "\t WAIT [s15] @0 time \n", + "\t REG_WR r8 op -op(r8 + #1) \n", + "\t TIME #860 inc_ref \n", + "\t REG_WR r0 imm #123456789 \n", + "\t REG_WR r1 imm #9 \n", + "\t REG_WR s15 label gen_rnd_seq \n", + "\t CALL [s15] \n", + "\t REG_WR r4 imm #2 \n", + "\t REG_WR r_wave wmem [r4] \n", + "\t REG_WR w1 op -op(w1 + r10) \n", + "\t WPORT_WR p0 r_wave \n", + "\t WPORT_WR p0 wmem [&10] @0 \n", + "\t TRIG p0 set @86 \n", + "\t TRIG p9 set @86 \n", + "\t TRIG p10 set @86 \n", + "\t TRIG p0 clr @96 \n", + "\t TRIG p9 clr @96 \n", + "\t TRIG p10 clr @96 \n", + "\t TIME #430 inc_ref \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s15 imm #53 \n", + "\t WAIT [s15] @0 time \n", + "\t REG_WR r8 op -op(r8 + #1) \n", + "\t REG_WR s15 imm #57 \n", + "\t WAIT [s15] @0 time \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t REG_WR s15 label reps \n", + "\t TEST -op(r2 - #0) \n", + "\t JUMP [s15] -if(NZ) -wr(r2 op) -op(r2 + #1) \n", + "\t REG_WR s15 imm #64 \n", + "\t JUMP [s15] \n", + "\tgen_rnd_seq:\n", + "\t REG_WR s1 op -op(r0) \n", + "\t REG_WR r10 imm #0 \n", + "\tgen_seq_loop:\n", + "\t REG_WR s15 label gen_seq_end \n", + "\t TEST -op(r1 - #0) -uf \n", + "\t JUMP [s15] -if(Z) \n", + "\t REG_WR r4 op -op(s1 AND #h0F) \n", + "\t REG_WR s15 label gen_seq_loop \n", + "\t TEST -op(r4 - #10) -uf \n", + "\t JUMP [s15] -if(NS) \n", + "\tgen_seq_checkZ:\n", + "\t REG_WR s15 label gen_seq_checkZov2 \n", + "\t TEST -op(r4 - #1) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t JUMP [s15] \n", + "\tgen_seq_checkZov2:\n", + "\t REG_WR s15 label gen_seq_check-Zov2 \n", + "\t TEST -op(r4 - #4) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t JUMP [s15] \n", + "\tgen_seq_check-Zov2:\n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t TEST -op(r4 - #7) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 - r9) \n", + "\tgen_seq_pulse:\n", + "\t REG_WR r_wave wmem [r4] \n", + "\t REG_WR w1 op -op(w1 + r10) \n", + "\t WPORT_WR p0 r_wave \n", + "\tgen_seq_next_gate:\n", + "\t REG_WR r1 op -op(r1 + #-1) \n", + "\t REG_WR s15 label gen_seq_loop \n", + "\t JUMP [s15] \n", + "\tgen_seq_end:\n", + "\tRET\n", + "\n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce001820000000000\n", + "4c080000000000d700\n", + "8c6000000000000022\n", + "8c6000000000000028\n", + "8c6000002000000029\n", + "4c080000000000d700\n", + "8c600000000000050f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "4c080000000001ae00\n", + "8c60000003ade68aa0\n", + "8c60000000000004a1\n", + "8c600000000000208f\n", + "2c4000000000000000\n", + "8c6000000000000124\n", + "8c4004800000000000\n", + "840000002095000041\n", + "cdc000000000000000\n", + "dce001400000000000\n", + "dda000300000002b00\n", + "dda000348000002b00\n", + "dda000350000002b00\n", + "dda000100000003000\n", + "dda000148000003000\n", + "dda000150000003000\n", + "4c080000000000d700\n", + "4c080000000000d700\n", + "8c6000000000000f8f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "8800000014000000a8\n", + "4c080000000001ae00\n", + "8c60000003ade68aa0\n", + "8c60000000000004a1\n", + "8c600000000000208f\n", + "2c4000000000000000\n", + "8c6000000000000124\n", + "8c4004800000000000\n", + "840000002095000041\n", + "cdc000000000000000\n", + "dce001400000000000\n", + "dda000300000002b00\n", + "dda000348000002b00\n", + "dda000350000002b00\n", + "dda000100000003000\n", + "dda000148000003000\n", + "dda000150000003000\n", + "4c080000000000d700\n", + "4c080000000000d700\n", + "8c6000000000001a8f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "8800000014000000a8\n", + "8c6000000000001c8f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "4c080000000000d700\n", + "88000000060000008c\n", + "8c600000000000028f\n", + "081100001100000000\n", + "2988000011000000a2\n", + "8c600000000000200f\n", + "2c0000000000000000\n", + "840000001000000001\n", + "8c600000000000002a\n", + "8c600000000000308f\n", + "081100001080000000\n", + "2c8000000000000000\n", + "8804000000800007a4\n", + "8c600000000000218f\n", + "081100001200000500\n", + "2e0000000000000000\n", + "8c600000000000288f\n", + "081100001200000080\n", + "2d8000000000000000\n", + "84000000151480002a\n", + "84000000151480002a\n", + "8c6000000000002d8f\n", + "2c0000000000000000\n", + "8c6000000000002b8f\n", + "081100001200000200\n", + "2d8000000000000000\n", + "84000000151480002a\n", + "8c6000000000002d8f\n", + "2c0000000000000000\n", + "8c6000000000002d8f\n", + "081100001200000380\n", + "2d8000000000000000\n", + "84020000151480002a\n", + "8c4004800000000000\n", + "840000002095000041\n", + "cdc000000000000000\n", + "8800000010ffffffa1\n", + "8c600000000000218f\n", + "2c0000000000000000\n", + "2c6000000000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_0000003c_00000ccc_000000_00000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00007ffe_000000_00000000_0d5acdad\n", + "___0008_0000003c_00007ffe_000000_c0000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_c0000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_80000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_40000000_0d5acdad\n", + "___0009_0000003c_00001999_000000_00000000_0d5acdac\n", + "___0009_0000003c_00001999_000000_00000000_0d5acdac\n", + "___0108_00000003_00000000_000000_00000000_cbeaaaae\n", + "Dumped SG envelope table memory to file sg_0.mem\n" + ] + } + ], + "source": [ + "# print the program\n", + "print(prog)\n", + "\n", + "# generate rtl simulation inputs\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0, gen_file=True)" + ] + }, + { + "cell_type": "code", + "execution_count": 28, + "id": "da2b8ba0", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "- Experiment Start Time: 255602 ns\n", + " - Depth array 1 - time elapsed: 3002402 ns\n", + " - Sequence run time: (0): 2023 ms (1): 2021 ms (2): 2021 ms (3): 2021 ms (4): 2021 ms (5): 2021 ms (6): 2025 ms (7): 2021 ms (8): 2021 ms (9): 2021 ms (10): 2021 ms (11): 2021 ms (12): 2025 ms (13): 2021 ms (14): 2021 ms (15): 2021 ms (16): 2021 ms (17): 2021 ms (18): 2025 ms (19): 2021 ms (20): 2021 ms (21): 2021 ms (22): 2021 ms (23): 2021 ms (24): 2025 ms (25): 2021 ms (26): 2021 ms (27): 2021 ms (28): 2021 ms (29): 2021 ms (30): 2025 ms (31): 2021 ms (32): 2021 ms (33): 2021 ms (34): 2021 ms (35): 2021 ms (36): 2025 ms (37): 2021 ms (38): 2021 ms (39): 2021 ms \n", + " - Sequence Total time: 82558 ms (Run time: 80882 ms - Overhead time: 1675 ms)\n", + " - Depth array 16 - time elapsed: 82561095103 ns\n", + " - Sequence run time: (0): 2038 ms (1): 2038 ms (2): 2043 ms (3): 2039 ms (4): 2039 ms (5): 2039 ms (6): 2038 ms (7): 2038 ms (8): 2043 ms (9): 2038 ms (10): 2039 ms (11): 2039 ms (12): 2038 ms (13): 2038 ms (14): 2043 ms (15): 2039 ms (16): 2039 ms (17): 2039 ms (18): 2038 ms (19): 2039 ms (20): 2043 ms (21): 2039 ms (22): 2039 ms (23): 2039 ms (24): 2039 ms (25): 2038 ms (26): 2044 ms (27): 2039 ms (28): 2039 ms (29): 2039 ms (30): 2039 ms (31): 2038 ms (32): 2043 ms (33): 2039 ms (34): 2039 ms (35): 2039 ms (36): 2039 ms (37): 2039 ms (38): 2043 ms (39): 2039 ms \n", + " - Sequence Total time: 83293 ms (Run time: 81595 ms - Overhead time: 1697 ms)\n", + " - Depth array 64 - time elapsed: 165854679625 ns\n", + " - Sequence run time: (0): 2096 ms (1): 2096 ms (2): 2096 ms (3): 2096 ms (4): 2101 ms (5): 2096 ms (6): 2096 ms (7): 2096 ms (8): 2096 ms (9): 2096 ms (10): 2101 ms (11): 2096 ms (12): 2096 ms (13): 2096 ms (14): 2096 ms (15): 2096 ms (16): 2101 ms (17): 2096 ms (18): 2096 ms (19): 2096 ms (20): 2096 ms (21): 2096 ms (22): 2101 ms (23): 2096 ms (24): 2096 ms (25): 2096 ms (26): 2096 ms (27): 2096 ms (28): 2101 ms (29): 2096 ms (30): 2096 ms (31): 2096 ms (32): 2096 ms (33): 2096 ms (34): 2101 ms (35): 2096 ms (36): 2096 ms (37): 2096 ms (38): 2096 ms (39): 2096 ms \n", + " - Sequence Total time: 85653 ms (Run time: 83895 ms - Overhead time: 1757 ms)\n", + " - Depth array 128 - time elapsed: 251508066395 ns\n", + " - Sequence run time: (0): 2178 ms (1): 2174 ms (2): 2173 ms (3): 2173 ms (4): 2173 ms (5): 2173 ms (6): 2178 ms (7): 2174 ms (8): 2173 ms (9): 2173 ms (10): 2173 ms (11): 2173 ms (12): 2178 ms (13): 2173 ms (14): 2173 ms (15): 2173 ms (16): 2173 ms (17): 2173 ms (18): 2178 ms (19): 2173 ms (20): 2173 ms (21): 2173 ms (22): 2173 ms (23): 2173 ms (24): 2178 ms (25): 2173 ms (26): 2173 ms (27): 2173 ms (28): 2173 ms (29): 2173 ms (30): 2178 ms (31): 2173 ms (32): 2173 ms (33): 2173 ms (34): 2173 ms (35): 2173 ms (36): 2178 ms (37): 2173 ms (38): 2173 ms (39): 2173 ms \n", + " - Sequence Total time: 88828 ms (Run time: 86976 ms - Overhead time: 1851 ms)\n", + " - Depth array 512 - time elapsed: 340336535973 ns\n", + " - Sequence run time: (0): 2634 ms (1): 2634 ms (2): 2639 ms (3): 2635 ms (4): 2634 ms (5): 2634 ms (6): 2634 ms (7): 2634 ms (8): 2634 ms (9): 2634 ms (10): 2634 ms (11): 2634 ms (12): 2634 ms (13): 2634 ms (14): 2634 ms (15): 2634 ms (16): 2634 ms (17): 2634 ms (18): 2634 ms (19): 2634 ms (20): 2634 ms (21): 2634 ms (22): 2634 ms (23): 2635 ms (24): 2634 ms (25): 2634 ms (26): 2634 ms (27): 2634 ms (28): 2634 ms (29): 2634 ms (30): 2634 ms (31): 2634 ms (32): 2634 ms (33): 2634 ms (34): 2634 ms (35): 2634 ms (36): 2634 ms (37): 2634 ms (38): 2634 ms (39): 2634 ms \n", + " - Sequence Total time: 109044 ms (Run time: 105378 ms - Overhead time: 3666 ms)\n", + " - Depth array 768 - time elapsed: 449381404075 ns\n", + " - Sequence run time: (0): 2941 ms (1): 2941 ms (2): 2941 ms (3): 2941 ms (4): 2941 ms (5): 2941 ms (6): 2941 ms (7): 2941 ms (8): 2941 ms (9): 2941 ms (10): 2941 ms (11): 2941 ms (12): 2941 ms (13): 2941 ms (14): 2941 ms (15): 2941 ms (16): 2941 ms (17): 2941 ms (18): 2941 ms (19): 2941 ms (20): 2941 ms (21): 2941 ms (22): 2941 ms (23): 2941 ms (24): 2942 ms (25): 2941 ms (26): 2941 ms (27): 2941 ms (28): 2941 ms (29): 2941 ms (30): 2941 ms (31): 2941 ms (32): 2941 ms (33): 2941 ms (34): 2941 ms (35): 2941 ms (36): 2941 ms (37): 2941 ms (38): 2941 ms (39): 2941 ms \n", + " - Sequence Total time: 120182 ms (Run time: 117659 ms - Overhead time: 2523 ms)\n", + " - Depth array 1024 - time elapsed: 569564289222 ns\n", + " - Sequence run time: (0): 3249 ms (1): 3248 ms (2): 3248 ms (3): 3248 ms (4): 3248 ms (5): 3248 ms (6): 3248 ms (7): 3249 ms (8): 3248 ms (9): 3248 ms (10): 3249 ms (11): 3248 ms (12): 3248 ms (13): 3248 ms (14): 3248 ms (15): 3248 ms (16): 3248 ms (17): 3248 ms (18): 3248 ms (19): 3249 ms (20): 3248 ms (21): 3248 ms (22): 3248 ms (23): 3248 ms (24): 3248 ms (25): 3248 ms (26): 3249 ms (27): 3248 ms (28): 3248 ms (29): 3248 ms (30): 3248 ms (31): 3248 ms (32): 3248 ms (33): 3248 ms (34): 3248 ms (35): 3248 ms (36): 3248 ms (37): 3248 ms (38): 3248 ms (39): 3248 ms \n", + " - Sequence Total time: 132758 ms (Run time: 129954 ms - Overhead time: 2804 ms)\n", + "- End Time: 1761689940698562728 - elapsed: 702323504258\n" + ] + } + ], + "source": [ + "# from datetime import datetime\n", + "import time\n", + "import pandas as pd\n", + "\n", + "I2 = []\n", + "I2_err = []\n", + "\n", + "rb_config['L'] = [1]\n", + "rb_config['N_L'] = len(rb_config['L'])\n", + "rb_config['N_G'] = 1 # a.k.a: rounds\n", + "rb_config['N_E'] = 1 # a.k.a: reps\n", + "\n", + "\n", + "# Original Settings\n", + "depth_array = [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48, 64, 80, 96, 128, 192, \n", + " 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216, 1280, 1344, 1408,\n", + " 1472, 1536, 1600, 1664, 1728, 1750]\n", + "reps = 4000\n", + "variety = 40\n", + "\n", + "\n", + "rb_config['relax_delay'] = 500 # us\n", + "rb_config['pulse_len_us'] = 0.1\n", + "\n", + "# # Test settings 1\n", + "# depth_array = [1, 16, 128, 1024]\n", + "# rb_config['reps'] = 4000\n", + "# variety = 2\n", + "\n", + "\n", + "# Test settings 2a - NO LFSR\n", + "rb_config['verbose'] = False\n", + "rb_config['use_lfsr'] = False\n", + "depth_array = [1, 16, 64, 128, 512, 768, 1024]\n", + "reps = 4000\n", + "variety = 40\n", + "\n", + "# # Test settings 2b - NO LFSR\n", + "# rb_config['verbose'] = False\n", + "# rb_config['use_lfsr'] = False\n", + "# depth_array = [1, 1024]\n", + "# reps = 4000\n", + "# variety = 5\n", + "\n", + "# Test settings 3a - LFSR\n", + "rb_config['verbose'] = False\n", + "rb_config['use_lfsr'] = True\n", + "depth_array = [1, 16, 64, 128, 512, 768, 1024]\n", + "reps = 4000\n", + "variety = 40\n", + "\n", + "# # Test settings 3b - LFSR\n", + "# rb_config['verbose'] = False\n", + "# rb_config['use_lfsr'] = True\n", + "# depth_array = [1, 1024]\n", + "# reps = 4000\n", + "# variety = 5\n", + "\n", + "# # Test settings 4 - LFSR\n", + "# rb_config['verbose'] = False\n", + "# rb_config['use_lfsr'] = True\n", + "# depth_array = [1, 5000]\n", + "# reps = 4000\n", + "# variety = 5\n", + "\n", + "# # Test settings 4 - LFSR\n", + "# rb_config['verbose'] = False\n", + "# rb_config['use_lfsr'] = True\n", + "# depth_array = [10]\n", + "# reps = 4000\n", + "# variety = 5\n", + "\n", + "# Code\n", + "t_start_ns = time.time_ns()\n", + "print('- Experiment Start Time: %0d ns' % (time.time_ns()-t_start_ns))\n", + "\n", + "th = -30\n", + "\n", + "t=time.time_ns()\n", + "\n", + "# Loop for different lengths\n", + "for d in depth_array:\n", + " dbg_i=0\n", + " t_sequence_start_ns = time.time_ns()\n", + " print(' - Depth array %0d - time elapsed: %0d ns' % (d,t_sequence_start_ns-t_start_ns) )\n", + " i2_temp = []\n", + " t_runtime_total_ns = 0\n", + " # Loop for different random sequences\n", + " print(' - Sequence run time: ', end=\" \")\n", + " for jj in range(variety):\n", + " # print('// DBG start: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " rb_config['test_seq'] = prog.generate_rbsequence(depth=d, gates_set=rb_config['gates_set'])\n", + " # print('// DBG gen_seq: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " rb_prog = RBSequenceProgram(soccfg, reps=reps, final_delay=rb_config['relax_delay'], cfg=rb_config)\n", + " # print('// DBG RBSeqProgram: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " t_runtime_start_ns = time.time_ns()\n", + " # avgi0, avgq0, avgi1, avgq1 = rb_prog.acquire(soc, load_pulses=True, progress=False, debug=False, single_shot=True)\n", + " # adc1, adc2 = rb_prog.acquire(soc, progress=False)\n", + " adc1 = rb_prog.acquire(soc, progress=False)\n", + " t_runtime_end_ns = time.time_ns()\n", + " t_runtime_total_ns += (t_runtime_end_ns-t_runtime_start_ns)\n", + " print(' (%0d): %0d ms' % (jj, (t_runtime_end_ns-t_runtime_start_ns)/1e6), end=\" \")\n", + "\n", + " # print('// DBG acquire: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + " \n", + " avgi0 = np.array([adc1[0][0][0]])\n", + " avgq0 = np.array([adc1[0][0][1]])\n", + " # avgi1 = adc2[0]\n", + " # avgq1 = adc2[1]\n", + " df = pd.DataFrame(avgi0, columns=['data'])\n", + " g = df['data'].apply(lambda x: 0 if x < th else 1).mean()\n", + " i2_temp.append(g) \n", + " # print('// DBG append: %0d - %0d ns' % (dbg_i, time.time_ns()-t)); t=time.time_ns(); dbg_i+=1\n", + "\n", + " print('')\n", + " I2.append(np.mean(i2_temp))\n", + " I2_err.append(np.std(i2_temp)/np.sqrt(variety))\n", + " t_sequence_end_ns = time.time_ns()\n", + " print(' - Sequence Total time: %0d ms (Run time: %0d ms - Overhead time: %0d ms)' % ((t_sequence_end_ns - t_sequence_start_ns)/1e6, t_runtime_total_ns/1e6, (t_sequence_end_ns - t_sequence_start_ns)/1e6 - t_runtime_total_ns/1e6))\n", + "\n", + "t_end_ns = int(time.time_ns())\n", + "print('- End Time: %0d - elapsed: %0d' % (t_end_ns, (t_end_ns-t_start_ns)))\n" + ] + }, + { + "cell_type": "code", + "execution_count": 26, + "id": "43667010", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='measure', t=0.0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=4000, name='reps')\n", + "\tWriteReg(dst='r8', src=0)\n", + "\tWriteReg(dst='r9', src=1073741824)\n", + "\tDelay(t=1.0, auto=False, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tWait(t=0.0, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=204.8, auto=False, tag='pre_seq_delay_000', t_params={'t': }, t_regs={'t': 88080})\n", + "\tWriteReg(dst='lfsr_seed', src=123456789)\n", + "\tWriteReg(dst='seq_length', src=1023)\n", + "\tCall(label='gen_rnd_seq')\n", + "\tWriteReg(dst='r4', src=8)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r_wave', 'SRC': 'wmem', 'ADDR': 'r4'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'w1', 'SRC': 'op', 'OP': 'w1 + r10'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'WPORT_WR', 'DST': '0', 'SRC': 'r_wave'}, addr_inc=1)\n", + "\tPulse(ch=0, name='ro_pulse', t=0.0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.2, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 86, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tDelay(t=102.4, auto=False, tag='post_seq_delay_000', t_params={'t': }, t_regs={'t': 44040})\n", + "\tDelay(t=1.0, auto=False, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tWait(t=0.0, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 0})\n", + "\tIncReg(dst='r8', src=1)\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=500, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 215040})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "\tLabel(label='gen_rnd_seq')\n", + "\tWriteReg(dst='s_rand', src='lfsr_seed')\n", + "\tWriteReg(dst='r10', src=0)\n", + "\tLabel(label='gen_seq_loop')\n", + "\tCondJump(label='gen_seq_end', arg1='seq_length', test='Z', op='-', arg2=0)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r4', 'SRC': 'op', 'OP': 's1 AND #h0F'}, addr_inc=1)\n", + "\tCondJump(label='gen_seq_loop', arg1='r4', test='NS', op='-', arg2=10)\n", + "\tLabel(label='gen_seq_checkZ')\n", + "\tCondJump(label='gen_seq_checkZov2', arg1='r4', test='NZ', op='-', arg2=1)\n", + "\tIncReg(dst='r10', src='r9')\n", + "\tIncReg(dst='r10', src='r9')\n", + "\tJump(label='gen_seq_pulse')\n", + "\tLabel(label='gen_seq_checkZov2')\n", + "\tCondJump(label='gen_seq_check-Zov2', arg1='r4', test='NZ', op='-', arg2=4)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r10', 'SRC': 'op', 'OP': 'r10 + r9'}, addr_inc=1)\n", + "\tJump(label='gen_seq_pulse')\n", + "\tLabel(label='gen_seq_check-Zov2')\n", + "\tCondJump(label='gen_seq_pulse', arg1='r4', test='NZ', op='-', arg2=7)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r10', 'SRC': 'op', 'OP': 'r10 - r9'}, addr_inc=1)\n", + "\tLabel(label='gen_seq_pulse')\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'r_wave', 'SRC': 'wmem', 'ADDR': 'r4'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'REG_WR', 'DST': 'w1', 'SRC': 'op', 'OP': 'w1 + r10'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'WPORT_WR', 'DST': '0', 'SRC': 'r_wave'}, addr_inc=1)\n", + "\tLabel(label='gen_seq_next_gate')\n", + "\tIncReg(dst='seq_length', src=-1)\n", + "\tJump(label='gen_seq_loop')\n", + "\tLabel(label='gen_seq_end')\n", + "\tAsmInst(inst={'CMD': 'RET'}, addr_inc=1)\n", + "registers:\n", + "\tlfsr_seed: QickRegisterV2(addr=0, init=None)\n", + "\tseq_length: QickRegisterV2(addr=1, init=None)\n", + "\treps: QickRegisterV2(addr=2, init=None)\n", + "pulses:\n", + "\tI: QickPulse(waveforms=[Waveform(name='I_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=3276, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tZ: QickPulse(waveforms=[Waveform(name='Z_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tX: QickPulse(waveforms=[Waveform(name='X_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tY: QickPulse(waveforms=[Waveform(name='Y_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=-1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tZ/2: QickPulse(waveforms=[Waveform(name='Z/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tX/2: QickPulse(waveforms=[Waveform(name='X/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tY/2: QickPulse(waveforms=[Waveform(name='Y/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=-1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-Z/2: QickPulse(waveforms=[Waveform(name='-Z/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-X/2: QickPulse(waveforms=[Waveform(name='-X/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=2147483648, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\t-Y/2: QickPulse(waveforms=[Waveform(name='-Y/2_w0', freq=QickRawParam(par='freq', start=224054701, spans={}, quantize=1, steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tro_pulse: QickPulse(waveforms=[Waveform(name='ro_pulse_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tend_seq_pulse: QickPulse(waveforms=[Waveform(name='end_seq_pulse_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=6553, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tmeasure: QickPulse(waveforms=[Waveform(name='measure_w0', freq=QickRawParam(par='freq', start=-873813330, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&12] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r2 imm #0 \n", + "\treps:\n", + "\t REG_WR r8 imm #0 \n", + "\t REG_WR r9 imm #1073741824 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s15 imm #10 \n", + "\t WAIT [s15] @0 time \n", + "\t TIME #88080 inc_ref \n", + "\t REG_WR r0 imm #123456789 \n", + "\t REG_WR r1 imm #1023 \n", + "\t REG_WR s15 label gen_rnd_seq \n", + "\t CALL [s15] \n", + "\t REG_WR r4 imm #8 \n", + "\t REG_WR r_wave wmem [r4] \n", + "\t REG_WR w1 op -op(w1 + r10) \n", + "\t WPORT_WR p0 r_wave \n", + "\t WPORT_WR p0 wmem [&10] @0 \n", + "\t TRIG p0 set @86 \n", + "\t TRIG p9 set @86 \n", + "\t TRIG p10 set @86 \n", + "\t TRIG p0 clr @96 \n", + "\t TRIG p9 clr @96 \n", + "\t TRIG p10 clr @96 \n", + "\t TIME #44040 inc_ref \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR s15 imm #31 \n", + "\t WAIT [s15] @0 time \n", + "\t REG_WR r8 op -op(r8 + #1) \n", + "\t REG_WR s15 imm #35 \n", + "\t WAIT [s15] @0 time \n", + "\t TIME #215040 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t REG_WR s15 label reps \n", + "\t TEST -op(r2 - #3999) \n", + "\t JUMP [s15] -if(NZ) -wr(r2 op) -op(r2 + #1) \n", + "\t REG_WR s15 imm #42 \n", + "\t JUMP [s15] \n", + "\tgen_rnd_seq:\n", + "\t REG_WR s1 op -op(r0) \n", + "\t REG_WR r10 imm #0 \n", + "\tgen_seq_loop:\n", + "\t REG_WR s15 label gen_seq_end \n", + "\t TEST -op(r1 - #0) -uf \n", + "\t JUMP [s15] -if(Z) \n", + "\t REG_WR r4 op -op(s1 AND #h0F) \n", + "\t REG_WR s15 label gen_seq_loop \n", + "\t TEST -op(r4 - #10) -uf \n", + "\t JUMP [s15] -if(NS) \n", + "\tgen_seq_checkZ:\n", + "\t REG_WR s15 label gen_seq_checkZov2 \n", + "\t TEST -op(r4 - #1) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t JUMP [s15] \n", + "\tgen_seq_checkZov2:\n", + "\t REG_WR s15 label gen_seq_check-Zov2 \n", + "\t TEST -op(r4 - #4) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 + r9) \n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t JUMP [s15] \n", + "\tgen_seq_check-Zov2:\n", + "\t REG_WR s15 label gen_seq_pulse \n", + "\t TEST -op(r4 - #7) -uf \n", + "\t JUMP [s15] -if(NZ) \n", + "\t REG_WR r10 op -op(r10 - r9) \n", + "\tgen_seq_pulse:\n", + "\t REG_WR r_wave wmem [r4] \n", + "\t REG_WR w1 op -op(w1 + r10) \n", + "\t WPORT_WR p0 r_wave \n", + "\tgen_seq_next_gate:\n", + "\t REG_WR r1 op -op(r1 + #-1) \n", + "\t REG_WR s15 label gen_seq_loop \n", + "\t JUMP [s15] \n", + "\tgen_seq_end:\n", + "\tRET\n", + "\n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce001820000000000\n", + "4c080000000000d700\n", + "8c6000000000000022\n", + "8c6000000000000028\n", + "8c6000002000000029\n", + "4c080000000000d700\n", + "8c600000000000050f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "4c0800000000ac0800\n", + "8c60000003ade68aa0\n", + "8c600000000001ffa1\n", + "8c600000000000158f\n", + "2c4000000000000000\n", + "8c6000000000000424\n", + "8c4004800000000000\n", + "840000002095000041\n", + "cdc000000000000000\n", + "dce001400000000000\n", + "dda000300000002b00\n", + "dda000348000002b00\n", + "dda000350000002b00\n", + "dda000100000003000\n", + "dda000148000003000\n", + "dda000150000003000\n", + "4c0800000000560400\n", + "4c080000000000d700\n", + "8c6000000000000f8f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "8800000014000000a8\n", + "8c600000000000118f\n", + "0811000005fffffb00\n", + "2911000005fffffb00\n", + "4c0800000001a40000\n", + "88000000060000008c\n", + "8c600000000000028f\n", + "08110000110007cf80\n", + "2988000011000000a2\n", + "8c600000000000150f\n", + "2c0000000000000000\n", + "840000001000000001\n", + "8c600000000000002a\n", + "8c600000000000258f\n", + "081100001080000000\n", + "2c8000000000000000\n", + "8804000000800007a4\n", + "8c600000000000168f\n", + "081100001200000500\n", + "2e0000000000000000\n", + "8c6000000000001d8f\n", + "081100001200000080\n", + "2d8000000000000000\n", + "84000000151480002a\n", + "84000000151480002a\n", + "8c600000000000228f\n", + "2c0000000000000000\n", + "8c600000000000208f\n", + "081100001200000200\n", + "2d8000000000000000\n", + "84000000151480002a\n", + "8c600000000000228f\n", + "2c0000000000000000\n", + "8c600000000000228f\n", + "081100001200000380\n", + "2d8000000000000000\n", + "84020000151480002a\n", + "8c4004800000000000\n", + "840000002095000041\n", + "cdc000000000000000\n", + "8800000010ffffffa1\n", + "8c600000000000168f\n", + "2c0000000000000000\n", + "2c6000000000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_0000003c_00000ccc_000000_00000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00007ffe_000000_00000000_0d5acdad\n", + "___0008_0000003c_00007ffe_000000_c0000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_c0000000_0d5acdad\n", + "___0008_0000003c_00001999_000000_00000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_80000000_0d5acdad\n", + "___0008_0000003c_00003fff_000000_40000000_0d5acdad\n", + "___0009_0000003c_00001999_000000_00000000_0d5acdac\n", + "___0009_0000003c_00001999_000000_00000000_0d5acdac\n", + "___0108_00000003_00000000_000000_00000000_cbeaaaae\n", + "Dumped SG envelope table memory to file sg_0.mem\n" + ] + } + ], + "source": [ + "# print the program\n", + "print(rb_prog)\n", + "\n", + "# generate rtl simulation inputs\n", + "rb_prog.print_pmem2hex()\n", + "rb_prog.print_wmem2hex()\n", + "rb_prog.print_sg_mem(sg_idx=0, gen_file=True)\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "8838aa9d", + "metadata": {}, + "outputs": [], + "source": [ + "from qick.tprocv2_assembler import Assembler\n", + "\n", + "prog_list = []\n", + "dict_label = { 'r_addr':'s15' }\n", + "\n", + "prog_list.append({'CMD':'REG_WR','DST':'r1','SRC':'op','OP':'MSH s7'})\n", + "prog_list.append({'CMD':'WPORT_WR','DST':'4','SRC':'wmem','ADDR':'r0'})\n", + "prog_list.append({'CMD':'DPORT_WR','DST':'0','SRC':'reg','DATA':'r0'})\n", + "\n", + "dict_label['END'] = '&'+str(len(prog_list)+1)\n", + "prog_list.append({'CMD':'JUMP','LABEL':'END'})\n", + "\n", + "p_bin = Assembler.list2bin(prog_list, dict_label)\n", + "p_asm = Assembler.list2asm(prog_list, dict_label)\n", + "\n", + "print(\"// Assembly Code\")\n", + "print(p_asm)\n", + "\n", + "print(\"// Assembly Binary\")\n", + "for l in p_bin[0]:\n", + " print(l)\n", + "\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "6cb27449", + "metadata": {}, + "outputs": [], + "source": [ + "asm = \"\"\"\n", + "// TEST program\n", + "// Write CORE_W_DT SREG\n", + "REG_WR s12 imm #12\n", + "DPORT_WR p0 imm 1\n", + "LABEL_ADDR:\n", + "REG_WR s_addr label LABEL_ADDR // write to s15 the address of label \"LABEL_ADDR\"\n", + ".END // replaced by JUMP HERE\n", + "\"\"\"\n", + "\n", + "p_txt, p_bin = Assembler.str_asm2bin(asm)\n", + "\n", + "print(\"// Assembly Binary\")\n", + "for l in p_txt:\n", + " print(l)\n", + "\n", + "# for l in p_bin:\n", + "# print(l)\n" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.10.4" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/firmware/notebooks/qick_testbench/test01_basic_multipulse.ipynb b/firmware/notebooks/qick_testbench/test01_basic_multipulse.ipynb new file mode 100644 index 000000000..690f17c36 --- /dev/null +++ b/firmware/notebooks/qick_testbench/test01_basic_multipulse.ipynb @@ -0,0 +1,471 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "32982695-822e-40aa-ac5c-9777a4d94fb2", + "metadata": {}, + "source": [ + "## setup" + ] + }, + { + "cell_type": "code", + "execution_count": 28, + "id": "3b5c048a", + "metadata": {}, + "outputs": [], + "source": [ + "# jupyter setup boilerplate\n", + "%matplotlib inline\n", + "import matplotlib.pyplot as plt\n", + "import numpy as np\n", + "\n", + "from qick import *\n", + "\n", + "# for now, all the tProc v2 classes need to be individually imported (can't use qick.*)\n", + "\n", + "# the main program class\n", + "from qick.asm_v2 import AveragerProgramV2\n", + "# for defining sweeps\n", + "from qick.asm_v2 import QickSpan, QickSweep1D" + ] + }, + { + "cell_type": "code", + "execution_count": 29, + "id": "ab849bc3", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "QICK running on ZCU216, software version 0.2.353\n", + "\n", + "Firmware configuration (built Sun Jun 15 17:47:17 2025):\n", + "\n", + "\tGlobal clocks (MHz): tProc dispatcher timing 430.080, RF reference 245.760\n", + "\tGroups of related clocks: [tProc core clock, tProc timing clock, DAC tile 1, DAC tile 2, DAC tile 3], [DAC tile 0], [ADC tile 2]\n", + "\n", + "\t16 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 65536 complex samples (6.838 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 0 is 0_228, on JHC1\n", + "\t1:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 16384 complex samples (1.709 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 1 is 1_228, on JHC2\n", + "\t2:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 32768 complex samples (3.419 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 2 is 2_228, on JHC1\n", + "\t3:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 16384 complex samples (1.709 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 3 is 3_228, on JHC2\n", + "\t4:\taxis_sg_mixmux8_v1 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 1, blk 0 is 0_229, on JHC1\n", + "\t5:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 16384 complex samples (38.095 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 1, blk 1 is 1_229, on JHC2\n", + "\t6:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 1, blk 2 is 2_229, on JHC1\n", + "\t7:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 16384 complex samples (38.095 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 1, blk 3 is 3_229, on JHC2\n", + "\t8:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 2, blk 0 is 0_230, on JHC3\n", + "\t9:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 2, blk 1 is 1_230, on JHC4\n", + "\t10:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 2, blk 2 is 2_230, on JHC3\n", + "\t11:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 2, blk 3 is 3_230, on JHC4\n", + "\t12:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 3, blk 0 is 0_231, on JHC3\n", + "\t13:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 3, blk 1 is 1_231, on JHC4\n", + "\t14:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 3, blk 2 is 2_231, on JHC3\n", + "\t15:\taxis_sg_int4_v2 - fs=6881.280 Msps, fabric=430.080 MHz\n", + "\t\tenvelope memory: 8192 complex samples (19.048 us)\n", + "\t\t32-bit DDS, range=1720.320 MHz\n", + "\t\tDAC tile 3, blk 3 is 3_231, on JHC4\n", + "\n", + "\t10 readout channels:\n", + "\t0:\taxis_dyn_readout_v1 - configured by tProc output 4\n", + "\t\tfs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 4096 decimated (13.333 us)\n", + "\t\ttriggered by tport 10, pin 0, feedback to tProc input 0\n", + "\t\tADC tile 2, blk 0 is 0_226, on JHC7\n", + "\t1:\taxis_dyn_readout_v1 - configured by tProc output 4\n", + "\t\tfs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 4096 decimated (13.333 us)\n", + "\t\ttriggered by tport 11, pin 0, feedback to tProc input 1\n", + "\t\tADC tile 2, blk 2 is 2_226, on JHC7\n", + "\t2:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 12, pin 0, feedback to tProc input 2\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t3:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 13, pin 0, feedback to tProc input 3\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t4:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 14, pin 0, feedback to tProc input 4\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t5:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 15, pin 0, feedback to tProc input 5\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t6:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 16, pin 0, feedback to tProc input 6\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t7:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 17, pin 0, feedback to tProc input 7\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t8:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 18, pin 0, feedback to tProc input 8\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\t9:\taxis_pfb_readout_v4 - configured by PYNQ\n", + "\t\tfs=2457.600 Msps, decimated=38.400 MHz, 32-bit DDS, range=38.400 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 1024 decimated (26.667 us)\n", + "\t\ttriggered by tport 19, pin 0, feedback to tProc input 9\n", + "\t\tADC tile 2, blk 1 is 1_226, on JHC8\n", + "\n", + "\t8 digital output pins:\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: qick_processor (\"v2\") rev 24, core execution clock 215.040 MHz\n", + "\t\tmemories (words): program 4096, data 16384, waveform 1024\n", + "\t\texternal start pin: PMOD1_0_LS\n", + "\t\texternal stop pin: None\n", + "\n", + "\tDDR4 memory buffer: 1073741824 samples (3.495 sec), 128 samples/transfer\n", + "\t\twired to readouts [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]\n", + "\n", + "\tMR buffer: 8192 samples (3.333 us), wired to readouts [0, 1]\n" + ] + } + ], + "source": [ + "soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/2025-06-15_216_tprocv2r24_standard/qick_216.bit')\n", + "soccfg = soc\n", + "print(soccfg)" + ] + }, + { + "cell_type": "code", + "execution_count": 30, + "id": "a7e9a2f0-2acd-4668-bba4-be18868f9c43", + "metadata": {}, + "outputs": [], + "source": [ + "# ZCU216 standard FW, full-speed gen\n", + "GEN_CH = 0\n", + "RO_CH = 0\n", + "TRIG_TIME = 0.40\n", + "FREQ = 500\n" + ] + }, + { + "cell_type": "markdown", + "id": "bb1f8b6c-563f-48b5-a864-4e9adac68a7d", + "metadata": {}, + "source": [ + "## basic multi-pulse program\n", + "Just a \"reps\" loop, no sweeping - like v1 AveragerProgram.\n", + "\n", + "In v2, you define all of your pulses, and then you can play them as needed. Contrast to v1, where only one pulse could be defined on a generator at a time." + ] + }, + { + "cell_type": "code", + "execution_count": 32, + "id": "ca193c79-0164-4079-9a64-b821725f0da1", + "metadata": {}, + "outputs": [ + { + "data": { + "application/vnd.jupyter.widget-view+json": { + "model_id": "1742f5653e8e4bd3a913edd729c0fb51", + "version_major": 2, + "version_minor": 0 + }, + "text/plain": [ + " 0%| | 0/10 [00:00" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "class MultiPulseProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " \n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " ramp_len = 0.2\n", + " self.add_gauss(ch=gen_ch, name=\"ramp\", sigma=ramp_len/10, length=ramp_len, even_length=True)\n", + " \n", + " self.add_pulse(ch=gen_ch, name=\"myflattop\", ro_ch=ro_ch, \n", + " style=\"flat_top\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " length=0.1,\n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mygaus\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"myconst\", ro_ch=ro_ch, \n", + " style=\"const\", \n", + " length=0.2, \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0,\n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"myflattop2\", ro_ch=ro_ch, \n", + " style=\"flat_top\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " length=0.1,\n", + " phase=90,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_readoutconfig(ch=ro_ch, name=\"myro\", freq=cfg['freq'], gen_ch=gen_ch)\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=ro_ch, name=\"myro\", t=0)\n", + " \n", + " def _body(self, cfg):\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + "\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop\", t=0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mygaus\", t=0.4)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myconst\", t=0.8)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop2\", t=1.2)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mygaus\", t=1.6)\n", + " \n", + "config = {'gen_ch': GEN_CH,\n", + " 'ro_ch': RO_CH,\n", + " 'freq': FREQ,\n", + " 'trig_time': TRIG_TIME,\n", + " 'ro_len': 1.9,\n", + " }\n", + "\n", + "prog = MultiPulseProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "iq_list = prog.acquire_decimated(soc, rounds=10)\n", + "t = prog.get_time_axis(ro_index=0)\n", + "\n", + "plt.plot(t, iq_list[0][:,0], label=\"I value\")\n", + "plt.plot(t, iq_list[0][:,1], label=\"Q value\")\n", + "plt.plot(t, np.abs(iq_list[0].dot([1,1j])), label=\"magnitude\")\n", + "plt.legend()\n", + "plt.ylabel(\"a.u.\")\n", + "plt.xlabel(\"us\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "7966461c-50d5-4268-945b-b0b6942a82e6", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='myro', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=1, name='reps')\n", + "\tTrigger(ros=[0], pins=[0], t=0.4, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 172, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tPulse(ch=0, name='mygaus', t='auto', tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tPulse(ch=0, name='mygaus', t='auto', tag=None, t_params={'t': }, t_regs={'t': 2})\n", + "\tPulse(ch=0, name='mygaus2', t='auto', tag=None, t_params={'t': }, t_regs={'t': 4})\n", + "\tPulse(ch=0, name='mygaus2', t='auto', tag=None, t_params={'t': }, t_regs={'t': 6})\n", + "\tPulse(ch=0, name='mygaus', t='auto', tag=None, t_params={'t': }, t_regs={'t': 9})\n", + "\tPulse(ch=0, name='mygaus', t='auto', tag=None, t_params={'t': }, t_regs={'t': 11})\n", + "\tPulse(ch=0, name='mygaus2', t='auto', tag=None, t_params={'t': }, t_regs={'t': 13})\n", + "\tPulse(ch=0, name='mygaus2', t='auto', tag=None, t_params={'t': }, t_regs={'t': 15})\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 602})\n", + "\tDelay(t=0.5, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 817})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "registers:\n", + "\treps: QickRegisterV2(addr=0, init=None)\n", + "pulses:\n", + "\tmygaus: QickPulse(waveforms=[Waveform(name='mygaus_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=3, conf=8)])\n", + "\tmygaus2: QickPulse(waveforms=[Waveform(name='mygaus2_w0', freq=QickRawParam(par='freq', start=224054700, spans={}, quantize=10, steps={}), phase=QickRawParam(par='phase', start=2147483648, spans={}, quantize=1, steps={}), env=3, gain=QickRawParam(par='gain', start=8191, spans={}, quantize=1, steps={}), length=3, conf=8)])\n", + "\tmyro: QickPulse(waveforms=[Waveform(name='myro_w0', freq=QickRawParam(par='freq', start=-873813330, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&2] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r0 imm #0 \n", + "\treps:\n", + "\t TRIG p0 set @172 \n", + "\t TRIG p9 set @172 \n", + "\t TRIG p10 set @172 \n", + "\t TRIG p0 clr @182 \n", + "\t TRIG p9 clr @182 \n", + "\t TRIG p10 clr @182 \n", + "\t WPORT_WR p0 wmem [&0] @0 \n", + "\t WPORT_WR p0 wmem [&0] @2 \n", + "\t WPORT_WR p0 wmem [&1] @4 \n", + "\t WPORT_WR p0 wmem [&1] @6 \n", + "\t WPORT_WR p0 wmem [&0] @9 \n", + "\t WPORT_WR p0 wmem [&0] @11 \n", + "\t WPORT_WR p0 wmem [&1] @13 \n", + "\t WPORT_WR p0 wmem [&1] @15 \n", + "\t WAIT [&20] @602 time \n", + "\t TIME #817 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t TEST -op(r0 - #0) \n", + "\t JUMP reps -if(NZ) -wr(r0 op) -op(r0 + #1) \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce000420000000000\n", + "4c080000000000d700\n", + "8c6000000000000020\n", + "dda000300000005600\n", + "dda000348000005600\n", + "dda000350000005600\n", + "dda000100000005b00\n", + "dda000148000005b00\n", + "dda000150000005b00\n", + "dce000000000000000\n", + "dce000000000000100\n", + "dce000200000000200\n", + "dce000200000000300\n", + "dce000000000000480\n", + "dce000000000000580\n", + "dce000200000000680\n", + "dce000200000000780\n", + "081100000580012800\n", + "391102600580012800\n", + "4c0800000000019880\n", + "88000000060000008c\n", + "081100001000000000\n", + "398800a010000000a0\n", + "3c0003200000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_00000003_00007ffe_000000_00000000_0d5acdac\n", + "___0008_00000003_00001fff_000003_80000000_0d5acdac\n", + "___0108_00000003_00000000_000000_00000000_cbeaaaae\n" + ] + } + ], + "source": [ + "# print the program - ugly!\n", + "print(prog)\n", + "\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "\n", + "prog.print_sg_mem(sg_idx=0, gen_file=True)\n" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.10.4" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/firmware/notebooks/qick_testbench/tests_generator.ipynb b/firmware/notebooks/qick_testbench/tests_generator.ipynb new file mode 100644 index 000000000..32a4b1b92 --- /dev/null +++ b/firmware/notebooks/qick_testbench/tests_generator.ipynb @@ -0,0 +1,2015 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "32982695-822e-40aa-ac5c-9777a4d94fb2", + "metadata": {}, + "source": [ + "## Load Libraries and Firmware" + ] + }, + { + "cell_type": "code", + "execution_count": 8, + "id": "3b5c048a", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "None\n", + "['/home/dmartin2/Projects/qick_internal_b_43_testbench/qick_lib/', '/home/dmartin2/Projects/qick_internal_b_43_testbench/qick_lib/', '/home/dmartin2/Projects/qick_internal_b_43_testbench/qick_lib/', '/usr/lib64/python39.zip', '/usr/lib64/python3.9', '/usr/lib64/python3.9/lib-dynload', '', '/home/dmartin2/venv/lib64/python3.9/site-packages', '/home/dmartin2/venv/lib/python3.9/site-packages']\n", + "0.2.367\n" + ] + } + ], + "source": [ + "USE_LOCAL_QICK = True\n", + "\n", + "if USE_LOCAL_QICK:\n", + " import sys\n", + " import os\n", + " print(sys.path.insert(0,\"/home/dmartin2/Projects/qick_internal_b_43_testbench/qick_lib/\"))\n", + " print(sys.path)\n", + "\n", + "\n", + "# jupyter setup boilerplate\n", + "%matplotlib inline\n", + "import matplotlib.pyplot as plt\n", + "import numpy as np\n", + "\n", + "from qick import *\n", + "\n", + "# for now, all the tProc v2 classes need to be individually imported (can't use qick.*)\n", + "\n", + "# the main program class\n", + "from qick.asm_v2 import AveragerProgramV2\n", + "# for defining sweeps\n", + "from qick.asm_v2 import QickSpan, QickSweep1D\n", + "\n", + "print(get_version())" + ] + }, + { + "cell_type": "code", + "execution_count": 9, + "id": "ab849bc3", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "QICK running on ZCU216, software version 0.2.367\n", + "\n", + "Firmware configuration (built Fri Aug 29 12:51:57 2025):\n", + "\n", + "\tGlobal clocks (MHz): tProc dispatcher timing 430.080, RF reference 245.760\n", + "\tGroups of related clocks: [tProc timing clock, DAC tile 1, DAC tile 2, DAC tile 3], [DAC tile 0], [ADC tile 2]\n", + "\n", + "\t1 signal generator channels:\n", + "\t0:\taxis_signal_gen_v6 - fs=9584.640 Msps, fabric=599.040 MHz\n", + "\t\tenvelope memory: 65536 complex samples (6.838 us)\n", + "\t\t32-bit DDS, range=9584.640 MHz\n", + "\t\tDAC tile 0, blk 0 is 0_228 on JHC1, or QICK box DAC port 0\n", + "\n", + "\t1 readout channels:\n", + "\t0:\taxis_dyn_readout_v1 - configured by tProc output 4\n", + "\t\tfs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz\n", + "\t\taxis_avg_buffer v1.2 (has edge counter, no weights)\n", + "\t\tmemory 8192 accumulated, 4096 decimated (13.333 us)\n", + "\t\ttriggered by tport 10, pin 0, feedback to tProc input 0\n", + "\t\tADC tile 2, blk 0 is 0_226 on JHC7, or QICK box ADC port 4\n", + "\n", + "\t8 digital output pins:\n", + "\t0:\tPMOD0_0_LS\n", + "\t1:\tPMOD0_1_LS\n", + "\t2:\tPMOD0_2_LS\n", + "\t3:\tPMOD0_3_LS\n", + "\t4:\tPMOD0_4_LS\n", + "\t5:\tPMOD0_5_LS\n", + "\t6:\tPMOD0_6_LS\n", + "\t7:\tPMOD0_7_LS\n", + "\n", + "\ttProc: qick_processor (\"v2\") rev 27, core execution clock 200.000 MHz\n", + "\t\tmemories (words): program 4096, data 16384, waveform 1024\n", + "\t\texternal start pin: None\n", + "\t\texternal stop pin: None\n", + "\n", + "\tDDR4 memory buffer: 1073741824 samples (3.495 sec), 128 samples/transfer\n", + "\t\twired to readouts [0]\n", + "\n", + "\tMR buffer: 8192 samples (3.333 us), wired to readouts [0]\n" + ] + } + ], + "source": [ + "QICK_EMU = True\n", + "# soccfg_file_name = '/home/xilinx/jupyter_notebooks/qick/firmware/testbench/qick_testbench/soccfg.json'\n", + "soccfg_file_name = '../../firmware/testbench/qick_testbench/soccfg.json'\n", + "\n", + "if QICK_EMU is False:\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/2024-09-28_216_tprocv2r21_rfb_standard/qick_216_rfb.bit')\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/2025-06-15_216_tprocv2r24_standard/qick_216.bit')\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250822_1/qick_216.bit')\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250828_1/qick_216.bit')\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250828_2/qick_216.bit')\n", + " # soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250829_1/qick_216.bit')\n", + " soc = QickSoc('/home/xilinx/jupyter_notebooks/fw/qick_tprocv2_216_standard_1ch_250829_2/qick_216.bit')\n", + " soccfg = soc\n", + "\n", + " # Dump Board SoC configuration in json format and create file\n", + " soccfg_json = soc.dump_cfg(gen_file_path=soccfg_file_name)\n", + " # print(soccfg_json)\n", + "else:\n", + " soc = None\n", + " # Load soccfg.json file as a new socemucfg object\n", + " soccfg = QickConfig(cfg=soccfg_file_name)\n", + "\n", + "print(soccfg)" + ] + }, + { + "cell_type": "markdown", + "id": "23efae60", + "metadata": {}, + "source": [ + "## basic multi-pulse program\n", + "Just a \"reps\" loop, no sweeping - like v1 AveragerProgram.\n", + "\n", + "In v2, you define all of your pulses, and then you can play them as needed. Contrast to v1, where only one pulse could be defined on a generator at a time." + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "id": "a56ba99e", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='myro', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=1, name='reps')\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.4, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 172, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tPulse(ch=0, name='myflattop', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tPulse(ch=0, name='mygaus', t=0.4, tag=None, t_params={'t': }, t_regs={'t': 172})\n", + "\tPulse(ch=0, name='myconst', t=0.8, tag=None, t_params={'t': }, t_regs={'t': 344})\n", + "\tPulse(ch=0, name='myflattop2', t=1.2, tag=None, t_params={'t': }, t_regs={'t': 516})\n", + "\tPulse(ch=0, name='mygaus', t=1.6, tag=None, t_params={'t': }, t_regs={'t': 688})\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 990})\n", + "\tDelay(t=0.5, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 1205})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "registers:\n", + "\treps: QickRegisterV2(addr=0, init=None)\n", + "pulses:\n", + "\tmyflattop: QickPulse(waveforms=[Waveform(name='myflattop_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8), Waveform(name='myflattop_w1', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9), Waveform(name='myflattop_w2', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8)])\n", + "\tmygaus: QickPulse(waveforms=[Waveform(name='mygaus_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=120, conf=8)])\n", + "\tmyconst: QickPulse(waveforms=[Waveform(name='myconst_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=120, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tmyflattop2: QickPulse(waveforms=[Waveform(name='myflattop2_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8), Waveform(name='myflattop2_w1', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9), Waveform(name='myflattop2_w2', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8)])\n", + "\tmyro: QickPulse(waveforms=[Waveform(name='myro_w0', freq=QickRawParam(par='freq', start=-174762666, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&8] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r0 imm #0 \n", + "\treps:\n", + "\t TRIG p0 set @172 \n", + "\t TRIG p9 set @172 \n", + "\t TRIG p10 set @172 \n", + "\t TRIG p0 clr @182 \n", + "\t TRIG p9 clr @182 \n", + "\t TRIG p10 clr @182 \n", + "\t WPORT_WR p0 wmem [&0] @0 \n", + "\t WPORT_WR p0 wmem [&1] @0 \n", + "\t WPORT_WR p0 wmem [&2] @0 \n", + "\t WPORT_WR p0 wmem [&3] @172 \n", + "\t WPORT_WR p0 wmem [&4] @344 \n", + "\t WPORT_WR p0 wmem [&5] @516 \n", + "\t WPORT_WR p0 wmem [&6] @516 \n", + "\t WPORT_WR p0 wmem [&7] @516 \n", + "\t WPORT_WR p0 wmem [&3] @688 \n", + "\t WAIT [&21] @990 time \n", + "\t TIME #1205 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t TEST -op(r0 - #0) \n", + "\t JUMP reps -if(NZ) -wr(r0 op) -op(r0 + #1) \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce001020000000000\n", + "4c080000000000d700\n", + "8c6000000000000020\n", + "dda000300000005600\n", + "dda000348000005600\n", + "dda000350000005600\n", + "dda000100000005b00\n", + "dda000148000005b00\n", + "dda000150000005b00\n", + "dce000000000000000\n", + "dce000200000000000\n", + "dce000400000000000\n", + "dce000600000005600\n", + "dce00080000000ac00\n", + "dce000a00000010200\n", + "dce000c00000010200\n", + "dce000e00000010200\n", + "dce000600000015800\n", + "08110000058001ea00\n", + "39110280058001ea00\n", + "4c0800000000025a80\n", + "88000000060000008c\n", + "081100001000000000\n", + "398800a010000000a0\n", + "3c0003400000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_0000003c_00007ffe_000000_00000000_02abc2bc\n", + "___0009_0000003c_00003fff_000000_00000000_02abc2bc\n", + "___0008_0000003c_00007ffe_00003c_00000000_02abc2bc\n", + "___0008_00000078_00007ffe_000000_00000000_02abc2bc\n", + "___0009_00000078_00007ffe_000000_00000000_02abc2bc\n", + "___0008_0000003c_00007ffe_000000_40000000_02abc2bc\n", + "___0009_0000003c_00003fff_000000_40000000_02abc2bc\n", + "___0008_0000003c_00007ffe_00003c_40000000_02abc2bc\n", + "___0108_00000003_00000000_000000_00000000_f5955556\n", + "Dumped SG envelope table memory to file sg_0.mem\n" + ] + } + ], + "source": [ + "GEN_CH = 0\n", + "RO_CH = 0\n", + "TRIG_TIME = 0.40\n", + "FREQ = 100\n", + "# FREQ = 0\n", + "\n", + "class MultiPulseProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " \n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " ramp_len = 0.2\n", + " self.add_gauss(ch=gen_ch, name=\"ramp\", sigma=ramp_len/10, length=ramp_len, even_length=True)\n", + " \n", + " self.add_pulse(ch=gen_ch, name=\"myflattop\", ro_ch=ro_ch, \n", + " style=\"flat_top\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " length=0.1,\n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mygaus\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"myconst\", ro_ch=ro_ch, \n", + " style=\"const\", \n", + " length=0.2, \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0,\n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"myflattop2\", ro_ch=ro_ch, \n", + " style=\"flat_top\", \n", + " envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " length=0.1,\n", + " phase=90,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_readoutconfig(ch=ro_ch, name=\"myro\", freq=cfg['freq'], gen_ch=gen_ch)\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=ro_ch, name=\"myro\", t=0)\n", + " \n", + " def _body(self, cfg):\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + "\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop\", t=0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mygaus\", t=0.4)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myconst\", t=0.8)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop2\", t=1.2)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mygaus\", t=1.6)\n", + " \n", + "config = {'gen_ch': GEN_CH,\n", + " 'ro_ch': RO_CH,\n", + " 'freq': FREQ,\n", + " 'trig_time': TRIG_TIME,\n", + " 'ro_len': 1.9,\n", + " }\n", + "\n", + "prog = MultiPulseProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "if QICK_EMU is False:\n", + " iq_list = prog.acquire_decimated(soc, rounds=1)\n", + " t = prog.get_time_axis(ro_index=0)\n", + "\n", + " plt.plot(t, iq_list[0][:,0], label=\"I value\")\n", + " plt.plot(t, iq_list[0][:,1], label=\"Q value\")\n", + " plt.plot(t, np.abs(iq_list[0].dot([1,1j])), label=\"magnitude\")\n", + " plt.legend()\n", + " plt.ylabel(\"a.u.\")\n", + " plt.xlabel(\"us\")\n", + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0,gen_file=True)" + ] + }, + { + "cell_type": "code", + "execution_count": 11, + "id": "87e69ea7", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='myro', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=1, name='reps')\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.4, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 172, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tPulse(ch=0, name='myflattop', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tPulse(ch=0, name='mygaus', t=0.4, tag=None, t_params={'t': }, t_regs={'t': 172})\n", + "\tPulse(ch=0, name='myconst', t=0.8, tag=None, t_params={'t': }, t_regs={'t': 344})\n", + "\tPulse(ch=0, name='myflattop2', t=1.2, tag=None, t_params={'t': }, t_regs={'t': 516})\n", + "\tPulse(ch=0, name='mygaus', t=1.6, tag=None, t_params={'t': }, t_regs={'t': 688})\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 990})\n", + "\tDelay(t=0.5, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 1205})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "registers:\n", + "\treps: QickRegisterV2(addr=0, init=None)\n", + "pulses:\n", + "\tmyflattop: QickPulse(waveforms=[Waveform(name='myflattop_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8), Waveform(name='myflattop_w1', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9), Waveform(name='myflattop_w2', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8)])\n", + "\tmygaus: QickPulse(waveforms=[Waveform(name='mygaus_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=120, conf=8)])\n", + "\tmyconst: QickPulse(waveforms=[Waveform(name='myconst_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=120, spans={}, quantize=1, steps={}), conf=9)])\n", + "\tmyflattop2: QickPulse(waveforms=[Waveform(name='myflattop2_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8), Waveform(name='myflattop2_w1', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=16383, spans={}, quantize=1, steps={}), length=QickRawParam(par='length', start=60, spans={}, quantize=1, steps={}), conf=9), Waveform(name='myflattop2_w2', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=2, steps={}), length=60, conf=8)])\n", + "\tmyro: QickPulse(waveforms=[Waveform(name='myro_w0', freq=QickRawParam(par='freq', start=-174762666, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&8] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r0 imm #0 \n", + "\treps:\n", + "\t TRIG p0 set @172 \n", + "\t TRIG p9 set @172 \n", + "\t TRIG p10 set @172 \n", + "\t TRIG p0 clr @182 \n", + "\t TRIG p9 clr @182 \n", + "\t TRIG p10 clr @182 \n", + "\t WPORT_WR p0 wmem [&0] @0 \n", + "\t WPORT_WR p0 wmem [&1] @0 \n", + "\t WPORT_WR p0 wmem [&2] @0 \n", + "\t WPORT_WR p0 wmem [&3] @172 \n", + "\t WPORT_WR p0 wmem [&4] @344 \n", + "\t WPORT_WR p0 wmem [&5] @516 \n", + "\t WPORT_WR p0 wmem [&6] @516 \n", + "\t WPORT_WR p0 wmem [&7] @516 \n", + "\t WPORT_WR p0 wmem [&3] @688 \n", + "\t WAIT [&21] @990 time \n", + "\t TIME #1205 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t TEST -op(r0 - #0) \n", + "\t JUMP reps -if(NZ) -wr(r0 op) -op(r0 + #1) \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce001020000000000\n", + "4c080000000000d700\n", + "8c6000000000000020\n", + "dda000300000005600\n", + "dda000348000005600\n", + "dda000350000005600\n", + "dda000100000005b00\n", + "dda000148000005b00\n", + "dda000150000005b00\n", + "dce000000000000000\n", + "dce000200000000000\n", + "dce000400000000000\n", + "dce000600000005600\n", + "dce00080000000ac00\n", + "dce000a00000010200\n", + "dce000c00000010200\n", + "dce000e00000010200\n", + "dce000600000015800\n", + "08110000058001ea00\n", + "39110280058001ea00\n", + "4c0800000000025a80\n", + "88000000060000008c\n", + "081100001000000000\n", + "398800a010000000a0\n", + "3c0003400000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_0000003c_00007ffe_000000_00000000_02abc2bc\n", + "___0009_0000003c_00003fff_000000_00000000_02abc2bc\n", + "___0008_0000003c_00007ffe_00003c_00000000_02abc2bc\n", + "___0008_00000078_00007ffe_000000_00000000_02abc2bc\n", + "___0009_00000078_00007ffe_000000_00000000_02abc2bc\n", + "___0008_0000003c_00007ffe_000000_40000000_02abc2bc\n", + "___0009_0000003c_00003fff_000000_40000000_02abc2bc\n", + "___0008_0000003c_00007ffe_00003c_40000000_02abc2bc\n", + "___0108_00000003_00000000_000000_00000000_f5955556\n", + "Dumped SG envelope table memory to file sg_0.mem\n" + ] + } + ], + "source": [ + "# Compile the experiment\n", + "prog = MultiPulseProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "# Dump the info required to run the experiment in the emulator\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0,gen_file=True)" + ] + }, + { + "cell_type": "markdown", + "id": "7b4a1d73", + "metadata": {}, + "source": [ + "## many envelopes pulses program\n", + "\n", + "Test of several pulses generation using different envelope types (gauss, cosine, triangular, drag)\n" + ] + }, + { + "cell_type": "code", + "execution_count": 12, + "id": "3169d763", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tWriteReg(dst='s_core_w1', src=0)\n", + "\tConfigReadout(ch=0, name='myro', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tDelay(t=1.0, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tOpenLoop(n=1, name='reps')\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=0.4, width=0.023251488095238096, ddr4=True, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 172, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 9, 10})\n", + "\tPulse(ch=0, name='mygauss', t=0, tag=None, t_params={'t': }, t_regs={'t': 0})\n", + "\tPulse(ch=0, name='mycosine', t=0.2, tag=None, t_params={'t': }, t_regs={'t': 86})\n", + "\tPulse(ch=0, name='mytriangle', t=0.4, tag=None, t_params={'t': }, t_regs={'t': 172})\n", + "\tPulse(ch=0, name='mydrag', t=0.8, tag=None, t_params={'t': }, t_regs={'t': 344})\n", + "\tPulse(ch=0, name='mycosine90', t=1, tag=None, t_params={'t': }, t_regs={'t': 430})\n", + "\tPulse(ch=0, name='mycosine180', t=1.2, tag=None, t_params={'t': }, t_regs={'t': 516})\n", + "\tPulse(ch=0, name='mycosine270', t=1.4, tag=None, t_params={'t': }, t_regs={'t': 602})\n", + "\tWait(t=0, auto=True, gens=False, ros=True, tag=None, no_warn=True, t_params={'t': }, t_regs={'t': 1032})\n", + "\tDelay(t=0.5, auto=True, gens=True, ros=True, tag=None, t_params={'t': }, t_regs={'t': 1247})\n", + "\tIncReg(dst='s_core_w1', src=1)\n", + "\tCloseLoop()\n", + "\tEnd()\n", + "registers:\n", + "\treps: QickRegisterV2(addr=0, init=None)\n", + "pulses:\n", + "\tmygauss: QickPulse(waveforms=[Waveform(name='mygauss_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=0, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tmycosine: QickPulse(waveforms=[Waveform(name='mycosine_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=90, conf=8)])\n", + "\tmytriangle: QickPulse(waveforms=[Waveform(name='mytriangle_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=150, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=60, conf=8)])\n", + "\tmydrag: QickPulse(waveforms=[Waveform(name='mydrag_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=0, spans={}, quantize=1, steps={}), env=210, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=90, conf=8)])\n", + "\tmycosine90: QickPulse(waveforms=[Waveform(name='mycosine90_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=1073741824, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=90, conf=8)])\n", + "\tmycosine180: QickPulse(waveforms=[Waveform(name='mycosine180_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=2147483648, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=90, conf=8)])\n", + "\tmycosine270: QickPulse(waveforms=[Waveform(name='mycosine270_w0', freq=QickRawParam(par='freq', start=44810940, spans={}, quantize=np.int64(10), steps={}), phase=QickRawParam(par='phase', start=-1073741824, spans={}, quantize=1, steps={}), env=60, gain=QickRawParam(par='gain', start=32766, spans={}, quantize=1, steps={}), length=90, conf=8)])\n", + "\tmyro: QickPulse(waveforms=[Waveform(name='myro_w0', freq=QickRawParam(par='freq', start=-174762666, spans={}, quantize=-39, steps={}), phase=0, env=0, gain=0, length=3, conf=264)])\n", + "expanded ASM:\n", + "\t NOP \n", + "\t REG_WR s12 imm #0 \n", + "\t WPORT_WR p4 wmem [&7] @0 \n", + "\t TIME #430 inc_ref \n", + "\t REG_WR r0 imm #0 \n", + "\treps:\n", + "\t TRIG p0 set @172 \n", + "\t TRIG p9 set @172 \n", + "\t TRIG p10 set @172 \n", + "\t TRIG p0 clr @182 \n", + "\t TRIG p9 clr @182 \n", + "\t TRIG p10 clr @182 \n", + "\t WPORT_WR p0 wmem [&0] @0 \n", + "\t WPORT_WR p0 wmem [&1] @86 \n", + "\t WPORT_WR p0 wmem [&2] @172 \n", + "\t WPORT_WR p0 wmem [&3] @344 \n", + "\t WPORT_WR p0 wmem [&4] @430 \n", + "\t WPORT_WR p0 wmem [&5] @516 \n", + "\t WPORT_WR p0 wmem [&6] @602 \n", + "\t WAIT [&19] @1032 time \n", + "\t TIME #1247 inc_ref \n", + "\t REG_WR s12 op -op(s12 + #1) \n", + "\t TEST -op(r0 - #0) \n", + "\t JUMP reps -if(NZ) -wr(r0 op) -op(r0 + #1) \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000000000000c\n", + "dce000e20000000000\n", + "4c080000000000d700\n", + "8c6000000000000020\n", + "dda000300000005600\n", + "dda000348000005600\n", + "dda000350000005600\n", + "dda000100000005b00\n", + "dda000148000005b00\n", + "dda000150000005b00\n", + "dce000000000000000\n", + "dce000200000002b00\n", + "dce000400000005600\n", + "dce00060000000ac00\n", + "dce00080000000d700\n", + "dce000a00000010200\n", + "dce000c00000012d00\n", + "08110000058001ff00\n", + "39110240058001ff00\n", + "4c0800000000026f80\n", + "88000000060000008c\n", + "081100001000000000\n", + "398800a010000000a0\n", + "3c0003000000000000\n", + "// WMEM content\n", + "// CONF_ LEN_ GAIN_ ENV_ PHASE_ FREQ\n", + "___0008_0000003c_00007ffe_000000_00000000_02abc2bc\n", + "___0008_0000005a_00007ffe_00003c_00000000_02abc2bc\n", + "___0008_0000003c_00007ffe_000096_00000000_02abc2bc\n", + "___0008_0000005a_00007ffe_0000d2_00000000_02abc2bc\n", + "___0008_0000005a_00007ffe_00003c_40000000_02abc2bc\n", + "___0008_0000005a_00007ffe_00003c_80000000_02abc2bc\n", + "___0008_0000005a_00007ffe_00003c_c0000000_02abc2bc\n", + "___0108_00000003_00000000_000000_00000000_f5955556\n", + "Dumped SG envelope table memory to file sg_0.mem\n" + ] + } + ], + "source": [ + "GEN_CH = 0\n", + "RO_CH = 0\n", + "TRIG_TIME = 0.40\n", + "FREQ = 100\n", + "\n", + "class ManyEnvelopesPulseProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " \n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " gauss_len = 0.1\n", + " self.add_gauss(ch=gen_ch, name=\"gauss\", sigma=gauss_len/10, length=gauss_len, even_length=True)\n", + " cosine_len = 0.15\n", + " self.add_cosine(ch=gen_ch, name=\"cosine\", length=cosine_len, even_length=True)\n", + " triangle_len = 0.1\n", + " self.add_triangle(ch=gen_ch, name=\"triangle\", length=triangle_len, even_length=True)\n", + " drag_len = 0.15\n", + " self.add_DRAG(ch=gen_ch, name=\"drag\", sigma=drag_len/10, delta=10, alpha=0.5, length=drag_len, even_length=True)\n", + " \n", + " self.add_pulse(ch=gen_ch, name=\"mygauss\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"gauss\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mycosine\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"cosine\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mytriangle\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"triangle\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mydrag\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"drag\", \n", + " freq=cfg['freq'], \n", + " phase=0,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mycosine90\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"cosine\", \n", + " freq=cfg['freq'], \n", + " phase=90,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mycosine180\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"cosine\", \n", + " freq=cfg['freq'], \n", + " phase=180,\n", + " gain=1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"mycosine270\", ro_ch=ro_ch, \n", + " style=\"arb\", \n", + " envelope=\"cosine\", \n", + " freq=cfg['freq'], \n", + " phase=-90,\n", + " gain=1.0, \n", + " )\n", + "\n", + "\n", + "\n", + " self.add_readoutconfig(ch=ro_ch, name=\"myro\", freq=cfg['freq'], gen_ch=gen_ch)\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=ro_ch, name=\"myro\", t=0)\n", + " \n", + " def _body(self, cfg):\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + "\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mygauss\", t=0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mycosine\", t=0.2)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mytriangle\", t=0.4)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mydrag\", t=0.8)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mycosine90\", t=1)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mycosine180\", t=1.2)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mycosine270\", t=1.4)\n", + "\n", + "config = {'gen_ch': GEN_CH,\n", + " 'ro_ch': RO_CH,\n", + " 'freq': FREQ,\n", + " 'trig_time': TRIG_TIME,\n", + " 'ro_len': 2.0,\n", + " }\n", + "\n", + "prog = ManyEnvelopesPulseProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "if QICK_EMU is False:\n", + " iq_list = prog.acquire_decimated(soc, rounds=1)\n", + " t = prog.get_time_axis(ro_index=0)\n", + "\n", + " plt.plot(t, iq_list[0][:,0], label=\"I value\")\n", + " plt.plot(t, iq_list[0][:,1], label=\"Q value\")\n", + " plt.plot(t, np.abs(iq_list[0].dot([1,1j])), label=\"magnitude\")\n", + " plt.legend()\n", + " plt.ylabel(\"a.u.\")\n", + " plt.xlabel(\"us\")\n", + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0,gen_file=True)" + ] + }, + { + "cell_type": "markdown", + "id": "46841009", + "metadata": { + "slideshow": { + "slide_type": "notes" + } + }, + "source": [ + "## tProc basic functionality\n", + "Write Data Registers" + ] + }, + { + "cell_type": "code", + "execution_count": 13, + "id": "d4b46563", + "metadata": {}, + "outputs": [ + { + "name": "stderr", + "output_type": "stream", + "text": [ + "Readout time 9 appears to conflict with previous readout ending at 104.796782?\n", + "Readout time 19 appears to conflict with previous readout ending at 109.558687?\n", + "Readout time 38 appears to conflict with previous readout ending at 119.082496?\n", + "Readout time 76 appears to conflict with previous readout ending at 138.130115?\n", + "Readout time 152 appears to conflict with previous readout ending at 176.225353?\n", + "Readout time 1 appears to conflict with previous readout ending at 100.034877?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n", + "Readout time 1 appears to conflict with previous readout ending at 101.000000?\n" + ] + }, + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tLabel(label='reg_wr_test')\n", + "\tWriteReg(dst='r0', src=12345678)\n", + "\tWriteReg(dst='r1', src=12345678)\n", + "\tWriteReg(dst='r2', src=12345678)\n", + "\tWriteReg(dst='r3', src=12345678)\n", + "\tWriteReg(dst='r4', src=12345678)\n", + "\tWriteReg(dst='r5', src=12345678)\n", + "\tWriteReg(dst='r6', src=12345678)\n", + "\tWriteReg(dst='r7', src=12345678)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tWriteReg(dst='r8', src=12345678)\n", + "\tWriteReg(dst='r9', src=12345678)\n", + "\tWriteReg(dst='r10', src=12345678)\n", + "\tWriteReg(dst='r11', src=12345678)\n", + "\tWriteReg(dst='r12', src=12345678)\n", + "\tWriteReg(dst='r13', src=12345678)\n", + "\tWriteReg(dst='r14', src=12345678)\n", + "\tWriteReg(dst='r15', src=12345678)\n", + "\tWait(t=2, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 860})\n", + "\tWriteReg(dst='r0', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r1', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r2', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r3', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r4', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r5', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r6', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r7', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r8', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r9', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r10', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r11', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r12', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r13', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r14', src='s_zero')\n", + "\tWait(t=0.1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 43})\n", + "\tWriteReg(dst='r15', src='s_zero')\n", + "\tLabel(label='time_test')\n", + "\tWait(t=3, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 1290})\n", + "\tWriteReg(dst='r15', src=11)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=4.7967819940476195, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 2063, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=12)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=9.558686755952381, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 4111, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=13)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=19.082496279761905, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 8207, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=14)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=38.130115327380956, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 16399, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=15)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=76.22535342261905, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 32783, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=16)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=152.41582961309524, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 65551, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=17)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=304.79678199404765, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 131087, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=18)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=609.5586867559524, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 262159, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=19)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1219.082496279762, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 524303, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=20)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=2438.130115327381, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 1048591, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=21)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=4876.225353422619, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 2097167, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=22)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=9752.415829613095, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 4194319, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=23)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=19504.79678199405, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 8388623, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=24)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=39009.558686755954, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 16777231, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=25)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=78019.08249627976, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 33554447, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=26)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=156038.1301153274, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 67108879, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=27)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=312076.22535342263, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 134217743, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=28)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=624152.4158296131, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 268435471, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=29)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1248304.7967819942, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 536870927, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=30)\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=2496609.558686756, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 1073741839, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWait(t=2496609.523809524, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 1073741824})\n", + "\tDelay(t=2496609.523809524, auto=False, tag=None, t_params={'t': }, t_regs={'t': 1073741824})\n", + "\tWriteReg(dst='r15', src=31)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=32)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=33)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=34)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=35)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=36)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=37)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=38)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=39)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=40)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=41)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=42)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=43)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=44)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=45)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=46)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=47)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tWriteReg(dst='r15', src=48)\n", + "\tWait(t=1, auto=False, tag=None, no_warn=False, t_params={'t': }, t_regs={'t': 430})\n", + "\tTrigger(ros=[0], tts=[], pins=[0], t=1, width=0.023251488095238096, ddr4=False, mr=False, tag=None, t_params={'t': , 'width': }, t_regs={'t': 430, 'width': 10}, outdict=defaultdict(, {}), trigset={0, 10})\n", + "\tEnd()\n", + "registers:\n", + "\tscratch: QickRegisterV2(addr=0, init=None)\n", + "pulses:\n", + "expanded ASM:\n", + "\treg_wr_test:\n", + "\t NOP \n", + "\treg_wr_test:\n", + "\t REG_WR r0 imm #12345678 \n", + "\t REG_WR r1 imm #12345678 \n", + "\t REG_WR r2 imm #12345678 \n", + "\t REG_WR r3 imm #12345678 \n", + "\t REG_WR r4 imm #12345678 \n", + "\t REG_WR r5 imm #12345678 \n", + "\t REG_WR r6 imm #12345678 \n", + "\t REG_WR r7 imm #12345678 \n", + "\t WAIT [&10] @430 time \n", + "\t REG_WR r8 imm #12345678 \n", + "\t REG_WR r9 imm #12345678 \n", + "\t REG_WR r10 imm #12345678 \n", + "\t REG_WR r11 imm #12345678 \n", + "\t REG_WR r12 imm #12345678 \n", + "\t REG_WR r13 imm #12345678 \n", + "\t REG_WR r14 imm #12345678 \n", + "\t REG_WR r15 imm #12345678 \n", + "\t WAIT [&20] @860 time \n", + "\t REG_WR r0 op -op(s0) \n", + "\t WAIT [&23] @43 time \n", + "\t REG_WR r1 op -op(s0) \n", + "\t WAIT [&26] @43 time \n", + "\t REG_WR r2 op -op(s0) \n", + "\t WAIT [&29] @43 time \n", + "\t REG_WR r3 op -op(s0) \n", + "\t WAIT [&32] @43 time \n", + "\t REG_WR r4 op -op(s0) \n", + "\t WAIT [&35] @43 time \n", + "\t REG_WR r5 op -op(s0) \n", + "\t WAIT [&38] @43 time \n", + "\t REG_WR r6 op -op(s0) \n", + "\t WAIT [&41] @43 time \n", + "\t REG_WR r7 op -op(s0) \n", + "\t WAIT [&44] @43 time \n", + "\t REG_WR r8 op -op(s0) \n", + "\t WAIT [&47] @43 time \n", + "\t REG_WR r9 op -op(s0) \n", + "\t WAIT [&50] @43 time \n", + "\t REG_WR r10 op -op(s0) \n", + "\t WAIT [&53] @43 time \n", + "\t REG_WR r11 op -op(s0) \n", + "\t WAIT [&56] @43 time \n", + "\t REG_WR r12 op -op(s0) \n", + "\t WAIT [&59] @43 time \n", + "\t REG_WR r13 op -op(s0) \n", + "\t WAIT [&62] @43 time \n", + "\t REG_WR r14 op -op(s0) \n", + "\t WAIT [&65] @43 time \n", + "\t REG_WR r15 op -op(s0) \n", + "\ttime_test:\n", + "\t WAIT [&68] @1290 time \n", + "\t REG_WR r15 imm #11 \n", + "\t TRIG p0 set @2063 \n", + "\t TRIG p10 set @2063 \n", + "\t TRIG p0 clr @2073 \n", + "\t TRIG p10 clr @2073 \n", + "\t REG_WR r15 imm #12 \n", + "\t TRIG p0 set @4111 \n", + "\t TRIG p10 set @4111 \n", + "\t TRIG p0 clr @4121 \n", + "\t TRIG p10 clr @4121 \n", + "\t REG_WR r15 imm #13 \n", + "\t TRIG p0 set @8207 \n", + "\t TRIG p10 set @8207 \n", + "\t TRIG p0 clr @8217 \n", + "\t TRIG p10 clr @8217 \n", + "\t REG_WR r15 imm #14 \n", + "\t TRIG p0 set @16399 \n", + "\t TRIG p10 set @16399 \n", + "\t TRIG p0 clr @16409 \n", + "\t TRIG p10 clr @16409 \n", + "\t REG_WR r15 imm #15 \n", + "\t TRIG p0 set @32783 \n", + "\t TRIG p10 set @32783 \n", + "\t TRIG p0 clr @32793 \n", + "\t TRIG p10 clr @32793 \n", + "\t REG_WR r15 imm #16 \n", + "\t TRIG p0 set @65551 \n", + "\t TRIG p10 set @65551 \n", + "\t TRIG p0 clr @65561 \n", + "\t TRIG p10 clr @65561 \n", + "\t REG_WR r15 imm #17 \n", + "\t TRIG p0 set @131087 \n", + "\t TRIG p10 set @131087 \n", + "\t TRIG p0 clr @131097 \n", + "\t TRIG p10 clr @131097 \n", + "\t REG_WR r15 imm #18 \n", + "\t TRIG p0 set @262159 \n", + "\t TRIG p10 set @262159 \n", + "\t TRIG p0 clr @262169 \n", + "\t TRIG p10 clr @262169 \n", + "\t REG_WR r15 imm #19 \n", + "\t TRIG p0 set @524303 \n", + "\t TRIG p10 set @524303 \n", + "\t TRIG p0 clr @524313 \n", + "\t TRIG p10 clr @524313 \n", + "\t REG_WR r15 imm #20 \n", + "\t TRIG p0 set @1048591 \n", + "\t TRIG p10 set @1048591 \n", + "\t TRIG p0 clr @1048601 \n", + "\t TRIG p10 clr @1048601 \n", + "\t REG_WR r15 imm #21 \n", + "\t TRIG p0 set @2097167 \n", + "\t TRIG p10 set @2097167 \n", + "\t TRIG p0 clr @2097177 \n", + "\t TRIG p10 clr @2097177 \n", + "\t REG_WR r15 imm #22 \n", + "\t TRIG p0 set @4194319 \n", + "\t TRIG p10 set @4194319 \n", + "\t TRIG p0 clr @4194329 \n", + "\t TRIG p10 clr @4194329 \n", + "\t REG_WR r15 imm #23 \n", + "\t TRIG p0 set @8388623 \n", + "\t TRIG p10 set @8388623 \n", + "\t TRIG p0 clr @8388633 \n", + "\t TRIG p10 clr @8388633 \n", + "\t REG_WR r15 imm #24 \n", + "\t TRIG p0 set @16777231 \n", + "\t TRIG p10 set @16777231 \n", + "\t TRIG p0 clr @16777241 \n", + "\t TRIG p10 clr @16777241 \n", + "\t REG_WR r15 imm #25 \n", + "\t TRIG p0 set @33554447 \n", + "\t TRIG p10 set @33554447 \n", + "\t TRIG p0 clr @33554457 \n", + "\t TRIG p10 clr @33554457 \n", + "\t REG_WR r15 imm #26 \n", + "\t TRIG p0 set @67108879 \n", + "\t TRIG p10 set @67108879 \n", + "\t TRIG p0 clr @67108889 \n", + "\t TRIG p10 clr @67108889 \n", + "\t REG_WR r15 imm #27 \n", + "\t TRIG p0 set @134217743 \n", + "\t TRIG p10 set @134217743 \n", + "\t TRIG p0 clr @134217753 \n", + "\t TRIG p10 clr @134217753 \n", + "\t REG_WR r15 imm #28 \n", + "\t TRIG p0 set @268435471 \n", + "\t TRIG p10 set @268435471 \n", + "\t TRIG p0 clr @268435481 \n", + "\t TRIG p10 clr @268435481 \n", + "\t REG_WR r15 imm #29 \n", + "\t TRIG p0 set @536870927 \n", + "\t TRIG p10 set @536870927 \n", + "\t TRIG p0 clr @536870937 \n", + "\t TRIG p10 clr @536870937 \n", + "\t REG_WR r15 imm #30 \n", + "\t TRIG p0 set @1073741839 \n", + "\t TRIG p10 set @1073741839 \n", + "\t TRIG p0 clr @1073741849 \n", + "\t TRIG p10 clr @1073741849 \n", + "\t REG_WR r0 imm #1073741814 \n", + "\t TEST -op(s11 - r0) \n", + "\t JUMP HERE -if(S) -op(s11 - r0) -uf \n", + "\t TIME #1073741824 inc_ref \n", + "\t REG_WR r15 imm #31 \n", + "\t WAIT [&175] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #32 \n", + "\t WAIT [&182] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #33 \n", + "\t WAIT [&189] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #34 \n", + "\t WAIT [&196] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #35 \n", + "\t WAIT [&203] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #36 \n", + "\t WAIT [&210] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #37 \n", + "\t WAIT [&217] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #38 \n", + "\t WAIT [&224] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #39 \n", + "\t WAIT [&231] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #40 \n", + "\t WAIT [&238] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #41 \n", + "\t WAIT [&245] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #42 \n", + "\t WAIT [&252] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #43 \n", + "\t WAIT [&259] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #44 \n", + "\t WAIT [&266] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #45 \n", + "\t WAIT [&273] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #46 \n", + "\t WAIT [&280] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #47 \n", + "\t WAIT [&287] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t REG_WR r15 imm #48 \n", + "\t WAIT [&294] @430 time \n", + "\t TRIG p0 set @430 \n", + "\t TRIG p10 set @430 \n", + "\t TRIG p0 clr @440 \n", + "\t TRIG p10 clr @440 \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c600000005e30a720\n", + "8c600000005e30a721\n", + "8c600000005e30a722\n", + "8c600000005e30a723\n", + "8c600000005e30a724\n", + "8c600000005e30a725\n", + "8c600000005e30a726\n", + "8c600000005e30a727\n", + "08110000058000d200\n", + "39110120058000d200\n", + "8c600000005e30a728\n", + "8c600000005e30a729\n", + "8c600000005e30a72a\n", + "8c600000005e30a72b\n", + "8c600000005e30a72c\n", + "8c600000005e30a72d\n", + "8c600000005e30a72e\n", + "8c600000005e30a72f\n", + "08110000058001a900\n", + "39110260058001a900\n", + "840000000000000020\n", + "081100000580001080\n", + "391102c00580001080\n", + "840000000000000021\n", + "081100000580001080\n", + "391103200580001080\n", + "840000000000000022\n", + "081100000580001080\n", + "391103800580001080\n", + "840000000000000023\n", + "081100000580001080\n", + "391103e00580001080\n", + "840000000000000024\n", + "081100000580001080\n", + "391104400580001080\n", + "840000000000000025\n", + "081100000580001080\n", + "391104a00580001080\n", + "840000000000000026\n", + "081100000580001080\n", + "391105000580001080\n", + "840000000000000027\n", + "081100000580001080\n", + "391105600580001080\n", + "840000000000000028\n", + "081100000580001080\n", + "391105c00580001080\n", + "840000000000000029\n", + "081100000580001080\n", + "391106200580001080\n", + "84000000000000002a\n", + "081100000580001080\n", + "391106800580001080\n", + "84000000000000002b\n", + "081100000580001080\n", + "391106e00580001080\n", + "84000000000000002c\n", + "081100000580001080\n", + "391107400580001080\n", + "84000000000000002d\n", + "081100000580001080\n", + "391107a00580001080\n", + "84000000000000002e\n", + "081100000580001080\n", + "391108000580001080\n", + "84000000000000002f\n", + "081100000580028000\n", + "391108600580028000\n", + "8c60000000000005af\n", + "dda000300000040780\n", + "dda000350000040780\n", + "dda000100000040c80\n", + "dda000150000040c80\n", + "8c600000000000062f\n", + "dda000300000080780\n", + "dda000350000080780\n", + "dda000100000080c80\n", + "dda000150000080c80\n", + "8c60000000000006af\n", + "dda000300000100780\n", + "dda000350000100780\n", + "dda000100000100c80\n", + "dda000150000100c80\n", + "8c600000000000072f\n", + "dda000300000200780\n", + "dda000350000200780\n", + "dda000100000200c80\n", + "dda000150000200c80\n", + "8c60000000000007af\n", + "dda000300000400780\n", + "dda000350000400780\n", + "dda000100000400c80\n", + "dda000150000400c80\n", + "8c600000000000082f\n", + "dda000300000800780\n", + "dda000350000800780\n", + "dda000100000800c80\n", + "dda000150000800c80\n", + "8c60000000000008af\n", + "dda000300001000780\n", + "dda000350001000780\n", + "dda000100001000c80\n", + "dda000150001000c80\n", + "8c600000000000092f\n", + "dda000300002000780\n", + "dda000350002000780\n", + "dda000100002000c80\n", + "dda000150002000c80\n", + "8c60000000000009af\n", + "dda000300004000780\n", + "dda000350004000780\n", + "dda000100004000c80\n", + "dda000150004000c80\n", + "8c6000000000000a2f\n", + "dda000300008000780\n", + "dda000350008000780\n", + "dda000100008000c80\n", + "dda000150008000c80\n", + "8c6000000000000aaf\n", + "dda000300010000780\n", + "dda000350010000780\n", + "dda000100010000c80\n", + "dda000150010000c80\n", + "8c6000000000000b2f\n", + "dda000300020000780\n", + "dda000350020000780\n", + "dda000100020000c80\n", + "dda000150020000c80\n", + "8c6000000000000baf\n", + "dda000300040000780\n", + "dda000350040000780\n", + "dda000100040000c80\n", + "dda000150040000c80\n", + "8c6000000000000c2f\n", + "dda000300080000780\n", + "dda000350080000780\n", + "dda000100080000c80\n", + "dda000150080000c80\n", + "8c6000000000000caf\n", + "dda000300100000780\n", + "dda000350100000780\n", + "dda000100100000c80\n", + "dda000150100000c80\n", + "8c6000000000000d2f\n", + "dda000300200000780\n", + "dda000350200000780\n", + "dda000100200000c80\n", + "dda000150200000c80\n", + "8c6000000000000daf\n", + "dda000300400000780\n", + "dda000350400000780\n", + "dda000100400000c80\n", + "dda000150400000c80\n", + "8c6000000000000e2f\n", + "dda000300800000780\n", + "dda000350800000780\n", + "dda000100800000c80\n", + "dda000150800000c80\n", + "8c6000000000000eaf\n", + "dda000301000000780\n", + "dda000351000000780\n", + "dda000101000000c80\n", + "dda000151000000c80\n", + "8c6000000000000f2f\n", + "dda000302000000780\n", + "dda000352000000780\n", + "dda000102000000c80\n", + "dda000152000000c80\n", + "8c6000001ffffffb20\n", + "041100000590000000\n", + "351115600590000000\n", + "4c0800002000000000\n", + "8c6000000000000faf\n", + "08110000058000d200\n", + "391115c0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000102f\n", + "08110000058000d200\n", + "391116a0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000010af\n", + "08110000058000d200\n", + "39111780058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000112f\n", + "08110000058000d200\n", + "39111860058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000011af\n", + "08110000058000d200\n", + "39111940058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000122f\n", + "08110000058000d200\n", + "39111a20058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000012af\n", + "08110000058000d200\n", + "39111b00058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000132f\n", + "08110000058000d200\n", + "39111be0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000013af\n", + "08110000058000d200\n", + "39111cc0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000142f\n", + "08110000058000d200\n", + "39111da0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000014af\n", + "08110000058000d200\n", + "39111e80058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000152f\n", + "08110000058000d200\n", + "39111f60058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000015af\n", + "08110000058000d200\n", + "39112040058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000162f\n", + "08110000058000d200\n", + "39112120058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000016af\n", + "08110000058000d200\n", + "39112200058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000172f\n", + "08110000058000d200\n", + "391122e0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c60000000000017af\n", + "08110000058000d200\n", + "391123c0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "8c600000000000182f\n", + "08110000058000d200\n", + "391124a0058000d200\n", + "dda00030000000d700\n", + "dda00035000000d700\n", + "dda00010000000dc00\n", + "dda00015000000dc00\n", + "3c0025600000000000\n" + ] + } + ], + "source": [ + "from qick.asm_v2 import QickProgramV2\n", + "\n", + "prog = QickProgramV2(soccfg)\n", + "prog.declare_readout(ch=0, length=100)\n", + "prog.label('reg_wr_test')\n", + "# Write all the Data registers with some value\n", + "prog.write_reg(dst='r0', src=12345678)\n", + "prog.write_reg(dst='r1', src=12345678)\n", + "prog.write_reg(dst='r2', src=12345678)\n", + "prog.write_reg(dst='r3', src=12345678)\n", + "prog.write_reg(dst='r4', src=12345678)\n", + "prog.write_reg(dst='r5', src=12345678)\n", + "prog.write_reg(dst='r6', src=12345678)\n", + "prog.write_reg(dst='r7', src=12345678)\n", + "prog.wait(t=1)\n", + "prog.write_reg(dst='r8', src=12345678)\n", + "prog.write_reg(dst='r9', src=12345678)\n", + "prog.write_reg(dst='r10', src=12345678)\n", + "prog.write_reg(dst='r11', src=12345678)\n", + "prog.write_reg(dst='r12', src=12345678)\n", + "prog.write_reg(dst='r13', src=12345678)\n", + "prog.write_reg(dst='r14', src=12345678)\n", + "prog.write_reg(dst='r15', src=12345678)\n", + "# Write all the Data registers to 0\n", + "prog.wait(t=2)\n", + "prog.write_reg(dst='r0', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r1', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r2', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r3', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r4', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r5', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r6', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r7', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r8', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r9', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r10', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r11', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r12', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r13', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r14', src='s_zero')\n", + "prog.wait(t=0.1)\n", + "prog.write_reg(dst='r15', src='s_zero')\n", + "\n", + "prog.label('time_test')\n", + "prog.wait(t=3)\n", + "# Test the Dispatcher execution time\n", + "for N in range(11,31):\n", + " prog.write_reg(dst='r15', src=N)\n", + " prog.trigger(ros=[0], pins=[0], t=prog.cycles2us(2**N+15))\n", + "\n", + "# Increase usr_time to test upper time bits\n", + "# Need to force internal register because tProc can't write it directly\n", + "# use an internal register to sync the testbench\n", + "# Wait for time to be 2**30\n", + "prog.wait(t=prog.cycles2us(2**30))\n", + "# Increase reference to 2**30\n", + "prog.delay(t=prog.cycles2us(2**30))\n", + "\n", + "for N in range(31,49):\n", + " prog.write_reg(dst='r15', src=N)\n", + " # Force reference from testbench to be 2**N\n", + " # prog.delay(t=prog.cycles2us(2**N))\n", + " # Wait 1us\n", + " prog.wait(t=1)\n", + " # Push trigger after another 1us\n", + " prog.trigger(ros=[0], pins=[0], t=1)\n", + "prog.end()\n", + "\n", + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n" + ] + }, + { + "cell_type": "markdown", + "id": "a48c1b1d", + "metadata": {}, + "source": [ + "## Test issue 359" + ] + }, + { + "cell_type": "code", + "execution_count": 14, + "id": "0ff8d24e", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "macros:\n", + "\tLabel(label='arith_test')\n", + "\tWriteReg(dst='r0', src=10)\n", + "\tWriteReg(dst='r1', src=3)\n", + "\tAsmInst(inst={'CMD': 'PA', 'C_OP': '3', 'R1': 'r0', 'R2': 'r1'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'PB', 'C_OP': '3', 'R1': 's6', 'R2': 'r0', 'R3': 'r1'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tAsmInst(inst={'CMD': 'NOP'}, addr_inc=1)\n", + "\tWriteReg(dst='r2', src=1234)\n", + "\tWriteReg(dst='r3', src='s6')\n", + "\tWriteReg(dst='r4', src='s7')\n", + "\tEnd()\n", + "registers:\n", + "pulses:\n", + "expanded ASM:\n", + "\tarith_test:\n", + "\t NOP \n", + "\tarith_test:\n", + "\t REG_WR r0 imm #10 \n", + "\t REG_WR r1 imm #3 \n", + "\t PA 3 r0 r1 \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t PB 3 s6 r0 r1 \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t NOP \n", + "\t REG_WR r2 imm #1234 \n", + "\t REG_WR r3 op -op(s6) \n", + "\t REG_WR r4 op -op(s7) \n", + "\t JUMP HERE \n", + "// PMEM content\n", + "000000000000000000\n", + "8c6000000000000520\n", + "8c60000000000001a1\n", + "644300001010800000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "646304200310000000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "000000000000000000\n", + "8c6000000000026922\n", + "840000000300000023\n", + "840000000380000024\n", + "3c0002400000000000\n" + ] + } + ], + "source": [ + "from qick.asm_v2 import QickProgramV2, AsmInst\n", + "\n", + "prog = QickProgramV2(soccfg)\n", + "prog.declare_readout(ch=0, length=100)\n", + "prog.label('arith_test')\n", + "prog.write_reg(dst='r0', src=10)\n", + "prog.write_reg(dst='r1', src=3)\n", + "# inst = AsmInst(inst={'CMD':\"REG_WR\", 'DST': 's2', 'SRC':'imm', 'LIT':'#49'}, addr_inc=1)\n", + "# prog.append_macro(inst)\n", + "# inst = AsmInst(inst={'CMD':\"ARITH\", 'C_OP': 'T', 'R1':'r0', 'R2':'r1'}, addr_inc=1)\n", + "# prog.append_macro(inst)\n", + "# inst = AsmInst(inst={'CMD': 'JUMP', 'IF': 'NF', 'ADDR': '&5'}, addr_inc=1)\n", + "# prog.append_macro(inst)\n", + "inst = AsmInst(inst={'CMD': 'PA', 'C_OP': '3', 'R1':'r0', 'R2':'r1'}, addr_inc=1)\n", + "prog.append_macro(inst)\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "inst = AsmInst(inst={'CMD': 'PB', 'C_OP': '3', 'R1':'s6', 'R2':'r0', 'R3':'r1'}, addr_inc=1)\n", + "prog.append_macro(inst)\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.nop()\n", + "prog.write_reg(dst='r2', src=1234)\n", + "prog.write_reg(dst='r3', src='s6')\n", + "prog.write_reg(dst='r4', src='s7')\n", + "\n", + "prog.end()\n", + "\n", + "print(prog)\n", + "\n", + "prog.print_pmem2hex()" + ] + }, + { + "cell_type": "markdown", + "id": "a5b08f06", + "metadata": {}, + "source": [ + "## Test issue 361" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "0ffc8fcb", + "metadata": {}, + "outputs": [], + "source": [ + "class RampProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " \n", + " self.add_triangle(gen_ch, \"myenv\", cfg['pulse_len'])\n", + " self.add_pulse(ch=gen_ch,\n", + " name=\"mypulse\",\n", + " ro_ch=ro_ch,\n", + " style=\"arb\",\n", + " freq=cfg['freq'],\n", + " envelope=\"myenv\",\n", + " phase=cfg['phase'],\n", + " gain=cfg['gain'],\n", + " )\n", + "\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " self.add_readoutconfig(ch=ro_ch,\n", + " name=\"myro\",\n", + " freq=cfg['freq'],\n", + " gen_ch=gen_ch)\n", + "\n", + " self.send_readoutconfig(ch=ro_ch,\n", + " name=\"myro\",\n", + " t=0)\n", + "\n", + " def _body(self, cfg):\n", + " self.delay(1.0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mypulse\", t=0)\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + " \n", + "config = \\\n", + "{\n", + " 'gen_ch': 0,\n", + " 'ro_ch': 0,\n", + " 'freq': 0,\n", + " 'trig_time': 0.44,\n", + " 'ro_len': 0.05,\n", + " 'pulse_len': 0.1,\n", + " 'gain': 1.0,\n", + " 'phase': 0.0\n", + "}\n", + "\n", + "prog = RampProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "# Test the decimated buffer\n", + "iq_list = prog.acquire_decimated(soc)\n", + "plt.plot(iq_list[0][:,0], label='I')\n", + "plt.plot(iq_list[0][:,1], label='Q')\n", + "plt.xlabel('time [samples]')\n", + "plt.ylabel('amplitude [arb. units]')\n", + "plt.legend()\n", + "\n", + "# print(iq_list[:10])\n", + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "# prog.print_sg_mem(sg_idx=0, gen_file=True)\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "222a4d5d", + "metadata": {}, + "outputs": [], + "source": [ + "# Start Debug Bridge Server if present\n", + "try:\n", + " bridge = soc._get_block('debug_bridge_0')\n", + " bridge.start_xvc_server(bufferLen=4096, serverAddress=\"0.0.0.0\", serverPort=2542, reconnect=True, verbose=True)\n", + "\n", + "except:\n", + " print('Debug blocks not found')" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "74462314", + "metadata": {}, + "outputs": [], + "source": [ + "## Do not forget to stop the XVC server once you finish.\n", + "bridge.stop_xvc_server()" + ] + }, + { + "cell_type": "markdown", + "id": "bc0f5c8a", + "metadata": {}, + "source": [ + "# Qubit Emulator \n", + "Frequency Sweep" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "8354da74", + "metadata": {}, + "outputs": [], + "source": [ + "class FrequencySweepProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " \n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " self.add_readoutconfig(ch=ro_ch, name=\"myro\", freq=cfg['freq'], gen_ch=gen_ch, outsel='product')\n", + "\n", + " # self.add_gauss(ch=gen_ch, name=\"ramp\", sigma=cfg['ramp_len']/10, length=cfg['ramp_len'], even_length=True)\n", + " self.add_pulse(ch=gen_ch, name=\"mypulse\", ro_ch=ro_ch, \n", + " style=\"const\", \n", + " # envelope=\"ramp\", \n", + " freq=cfg['freq'], \n", + " length=cfg['flat_len'],\n", + " phase=cfg['phase'],\n", + " gain=cfg['gain'], \n", + " )\n", + " # self.add_triangle(ch=gen_ch, name=\"ramp\", length=cfg['ramp_len'], even_length=True)\n", + " # self.add_pulse(ch=gen_ch, name=\"mypulse\", ro_ch=ro_ch, \n", + " # style=\"arb\", \n", + " # envelope=\"ramp\", \n", + " # freq=cfg['freq'], \n", + " # phase=cfg['phase'],\n", + " # gain=cfg['gain'], \n", + " # )\n", + "\n", + " self.add_loop(\"freq_sweep\", self.cfg[\"steps\"])\n", + "\n", + " def _body(self, cfg):\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=cfg['ro_ch'], name=\"myro\", t=0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"mypulse\", t=0.1)\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'])" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "48274e84", + "metadata": {}, + "outputs": [], + "source": [ + "GEN_CH = 0\n", + "RO_CH = 0\n", + "FREQ = 100\n", + "DELTA_FREQ = 10\n", + "\n", + "# do a sweep with STEPS points and plot decimated\n", + "config = {'steps': 11,\n", + " 'gen_ch': GEN_CH,\n", + " 'ro_ch': RO_CH,\n", + " 'freq': QickSweep1D(\"freq_sweep\", FREQ-DELTA_FREQ, FREQ+DELTA_FREQ),\n", + " 'trig_time': 0.5,\n", + " 'ro_len': 1.0,\n", + " 'flat_len': 0.8,\n", + " 'ramp_len': 0.1,\n", + " 'phase': 0,\n", + " 'gain': 0.5\n", + " }\n", + "\n", + "# prog = FrequencySweepProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "# iq_list = prog.acquire_decimated(soc, rounds=1)\n", + "\n", + "# plt.figure()\n", + "# t = prog.get_time_axis(ro_index=0)\n", + "# for ii, iq in enumerate(iq_list[0]):\n", + "# # plt.plot(t, iq[:,0], label=\"I value, step %d\"%(ii))\n", + "# # plt.plot(t, iq[:,1], label=\"Q value, step %d\"%(ii))\n", + "# plt.plot(t, np.abs(iq.dot([1,1j])), label=\"mag, step %d\"%(ii))\n", + "# plt.legend()\n", + "# plt.ylabel(\"a.u.\")\n", + "# plt.xlabel(\"us\")\n", + "\n", + "\n", + "prog = FrequencySweepProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "freqs = prog.get_pulse_param('myro', 'freq', as_array=True)\n", + "print(freqs)\n", + "iq_list = prog.acquire(soc, rounds=1, progress=True)\n", + "\n", + "plt.figure()\n", + "plt.plot(freqs, np.abs(iq_list[0][0].dot([1,1j])))\n", + "# plt.plot(np.angle(iq_list[0][0].dot([1,1j]), deg=True))\n", + "# plt.plot(iq_list[0][0,:,0], iq_list[0][0,:,1])\n", + "plt.ylabel(\"amp\")\n", + "plt.xlabel(\"freq\")\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "d88c4177", + "metadata": {}, + "outputs": [], + "source": [ + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0,gen_file=True)\n" + ] + }, + { + "cell_type": "markdown", + "id": "92fda648", + "metadata": {}, + "source": [ + "# Test issue 53 - SG ready to CDCSYNC & tPROC bug test\n", + "https://github.com/openquantumhardware/qick_internal/issues/53" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "48f5c94c", + "metadata": {}, + "outputs": [], + "source": [ + "GEN_CH = 0\n", + "RO_CH = 0\n", + "FREQ = 100\n", + "# FREQ = 0\n", + "\n", + "class MultiPulseProgram(AveragerProgramV2):\n", + " def _initialize(self, cfg):\n", + " ro_ch = cfg['ro_ch']\n", + " gen_ch = cfg['gen_ch']\n", + " \n", + " self.declare_gen(ch=gen_ch, nqz=1)\n", + " self.declare_readout(ch=ro_ch, length=cfg['ro_len'])\n", + "\n", + " ramp_len = self.cycles2us(20, gen_ch=gen_ch)\n", + " self.add_gauss(ch=gen_ch, name=\"ramp\", sigma=ramp_len/10, length=ramp_len, even_length=True)\n", + " \n", + " self.add_pulse(ch=gen_ch, name=\"myflattop\", ro_ch=ro_ch, \n", + " style = \"flat_top\", \n", + " envelope = \"ramp\", \n", + " freq = cfg['freq'], \n", + " length = 0.1,\n", + " phase = 0,\n", + " gain = 1.0, \n", + " )\n", + "\n", + " self.add_pulse(ch=gen_ch, name=\"myflattop2\", ro_ch=ro_ch, \n", + " style = \"flat_top\", \n", + " envelope = \"ramp\", \n", + " freq = cfg['freq'], \n", + " length = 0.1,\n", + " phase = 90,\n", + " gain = 0.5, \n", + " )\n", + "\n", + " self.add_readoutconfig(ch=ro_ch, name=\"myro\", freq=cfg['freq'], gen_ch=gen_ch)\n", + " # send the config to the dynamic RO\n", + " self.send_readoutconfig(ch=ro_ch, name=\"myro\", t=0)\n", + " \n", + " def _body(self, cfg):\n", + " self.trigger(ros=[cfg['ro_ch']], pins=[0], t=cfg['trig_time'], ddr4=True)\n", + "\n", + " for i in range(0,15):\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop\", t=1.0)\n", + " self.pulse(ch=cfg['gen_ch'], name=\"myflattop2\", t=1.0)\n", + " \n", + "config = {'gen_ch': GEN_CH,\n", + " 'ro_ch': RO_CH,\n", + " 'freq': FREQ,\n", + " 'trig_time': 1.0,\n", + " 'ro_len': 5.0,\n", + " }\n", + "\n", + "prog = MultiPulseProgram(soccfg, reps=1, final_delay=0.5, cfg=config)\n", + "\n", + "iq_list = prog.acquire_decimated(soc, rounds=10)\n", + "t = prog.get_time_axis(ro_index=0)\n", + "\n", + "plt.figure(figsize=[20,10])\n", + "plt.plot(t, iq_list[0][:,0], label=\"I value\")\n", + "plt.plot(t, iq_list[0][:,1], label=\"Q value\")\n", + "plt.plot(t, np.abs(iq_list[0].dot([1,1j])), label=\"magnitude\")\n", + "plt.legend()\n", + "plt.ylabel(\"a.u.\")\n", + "plt.xlabel(\"us\")\n", + "\n", + "print(prog)\n", + "prog.print_pmem2hex()\n", + "prog.print_wmem2hex()\n", + "prog.print_sg_mem(sg_idx=0,gen_file=True)" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "venv", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.9.21" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl b/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl new file mode 100644 index 000000000..a13a5df40 --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl @@ -0,0 +1,2698 @@ + +################################################################ +# This is a generated script based on design: d_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2020.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source d_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# lo_spi_mux, vect2bits_16 + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e + set_property BOARD_PART xilinx.com:zcu111:part0:1.4 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name d_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_quad_spi:3.2\ +xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:blk_mem_gen:8.4\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:smartconnect:1.0\ +QICK:QICK:axis_avg_buffer:1.2\ +xilinx.com:ip:axis_clock_converter:1.1\ +QICK:QICK:axis_constant:1.0\ +QICK:QICK:axis_readout_v2:1.0\ +xilinx.com:ip:axis_register_slice:1.1\ +QICK:QICK:axis_set_reg:1.0\ +QICK:QICK:axis_signal_gen_v6:1.0\ +xilinx.com:ip:axis_switch:1.1\ +QICK:QICK:axis_terminator:1.0\ +QICK:QICK:axis_tproc64x32_x8:1.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:system_ila:1.1\ +xilinx.com:ip:usp_rf_data_converter:2.4\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +lo_spi_mux\ +vect2bits_16\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] + + set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] + + set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] + + set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] + + set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] + + set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] + + set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] + + set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] + + set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] + + set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] + + set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] + + set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] + + set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] + + + # Create ports + set ATTN_CLK [ create_bd_port -dir O ATTN_CLK ] + set ATTN_LE [ create_bd_port -dir O -from 2 -to 0 ATTN_LE ] + set ATTN_SI [ create_bd_port -dir O ATTN_SI ] + set BIAS_CE [ create_bd_port -dir O -from 0 -to 0 BIAS_CE ] + set BIAS_CLR [ create_bd_port -dir O -from 0 -to 0 BIAS_CLR ] + set BIAS_RESET [ create_bd_port -dir O -from 0 -to 0 BIAS_RESET ] + set BIAS_S [ create_bd_port -dir O -from 3 -to 0 BIAS_S ] + set BIAS_SCLK [ create_bd_port -dir O BIAS_SCLK ] + set BIAS_SDI [ create_bd_port -dir O BIAS_SDI ] + set BIAS_SDO [ create_bd_port -dir I BIAS_SDO ] + set LO_CS0 [ create_bd_port -dir O LO_CS0 ] + set LO_CS1 [ create_bd_port -dir O LO_CS1 ] + set LO_MISO0 [ create_bd_port -dir I LO_MISO0 ] + set LO_MISO1 [ create_bd_port -dir I LO_MISO1 ] + set LO_MOSI [ create_bd_port -dir O LO_MOSI ] + set LO_SCLK [ create_bd_port -dir O LO_SCLK ] + set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] + set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] + set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] + set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] + set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] + set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] + set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] + set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] + set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] + set PWR_SYNC [ create_bd_port -dir O -from 0 -to 0 PWR_SYNC ] + set RST_5VEN [ create_bd_port -dir O -from 0 -to 0 RST_5VEN ] + set S [ create_bd_port -dir O -from 3 -to 0 S ] + set SCLK [ create_bd_port -dir O SCLK ] + set SDI [ create_bd_port -dir O SDI ] + set SDO [ create_bd_port -dir I SDO ] + + # Create instance: attn_spi, and set properties + set attn_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 attn_spi ] + set_property -dict [ list \ + CONFIG.C_NUM_SS_BITS {3} \ + CONFIG.C_NUM_TRANSFER_BITS {16} \ + ] $attn_spi + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ECC_TYPE {0} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [ list \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Read_Width_B {64} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_B {64} \ + ] $axi_bram_ctrl_0_bram + + # Create instance: axi_dma_avg, and set properties + set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_avg + + # Create instance: axi_dma_buf, and set properties + set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_buf + + # Create instance: axi_dma_gen, and set properties + set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {1} \ + CONFIG.c_include_s2mm {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_gen + + # Create instance: axi_dma_tproc, and set properties + set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] + set_property -dict [ list \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_tproc + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {5} \ + ] $axi_smc + + # Create instance: axis_avg_buffer_0, and set properties + set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_0 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_0 + + # Create instance: axis_avg_buffer_1, and set properties + set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_1 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_1 + + # Create instance: axis_clk_cnvrt_avg_0, and set properties + set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] + + # Create instance: axis_clk_cnvrt_avg_1, and set properties + set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] + + # Create instance: axis_clk_cnvrt_gen_3, and set properties + set axis_clk_cnvrt_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_3 ] + + # Create instance: axis_clk_cnvrt_gen_4, and set properties + set axis_clk_cnvrt_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_4 ] + + # Create instance: axis_clk_cnvrt_gen_5, and set properties + set axis_clk_cnvrt_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_5 ] + + # Create instance: axis_clk_cnvrt_gen_6, and set properties + set axis_clk_cnvrt_gen_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_6 ] + + # Create instance: axis_constant_0, and set properties + set axis_constant_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_constant:1.0 axis_constant_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + ] $axis_constant_0 + + # Create instance: axis_constant_1, and set properties + set axis_constant_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_constant:1.0 axis_constant_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + ] $axis_constant_1 + + # Create instance: axis_readout_v2_0, and set properties + set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_0 ] + + # Create instance: axis_readout_v2_1, and set properties + set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_1 ] + + # Create instance: axis_register_slice_0, and set properties + set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] + + # Create instance: axis_register_slice_1, and set properties + set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] + + # Create instance: axis_set_reg_0, and set properties + set axis_set_reg_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_set_reg:1.0 axis_set_reg_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {160} \ + ] $axis_set_reg_0 + + # Create instance: axis_signal_gen_v6_0, and set properties + set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] + + # Create instance: axis_signal_gen_v6_1, and set properties + set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] + + # Create instance: axis_signal_gen_v6_2, and set properties + set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] + + # Create instance: axis_signal_gen_v6_3, and set properties + set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] + + # Create instance: axis_signal_gen_v6_4, and set properties + set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] + + # Create instance: axis_signal_gen_v6_5, and set properties + set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] + + # Create instance: axis_signal_gen_v6_6, and set properties + set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] + + # Create instance: axis_switch_avg, and set properties + set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_avg + + # Create instance: axis_switch_buf, and set properties + set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_buf + + # Create instance: axis_switch_gen, and set properties + set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI {7} \ + CONFIG.NUM_SI {1} \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_gen + + # Create instance: axis_terminator_0, and set properties + set axis_terminator_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_terminator:1.0 axis_terminator_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {256} \ + ] $axis_terminator_0 + + # Create instance: axis_terminator_1, and set properties + set axis_terminator_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_terminator:1.0 axis_terminator_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {256} \ + ] $axis_terminator_1 + + # Create instance: axis_tproc64x32_x8_0, and set properties + set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] + set_property -dict [ list \ + CONFIG.DMEM_N {12} \ + CONFIG.PMEM_N {20} \ + ] $axis_tproc64x32_x8_0 + + # Create instance: bias_constant_0, and set properties + set bias_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 bias_constant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $bias_constant_0 + + # Create instance: bias_constant_1, and set properties + set bias_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 bias_constant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + ] $bias_constant_1 + + # Create instance: clk_adc0_x2, and set properties + set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {52.08} \ + CONFIG.CLKOUT1_JITTER {81.938} \ + CONFIG.CLKOUT1_PHASE_ERROR {82.655} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {384} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {6.250} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.208} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.125} \ + ] $clk_adc0_x2 + + # Create instance: dac_bias_spi, and set properties + set dac_bias_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 dac_bias_spi ] + set_property -dict [ list \ + CONFIG.C_NUM_SS_BITS {4} \ + CONFIG.C_NUM_TRANSFER_BITS {8} \ + ] $dac_bias_spi + + # Create instance: dig_lconstant_1, and set properties + set dig_lconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 dig_lconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + ] $dig_lconstant_1 + + # Create instance: lo_spi, and set properties + set lo_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 lo_spi ] + set_property -dict [ list \ + CONFIG.C_NUM_SS_BITS {2} \ + CONFIG.C_NUM_TRANSFER_BITS {8} \ + ] $lo_spi + + # Create instance: lo_spi_mux_0, and set properties + set block_name lo_spi_mux + set block_cell_name lo_spi_mux_0 + if { [catch {set lo_spi_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $lo_spi_mux_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {26} \ + ] $ps8_0_axi_periph + + # Create instance: psf_spi, and set properties + set psf_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 psf_spi ] + set_property -dict [ list \ + CONFIG.C_NUM_SS_BITS {4} \ + CONFIG.C_NUM_TRANSFER_BITS {8} \ + ] $psf_spi + + # Create instance: rst_100, and set properties + set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] + + # Create instance: rst_adc0, and set properties + set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] + + # Create instance: rst_adc0_x2, and set properties + set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] + + # Create instance: rst_dac0, and set properties + set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] + + # Create instance: rst_dac1, and set properties + set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] + + # Create instance: system_ila_0, and set properties + set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] + set_property -dict [ list \ + CONFIG.C_BRAM_CNT {6} \ + CONFIG.C_MON_TYPE {MIX} \ + CONFIG.C_NUM_MONITOR_SLOTS {1} \ + CONFIG.C_SLOT {0} \ + CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + ] $system_ila_0 + + # Create instance: system_ila_1, and set properties + set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] + set_property -dict [ list \ + CONFIG.C_BRAM_CNT {6} \ + CONFIG.C_MON_TYPE {MIX} \ + CONFIG.C_NUM_MONITOR_SLOTS {1} \ + CONFIG.C_SLOT {0} \ + CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + ] $system_ila_1 + + # Create instance: usp_rf_data_converter_0, and set properties + set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] + set_property -dict [ list \ + CONFIG.ADC0_Enable {1} \ + CONFIG.ADC0_Fabric_Freq {384.000} \ + CONFIG.ADC0_Outclk_Freq {192.000} \ + CONFIG.ADC0_PLL_Enable {true} \ + CONFIG.ADC0_Refclk_Freq {204.800} \ + CONFIG.ADC0_Sampling_Rate {3.072} \ + CONFIG.ADC_Decimation_Mode00 {1} \ + CONFIG.ADC_Decimation_Mode01 {1} \ + CONFIG.ADC_Decimation_Mode02 {1} \ + CONFIG.ADC_Decimation_Mode03 {1} \ + CONFIG.ADC_Mixer_Type00 {0} \ + CONFIG.ADC_Mixer_Type01 {0} \ + CONFIG.ADC_Mixer_Type02 {0} \ + CONFIG.ADC_Mixer_Type03 {0} \ + CONFIG.ADC_Slice00_Enable {true} \ + CONFIG.ADC_Slice01_Enable {true} \ + CONFIG.ADC_Slice02_Enable {true} \ + CONFIG.ADC_Slice03_Enable {true} \ + CONFIG.DAC0_Enable {1} \ + CONFIG.DAC0_Fabric_Freq {384.000} \ + CONFIG.DAC0_Outclk_Freq {384.000} \ + CONFIG.DAC0_PLL_Enable {true} \ + CONFIG.DAC0_Refclk_Freq {204.800} \ + CONFIG.DAC0_Sampling_Rate {6.144} \ + CONFIG.DAC1_Enable {1} \ + CONFIG.DAC1_Fabric_Freq {384.000} \ + CONFIG.DAC1_Outclk_Freq {384.000} \ + CONFIG.DAC1_PLL_Enable {true} \ + CONFIG.DAC1_Refclk_Freq {204.800} \ + CONFIG.DAC1_Sampling_Rate {6.144} \ + CONFIG.DAC_Interpolation_Mode00 {1} \ + CONFIG.DAC_Interpolation_Mode01 {1} \ + CONFIG.DAC_Interpolation_Mode02 {1} \ + CONFIG.DAC_Interpolation_Mode10 {1} \ + CONFIG.DAC_Interpolation_Mode11 {1} \ + CONFIG.DAC_Interpolation_Mode12 {1} \ + CONFIG.DAC_Interpolation_Mode13 {1} \ + CONFIG.DAC_Mixer_Type00 {0} \ + CONFIG.DAC_Mixer_Type01 {0} \ + CONFIG.DAC_Mixer_Type02 {0} \ + CONFIG.DAC_Mixer_Type10 {0} \ + CONFIG.DAC_Mixer_Type11 {0} \ + CONFIG.DAC_Mixer_Type12 {0} \ + CONFIG.DAC_Mixer_Type13 {0} \ + CONFIG.DAC_Slice00_Enable {true} \ + CONFIG.DAC_Slice01_Enable {true} \ + CONFIG.DAC_Slice02_Enable {true} \ + CONFIG.DAC_Slice10_Enable {true} \ + CONFIG.DAC_Slice11_Enable {true} \ + CONFIG.DAC_Slice12_Enable {true} \ + CONFIG.DAC_Slice13_Enable {true} \ + ] $usp_rf_data_converter_0 + + # Create instance: vect2bits_16_0, and set properties + set block_name vect2bits_16 + set block_cell_name vect2bits_16_0 + if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $vect2bits_16_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {64} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_1 + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_2 + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {8} \ + ] $xlconstant_3 + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {out} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {out} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {out} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {1.999980} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {50} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {15} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {2} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {FALSE} \ + CONFIG.PSU__PL_CLK2_BUF {FALSE} \ + CONFIG.PSU__PL_CLK3_BUF {FALSE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {low} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {\ +SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \ +SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \ +SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB;\ +RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \ +SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB;\ +RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {\ +SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\ +WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\ +UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\ +Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\ +WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\ +UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__MASTERS {\ +USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {\ +GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {\ +LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {1} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__RESET__ENABLE {0} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB0__RESET__ENABLE {0} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__RESET__ENABLE {0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {1} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $zynq_ultra_ps_e_0 + + # Create interface connections + connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM1 [get_bd_intf_pins axi_dma_mr/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] + connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] + connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] + connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] + connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] + connect_bd_intf_net -intf_net axi_smc_1_M00_AXI [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] [get_bd_intf_pins axis_switch_ddr/S00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M00_AXIS [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_broadcaster_1/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M01_AXIS [get_bd_intf_pins axis_broadcaster_1/M01_AXIS] [get_bd_intf_pins axis_switch_ddr/S01_AXIS] + connect_bd_intf_net -intf_net axis_buffer_ddr_v1_0_m_axi [get_bd_intf_pins axi_smc_1/S01_AXI] [get_bd_intf_pins axis_buffer_ddr_v1_0/m_axi] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m0_axis [get_bd_intf_pins axis_cdcsync_v1_0/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m1_axis [get_bd_intf_pins axis_cdcsync_v1_0/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_2/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m0_axis [get_bd_intf_pins axis_cdcsync_v1_1/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_3/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m1_axis [get_bd_intf_pins axis_cdcsync_v1_1/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_4/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m2_axis [get_bd_intf_pins axis_cdcsync_v1_1/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_5/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m3_axis [get_bd_intf_pins axis_cdcsync_v1_1/m3_axis] [get_bd_intf_pins axis_signal_gen_v6_6/s1_axis] + connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] + connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] + connect_bd_intf_net -intf_net axis_clock_converter_0_M_AXIS [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axis] [get_bd_intf_pins axis_clock_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins axis_clock_converter_0/S_AXIS] [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_mr/S00_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_broadcaster_0/S_AXIS] [get_bd_intf_pins axis_readout_v2_0/m1_axis] + connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_mr/S01_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_broadcaster_1/S_AXIS] [get_bd_intf_pins axis_readout_v2_1/m1_axis] + connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] + connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s01_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_2_m_axis [get_bd_intf_pins axis_signal_gen_v6_2/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s02_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_3_m_axis [get_bd_intf_pins axis_signal_gen_v6_3/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s10_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_4_m_axis [get_bd_intf_pins axis_signal_gen_v6_4/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s11_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_5_m_axis [get_bd_intf_pins axis_signal_gen_v6_5/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s12_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_6_m_axis [get_bd_intf_pins axis_signal_gen_v6_6/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s13_axis] + connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v6_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v6_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v6_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v6_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v6_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] + connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_ddr_M00_AXIS [get_bd_intf_pins axis_dwidth_converter_0/S_AXIS] [get_bd_intf_pins axis_switch_ddr/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_mr_M00_AXIS [get_bd_intf_pins axis_switch_mr/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_cdcsync_v1_0/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_cdcsync_v1_1/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_cdcsync_v1_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_cdcsync_v1_1/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_cdcsync_v1_1/s3_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] + connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] + connect_bd_intf_net -intf_net dac1_clk_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac1_clk] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_pl] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_sysclk1_300mhz_1 [get_bd_intf_ports sys_clk_ddr4] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_mr/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v6_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v6_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v6_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v6_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M21_AXI [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M21_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M22_AXI [get_bd_intf_pins axis_switch_ddr/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M22_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M23_AXI [get_bd_intf_pins axis_switch_mr/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M23_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M24_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M24_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M25_AXI [get_bd_intf_pins axi_dma_mr/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M25_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M26_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M26_AXI] + connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout00] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout01 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout01] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout02 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout02] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout10 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout10] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout11 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout11] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout12 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout12] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout13 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout13] + connect_bd_intf_net -intf_net vin0_1 [get_bd_intf_ports vin0] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] + connect_bd_intf_net -intf_net vin1_1 [get_bd_intf_ports vin1] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins axi_smc_1/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] + + # Create port connections + connect_bd_net -net PMOD1_0_LS_1 [get_bd_ports PMOD1_0_LS] [get_bd_pins axis_tproc64x32_x8_0/start] + connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] + connect_bd_net -net axi_dma_avg_s2mm_introut [get_bd_pins axi_dma_avg/s2mm_introut] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net axi_dma_buf_s2mm_introut [get_bd_pins axi_dma_buf/s2mm_introut] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net axi_dma_gen_mm2s_introut [get_bd_pins axi_dma_gen/mm2s_introut] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net axi_dma_mr_s2mm_introut [get_bd_pins axi_dma_mr/s2mm_introut] [get_bd_pins xlconcat_0/In5] + connect_bd_net -net axi_dma_tproc_mm2s_introut [get_bd_pins axi_dma_tproc/mm2s_introut] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net axi_dma_tproc_s2mm_introut [get_bd_pins axi_dma_tproc/s2mm_introut] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] + connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] + connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] + connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins axis_broadcaster_1/aclk] [get_bd_pins axis_clock_converter_0/s_axis_aclk] [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_switch_ddr/aclk] [get_bd_pins axis_switch_mr/aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] + connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_smc_1/aclk] [get_bd_pins axis_buffer_ddr_v1_0/aclk] [get_bd_pins axis_clock_converter_0/m_axis_aclk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ddr4/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins rst_ddr4/ext_reset_in] + connect_bd_net -net rst_100_bus_struct_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_100/bus_struct_reset] + connect_bd_net -net rst_adc0_peripheral_reset [get_bd_pins clk_adc0_x2/reset] [get_bd_pins rst_adc0/peripheral_reset] + connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins axis_broadcaster_1/aresetn] [get_bd_pins axis_clock_converter_0/s_axis_aresetn] [get_bd_pins axis_dwidth_converter_0/aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_switch_ddr/aresetn] [get_bd_pins axis_switch_mr/aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] + connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_0/m_axis_aresetn] [get_bd_pins axis_cdcsync_v1_0/s_axis_aresetn] [get_bd_pins axis_cdcsync_v1_1/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_signal_gen_v6_2/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] + connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_1/m_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/aresetn] [get_bd_pins axis_signal_gen_v6_4/aresetn] [get_bd_pins axis_signal_gen_v6_5/aresetn] [get_bd_pins axis_signal_gen_v6_6/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s1_axis_aresetn] + connect_bd_net -net rst_ddr4_0_333M_peripheral_aresetn [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axis_buffer_ddr_v1_0/aresetn] [get_bd_pins axis_clock_converter_0/m_axis_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ddr4/peripheral_aresetn] + connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_mr/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_ddr/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_mr/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/M21_ARESETN] [get_bd_pins ps8_0_axi_periph/M22_ARESETN] [get_bd_pins ps8_0_axi_periph/M23_ARESETN] [get_bd_pins ps8_0_axi_periph/M24_ARESETN] [get_bd_pins ps8_0_axi_periph/M25_ARESETN] [get_bd_pins ps8_0_axi_periph/M26_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] + connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] + connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cdcsync_v1_0/m_axis_aclk] [get_bd_pins axis_cdcsync_v1_0/s_axis_aclk] [get_bd_pins axis_cdcsync_v1_1/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins axis_signal_gen_v6_2/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] + connect_bd_net -net usp_rf_data_converter_0_clk_dac1 [get_bd_pins axis_cdcsync_v1_1/m_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/aclk] [get_bd_pins axis_signal_gen_v6_4/aclk] [get_bd_pins axis_signal_gen_v6_5/aclk] [get_bd_pins axis_signal_gen_v6_6/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac1] [get_bd_pins usp_rf_data_converter_0/s1_axis_aclk] + connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_16_0/dout0] + connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_16_0/dout1] + connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_16_0/dout2] + connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_16_0/dout3] + connect_bd_net -net vect2bits_16_0_dout4 [get_bd_ports PMOD0_4_LS] [get_bd_pins vect2bits_16_0/dout4] + connect_bd_net -net vect2bits_16_0_dout5 [get_bd_ports PMOD0_5_LS] [get_bd_pins vect2bits_16_0/dout5] + connect_bd_net -net vect2bits_16_0_dout6 [get_bd_ports PMOD0_6_LS] [get_bd_pins vect2bits_16_0/dout6] + connect_bd_net -net vect2bits_16_0_dout7 [get_bd_ports PMOD0_7_LS] [get_bd_pins vect2bits_16_0/dout7] + connect_bd_net -net vect2bits_16_0_dout8 [get_bd_pins axis_buffer_ddr_v1_0/trigger] [get_bd_pins vect2bits_16_0/dout8] + connect_bd_net -net vect2bits_16_0_dout9 [get_bd_pins mr_buffer_et_0/trigger] [get_bd_pins vect2bits_16_0/dout9] + connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout14] + connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout15] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] + connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_mr/m_axi_s2mm_aclk] [get_bd_pins axi_dma_mr/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_ddr/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_mr/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/M21_ACLK] [get_bd_pins ps8_0_axi_periph/M22_ACLK] [get_bd_pins ps8_0_axi_periph/M23_ACLK] [get_bd_pins ps8_0_axi_periph/M24_ACLK] [get_bd_pins ps8_0_axi_periph/M25_ACLK] [get_bd_pins ps8_0_axi_periph/M26_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axis_buffer_ddr_v1_0/m_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0xA0252000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_mr/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0240000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0241000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0242000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0243000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0253000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force + assign_bd_address -offset 0xA0244000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0245000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force + assign_bd_address -offset 0xA0254000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_buffer_ddr_v1_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0246000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0247000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force + assign_bd_address -offset 0xA0248000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0249000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force + assign_bd_address -offset 0xA024A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_2/s_axi/reg0] -force + assign_bd_address -offset 0xA024B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_3/s_axi/reg0] -force + assign_bd_address -offset 0xA024C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_4/s_axi/reg0] -force + assign_bd_address -offset 0xA024D000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_5/s_axi/reg0] -force + assign_bd_address -offset 0xA024E000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_6/s_axi/reg0] -force + assign_bd_address -offset 0xA024F000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0250000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0255000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_ddr/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0251000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0256000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_mr/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force + assign_bd_address -offset 0x000500000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0xA0257000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force + assign_bd_address -offset 0xA0280000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.322782", + "Default View_TopLeft":"-1131,-1242", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port adc0_clk -pg 1 -lvl 17 -x 7420 -y 2060 -defaultsOSRD -right +preplace port dac0_clk -pg 1 -lvl 17 -x 7420 -y 2100 -defaultsOSRD -right +preplace port dac1_clk -pg 1 -lvl 17 -x 7420 -y 2080 -defaultsOSRD -right +preplace port ddr4_pl -pg 1 -lvl 17 -x 7420 -y 1210 -defaultsOSRD +preplace port sys_clk_ddr4 -pg 1 -lvl 17 -x 7420 -y 1140 -defaultsOSRD -right +preplace port sysref_in -pg 1 -lvl 17 -x 7420 -y 2040 -defaultsOSRD -right +preplace port vin0 -pg 1 -lvl 17 -x 7420 -y 1990 -defaultsOSRD -right +preplace port vin1 -pg 1 -lvl 17 -x 7420 -y 2010 -defaultsOSRD -right +preplace port vout0 -pg 1 -lvl 17 -x 7420 -y 1640 -defaultsOSRD +preplace port vout1 -pg 1 -lvl 17 -x 7420 -y 1660 -defaultsOSRD +preplace port vout2 -pg 1 -lvl 17 -x 7420 -y 1680 -defaultsOSRD +preplace port vout3 -pg 1 -lvl 17 -x 7420 -y 1700 -defaultsOSRD +preplace port vout4 -pg 1 -lvl 17 -x 7420 -y 1720 -defaultsOSRD +preplace port vout5 -pg 1 -lvl 17 -x 7420 -y 1740 -defaultsOSRD +preplace port vout6 -pg 1 -lvl 17 -x 7420 -y 1760 -defaultsOSRD +preplace port port-id_PMOD0_0_LS -pg 1 -lvl 17 -x 7420 -y 3360 -defaultsOSRD +preplace port port-id_PMOD0_1_LS -pg 1 -lvl 17 -x 7420 -y 3380 -defaultsOSRD +preplace port port-id_PMOD0_2_LS -pg 1 -lvl 17 -x 7420 -y 3400 -defaultsOSRD +preplace port port-id_PMOD0_3_LS -pg 1 -lvl 17 -x 7420 -y 3420 -defaultsOSRD +preplace port port-id_PMOD0_4_LS -pg 1 -lvl 17 -x 7420 -y 3440 -defaultsOSRD +preplace port port-id_PMOD0_5_LS -pg 1 -lvl 17 -x 7420 -y 3460 -defaultsOSRD +preplace port port-id_PMOD0_6_LS -pg 1 -lvl 17 -x 7420 -y 3480 -defaultsOSRD +preplace port port-id_PMOD0_7_LS -pg 1 -lvl 17 -x 7420 -y 3500 -defaultsOSRD +preplace port port-id_PMOD1_0_LS -pg 1 -lvl 0 -x -40 -y 2350 -defaultsOSRD +preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 150 -y 2430 -defaultsOSRD +preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 820 -y 2610 -defaultsOSRD +preplace inst axi_dma_avg -pg 1 -lvl 13 -x 6160 -y 440 -defaultsOSRD +preplace inst axi_dma_buf -pg 1 -lvl 13 -x 6160 -y 720 -defaultsOSRD -resize 320 156 +preplace inst axi_dma_gen -pg 1 -lvl 2 -x 820 -y 1350 -defaultsOSRD +preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 820 -y 1900 -defaultsOSRD +preplace inst axi_smc -pg 1 -lvl 3 -x 1280 -y -420 -defaultsOSRD +preplace inst axi_smc_1 -pg 1 -lvl 15 -x 6840 -y 1290 -defaultsOSRD +preplace inst axis_avg_buffer_0 -pg 1 -lvl 11 -x 5290 -y 400 -defaultsOSRD +preplace inst axis_avg_buffer_1 -pg 1 -lvl 11 -x 5290 -y 730 -defaultsOSRD -resize 220 236 +preplace inst axis_broadcaster_0 -pg 1 -lvl 10 -x 4830 -y 460 -defaultsOSRD +preplace inst axis_broadcaster_1 -pg 1 -lvl 10 -x 4830 -y 810 -defaultsOSRD -resize 280 116 +preplace inst axis_buffer_ddr_v1_0 -pg 1 -lvl 14 -x 6560 -y 1270 -defaultsOSRD +preplace inst axis_cdcsync_v1_0 -pg 1 -lvl 3 -x 1280 -y 1870 -defaultsOSRD +preplace inst axis_cdcsync_v1_1 -pg 1 -lvl 3 -x 1280 -y 2330 -defaultsOSRD +preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 12 -x 5730 -y -20 -defaultsOSRD +preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 12 -x 5730 -y 160 -defaultsOSRD -resize 220 156 +preplace inst axis_clock_converter_0 -pg 1 -lvl 13 -x 6160 -y 1290 -defaultsOSRD +preplace inst axis_dwidth_converter_0 -pg 1 -lvl 12 -x 5730 -y 1300 -defaultsOSRD +preplace inst axis_readout_v2_0 -pg 1 -lvl 9 -x 4520 -y 430 -defaultsOSRD +preplace inst axis_readout_v2_1 -pg 1 -lvl 9 -x 4520 -y 780 -defaultsOSRD +preplace inst axis_register_slice_0 -pg 1 -lvl 8 -x 4190 -y 460 -defaultsOSRD +preplace inst axis_register_slice_1 -pg 1 -lvl 8 -x 4190 -y 810 -defaultsOSRD -resize 180 116 +preplace inst axis_set_reg_0 -pg 1 -lvl 6 -x 3080 -y 3510 -defaultsOSRD +preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 6 -x 3080 -y 1430 -defaultsOSRD +preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 6 -x 3080 -y 1690 -defaultsOSRD -resize 220 236 +preplace inst axis_signal_gen_v6_2 -pg 1 -lvl 6 -x 3080 -y 1950 -defaultsOSRD -resize 220 236 +preplace inst axis_signal_gen_v6_3 -pg 1 -lvl 6 -x 3080 -y 2360 -defaultsOSRD -resize 220 236 +preplace inst axis_signal_gen_v6_4 -pg 1 -lvl 6 -x 3080 -y 2620 -defaultsOSRD -resize 220 236 +preplace inst axis_signal_gen_v6_5 -pg 1 -lvl 6 -x 3080 -y 2880 -defaultsOSRD -resize 220 236 +preplace inst axis_signal_gen_v6_6 -pg 1 -lvl 6 -x 3080 -y 3140 -defaultsOSRD -resize 220 236 +preplace inst axis_switch_avg -pg 1 -lvl 12 -x 5730 -y 420 -defaultsOSRD +preplace inst axis_switch_buf -pg 1 -lvl 12 -x 5730 -y 730 -defaultsOSRD -resize 240 196 +preplace inst axis_switch_ddr -pg 1 -lvl 11 -x 5290 -y 1280 -defaultsOSRD +preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1280 -y 1390 -defaultsOSRD +preplace inst clk_adc0_x2 -pg 1 -lvl 4 -x 1840 -y 580 -defaultsOSRD +preplace inst ddr4_0 -pg 1 -lvl 16 -x 7220 -y 1270 -defaultsOSRD +preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 2530 -y -580 -defaultsOSRD +preplace inst rst_100 -pg 1 -lvl 4 -x 1840 -y -170 -defaultsOSRD +preplace inst rst_adc0 -pg 1 -lvl 4 -x 1840 -y 10 -defaultsOSRD -resize 320 156 +preplace inst rst_adc0_x2 -pg 1 -lvl 4 -x 1840 -y 730 -defaultsOSRD -resize 320 156 +preplace inst rst_dac0 -pg 1 -lvl 4 -x 1840 -y 190 -defaultsOSRD -resize 320 156 +preplace inst rst_dac1 -pg 1 -lvl 4 -x 1840 -y 370 -defaultsOSRD -resize 320 156 +preplace inst rst_ddr4 -pg 1 -lvl 4 -x 1840 -y 910 -defaultsOSRD +preplace inst usp_rf_data_converter_0 -pg 1 -lvl 7 -x 3820 -y 1720 -defaultsOSRD +preplace inst vect2bits_16_0 -pg 1 -lvl 12 -x 5730 -y 3510 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 1 -x 150 -y 2550 -defaultsOSRD +preplace inst xlconstant_1 -pg 1 -lvl 1 -x 150 -y 2660 -defaultsOSRD -resize 140 88 +preplace inst xlconstant_2 -pg 1 -lvl 1 -x 150 -y 2770 -defaultsOSRD -resize 140 88 +preplace inst xlconstant_3 -pg 1 -lvl 1 -x 150 -y 2880 -defaultsOSRD -resize 140 88 +preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 4 -x 1840 -y -380 -defaultsOSRD +preplace inst axis_switch_mr -pg 1 -lvl 11 -x 5290 -y 970 -defaultsOSRD +preplace inst mr_buffer_et_0 -pg 1 -lvl 12 -x 5730 -y 970 -defaultsOSRD +preplace inst axi_dma_mr -pg 1 -lvl 13 -x 6160 -y 960 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 2 -x 820 -y -140 -defaultsOSRD +preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 820 -y 2250 -defaultsOSRD +preplace inst axi_intc_0 -pg 1 -lvl 3 -x 1280 -y -140 -defaultsOSRD +preplace netloc PMOD1_0_LS_1 1 0 2 N 2350 300J +preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 370 2400n +preplace netloc axi_dma_avg_s2mm_introut 1 1 13 330 1110 N 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 6380 +preplace netloc axi_dma_buf_s2mm_introut 1 1 13 360 1090 N 1090 NJ 1090 2240J 680 NJ 680 NJ 680 NJ 680 4300J 610 NJ 610 4990J 560 5490J 550 NJ 550 6340 +preplace netloc axi_dma_gen_mm2s_introut 1 1 2 370 -260 1000 +preplace netloc axi_dma_mr_s2mm_introut 1 1 13 370 1070 N 1070 NJ 1070 2250J 690 NJ 690 NJ 690 NJ 690 4320J 620 NJ 620 5030J 570 5520J 560 NJ 560 6350 +preplace netloc axi_dma_tproc_mm2s_introut 1 1 2 360 -280 1020 +preplace netloc axi_dma_tproc_s2mm_introut 1 1 2 380 -250 1010 +preplace netloc axi_intc_0_irq 1 3 1 1430 -340n +preplace netloc axis_set_reg_0_dout 1 6 6 N 3510 N 3510 N 3510 N 3510 N 3510 N +preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 380 2470 1000 +preplace netloc clk_adc0_x2_clk_out1 1 3 10 1520 1060 2190 1060 N 1060 3320 1020 3980 710 4390 640 4660 650 5080 1090 5560 1210 5900 +preplace netloc clk_adc0_x2_locked 1 3 2 1530 1040 2150 +preplace netloc ddr4_0_c0_ddr4_ui_clk 1 3 14 1470 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 4300 1160 NJ 1160 NJ 1160 NJ 1160 5910J 1180 6430 1150 6700 1150 N 1150 7400 +preplace netloc ddr4_0_c0_ddr4_ui_clk_sync_rst 1 3 14 1490 1140 N 1140 N 1140 3270 1300 N 1300 N 1300 N 1300 4990 1400 N 1400 N 1400 N 1400 N 1400 N 1400 7400 +preplace netloc rst_100_bus_struct_reset 1 4 12 2250J 240 NJ 240 NJ 240 NJ 240 N 240 NJ 240 NJ 240 5480J 280 NJ 280 N 280 N 280 6990 +preplace netloc rst_adc0_peripheral_reset 1 3 2 1510 1050 2170 +preplace netloc rst_adc0_x2_peripheral_aresetn 1 4 9 2210 1010 N 1010 3290 1010 3990 720 4380 650 4650J 680 5090 1100 5570 1220 5920 +preplace netloc rst_dac0_peripheral_aresetn 1 1 11 370 2040 1090J 1270 N 1270 2230 1270 2800 1270 3260J 210 3960 200 N 200 NJ 200 N 200 5430 +preplace netloc rst_dac1_peripheral_aresetn 1 2 5 1120 2090 N 2090 2220 2090 2830 2090 3320J +preplace netloc rst_ddr4_0_333M_peripheral_aresetn 1 4 12 2200 1000 N 1000 N 1000 4010 730 4360 660 N 660 5070 590 N 590 5930 1140 6410 1140 6680 1200 6980 +preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 14 0 2320 300 1440 1080 1150 N 1150 2260J 1150 2730 1170 3250 1170 N 1170 4340 1170 N 1170 5000 250 5510 600 5980 1100 6390 +preplace netloc usp_rf_data_converter_0_clk_adc0 1 3 5 1480 1080 NJ 1080 N 1080 NJ 1080 3960 +preplace netloc usp_rf_data_converter_0_clk_dac0 1 1 11 360 2460 1110 2000 1430 1870 NJ 1870 2840 1290 3220J 1290 4000 210 N 210 NJ 210 N 210 5460 +preplace netloc usp_rf_data_converter_0_clk_dac1 1 2 6 1130 2100 1460 2100 NJ 2100 2820 2100 3340J 2000 3990 +preplace netloc vect2bits_16_0_dout0 1 12 5 N 3360 N 3360 N 3360 N 3360 N +preplace netloc vect2bits_16_0_dout1 1 12 5 N 3380 N 3380 N 3380 N 3380 N +preplace netloc vect2bits_16_0_dout2 1 12 5 N 3400 N 3400 N 3400 N 3400 N +preplace netloc vect2bits_16_0_dout3 1 12 5 N 3420 N 3420 N 3420 N 3420 N +preplace netloc vect2bits_16_0_dout4 1 12 5 NJ 3440 N 3440 N 3440 NJ 3440 N +preplace netloc vect2bits_16_0_dout5 1 12 5 NJ 3460 N 3460 N 3460 NJ 3460 N +preplace netloc vect2bits_16_0_dout6 1 12 5 NJ 3480 N 3480 N 3480 NJ 3480 N +preplace netloc vect2bits_16_0_dout7 1 12 5 NJ 3500 N 3500 N 3500 NJ 3500 N +preplace netloc vect2bits_16_0_dout8 1 12 2 5970 1190 6400 +preplace netloc vect2bits_16_0_dout9 1 11 2 5570 610 5890 +preplace netloc vect2bits_16_0_dout14 1 10 3 5120 2320 N 2320 5880 +preplace netloc vect2bits_16_0_dout15 1 10 3 5130 2330 N 2330 5870 +preplace netloc xlconcat_0_dout 1 2 1 1070 -140n +preplace netloc xlconstant_0_dout 1 1 1 320 2550n +preplace netloc xlconstant_1_dout 1 1 1 340 2650n +preplace netloc xlconstant_2_dout 1 1 1 320 2670n +preplace netloc xlconstant_3_dout 1 1 1 370 2690n +preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 14 -10 2300 290 1450 1030 -550 1460 -550 2280 60 2750 1050 3310 1050 N 1050 4310 670 N 670 5040 260 5540 580 5970 1090 6420 +preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 3 2 1500 1030 2160 +preplace netloc adc0_clk_1 1 6 11 3370 2060 N 2060 N 2060 N 2060 N 2060 N 2060 N 2060 N 2060 N 2060 N 2060 N +preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 320 2430n +preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 380 2020 1000 +preplace netloc axi_dma_0_M_AXI_MM2S 1 2 1 1040 -490n +preplace netloc axi_dma_0_M_AXI_S2MM 1 2 1 1060J -470n +preplace netloc axi_dma_0_M_AXI_S2MM1 1 2 12 1110 -280 N -280 2230 70 2920 220 N 220 N 220 N 220 N 220 N 220 5560 270 N 270 6370 +preplace netloc axi_dma_1_M_AXIS_MM2S 1 2 1 N 1340 +preplace netloc axi_dma_1_M_AXI_MM2S 1 2 1 1050J -450n +preplace netloc axi_dma_avg_M_AXI_S2MM 1 2 12 1080 -1230 N -1230 N -1230 N -1230 N -1230 N -1230 N -1230 N -1230 N -1230 N -1230 N -1230 6340 +preplace netloc axi_dma_buf_M_AXI_S2MM 1 2 12 1090 1120 N 1120 N 1120 N 1120 N 1120 N 1120 N 1120 N 1120 N 1120 N 1120 N 1120 6360 +preplace netloc axi_smc_1_M00_AXI 1 15 1 7000 1260n +preplace netloc axi_smc_M00_AXI 1 3 1 N -420 +preplace netloc axis_avg_buffer_0_m0_axis 1 11 1 5460 360n +preplace netloc axis_avg_buffer_0_m1_axis 1 11 1 5460 400n +preplace netloc axis_avg_buffer_0_m2_axis 1 11 1 5450 -60n +preplace netloc axis_avg_buffer_1_m0_axis 1 11 1 5480 380n +preplace netloc axis_avg_buffer_1_m1_axis 1 11 1 5460 690n +preplace netloc axis_avg_buffer_1_m2_axis 1 11 1 5440 120n +preplace netloc axis_broadcaster_0_M00_AXIS 1 10 1 4990 320n +preplace netloc axis_broadcaster_0_M01_AXIS 1 10 1 5010 470n +preplace netloc axis_broadcaster_1_M00_AXIS 1 10 1 5110 650n +preplace netloc axis_broadcaster_1_M01_AXIS 1 10 1 4990 820n +preplace netloc axis_buffer_ddr_v1_0_m_axi 1 14 1 N 1280 +preplace netloc axis_cdcsync_v1_0_m0_axis 1 3 3 1440 1370 N 1370 NJ +preplace netloc axis_cdcsync_v1_0_m1_axis 1 3 3 1520 1630 NJ 1630 N +preplace netloc axis_cdcsync_v1_0_m2_axis 1 3 3 N 1880 NJ 1880 2770 +preplace netloc axis_cdcsync_v1_1_m0_axis 1 3 3 N 2300 NJ 2300 N +preplace netloc axis_cdcsync_v1_1_m1_axis 1 3 3 N 2320 NJ 2320 2720 +preplace netloc axis_cdcsync_v1_1_m2_axis 1 3 3 N 2340 NJ 2340 2700 +preplace netloc axis_cdcsync_v1_1_m3_axis 1 3 3 N 2360 NJ 2360 2690 +preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 12 310 -270 NJ -270 N -270 2270J 80 2900 230 NJ 230 N 230 N 230 NJ 230 N 230 5550 260 5890 +preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 12 340 1010 NJ 1010 N 1010 2180J 990 N 990 NJ 990 3960 700 4350 630 NJ 630 5060 580 5530 570 5870 +preplace netloc axis_clock_converter_0_M_AXIS 1 13 1 6360 1210n +preplace netloc axis_dwidth_converter_0_M_AXIS 1 12 1 5980 1250n +preplace netloc axis_readout_v2_0_m0_axis 1 9 2 4670 640 5030 +preplace netloc axis_readout_v2_0_m1_axis 1 9 1 N 440 +preplace netloc axis_readout_v2_1_m0_axis 1 9 2 4640 930 N +preplace netloc axis_readout_v2_1_m1_axis 1 9 1 N 790 +preplace netloc axis_register_slice_0_M_AXIS 1 8 1 4300 380n +preplace netloc axis_register_slice_1_M_AXIS 1 8 1 4370 730n +preplace netloc axis_signal_gen_v6_0_m_axis 1 6 1 3230 1430n +preplace netloc axis_signal_gen_v6_1_m_axis 1 6 1 3210 1550n +preplace netloc axis_signal_gen_v6_2_m_axis 1 6 1 3230 1570n +preplace netloc axis_signal_gen_v6_3_m_axis 1 6 1 3240 1590n +preplace netloc axis_signal_gen_v6_4_m_axis 1 6 1 3300 1610n +preplace netloc axis_signal_gen_v6_5_m_axis 1 6 1 3330 1630n +preplace netloc axis_signal_gen_v6_6_m_axis 1 6 1 3350 1650n +preplace netloc axis_switch_0_M00_AXIS 1 3 3 N 1330 N 1330 2880 +preplace netloc axis_switch_0_M01_AXIS 1 3 3 N 1350 N 1350 2870 +preplace netloc axis_switch_0_M02_AXIS 1 3 3 1420 1380 N 1380 2850 +preplace netloc axis_switch_0_M03_AXIS 1 3 3 1450 1400 N 1400 2790 +preplace netloc axis_switch_0_M04_AXIS 1 3 3 1420 1420 N 1420 2760 +preplace netloc axis_switch_0_M05_AXIS 1 3 3 1420 1440 N 1440 2740 +preplace netloc axis_switch_0_M06_AXIS 1 3 3 1420 1460 N 1460 2710 +preplace netloc axis_switch_avg_M00_AXIS 1 12 1 N 420 +preplace netloc axis_switch_buf_M00_AXIS 1 12 1 5940 700n +preplace netloc axis_switch_ddr_M00_AXIS 1 11 1 N 1280 +preplace netloc axis_switch_mr_M00_AXIS 1 11 1 5450 890n +preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 370 2030 1000 +preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 4 N 2180 N 2180 N 2180 2680 +preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 1070 1800n +preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 1 1080 1820n +preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 1 1100 1840n +preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 N 2260 +preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 N 2280 +preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 N 2300 +preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 N 2320 +preplace netloc dac0_clk_1 1 6 11 3360 2100 N 2100 N 2100 N 2100 N 2100 N 2100 N 2100 N 2100 N 2100 N 2100 N +preplace netloc dac1_clk_1 1 6 11 3380 2080 N 2080 N 2080 N 2080 N 2080 N 2080 N 2080 N 2080 N 2080 N 2080 N +preplace netloc ddr4_0_C0_DDR4 1 16 1 N 1210 +preplace netloc default_sysclk1_300mhz_1 1 15 2 7000 1140 N +preplace netloc mr_buffer_et_0_m00_axis 1 12 1 5960 940n +preplace netloc ps8_0_axi_periph_M00_AXI 1 1 5 350 470 N 470 N 470 NJ 470 2710 +preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 320 480 N 480 N 480 NJ 480 2700 +preplace netloc ps8_0_axi_periph_M02_AXI 1 5 1 2940 -800n +preplace netloc ps8_0_axi_periph_M03_AXI 1 5 1 2930 -780n +preplace netloc ps8_0_axi_periph_M04_AXI 1 5 1 2910 -760n +preplace netloc ps8_0_axi_periph_M05_AXI 1 5 1 2890 -740n +preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 380 500 N 500 N 500 NJ 500 2730 +preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 1100 510 N 510 NJ 510 2720 +preplace netloc ps8_0_axi_periph_M08_AXI 1 5 2 N -680 3280 +preplace netloc ps8_0_axi_periph_M09_AXI 1 5 6 N -660 N -660 N -660 N -660 N -660 5120 +preplace netloc ps8_0_axi_periph_M10_AXI 1 5 6 N -640 N -640 N -640 N -640 N -640 5100 +preplace netloc ps8_0_axi_periph_M11_AXI 1 5 1 2860 -620n +preplace netloc ps8_0_axi_periph_M12_AXI 1 5 1 2810 -600n +preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 -20 490 N 490 NJ 490 N 490 NJ 490 2680 +preplace netloc ps8_0_axi_periph_M14_AXI 1 5 1 2780 -560n +preplace netloc ps8_0_axi_periph_M15_AXI 1 5 4 N -540 N -540 N -540 4380 +preplace netloc ps8_0_axi_periph_M16_AXI 1 5 4 N -520 N -520 N -520 4330 +preplace netloc ps8_0_axi_periph_M17_AXI 1 5 7 N -500 NJ -500 N -500 N -500 N -500 N -500 5570 +preplace netloc ps8_0_axi_periph_M18_AXI 1 5 7 N -480 NJ -480 N -480 N -480 N -480 N -480 5500 +preplace netloc ps8_0_axi_periph_M19_AXI 1 5 8 N -460 N -460 N -460 N -460 N -460 N -460 N -460 5980 +preplace netloc ps8_0_axi_periph_M20_AXI 1 5 8 N -440 N -440 N -440 N -440 N -440 N -440 N -440 5960 +preplace netloc ps8_0_axi_periph_M21_AXI 1 5 9 N -420 NJ -420 NJ -420 N -420 NJ -420 NJ -420 N -420 N -420 6440 +preplace netloc ps8_0_axi_periph_M22_AXI 1 5 6 N -400 NJ -400 N -400 N -400 N -400 5020 +preplace netloc ps8_0_axi_periph_M23_AXI 1 5 6 N -380 N -380 N -380 N -380 N -380 5050 +preplace netloc ps8_0_axi_periph_M24_AXI 1 5 7 N -360 N -360 N -360 N -360 N -360 N -360 5470 +preplace netloc ps8_0_axi_periph_M25_AXI 1 5 8 N -340 N -340 N -340 N -340 N -340 N -340 N -340 5950 +preplace netloc ps8_0_axi_periph_M26_AXI 1 2 4 1110 1020 N 1020 N 1020 2690 +preplace netloc sysref_in_1 1 6 11 3410 2040 N 2040 N 2040 N 2040 N 2040 N 2040 N 2040 N 2040 N 2040 N 2040 N +preplace netloc usp_rf_data_converter_0_m00_axis 1 7 1 3970 440n +preplace netloc usp_rf_data_converter_0_m02_axis 1 7 1 4020 790n +preplace netloc usp_rf_data_converter_0_vout00 1 7 10 N 1640 N 1640 N 1640 N 1640 N 1640 N 1640 N 1640 N 1640 N 1640 N +preplace netloc usp_rf_data_converter_0_vout01 1 7 10 N 1660 N 1660 N 1660 N 1660 N 1660 N 1660 N 1660 N 1660 N 1660 N +preplace netloc usp_rf_data_converter_0_vout02 1 7 10 N 1680 N 1680 N 1680 N 1680 N 1680 N 1680 N 1680 N 1680 N 1680 N +preplace netloc usp_rf_data_converter_0_vout10 1 7 10 N 1700 N 1700 N 1700 N 1700 N 1700 N 1700 N 1700 N 1700 N 1700 N +preplace netloc usp_rf_data_converter_0_vout11 1 7 10 N 1720 N 1720 N 1720 N 1720 N 1720 N 1720 N 1720 N 1720 N 1720 N +preplace netloc usp_rf_data_converter_0_vout12 1 7 10 N 1740 N 1740 N 1740 N 1740 N 1740 N 1740 N 1740 N 1740 N 1740 N +preplace netloc usp_rf_data_converter_0_vout13 1 7 10 N 1760 N 1760 N 1760 N 1760 N 1760 N 1760 N 1760 N 1760 N 1760 N +preplace netloc vin0_1 1 6 11 3390 1990 N 1990 N 1990 N 1990 N 1990 N 1990 N 1990 N 1990 N 1990 N 1990 N +preplace netloc vin1_1 1 6 11 3400 2010 N 2010 N 2010 N 2010 N 2010 N 2010 N 2010 N 2010 N 2010 N 2010 N +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 4 1 2170J -1160n +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM1_FPD 1 4 11 2160J -1220 NJ -1220 NJ -1220 NJ -1220 N -1220 NJ -1220 NJ -1220 NJ -1220 NJ -1220 N -1220 6690 +levelinfo -pg 1 -40 150 820 1280 1840 2530 3080 3820 4190 4520 4830 5290 5730 6160 6560 6840 7220 7420 +pagesize -pg 1 -db -bbox -sgen -190 -1790 7570 4060 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/firmware/xdc/ios.xdc b/firmware/projects/qick_tprocv1_111_standard/ios.xdc similarity index 68% rename from firmware/xdc/ios.xdc rename to firmware/projects/qick_tprocv1_111_standard/ios.xdc index 542edb2a7..ec196598e 100644 --- a/firmware/xdc/ios.xdc +++ b/firmware/projects/qick_tprocv1_111_standard/ios.xdc @@ -6,17 +6,17 @@ set_property PACKAGE_PIN H16 [get_ports "PMOD0_2_LS"]; set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS"]; set_property PACKAGE_PIN H17 [get_ports "PMOD0_3_LS"]; set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS"]; -#set_property PACKAGE_PIN J16 [get_ports "PMOD0_4_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]; -#set_property PACKAGE_PIN K16 [get_ports "PMOD0_5_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]; -#set_property PACKAGE_PIN H15 [get_ports "PMOD0_6_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]; -#set_property PACKAGE_PIN J15 [get_ports "PMOD0_7_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]; +set_property PACKAGE_PIN J16 [get_ports "PMOD0_4_LS"]; +set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]; +set_property PACKAGE_PIN K16 [get_ports "PMOD0_5_LS"]; +set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]; +set_property PACKAGE_PIN H15 [get_ports "PMOD0_6_LS"]; +set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]; +set_property PACKAGE_PIN J15 [get_ports "PMOD0_7_LS"]; +set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]; -#set_property PACKAGE_PIN L14 [get_ports "PMOD1_0_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]; +set_property PACKAGE_PIN L14 [get_ports "PMOD1_0_LS"]; +set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]; #set_property PACKAGE_PIN L15 [get_ports "PMOD1_1_LS"]; #set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"]; #set_property PACKAGE_PIN M13 [get_ports "PMOD1_2_LS"]; diff --git a/firmware/projects/qick_tprocv1_111_standard/out/qick_111.bit b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.bit new file mode 120000 index 000000000..32c82e18f --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.bit @@ -0,0 +1 @@ +../top/top.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/firmware/projects/qick_tprocv1_111_standard/out/qick_111.hwh b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.hwh new file mode 120000 index 000000000..2ecfd9ba7 --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.hwh @@ -0,0 +1 @@ +../top/top.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/firmware/projects/qick_tprocv1_111_standard/out/qick_111.ltx b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.ltx new file mode 120000 index 000000000..87dc36017 --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_standard/out/qick_111.ltx @@ -0,0 +1 @@ +../top/top.runs/impl_1/d_1_wrapper.ltx \ No newline at end of file diff --git a/firmware/projects/qick_tprocv1_111_standard/proj.tcl b/firmware/projects/qick_tprocv1_111_standard/proj.tcl new file mode 100644 index 000000000..f6fbbfb74 --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_standard/proj.tcl @@ -0,0 +1,95 @@ +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "top" + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.4" -objects $obj +set_property -name "corecontainer.enable" -value "1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_core_container" -value "1" -objects $obj +set_property -name "enable_resource_estimation" -value "0" -objects $obj +set_property -name "dsa.board_id" -value "zcu111" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "zcu111" -objects $obj +set_property -name "revised_directory_structure" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../../ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [ file normalize "$origin_dir/../../hdl/vect2bits_16.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set files [list \ + [ file normalize "$origin_dir/timing.xdc"] \ + [ file normalize "$origin_dir/ios.xdc"] \ +] +add_files -fileset $obj $files + +# Source Block Design. +set file "[file normalize "$origin_dir/bd_2022-1.tcl"]" +source $file + +# Update compile order. +#update_compile_order -fileset sources_1 + +# Set sources_1 fileset object +set obj [get_filesets sources_1] + +# Create HDL Wrapper. +make_wrapper -files [get_files d_1.bd] -top + +# Add files to sources_1 fileset +set files [list \ + [file normalize "${origin_dir}/top/top.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ +] +add_files -fileset $obj $files + +set_property strategy "Performance_Explore" [get_runs impl_1] diff --git a/firmware/projects/qick_tprocv1_111_standard/timing.xdc b/firmware/projects/qick_tprocv1_111_standard/timing.xdc new file mode 100644 index 000000000..b04aa8531 --- /dev/null +++ b/firmware/projects/qick_tprocv1_111_standard/timing.xdc @@ -0,0 +1,48 @@ +set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/s_axi_aclk]]] +set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] +set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] +set clk_dac1 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac1]]] +set clk_ddr4 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/ddr4_0/c0_ddr4_ui_clk]]] + +#set_clock_group -name clk_axi_to_fabric -asynchronous \ +# -group [get_clocks $clk_axi] \ +# -group [get_clocks $clk_dac0] \ +# -group [get_clocks $clk_dac1] \ +# -group [get_clocks $clk_adc0_x2] + +#set_clock_group -name clk_adc_to_adc_x2 -asynchronous \ +# -group [get_clocks $clk_adc0] \ +# -group [get_clocks $clk_adc0_x2] + + + +set_clock_group -name clk_axi_to_adc0_x2 -asynchronous \ + -group [get_clocks $clk_axi] \ + -group [get_clocks $clk_adc0_x2] + +set_clock_group -name clk_axi_to_dac0 -asynchronous \ + -group [get_clocks $clk_axi] \ + -group [get_clocks $clk_dac0] + +set_clock_group -name clk_axi_to_dac1 -asynchronous \ + -group [get_clocks $clk_axi] \ + -group [get_clocks $clk_dac1] + +set_clock_group -name clk_tproc_to_dac1 -asynchronous \ + -group [get_clocks $clk_dac0] \ + -group [get_clocks $clk_dac1] + +set_clock_group -name clk_tproc_to_adc0_x2 -asynchronous \ + -group [get_clocks $clk_dac0] \ + -group [get_clocks $clk_adc0_x2] + +set_clock_group -name clk_axi_to_ddr4 -asynchronous \ + -group [get_clocks $clk_axi] \ + -group [get_clocks $clk_ddr4] + +set_clock_group -name clk_ddr4_to_adc0_x2 -asynchronous \ + -group [get_clocks $clk_ddr4] \ + -group [get_clocks $clk_adc0_x2] + +set_false_path -from [get_cells d_1_i/axis_set_reg_0/U0/dout_r_reg*] + diff --git a/firmware/projects/qick_tprocv1_216_standard/bd_2022-1.tcl b/firmware/projects/qick_tprocv1_216_standard/bd_2022-1.tcl new file mode 100644 index 000000000..c8a6c5266 --- /dev/null +++ b/firmware/projects/qick_tprocv1_216_standard/bd_2022-1.tcl @@ -0,0 +1,2538 @@ + +################################################################ +# This is a generated script based on design: d_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source d_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# vect2bits_16 + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu49dr-ffvf1760-2-e + set_property BOARD_PART xilinx.com:zcu216:part0:2.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name d_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:blk_mem_gen:8.4\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:smartconnect:1.0\ +QICK:QICK:axis_avg_buffer:1.2\ +xilinx.com:ip:axis_broadcaster:1.1\ +QICK:QICK:axis_buffer_ddr_v1:1.0\ +QICK:QICK:axis_cdcsync_v1:1.0\ +xilinx.com:ip:axis_clock_converter:1.1\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +QICK:QICK:axis_readout_v2:1.0\ +xilinx.com:ip:axis_register_slice:1.1\ +QICK:QICK:axis_set_reg:1.0\ +QICK:QICK:axis_signal_gen_v6:1.0\ +xilinx.com:ip:axis_switch:1.1\ +QICK:QICK:axis_tproc64x32_x8:1.0\ +xilinx.com:ip:ddr4:2.2\ +QICK:QICK:mr_buffer_et:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:usp_rf_data_converter:2.6\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:zynq_ultra_ps_e:3.4\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +vect2bits_16\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk_0 ] + + set dac2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk_0 ] + + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_sysclk_c0_300mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_sysclk_c0_300mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_sysclk_c0_300mhz + + set sysref_in_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in_0 ] + + set vin20_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin20_0 ] + + set vin22_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin22_0 ] + + set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] + + set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] + + set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] + + set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] + + set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] + + set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] + + set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] + + + # Create ports + set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] + set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] + set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] + set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] + set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] + set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] + set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] + set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] + set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [ list \ + CONFIG.Byte_Size {8} \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Read_Width_B {64} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_B {64} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $axi_bram_ctrl_0_bram + + # Create instance: axi_dma_avg, and set properties + set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_avg + + # Create instance: axi_dma_buf, and set properties + set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_buf + + # Create instance: axi_dma_gen, and set properties + set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] + set_property -dict [ list \ + CONFIG.c_include_s2mm {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_gen + + # Create instance: axi_dma_mr, and set properties + set axi_dma_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mr ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_mr + + # Create instance: axi_dma_tproc, and set properties + set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] + set_property -dict [ list \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_tproc + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + set_property -dict [ list \ + CONFIG.C_IRQ_CONNECTION {1} \ + ] $axi_intc_0 + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {6} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + + # Create instance: axis_avg_buffer_0, and set properties + set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_0 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_0 + + # Create instance: axis_avg_buffer_1, and set properties + set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_1 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_1 + + # Create instance: axis_broadcaster_0, and set properties + set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_0 + + # Create instance: axis_broadcaster_1, and set properties + set axis_broadcaster_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_1 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_1 + + # Create instance: axis_buffer_ddr_v1_0, and set properties + set axis_buffer_ddr_v1_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_buffer_ddr_v1:1.0 axis_buffer_ddr_v1_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.TARGET_SLAVE_BASE_ADDR {0x00000000} \ + ] $axis_buffer_ddr_v1_0 + + # Create instance: axis_cdcsync_v1_0, and set properties + set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_0 + + # Create instance: axis_cdcsync_v1_1, and set properties + set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_1 + + # Create instance: axis_clk_cnvrt_avg_0, and set properties + set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] + + # Create instance: axis_clk_cnvrt_avg_1, and set properties + set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] + + # Create instance: axis_clock_converter_0, and set properties + set axis_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_0 ] + + # Create instance: axis_dwidth_converter_0, and set properties + set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ] + set_property -dict [ list \ + CONFIG.M_TDATA_NUM_BYTES {32} \ + ] $axis_dwidth_converter_0 + + # Create instance: axis_readout_v2_0, and set properties + set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_0 ] + + # Create instance: axis_readout_v2_1, and set properties + set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_1 ] + + # Create instance: axis_register_slice_0, and set properties + set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] + + # Create instance: axis_register_slice_1, and set properties + set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] + + # Create instance: axis_register_slice_2, and set properties + set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] + + # Create instance: axis_register_slice_3, and set properties + set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] + + # Create instance: axis_register_slice_4, and set properties + set axis_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_4 ] + + # Create instance: axis_register_slice_5, and set properties + set axis_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_5 ] + + # Create instance: axis_register_slice_6, and set properties + set axis_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_6 ] + + # Create instance: axis_register_slice_7, and set properties + set axis_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_7 ] + + # Create instance: axis_register_slice_8, and set properties + set axis_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_8 ] + + # Create instance: axis_set_reg_0, and set properties + set axis_set_reg_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_set_reg:1.0 axis_set_reg_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {160} \ + ] $axis_set_reg_0 + + # Create instance: axis_signal_gen_v6_0, and set properties + set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] + + # Create instance: axis_signal_gen_v6_1, and set properties + set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] + + # Create instance: axis_signal_gen_v6_2, and set properties + set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] + + # Create instance: axis_signal_gen_v6_3, and set properties + set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] + + # Create instance: axis_signal_gen_v6_4, and set properties + set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] + + # Create instance: axis_signal_gen_v6_5, and set properties + set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] + + # Create instance: axis_signal_gen_v6_6, and set properties + set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] + + # Create instance: axis_switch_avg, and set properties + set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_avg + + # Create instance: axis_switch_buf, and set properties + set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_buf + + # Create instance: axis_switch_ddr, and set properties + set axis_switch_ddr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_ddr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_ddr + + # Create instance: axis_switch_gen, and set properties + set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI {7} \ + CONFIG.NUM_SI {1} \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_gen + + # Create instance: axis_switch_mr, and set properties + set axis_switch_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_mr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_mr + + # Create instance: axis_tproc64x32_x8_0, and set properties + set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] + set_property -dict [ list \ + CONFIG.DMEM_N {12} \ + CONFIG.PMEM_N {20} \ + ] $axis_tproc64x32_x8_0 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiDataWidth {256} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_Clamshell {true} \ + CONFIG.C0.DDR4_DataWidth {32} \ + CONFIG.C0.DDR4_InputClockPeriod {3334} \ + CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c0_300mhz} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + ] $ddr4_0 + + # Create instance: mr_buffer_et_0, and set properties + set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv QICK:QICK:mr_buffer_et:1.1 mr_buffer_et_0 ] + set_property -dict [ list \ + CONFIG.B {32} \ + CONFIG.N {10} \ + ] $mr_buffer_et_0 + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {27} \ + ] $ps8_0_axi_periph + + # Create instance: rst_100, and set properties + set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] + + # Create instance: rst_adc, and set properties + set rst_adc [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_adc + + # Create instance: rst_dac2, and set properties + set rst_dac2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac2 ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_dac2 + + # Create instance: rst_dac3, and set properties + set rst_dac3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac3 ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_dac3 + + # Create instance: rst_ddr4, and set properties + set rst_ddr4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4 ] + + # Create instance: usp_rf_data_converter_0, and set properties + set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.6 usp_rf_data_converter_0 ] + set_property -dict [ list \ + CONFIG.ADC2_Clock_Dist {0} \ + CONFIG.ADC2_Fabric_Freq {307.200} \ + CONFIG.ADC2_Outclk_Freq {307.200} \ + CONFIG.ADC2_PLL_Enable {true} \ + CONFIG.ADC2_Refclk_Freq {245.760} \ + CONFIG.ADC2_Sampling_Rate {2.4576} \ + CONFIG.ADC3_Enable {0} \ + CONFIG.ADC3_Fabric_Freq {0.0} \ + CONFIG.ADC_Coarse_Mixer_Freq20 {3} \ + CONFIG.ADC_Coarse_Mixer_Freq22 {3} \ + CONFIG.ADC_Coarse_Mixer_Freq30 {0} \ + CONFIG.ADC_Data_Width20 {8} \ + CONFIG.ADC_Decimation_Mode20 {1} \ + CONFIG.ADC_Decimation_Mode22 {1} \ + CONFIG.ADC_Decimation_Mode30 {0} \ + CONFIG.ADC_Mixer_Type20 {1} \ + CONFIG.ADC_Mixer_Type22 {1} \ + CONFIG.ADC_Mixer_Type30 {3} \ + CONFIG.ADC_OBS22 {false} \ + CONFIG.ADC_OBS31 {false} \ + CONFIG.ADC_OBS32 {false} \ + CONFIG.ADC_OBS33 {false} \ + CONFIG.ADC_RESERVED_1_20 {false} \ + CONFIG.ADC_RESERVED_1_21 {false} \ + CONFIG.ADC_RESERVED_1_22 {false} \ + CONFIG.ADC_RESERVED_1_23 {false} \ + CONFIG.ADC_RESERVED_1_30 {false} \ + CONFIG.ADC_RESERVED_1_31 {false} \ + CONFIG.ADC_RESERVED_1_32 {false} \ + CONFIG.ADC_RESERVED_1_33 {false} \ + CONFIG.ADC_Slice00_Enable {false} \ + CONFIG.ADC_Slice20_Enable {true} \ + CONFIG.ADC_Slice21_Enable {false} \ + CONFIG.ADC_Slice22_Enable {true} \ + CONFIG.ADC_Slice30_Enable {false} \ + CONFIG.DAC2_Clock_Dist {1} \ + CONFIG.DAC2_Fabric_Freq {430.080} \ + CONFIG.DAC2_Outclk_Freq {430.080} \ + CONFIG.DAC2_PLL_Enable {true} \ + CONFIG.DAC2_Refclk_Freq {245.760} \ + CONFIG.DAC2_Sampling_Rate {6.88128} \ + CONFIG.DAC3_Clock_Source {6} \ + CONFIG.DAC3_Fabric_Freq {430.080} \ + CONFIG.DAC3_Outclk_Freq {430.080} \ + CONFIG.DAC3_PLL_Enable {true} \ + CONFIG.DAC3_Refclk_Freq {245.760} \ + CONFIG.DAC3_Sampling_Rate {6.88128} \ + CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq21 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq22 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq23 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq30 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq31 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq32 {3} \ + CONFIG.DAC_Interpolation_Mode20 {1} \ + CONFIG.DAC_Interpolation_Mode21 {1} \ + CONFIG.DAC_Interpolation_Mode22 {1} \ + CONFIG.DAC_Interpolation_Mode23 {1} \ + CONFIG.DAC_Interpolation_Mode30 {1} \ + CONFIG.DAC_Interpolation_Mode31 {1} \ + CONFIG.DAC_Interpolation_Mode32 {1} \ + CONFIG.DAC_Mixer_Type20 {1} \ + CONFIG.DAC_Mixer_Type21 {1} \ + CONFIG.DAC_Mixer_Type22 {1} \ + CONFIG.DAC_Mixer_Type23 {1} \ + CONFIG.DAC_Mixer_Type30 {1} \ + CONFIG.DAC_Mixer_Type31 {1} \ + CONFIG.DAC_Mixer_Type32 {1} \ + CONFIG.DAC_Mode20 {3} \ + CONFIG.DAC_Mode21 {3} \ + CONFIG.DAC_Mode22 {3} \ + CONFIG.DAC_Mode23 {3} \ + CONFIG.DAC_Mode30 {3} \ + CONFIG.DAC_Mode31 {3} \ + CONFIG.DAC_Mode32 {3} \ + CONFIG.DAC_Slice20_Enable {true} \ + CONFIG.DAC_Slice21_Enable {true} \ + CONFIG.DAC_Slice22_Enable {true} \ + CONFIG.DAC_Slice23_Enable {true} \ + CONFIG.DAC_Slice30_Enable {true} \ + CONFIG.DAC_Slice31_Enable {true} \ + CONFIG.DAC_Slice32_Enable {true} \ + CONFIG.DAC_Slice33_Enable {false} \ + CONFIG.DAC_VOP_Mode {0} \ + ] $usp_rf_data_converter_0 + + # Create instance: vect2bits_16_0, and set properties + set block_name vect2bits_16 + set block_cell_name vect2bits_16_0 + if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $vect2bits_16_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + + # Create instance: xlconcat_1, and set properties + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {6} \ + ] $xlconcat_1 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {64} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_1 + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {8} \ + ] $xlconstant_2 + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_3 + + # Create instance: xlconstant_4, and set properties + set xlconstant_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_4 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {12} \ + ] $xlconstant_4 + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {inout} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {inout} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {inout} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {inout} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {out} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {\ +Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\ +Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART\ +0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1\ +MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU\ +GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1\ +MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {\ +sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1049.999878} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1066} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.999977} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.999977} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {11} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {46.5} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.000} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999985} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {0} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {