https://github.com/buserror/simavr/blob/master/simavr/sim/avr_uart.c#L248 Sometimes (most of the time?) there are zero parity bits but simavr assume's there's always one.
https://github.com/buserror/simavr/blob/master/simavr/sim/avr_uart.c#L248
Sometimes (most of the time?) there are zero parity bits but simavr assume's there's always one.