diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 0d69098eddd90..08008b2885c0c 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -487,6 +487,7 @@ static int panel_dpi_probe(struct device *dev, of_property_read_u32(np, "width-mm", &desc->size.width); of_property_read_u32(np, "height-mm", &desc->size.height); + of_property_read_u32(np, "bus-format", &desc->bus_format); /* Extract bus_flags from display_timing */ bus_flags = 0; diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index dbfbde24698ef..aa1273dca6859 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -7,7 +7,9 @@ #include #include +#include #include +#include #include #include @@ -21,6 +23,18 @@ #include "rockchip_drm_drv.h" #include "rockchip_rgb.h" +/* + * RV1106 routes the VOP's parallel-RGB output through two GRF "bypass" + * gates that come up enabled at reset. The vendor 5.10 rgb driver + * clears them (HIWORD write, bits[1:0]=0) on enable; mainline's + * rockchip_rgb is a stripped library that never touches the GRF, so on + * a fresh boot the data path stays in bypass and the panel shows + * corrupted output. Clear both gates for the RGB use case. + */ +#define RV1106_VENC_GRF_VOP_IO_WRAPPER 0x1000c +#define RV1106_VOGRF_VOP_PIPE_BYPASS 0x60034 +#define RV1106_GRF_BYPASS_CLEAR (0x3 << 16) /* mask bits[1:0], value 0 */ + struct rockchip_rgb { struct device *dev; struct drm_device *drm_dev; @@ -45,17 +59,28 @@ rockchip_rgb_encoder_atomic_check(struct drm_encoder *encoder, else bus_format = MEDIA_BUS_FMT_RGB888_1X24; + /* + * output_bpc gates the dither-down stage in vop_crtc_atomic_enable + * (it computes dither_bpc = output_bpc ? : 10 and only enables dither + * when that is 6). Mainline sets output_bpc only on the eDP path, so a + * raw-RGB panel kept out_mode=P666 with the 24->18-bit dither block + * disabled and the parallel output was truncated, not reduced. Set it + * from the bus format so the dither stage matches the panel depth. + */ switch (bus_format) { case MEDIA_BUS_FMT_RGB666_1X18: s->output_mode = ROCKCHIP_OUT_MODE_P666; + s->output_bpc = 6; break; case MEDIA_BUS_FMT_RGB565_1X16: s->output_mode = ROCKCHIP_OUT_MODE_P565; + s->output_bpc = 5; break; case MEDIA_BUS_FMT_RGB888_1X24: case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: default: s->output_mode = ROCKCHIP_OUT_MODE_P888; + s->output_bpc = 8; break; } @@ -168,6 +193,30 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, goto err_free_connector; } + /* + * RV1106: take the VOP->RGB IO wrapper and VOP pipe out of bypass. + * These GRF gates reset to "bypass" and mainline never clears them, + * leaving the parallel-RGB data path corrupted. Guarded on the GRF + * being the rv1106 grf so this is a no-op on other SoCs. + */ + { + struct device_node *grf_np; + struct regmap *grf; + + grf_np = of_parse_phandle(dev->of_node, "rockchip,grf", 0); + if (grf_np && of_device_is_compatible(grf_np, "rockchip,rv1106-grf")) { + grf = syscon_node_to_regmap(grf_np); + if (!IS_ERR(grf)) { + regmap_write(grf, RV1106_VENC_GRF_VOP_IO_WRAPPER, + RV1106_GRF_BYPASS_CLEAR); + regmap_write(grf, RV1106_VOGRF_VOP_PIPE_BYPASS, + RV1106_GRF_BYPASS_CLEAR); + DRM_DEV_INFO(dev, "rv1106: cleared VOP RGB bypass gates\n"); + } + } + of_node_put(grf_np); + } + return rgb; err_free_connector: diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index f7d0edd762b36..3be6a0e5b9f2f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1122,6 +1122,28 @@ static const struct vop_data rk3328_vop = { .max_output = { 4096, 2160 }, }; +/* + * RV1106 VOP. The IP is functionally identical to PX30's "lit" VOP variant + * (which is itself the same IP as RK3366-LIT in the vendor SDK) -- register + * addresses, interrupt layout, and single-primary-window structure all match, + * so we reuse PX30's per-block tables verbatim. RV1106-specific bits from the + * vendor 5.10 source are: a different VOP_VERSION (2, 0xc), a smaller native + * resolution cap (1280x1280), and a GRF-driven dclk-inversion knob. The GRF + * knob has no 6.6 equivalent (struct vop_data lost grf_ctrl), so we skip it; + * it can be re-added via a driver-core change later if a board needs it. + */ +static const struct vop_data rv1106_vop = { + .version = VOP_VERSION(2, 0xc), + .intr = &px30_intr, + .feature = VOP_FEATURE_INTERNAL_RGB, + .common = &px30_common, + .modeset = &px30_modeset, + .output = &px30_output, + .win = px30_vop_lit_win_data, + .win_size = ARRAY_SIZE(px30_vop_lit_win_data), + .max_output = { 1280, 1280 }, +}; + static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, @@ -1149,6 +1171,8 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3228_vop }, { .compatible = "rockchip,rk3328-vop", .data = &rk3328_vop }, + { .compatible = "rockchip,rv1106-vop", + .data = &rv1106_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 001ceee5673e4..674f7488b9a6b 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -743,6 +743,7 @@ static struct nvmem_config otp_config = { .read_only = true, .reg_read = rockchip_otp_read, .reg_write = rockchip_otp_write, + .add_legacy_fixed_of_cells = true, .stride = 1, .word_size = 1, }; diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile index 9f75a77907ac6..8015b2c47bf21 100644 --- a/drivers/soc/rockchip/Makefile +++ b/drivers/soc/rockchip/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o obj-$(CONFIG_ROCKCHIP_HW_DECOMPRESS_USER) += rockchip_decompress_user.o obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o obj-$(CONFIG_ROCKCHIP_IOMUX) += iomux.o -obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o obj-$(CONFIG_ROCKCHIP_DTPM) += dtpm.o obj-$(CONFIG_ROCKCHIP_FIQ_DEBUGGER) += fiq_debugger/ obj-$(CONFIG_ROCKCHIP_VENDOR_STORAGE) += rk_vendor_storage.o diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h new file mode 100644 index 0000000000000..034ae05b7ff5e --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H + +/* pll clocks */ +#define PLL_GPLL 1 +#define ARMCLK 2 +#define PLL_DPLL 3 + +/* clk (clocks) */ +#define XIN_OSC0_HALF 5 +#define CLK_GPLL_DIV24 6 +#define CLK_GPLL_DIV12 7 +#define CLK_GPLL_DIV6 8 +#define CLK_GPLL_DIV4 9 +#define CLK_GPLL_DIV3 10 +#define CLK_GPLL_DIV2P5 11 +#define CLK_GPLL_DIV2 12 +#define CLK_UART0_SRC 13 +#define CLK_UART1_SRC 14 +#define CLK_UART2_SRC 15 +#define CLK_UART0_FRAC 16 +#define CLK_UART1_FRAC 17 +#define CLK_UART2_FRAC 18 +#define CLK_SAI_SRC 19 +#define CLK_SAI_FRAC 20 +#define LSCLK_NPU_SRC 21 +#define CLK_NPU_SRC 22 +#define ACLK_VEPU_SRC 23 +#define CLK_VEPU_SRC 24 +#define ACLK_VI_SRC 25 +#define CLK_ISP_SRC 26 +#define DCLK_VICAP 27 +#define CCLK_EMMC 28 +#define CCLK_SDMMC0 29 +#define SCLK_SFC_2X 30 +#define LSCLK_PERI_SRC 31 +#define ACLK_PERI_SRC 32 +#define HCLK_HPMCU 33 +#define SCLK_UART0 34 +#define SCLK_UART1 35 +#define SCLK_UART2 36 +#define CLK_I2C_PMU 37 +#define CLK_I2C_PERI 38 +#define CLK_SPI0 39 +#define CLK_PWM0_SRC 40 +#define CLK_PWM1 41 +#define CLK_PWM2 42 +#define DCLK_DECOM_SRC 43 +#define CCLK_SDMMC1 44 +#define CLK_CORE_CRYPTO 45 +#define CLK_PKA_CRYPTO 46 +#define CLK_CORE_RGA 47 +#define MCLK_SAI_SRC 48 +#define CLK_FREQ_PWM0_SRC 49 +#define CLK_COUNTER_PWM0_SRC 50 +#define PCLK_TOP_ROOT 51 +#define CLK_REF_MIPI0 52 +#define CLK_MIPI0_OUT2IO 53 +#define CLK_REF_MIPI1 54 +#define CLK_MIPI1_OUT2IO 55 +#define MCLK_SAI_OUT2IO 56 +#define ACLK_NPU_ROOT 57 +#define HCLK_RKNN 58 +#define ACLK_RKNN 59 +#define LSCLK_VEPU_ROOT 60 +#define HCLK_VEPU 61 +#define ACLK_VEPU 62 +#define CLK_CORE_VEPU 63 +#define PCLK_IOC_VCCIO3 64 +#define PCLK_ACODEC 65 +#define PCLK_USBPHY 66 +#define LSCLK_VI_100M 67 +#define LSCLK_VI_ROOT 68 +#define HCLK_ISP 69 +#define ACLK_ISP 70 +#define CLK_CORE_ISP 71 +#define ACLK_VICAP 72 +#define HCLK_VICAP 73 +#define ISP0CLK_VICAP 74 +#define PCLK_CSI2HOST0 75 +#define PCLK_CSI2HOST1 76 +#define HCLK_EMMC 77 +#define HCLK_SFC 78 +#define HCLK_SFC_XIP 79 +#define HCLK_SDMMC0 80 +#define PCLK_CSIPHY 81 +#define PCLK_GPIO1 82 +#define DBCLK_GPIO1 83 +#define PCLK_IOC_VCCIO47 84 +#define LSCLK_DDR_ROOT 85 +#define CLK_TIMER_DDRMON 86 +#define LSCLK_PMU_ROOT 87 +#define PCLK_PMU 88 +#define XIN_RC_DIV 89 +#define CLK_32K 90 +#define PCLK_PMU_GPIO0 91 +#define DBCLK_PMU_GPIO0 92 +#define CLK_DDR_FAIL_SAFE 93 +#define PCLK_PMU_HP_TIMER 94 +#define CLK_PMU_32K_HP_TIMER 95 +#define PCLK_PWM0 96 +#define CLK_PWM0 97 +#define CLK_OSC_PWM0 98 +#define CLK_RC_PWM0 99 +#define CLK_FREQ_PWM0 100 +#define CLK_COUNTER_PWM0 101 +#define PCLK_I2C0 102 +#define CLK_I2C0 103 +#define PCLK_UART0 104 +#define PCLK_IOC_PMUIO0 105 +#define CLK_REFOUT 106 +#define CLK_PREROLL 107 +#define CLK_PREROLL_32K 108 +#define CLK_LPMCU_PMU 109 +#define PCLK_SPI2AHB 110 +#define HCLK_SPI2AHB 111 +#define SCLK_SPI2AHB 112 +#define PCLK_WDT_LPMCU 113 +#define TCLK_WDT_LPMCU 114 +#define HCLK_SFC_PMU1 115 +#define HCLK_SFC_XIP_PMU1 116 +#define SCLK_SFC_2X_PMU1 117 +#define CLK_LPMCU 118 +#define CLK_LPMCU_RTC 119 +#define PCLK_LPMCU_MAILBOX 120 +#define PCLK_IOC_PMUIO1 121 +#define PCLK_CRU_PMU1 122 +#define PCLK_PERI_ROOT 123 +#define PCLK_RTC_ROOT 124 +#define CLK_TIMER_ROOT 125 +#define PCLK_TIMER 126 +#define CLK_TIMER0 127 +#define CLK_TIMER1 128 +#define CLK_TIMER2 129 +#define CLK_TIMER3 130 +#define CLK_TIMER4 131 +#define CLK_TIMER5 132 +#define PCLK_STIMER 133 +#define CLK_STIMER0 134 +#define CLK_STIMER1 135 +#define PCLK_WDT_NS 136 +#define TCLK_WDT_NS 137 +#define PCLK_WDT_S 138 +#define TCLK_WDT_S 139 +#define PCLK_WDT_HPMCU 140 +#define TCLK_WDT_HPMCU 141 +#define PCLK_I2C1 142 +#define CLK_I2C1 143 +#define PCLK_I2C2 144 +#define CLK_I2C2 145 +#define PCLK_I2C3 146 +#define CLK_I2C3 147 +#define PCLK_I2C4 148 +#define CLK_I2C4 149 +#define PCLK_SPI0 150 +#define PCLK_PWM1 151 +#define CLK_OSC_PWM1 152 +#define PCLK_PWM2 153 +#define CLK_OSC_PWM2 154 +#define PCLK_UART2 155 +#define PCLK_UART1 156 +#define ACLK_RKDMA 157 +#define PCLK_TSADC 158 +#define CLK_TSADC 159 +#define CLK_TSADC_TSEN 160 +#define PCLK_SARADC 161 +#define CLK_SARADC 162 +#define PCLK_GPIO2 163 +#define DBCLK_GPIO2 164 +#define PCLK_IOC_VCCIO6 165 +#define ACLK_USBOTG 166 +#define CLK_REF_USBOTG 167 +#define HCLK_SDMMC1 168 +#define HCLK_SAI 169 +#define MCLK_SAI 170 +#define ACLK_CRYPTO 171 +#define HCLK_CRYPTO 172 +#define HCLK_RK_RNG_NS 173 +#define HCLK_RK_RNG_S 174 +#define PCLK_OTPC_NS 175 +#define CLK_OTPC_ROOT_NS 176 +#define CLK_SBPI_OTPC_NS 177 +#define CLK_USER_OTPC_NS 178 +#define PCLK_OTPC_S 179 +#define CLK_OTPC_ROOT_S 180 +#define CLK_SBPI_OTPC_S 181 +#define CLK_USER_OTPC_S 182 +#define CLK_OTPC_ARB 183 +#define PCLK_OTP_MASK 184 +#define HCLK_RGA 185 +#define ACLK_RGA 186 +#define ACLK_MAC 187 +#define PCLK_MAC 188 +#define CLK_MACPHY 189 +#define ACLK_SPINLOCK 190 +#define HCLK_CACHE 191 +#define PCLK_HPMCU_MAILBOX 192 +#define PCLK_HPMCU_INTMUX 193 +#define CLK_HPMCU 194 +#define CLK_HPMCU_RTC 195 +#define DCLK_DECOM 196 +#define ACLK_DECOM 197 +#define PCLK_DECOM 198 +#define ACLK_SYS_SRAM 199 +#define PCLK_DMA2DDR 200 +#define ACLK_DMA2DDR 201 +#define PCLK_DCF 202 +#define ACLK_DCF 203 +#define MCLK_ACODEC_TX 204 +#define SCLK_UART0_SRC 205 +#define SCLK_UART1_SRC 206 +#define SCLK_UART2_SRC 207 +#define XIN_RC_SRC 208 +#define CLK_UTMI_USBOTG 209 +#define CLK_REF_USBPHY 230 + +#define CLK_NR_CLKS (CLK_REF_USBPHY + 1) + +// PERICRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_PERI_BIU 0x00000002 +#define SRST_HRESETN_HPMCU_BIU 0x00000003 +#define SRST_LSRESETN_PERI_BIU 0x00000004 +#define SRST_PRESETN_PERI_BIU 0x00000005 +#define SRST_PRESETN_RTC_BIU 0x00000006 +#define SRST_HRESETN_BOOTROM 0x00000007 + +// PERICRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_TIMER 0x00000010 +#define SRST_RESETN_TIMER0 0x00000011 +#define SRST_RESETN_TIMER1 0x00000012 +#define SRST_RESETN_TIMER2 0x00000013 +#define SRST_RESETN_TIMER3 0x00000014 +#define SRST_RESETN_TIMER4 0x00000015 +#define SRST_RESETN_TIMER5 0x00000016 +#define SRST_PRESETN_STIMER 0x00000017 +#define SRST_RESETN_STIMER0 0x00000018 +#define SRST_RESETN_STIMER1 0x00000019 + +// PERICRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_PRESETN_WDT_NS 0x00000020 +#define SRST_TRESETN_WDT_NS 0x00000021 +#define SRST_PRESETN_WDT_S 0x00000022 +#define SRST_TRESETN_WDT_S 0x00000023 +#define SRST_PRESETN_WDT_HPMCU 0x00000024 +#define SRST_TRESETN_WDT_HPMCU 0x00000025 +#define SRST_PRESETN_I2C1 0x00000026 +#define SRST_RESETN_I2C1 0x00000027 +#define SRST_PRESETN_I2C2 0x00000028 +#define SRST_RESETN_I2C2 0x00000029 +#define SRST_PRESETN_I2C3 0x0000002A +#define SRST_RESETN_I2C3 0x0000002B +#define SRST_PRESETN_I2C4 0x0000002C +#define SRST_RESETN_I2C4 0x0000002D + +// PERICRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_PRESETN_UART2 0x00000030 +#define SRST_SRESETN_UART2 0x00000031 +#define SRST_PRESETN_UART1 0x00000032 +#define SRST_SRESETN_UART1 0x00000033 +#define SRST_PRESETN_SPI0 0x0000003A +#define SRST_RESETN_SPI0 0x0000003B + +// PERICRU_SOFTRST_CON04(Offset:0xA10) +#define SRST_PRESETN_PWM1 0x00000046 +#define SRST_RESETN_PWM1 0x00000047 +#define SRST_PRESETN_PWM2 0x0000004C +#define SRST_RESETN_PWM2 0x0000004D + +// PERICRU_SOFTRST_CON05(Offset:0xA14) +#define SRST_ARESETN_RKDMA 0x00000058 +#define SRST_PRESETN_TSADC 0x00000059 +#define SRST_RESETN_TSADC 0x0000005A +#define SRST_PRESETN_SARADC 0x0000005C +#define SRST_RESETN_SARADC 0x0000005D + +// PERICRU_SOFTRST_CON06(Offset:0xA18) +#define SRST_RESETN_SARADC_PHY 0x00000060 +#define SRST_PRESETN_RTC_TEST 0x00000061 +#define SRST_PRESETN_GPIO2 0x00000063 +#define SRST_DBRESETN_GPIO2 0x00000064 +#define SRST_PRESETN_IOC_VCCIO6 0x00000065 +#define SRST_PRESETN_PERI_SGRF 0x00000066 +#define SRST_PRESETN_PERI_GRF 0x00000067 +#define SRST_PRESETN_CRU_PERI 0x00000068 +#define SRST_ARESETN_USBOTG 0x00000069 + +// PERICRU_SOFTRST_CON07(Offset:0xA1C) +#define SRST_HRESETN_SDMMC1 0x00000070 +#define SRST_HRESETN_SAI 0x00000071 +#define SRST_MRESETN_SAI 0x00000072 + +// PERICRU_SOFTRST_CON08(Offset:0xA20) +#define SRST_RESETN_CORE_CRYPTO 0x00000080 +#define SRST_RESETN_PKA_CRYPTO 0x00000081 +#define SRST_ARESETN_CRYPTO 0x00000082 +#define SRST_HRESETN_CRYPTO 0x00000083 +#define SRST_HRESETN_RK_RNG_NS 0x00000084 +#define SRST_HRESETN_RK_RNG_S 0x00000085 +#define SRST_PRESETN_OTPC_NS 0x00000086 +#define SRST_RESETN_SBPI_OTPC_NS 0x00000088 +#define SRST_RESETN_USER_OTPC_NS 0x00000089 +#define SRST_PRESETN_OTPC_S 0x0000008A +#define SRST_RESETN_SBPI_OTPC_S 0x0000008C +#define SRST_RESETN_USER_OTPC_S 0x0000008D +#define SRST_RESETN_OTPC_ARB 0x0000008E +#define SRST_PRESETN_OTP_MASK 0x0000008F + +// PERICRU_SOFTRST_CON09(Offset:0xA24) +#define SRST_HRESETN_RGA 0x00000090 +#define SRST_ARESETN_RGA 0x00000091 +#define SRST_RESETN_CORE_RGA 0x00000092 +#define SRST_ARESETN_MAC 0x00000093 +#define SRST_RESETN_MACPHY 0x0000009B + +// PERICRU_SOFTRST_CON10(Offset:0xA28) +#define SRST_ARESETN_SPINLOCK 0x000000A0 +#define SRST_HRESETN_CACHE 0x000000A1 +#define SRST_PRESETN_HPMCU_MAILBOX 0x000000A2 +#define SRST_PRESETN_HPMCU_INTMUX 0x000000A3 +#define SRST_RESETN_HPMCU_FULL_CLUSTER 0x000000A4 +#define SRST_RESETN_HPMCU_PWUP 0x000000A5 +#define SRST_RESETN_HPMCU_ONLY_CORE 0x000000A6 +#define SRST_TRESETN_HPMCU_JTAG 0x000000A7 + +// PERICRU_SOFTRST_CON11(Offset:0xA2C) +#define SRST_DRESETN_DECOM 0x000000B0 +#define SRST_ARESETN_DECOM 0x000000B1 +#define SRST_PRESETN_DECOM 0x000000B2 +#define SRST_ARESETN_SYS_SRAM 0x000000B3 +#define SRST_PRESETN_DMA2DDR 0x000000B4 +#define SRST_ARESETN_DMA2DDR 0x000000B5 +#define SRST_PRESETN_DCF 0x000000B6 +#define SRST_ARESETN_DCF 0x000000B7 +#define SRST_RESETN_USBPHY_POR 0x000000BC +#define SRST_RESETN_USBPHY_OTG 0x000000BD + +// ======================= VEPUCRU module definition bank=1 ======================= +// VEPUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_VEPU_BIU 0x00040001 +#define SRST_LSRESETN_VEPU_BIU 0x00040002 +#define SRST_RESETN_REF_PVTPLL_VEPU 0x00040003 +#define SRST_HRESETN_VEPU 0x00040004 +#define SRST_ARESETN_VEPU 0x00040005 +#define SRST_RESETN_CORE_VEPU 0x00040006 +#define SRST_PRESETN_VEPU_PVTPLL 0x00040007 +#define SRST_PRESETN_CRU_VEPU 0x00040008 +#define SRST_PRESETN_VEPU_GRF 0x0004000A +#define SRST_PRESETN_IOC_VCCIO3 0x0004000B +#define SRST_PRESETN_ACODEC 0x0004000D +#define SRST_PRESETN_USBPHY 0x0004000E + +// ======================= NPUCRU module definition bank=2 ======================== +// NPUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_NPU 0x00080000 +#define SRST_ARESETN_NPU_BIU 0x00080002 +#define SRST_LSRESETN_NPU_BIU 0x00080003 +#define SRST_HRESETN_RKNN 0x00080004 +#define SRST_ARESETN_RKNN 0x00080005 +#define SRST_PRESETN_NPU_PVTPLL 0x00080006 +#define SRST_PRESETN_CRU_NPU 0x00080007 +#define SRST_PRESETN_NPU_GRF 0x00080009 + +// ======================== VICRU module definition bank=3 ======================== +// VICRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_LSRESETN_VI_BIU 0x000c0001 +#define SRST_ARESETN_VI_BIU 0x000c0002 +#define SRST_RESETN_REF_PVTPLL_ISP 0x000c0003 +#define SRST_RESETN_CORE_ISP 0x000c0006 + +// VICRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_DRESETN_VICAP 0x000c0010 +#define SRST_ARESETN_VICAP 0x000c0012 +#define SRST_HRESETN_VICAP 0x000c0013 +#define SRST_ISP0RESETN_VICAP 0x000c0018 +#define SRST_PRESETN_CSI2HOST0 0x000c0019 +#define SRST_PRESETN_CSI2HOST1 0x000c001B +#define SRST_SRESETN_SFC_2X 0x000c001C +#define SRST_HRESETN_EMMC 0x000c001D +#define SRST_HRESETN_SFC 0x000c001E +#define SRST_HRESETN_SFC_XIP 0x000c001F + +// VICRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_HRESETN_SDMMC0 0x000c0020 +#define SRST_PRESETN_CSIPHY 0x000c0022 +#define SRST_PRESETN_GPIO1 0x000c0023 +#define SRST_DBRESETN_GPIO1 0x000c0024 +#define SRST_PRESETN_IOC_VCCIO47 0x000c0025 +#define SRST_PRESETN_VI_GRF 0x000c0026 +#define SRST_PRESETN_CRU_VI 0x000c0028 +#define SRST_PRESETN_VI_PVTPLL 0x000c0029 + +// ======================= CORECRU module definition bank=4 ======================= +// CORECRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_CORE 0x00100000 +#define SRST_NCOREPORESET 0x00100001 +#define SRST_NCORESET 0x00100002 +#define SRST_NDBGRESET 0x00100003 +#define SRST_NL2RESET 0x00100004 +#define SRST_ARESETN_CORE_BIU 0x00100005 +#define SRST_PRESETN_CORE_BIU 0x00100006 +#define SRST_HRESETN_CORE_BIU 0x00100007 +#define SRST_PRESETN_DBG 0x00100008 +#define SRST_POTRESETN_DBG 0x00100009 +#define SRST_NTRESETN_DBG 0x0010000A + +// ======================= DDRCRU module definition bank=5 ======================== +// DDRCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_LSRESETN_DDR_BIU 0x00140001 +#define SRST_PRESETN_DDRC 0x00140002 +#define SRST_PRESETN_DDRMON 0x00140003 +#define SRST_RESETN_TIMER_DDRMON 0x00140004 +#define SRST_PRESETN_DFICTRL 0x00140005 +#define SRST_PRESETN_DDR_GRF 0x00140006 +#define SRST_PRESETN_CRU_DDR 0x00140007 +#define SRST_HRESETN_DDRPHY 0x00140008 + +// ====================== SUBDDRCRU module definition bank=6 ====================== +// SUBDDRCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_DDR_BIU 0x00160001 +#define SRST_ARESETN_DDRSCH_CPU 0x00160002 +#define SRST_ARESETN_DDRSCH_VI 0x00160004 +#define SRST_ARESETN_DDRSCH_NPVD 0x00160005 +#define SRST_RESETN_CORE_DDRC 0x00160006 +#define SRST_RESETN_DDRMON 0x00160007 +#define SRST_RESETN_DFICTRL 0x00160008 +#define SRST_RESETN_DFI_SCRAMBLE 0x00160009 + +// ======================= TOPCRU module definition bank=7 ======================== +// TOPCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_CRU 0x00180000 +#define SRST_PRESETN_CRU_BIU 0x00180001 +#define SRST_RESETN_DDRPHY 0x0018000C + +//======================= PMUCRU module definition bank=8 ======================== +// PMUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_PMU_GPIO0 0x001c0004 +#define SRST_DBRESETN_PMU_GPIO0 0x001c0005 +#define SRST_RESETN_DDR_FAIL_SAFE 0x001c0008 +#define SRST_PRESETN_PMU_HP_TIMER 0x001c0009 +#define SRST_RESETN_PMU_HP_TIMER 0x001c000A +#define SRST_RESETN_PMU_32K_HP_TIMER 0x001c000B +#define SRST_PRESETN_I2C0 0x001c000C +#define SRST_RESETN_I2C0 0x001c000D +#define SRST_PRESETN_UART0 0x001c000E +#define SRST_SRESETN_UART0 0x001c000F + +// PMUCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_IOC_PMUIO0 0x001c0010 +#define SRST_PRESETN_CRU_PMU 0x001c0011 +#define SRST_PRESETN_PMU_GRF 0x001c0012 +#define SRST_PRESETN_PMU_SGRF 0x001c0013 +#define SRST_PRESETN_PMU_SGRF_REMAP 0x001c0014 +#define SRST_RESETN_PREROLL 0x001c0016 +#define SRST_RESETN_PREROLL_32K 0x001c0017 +#define SRST_HRESETN_PMU_SRAM 0x001c0018 +#define SRST_PRESETN_PWM0 0x001c0019 +#define SRST_RESETN_PWM0 0x001c001A + +// PMUCRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_RESETN_LPMCU 0x001c0020 +#define SRST_RESETN_LPMCU_PWRUP 0x001c0021 +#define SRST_RESETN_LPMCU_CPU 0x001c0022 +#define SRST_TRESETN_LPMCU_CPU 0x001c0023 + +// ======================= PMU1CRU module definition bank=9 ======================= +// PMU1CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_SPI2AHB 0x00200000 +#define SRST_HRESETN_SPI2AHB 0x00200001 +#define SRST_SRESETN_SPI2AHB 0x00200002 +#define SRST_LSRESETN_PMU_BIU 0x00200003 +#define SRST_PRESETN_WDT_LPMCU 0x00200009 +#define SRST_TRESETN_WDT_LPMCU 0x0020000A +#define SRST_HRESETN_SFC_PMU1 0x0020000C +#define SRST_HRESETN_SFC_XIP_PMU1 0x0020000D +#define SRST_SRESETN_SFC_2X_PMU1 0x0020000E + +// PMU1CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_LPMCU_MAILBOX 0x00200018 +#define SRST_PRESETN_IOC_PMUIO1 0x00200019 +#define SRST_PRESETN_CRU_PMU1 0x0020001A + +#define CLK_NR_SRST (SRST_PRESETN_CRU_PMU1 + 1) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rv1103b.h b/include/dt-bindings/suspend/rockchip-rv1103b.h new file mode 100644 index 0000000000000..b8f7f74467a32 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rv1103b.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RV1103B_PM_H__ +#define __DT_BINDINGS_RV1103B_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_ARMPD BIT(0) +#define RKPM_SLP_ARMOFF BIT(1) +#define RKPM_SLP_ARMOFF_DDRPD BIT(2) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(3) +#define RKPM_SLP_ARMOFF_PMUOFF BIT(4) + +#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +#define RKPM_SLP_CLK_GT BIT(16) +#define RKPM_SLP_PMIC_LP BIT(17) + +#define RKPM_SLP_32K_EXT BIT(24) +#define RKPM_SLP_TIME_OUT_WKUP BIT(25) +#define RKPM_SLP_PMU_DBG BIT(26) +#define RKPM_SLP_LP_PR BIT(27) + +/* the wake up source */ +#define RKPM_GPIO0_WKUP_EN BIT(0) +#define RKPM_SDMMC0_WKUP_EN BIT(1) +#define RKPM_SDIO_WKUP_EN BIT(2) +#define RKPM_USBDEV_WKUP_EN BIT(3) +#define RKPM_UART0_WKUP_EN BIT(4) +#define RKPM_PWM0_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_HPTIMER_WKUP_EN BIT(7) +#define RKPM_SYS_INT_WKUP_EN BIT(8) +#define RKPM_AOV_WKUP_EN BIT(9) +#define RKPM_TIMEOUT_WKUP_EN BIT(10) + +/* io config */ +#define RKPM_IO_CFG_IOMUX_SFT 0 +#define RKPM_IO_CFG_GPIO_DIR_SFT 8 +#define RKPM_IO_CFG_GPIO_LVL_SFT 9 +#define RKPM_IO_CFG_PULL_SFT 10 +#define RKPM_IO_CFG_ID_SFT 16 + +#define RKPM_IO_CFG_IOMUX_MSK 0x3f +#define RKPM_IO_CFG_GPIO_DIR_MSK 0x1 +#define RKPM_IO_CFG_GPIO_LVL_MSK 0x1 +#define RKPM_IO_CFG_PULL_MSK 0x3 +#define RKPM_IO_CFG_ID_MSK 0xffff + +#define RKPM_IO_CFG_IOMUX_GPIO_VAL 0 +#define RKPM_IO_CFG_GPIO_DIR_INPUT_VAL 0 +#define RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL 1 +#define RKPM_IO_CFG_GPIO_LVL_LOW_VAL 0 +#define RKPM_IO_CFG_GPIO_LVL_HIGH_VAL 1 +#define RKPM_IO_CFG_PULL_NONE_VAL 0 +#define RKPM_IO_CFG_PULL_UP_VAL 1 +#define RKPM_IO_CFG_PULL_DOWN_VAL 2 + +#define RKPM_IO_CFG_IOMUX(func) ((func) << RKPM_IO_CFG_IOMUX_SFT) +#define RKPM_IO_CFG_GPIO_DIR_INPUT \ + (RKPM_IO_CFG_GPIO_DIR_INPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT) +#define RKPM_IO_CFG_GPIO_DIR_OUTPUT \ + (RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT) +#define RKPM_IO_CFG_GPIO_LVL_LOW \ + (RKPM_IO_CFG_GPIO_LVL_LOW_VAL << RKPM_IO_CFG_GPIO_LVL_SFT) +#define RKPM_IO_CFG_GPIO_LVL_HIGH \ + (RKPM_IO_CFG_GPIO_LVL_HIGH_VAL << RKPM_IO_CFG_GPIO_LVL_SFT) +#define RKPM_IO_CFG_PULL_NONE \ + (RKPM_IO_CFG_PULL_NONE_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_PULL_UP \ + (RKPM_IO_CFG_PULL_UP_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_PULL_DOWN \ + (RKPM_IO_CFG_PULL_DOWN_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_ID(id) ((id) << RKPM_IO_CFG_ID_SFT) +#define RKPM_IO_CFG_IOMUX_GPIO \ + RKPM_IO_CFG_IOMUX(RKPM_IO_CFG_IOMUX_GPIO_VAL) + +#define RKPM_IO_CFG_GET_IOMUX(cfg) \ + (((cfg) >> RKPM_IO_CFG_IOMUX_SFT) & RKPM_IO_CFG_IOMUX_MSK) +#define RKPM_IO_CFG_GET_GPIO_DIR(cfg) \ + (((cfg) >> RKPM_IO_CFG_GPIO_DIR_SFT) & RKPM_IO_CFG_GPIO_DIR_MSK) +#define RKPM_IO_CFG_GET_GPIO_LVL(cfg) \ + (((cfg) >> RKPM_IO_CFG_GPIO_LVL_SFT) & RKPM_IO_CFG_GPIO_LVL_MSK) +#define RKPM_IO_CFG_GET_PULL(cfg) \ + (((cfg) >> RKPM_IO_CFG_PULL_SFT) & RKPM_IO_CFG_PULL_MSK) +#define RKPM_IO_CFG_GET_ID(cfg) \ + (((cfg) >> RKPM_IO_CFG_ID_SFT) & RKPM_IO_CFG_ID_MSK) + +#endif diff --git a/include/linux/extcon.h b/include/linux/extcon.h index e596a0abcb274..2a62f6fd23eb2 100644 --- a/include/linux/extcon.h +++ b/include/linux/extcon.h @@ -37,6 +37,7 @@ /* USB external connector */ #define EXTCON_USB 1 #define EXTCON_USB_HOST 2 +#define EXTCON_USB_VBUS_EN 3 /* * Charging external connector diff --git a/scripts/Makefile b/scripts/Makefile index 497537bd46bd1..52ce55ab3f61a 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -9,6 +9,7 @@ hostprogs-always-$(CONFIG_BUILDTIME_TABLE_SORT) += sorttable hostprogs-always-$(CONFIG_ASN1) += asn1_compiler hostprogs-always-$(CONFIG_MODULE_SIG_FORMAT) += sign-file hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert +hostprogs-always-$(CONFIG_ARCH_ROCKCHIP) += resource_tool hostprogs-always-$(CONFIG_ARCH_ROCKCHIP) += resource_tool hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_builder hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_gen diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.c b/sound/soc/rockchip/rockchip_i2s_tdm.c index 7ae93cbaea9a7..88fe5fcdf4558 100644 --- a/sound/soc/rockchip/rockchip_i2s_tdm.c +++ b/sound/soc/rockchip/rockchip_i2s_tdm.c @@ -1058,6 +1058,7 @@ static const struct of_device_id rockchip_i2s_tdm_match[] = { { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, { .compatible = "rockchip,rk3588-i2s-tdm" }, { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, + { .compatible = "rockchip,rv1106-i2s-tdm" }, {}, };