arm64:dts:aspeed: Add DIMM devices for SP7#263
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Add DIMM SPD and PMIC devices to SP& platforms for i3c2 (P0) and i3c3 (P1). The i3c buses will run in i2c mode from BMC side. Tested: - verified in Congo and Morocco Signed-off-by: modolaty <mohsen.dolaty@amd.com>
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I noticed that most of this is duplicated between the platforms. Should we have a dtsi for the common changes and just include the dtsi when applicable for the specific platform dtses? (not really applicable for this review, but just a thought) |
mahkurap
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May 6, 2026
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mahkurap
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There is a typo in the commit message. instead of sp8, it is spelled as sp&.
| #define JESD300_PMIC_I2C_MODE(bus, index, addr) \ | ||
| pmic_ ## bus ## _ ## index: pmic@addr{ \ | ||
| reg = <0x ## addr 0x0 0x40>; \ | ||
| compatible = "eeprom"; \ |
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Add DIMM SPD and PMIC devices to SP& platforms for i3c2 (P0) and i3c3 (P1).
The i3c buses will run in i2c mode from BMC side.
Tested: