This repository contains Verilog codes, including both RTL designs and related modules. If anyone has any doubts about the code, finds any errors, or needs any specific Verilog code, feel free to email me at "arjunpshetty.0@gmail.com".
note : This folder contains project from AMD Vivado & iverilog gtkwave. Folders include files written in languages other than Verilog, as they are part of the project structure.