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1. AXI4-RISCV-UVM AXI4-RISCV-UVM Public

   RISC-V SoC verification project using SystemVerilog, AXI4-style DMA, SVA, UVM monitors, scoreboards, and functional coverage.

   SystemVerilog 1

2. Esp32-IOT-Vehicular-system Esp32-IOT-Vehicular-system Public

   A scalable ESP32-based Vehicular IoT system for real-time monitoring using sensors like accelerometer, flame, shock, PIR, and DHT11. Features RF communication via nRF24L01+, secure data upload to A…

   C++

3. Neurosense Neurosense Public

   Wearable health monitor and sleep stage detector

   Jupyter Notebook

4. p3dx-top p3dx-top Public

   Forked from datakaveri/p3dx-top

   TOP - TEE Orchestrator Protocol

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5. memory-subsystem-rtl-verification memory-subsystem-rtl-verification Public

   Designed a high-performance cache memory subsystem with ECC (SEC-DED) and built-in self-test (BIST) for reliability and fault coverage. Developed a SystemVerilog verification environment with error…

   SystemVerilog

6. uart-fpga-subsystem uart-fpga-subsystem Public

   FPGA-targeted UART communication subsystem in SystemVerilog with 16x RX oversampling, TX/RX FIFOs, register interface, loopback mode, self-checking verification, assertions, coverage, and Vivado Ar…

   SystemVerilog