RISCV 5 Stage Pipelined Processor

A 64-bit, 5-stage pipelined RISC-V processor implemented in Verilog. This project represents Phase II of the Introduction to Processor Architecture course, upgrading a baseline sequential datapath into a fully pipelined and optimized architecture.

Project Overview

This processor accurately implements a 5-stage instruction pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), and Write Back (WB). It features full hazard handling capabilities, including data forwarding, load-use stall insertion, and control hazard flushing.

Supported Instruction Subset

• Arithmetic/Logic (R-Type & I-Type): add, sub, and, or, addi
• Memory (I-Type & S-Type): ld (Load Doubleword), sd (Store Doubleword)
• Control Flow (B-Type): beq (Branch if Equal)

Architectural Features & Hazard Resolution

• Data Forwarding Unit: Resolves EX-to-EX and MEM-to-EX data hazards without stalling the pipeline.
• Hazard Detection Unit: Detects Load-Use hazards and seamlessly stalls the Program Counter and IF/ID register while inserting a bubble (NOP) into the control path.
• Control Hazard Handling: Statically predicts branches as "Not Taken". Upon a taken branch, the datapath dynamically flushes the IF/ID and ID/EX registers.

Optimizations

This processor goes beyond the baseline requirements by implementing several architectural enhancements:

1. Reduced Branch Misprediction Penalty: Branch target calculation and zero-flag evaluation are moved from the MEM stage to the EX stage. This early branch resolution reduces the flush penalty from 3 clock cycles down to 2 clock cycles.
2. Internal Register Bypassing: Solves Write-Back to Decode (WB-to-ID) hazards. If a register is read in the same clock cycle it is being written, internal forwarding multiplexers inside the Register File instantly bypass the memory array, preventing unnecessary stalls.
3. Extended Immediate Generation: The Immediate Generator is built to support extracting and sign-extending complex 20-bit immediates for U-type (lui, auipc) and J-type (jal) instructions, laying the groundwork for a larger ISA implementation.

Simulation and Testing

This project is simulated using Icarus Verilog (iverilog). Instructions are fed to the processor via an instructions.txt file containing machine code in Big-Endian byte format.

How to Run

Ensure all Verilog files are in the root directory (along with the alu/ subfolder and Testbenches/pipe_tb.v). Use the following command to compile and execute the testbench:

iverilog -I pipe_tb -o sim_pipe && ./sim_pipe

Output

• Terminal: Displays a dynamic cycle-by-cycle output of the pipeline terminating perfectly upon fetching an empty instruction memory block.
• register_file.txt: Generates a text file dumping the final hexadecimal state of all 32 registers, followed by the total clock cycle count.
• pipe_wave.vcd: Generates a VCD file for detailed waveform analysis using GTKWave.