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2 changes: 1 addition & 1 deletion compiler/src/main/scala/edg/compiler/Compiler.scala
Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,7 @@ class AssignNamer() {
}

object Compiler {
final val kExpectedProtoVersion = 12
final val kExpectedProtoVersion = 13
}

/** Compiler for a particular design, with an associated library to elaborate references from.
Expand Down
14 changes: 14 additions & 0 deletions compiler/src/main/scala/edg/compiler/ExprEvaluate.scala
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,23 @@ object ExprEvaluate {
case (FloatPromotable(lhs), FloatValue(rhs)) => FloatValue(lhs + rhs)
case (IntValue(lhs), IntValue(rhs)) => IntValue(lhs + rhs)
case (TextValue(lhs), TextValue(rhs)) => TextValue(lhs + rhs)
case (ArrayValue(lhss), ArrayValue(rhss)) =>
if ((lhss.map(_.getClass) ++ rhss.map(_.getClass)).distinct.size > 1) {
throw new ExprEvaluateException(s"Attempt to concat array of differing types $lhss, $rhss")
}
ArrayValue(lhss ++ rhss)
case _ =>
throw new ExprEvaluateException(s"Unknown binary operand types in $lhs ${binary.op} $rhs from $binary")
}
case Op.SHRINK_SUB => (lhs, rhs) match {
case (RangeValue(lhsMin, lhsMax), RangeValue(rhsMin, rhsMax)) => RangeValue(lhsMin - rhsMin, lhsMax - rhsMax)
case (RangeEmpty, RangeEmpty) => RangeEmpty
case (lhs: RangeValue, RangeEmpty) => RangeEmpty
case (RangeEmpty, rhs: RangeValue) => RangeEmpty
case _ =>
throw new ExprEvaluateException(s"Unknown binary operand types in $lhs ${binary.op} $rhs from $binary")
}

case Op.MULT => (lhs, rhs) match {
case (RangeValue(lhsMin, lhsMax), RangeValue(rhsMin, rhsMax)) =>
val all = Seq(lhsMin * rhsMin, lhsMin * rhsMax, lhsMax * rhsMin, lhsMax * rhsMax)
Expand Down
3 changes: 2 additions & 1 deletion compiler/src/main/scala/edg/compiler/ExprToString.scala
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ class ExprToString() extends ValueExprMap[String] {
object InfixOp {
def unapply(op: Op): Option[String] = op match {
case Op.ADD => Some("+")
case Op.SHRINK_SUB => Some("↓-")
case Op.MULT => Some("×")
case Op.SHRINK_MULT => Some("↓×")
case Op.AND => Some("&&")
Expand All @@ -61,7 +62,7 @@ class ExprToString() extends ValueExprMap[String] {
}
object PrefixOp {
def unapply(op: Op): Option[String] = op match {
case Op.ADD | Op.MULT | Op.SHRINK_MULT => None
case Op.ADD | Op.SHRINK_SUB | Op.MULT | Op.SHRINK_MULT => None
case Op.AND | Op.OR | Op.XOR | Op.IMPLIES | Op.EQ | Op.NEQ => None
case Op.GT | Op.GTE | Op.LT | Op.LTE => None
case Op.MAX => Some("max")
Expand Down
65 changes: 59 additions & 6 deletions compiler/src/test/scala/edg/compiler/ExprEvaluateTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,22 @@ class ExprEvaluateTest extends AnyFlatSpec {
) should equal(FloatValue(2.0))
}

it should "handle shrink multiply" in {
it should "handle shrink range ops" in {
import edgir.expr.expr.BinaryExpr.Op

evalTest.map( // test x - x = 0 property
ValueExpr.BinOp(
Op.SHRINK_SUB,
ValueExpr.Literal(10.0, 20.0),
ValueExpr.Literal(10.0, 20.0)
)) should equal(RangeValue(0.0, 0.0))
evalTest.map( // ... and with negative numbers
ValueExpr.BinOp(
Op.SHRINK_SUB,
ValueExpr.Literal(-20.0, -10.0),
ValueExpr.Literal(-20.0, -10.0)
)) should equal(RangeValue(0.0, 0.0))

evalTest.map( // test x * 1/x = 1 property
ValueExpr.BinOp(
Op.SHRINK_MULT,
Expand Down Expand Up @@ -297,17 +311,56 @@ class ExprEvaluateTest extends AnyFlatSpec {
) should equal(IntValue(3))
}

it should "handle array binary ops" in {
import edgir.expr.expr.BinaryExpr.Op
evalTest.map(
ValueExpr.BinOp(
Op.ADD,
ValueExpr.Literal(Seq()),
ValueExpr.Literal(Seq())
)
) should equal(ArrayValue(Seq()))

evalTest.map(
ValueExpr.BinOp(
Op.ADD,
ValueExpr.Literal(Seq(Literal.Integer(0), Literal.Integer(1))),
ValueExpr.Literal(Seq())
)
) should equal(ArrayValue(Seq(IntValue(0), IntValue(1))))

evalTest.map(
ValueExpr.BinOp(
Op.ADD,
ValueExpr.Literal(Seq(Literal.Integer(0), Literal.Integer(1))),
ValueExpr.Literal(Seq(Literal.Integer(3), Literal.Integer(4), Literal.Integer(5)))
)
) should equal(ArrayValue(Seq(IntValue(0), IntValue(1), IntValue(3), IntValue(4), IntValue(5))))

evalTest.map(
ValueExpr.BinOp(
Op.ADD,
ValueExpr.Literal(Seq(Literal.Text("A"), Literal.Text("B"))),
ValueExpr.Literal(Seq(Literal.Text("D"), Literal.Text("E"), Literal.Text("F")))
)
) should equal(ArrayValue(Seq(TextValue("A"), TextValue("B"), TextValue("D"), TextValue("E"), TextValue("F"))))

assertThrows[ExprEvaluateException] { // can't mix and match types
evalTest.map(ValueExpr.BinOp(
Op.ADD,
ValueExpr.Literal(Seq(Literal.Text("A"))),
ValueExpr.Literal(Seq(Literal.Integer(0)))
))
}
}

it should "handle array unary set ops" in {
import edg.ExprBuilder.Literal
import edgir.expr.expr.UnarySetExpr.Op
evalTest.map(
ValueExpr.UnarySetOp(
Op.NEGATE,
ValueExpr.Literal(Seq(
Literal.Boolean(false),
Literal.Boolean(true),
Literal.Boolean(false),
)),
ValueExpr.Literal(Seq(Literal.Boolean(false), Literal.Boolean(true), Literal.Boolean(false))),
ValueExpr.Array(Seq())
)
) should equal(ArrayValue(Seq(BooleanValue(true), BooleanValue(false), BooleanValue(true))))
Expand Down
2 changes: 1 addition & 1 deletion edg/circuits/I2cBitBang.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ class I2cControllerBitBang(BitBangAdapter, Block):

def __init__(self) -> None:
super().__init__()
self.i2c = self.Port(I2cController.empty(), [Output])
self.i2c = self.Port(I2cController(DigitalBidir.empty()), [Output])
self.scl = self.Port(DigitalBidir.empty())
self.sda = self.Port(DigitalBidir.empty())

Expand Down
6 changes: 3 additions & 3 deletions edg/circuits/I2cPullup.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@


class I2cPullup(Interface, Block):
def __init__(self) -> None:
def __init__(self, resistance: RangeLike = 4.7 * kOhm(tol=0.05)) -> None:
super().__init__()

self.resistance = self.ArgParameter(resistance)
# TODO restrictions on I2C voltage, current draw modeling
self.pwr = self.Port(VoltageSink.empty(), [Power])
self.i2c = self.Port(I2cPullupPort.empty(), [InOut])
Expand All @@ -15,6 +15,6 @@ def __init__(self) -> None:
def contents(self) -> None:
super().contents()

res_model = PullupResistor(4.7 * kOhm(tol=0.05))
res_model = PullupResistor(self.resistance)
self.scl_res = self.Block(res_model).connected(self.pwr, self.i2c.scl)
self.sda_res = self.Block(res_model).connected(self.pwr, self.i2c.sda)
5 changes: 4 additions & 1 deletion edg/core/ArrayExpr.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

from typing_extensions import TypeVar, override

from .Binding import EqOp, ArrayBinding, UnarySetOpBinding, BinarySetOpBinding
from .Binding import EqOp, ArrayBinding, UnarySetOpBinding, BinarySetOpBinding, BinaryOpBinding
from .ConstraintExpr import (
ConstraintExpr,
IntLike,
Expand Down Expand Up @@ -110,6 +110,9 @@ def all_unique(self) -> BoolExpr:
def all_equal(self) -> BoolExpr:
return BoolExpr()._new_bind(UnarySetOpBinding(self, EqOp.all_equal, BoolExpr._to_expr_type(True)))

def concat(self: SelfType, other: ArrayCastableType) -> SelfType:
return self._new_bind(BinaryOpBinding(self, self._to_expr_type(other), NumericOp.add))


ArrayBoolLike = Union["ArrayBoolExpr", Sequence[BoolLike]]

Expand Down
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