A high school research project comparing the Von Neumann bottleneck against a 2×2 systolic array architecture, implemented on Arduino Nano boards.
SAVANT is a hands-on experiment that physically builds and measures two computing paradigms side by side:
- Control group — a single Arduino Nano sequentially accessing a shared array, modeling Von Neumann-style memory bottleneck behavior
- Experimental group — four Arduino Nanos wired in a 2×2 grid, each acting as a Processing Element (PE) in a miniature systolic array
Two data flow modes are tested on the systolic array: Output Stationary (OS) and Weight Stationary (WS), following the classification from Raja (2024).
| Component | Qty |
|---|---|
| Arduino Nano (CH340, SZH-EK025) | 5 |
| Mini breadboard | 1–2 |
| Jumper wires (F-F) | 1–2 sets |
Total cost: ~₩66,300
SAVANT/
├── single_board.ino # Control group (sequential)
├── OS_PE00.ino # Output Stationary — top-left
├── OS_PE01.ino # Output Stationary — top-right
├── OS_PE10.ino # Output Stationary — bottom-left
├── OS_PE11.ino # Output Stationary — bottom-right
├── WS_PE00.ino # Weight Stationary — top-left
├── WS_PE01.ino # Weight Stationary — top-right
├── WS_PE10.ino # Weight Stationary — bottom-left
├── WS_PE11.ino # Weight Stationary — bottom-right
└── README.md
- Upload PE(1,1) → PE(0,1) → PE(1,0) → PE(0,0) last
- Open Serial Monitor on PE(0,0) and PE(1,1) at 9600 baud
- Press reset on PE(0,0) to start
- Record processing time (µs) and communication count from Serial Monitor
- Repeat ≥5 times per condition
| Type | Variable |
|---|---|
| Independent | Processing structure, data flow (OS/WS), matrix size (M×N×P) |
| Dependent | Processing time (µs), memory/communication access count |
Theoretical cycle count is calculated using the formula from Raja (2024):
N_C = 2·S_R + S_C + T − 2
Tejas Raja, "Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks", arXiv:2410.22595, 2024.