Skip to content
View JoonatanAlanampa's full-sized avatar
  • Helsinki, Finland

Block or report JoonatanAlanampa

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
JoonatanAlanampa/README.md

Hi there 👋

MSc. All content in my GitHub repositories has been created in collaboration with AI.

Pinned Loading

  1. devphys devphys Public

    Open-source TCAD for SkyWater Sky130 calibrated against measured silicon from 300 K to 77 K - drift-diffusion, dopant freeze-out, cryogenic SS saturation quantified, OpenVAF/ngspice compact-model loop

    Python 3 2

  2. cartridge_pmod cartridge_pmod Public

    QSPI flash + PSRAM + audio cartridge Pmod for TinyTapeout — a drop-in remix of the stock QSPI Pmod with sigma-delta audio (RC filter + amp + jack) on the CS2 pin. KiCad, JLC-assemblable

    Python 1

  3. ulx3s-cover ulx3s-cover Public

    A laser-cut plexiglass cover for the ULX3S FPGA board — none is sold, so this generates one: two 3 mm clear acrylic plates on M3 nylon standoffs, J1/J2 left completely open, DXF and SVG cut files d…

    Python

  4. koti koti Public

    A home computer built from the CPU up: an RV32IMA core with an sv32 MMU running mainline Linux 6.12 on a ULX3S 85F FPGA — 32 MB SDRAM, microSD, HDMI console, USB keyboard, networking, and it boots …

    SystemVerilog 1

  5. stdcells stdcells Public

    A standard-cell library I designed from scratch for sky130: transistor sizing from device physics, my own gdstk layouts signed off with the official KLayout DRC/LVS decks, and my own ngspice-to-Lib…

    Python

  6. vertical-slice vertical-slice Public

    The fabricated CORDIC-1, rebuilt on a standard-cell library I designed myself: device physics, transistor sizing, cell layouts and ngspice-to-Liberty characterization all mine. Same RTL bit for bit…

    Verilog