EE grad student at the University of Ottawa (MEng '28) — Digital VLSI, RTL Design, and AI hardware.
My work spans the full RTL-to-GDS stack: writing synthesizable SystemVerilog, running physical design flows through OpenLane2 and Cadence, and targeting open silicon shuttles. I'm particularly interested in AI accelerator architecture and the tooling that makes open-source silicon practical.
Currently targeting roles in digital design, DV, and physical design at AI chip companies.
HDLs: 
EDA: 
Languages: 
Hierarchical 32-bit ALU supporting 14 operations, taken through a complete professional VLSI flow: RTL → synthesis (Cadence Genus) → place & route (Cadence Innovus) → DRC signoff → GDS tape-out. Two implementations benchmarked: structural (1,412 μm², 70.76 ns) vs. behavioral (1,524 μm², 60.96 ns). Clean DRC, zero connectivity errors.
SystemVerilog Cadence Genus Cadence Innovus 45nm CMOS VLSI
3-stage pipelined RV32IM_Zicsr core in SystemVerilog — full M-extension (MUL/DIV/REM), CSR file, WB→DE forwarding, custom assembler and reference ISS. Verified end-to-end with four self-checking programs; Yosys netlist generated.
SystemVerilog Yosys RISC-V Icarus Verilog
Capstone project: custom CNN (98% accuracy, 97% fire recall) on NASA MODIS satellite imagery, deployed on Google Cloud with a Flask backend and real-time alert system. 7,336-image test set processed in 20 seconds (0.003 s/image).
Python TensorFlow Keras Flask CNN Google Cloud
Two-player Pong in pure RTL — no CPU. VGA rendering at 640×480@60Hz, ADXL345 accelerometer paddle control via SPI, 7-segment scoreboard. 1,789 LEs (4% of MAX10), Fmax 80.73 MHz.
SystemVerilog FPGA Quartus VGA SPI DE10-Lite
| Domain | Tools & Technologies |
|---|---|
| RTL Design | SystemVerilog, Verilog (IEEE 1800-2012) |
| Synthesis | Cadence Genus, Yosys, OpenLane2 |
| Physical Design | Cadence Innovus, OpenROAD |
| Simulation | ModelSim, Icarus Verilog, GTKWave |
| FPGA | Intel Quartus Prime, DE10-Lite (MAX10) |
| Open Silicon | OpenLane2, SKY130 PDK |
| Timing Analysis | OpenSTA, Cadence Tempus |
| ML / Python | TensorFlow, Keras, NumPy, Flask |
| Processes | 45nm GPDK CMOS (Cadence) · SKY130 (open PDK) |
- OpenLane2 setup for RTL-to-GDS flows on SKY130 (RISC-V core hardening)
- RV32IM_Zicsr pipeline — extending toward a MAC instruction for neural network workloads and OpenLane2 GDS hardening
- Open-source contribution — scoping a good-first-issue in OpenLane2 or Yosys
University of Ottawa — MEng Electrical Engineering, expected 2028
York University (Lassonde) — BEng Electrical Engineering