[Chore] Fallback unsupported PTX TIR tests to upstream state

[toudefu]

Motivation

This PR reverts several PTX-specific TensorIR (TIR) test cases back to their upstream main state.

Currently, these tests heavily rely on NVIDIA-specific hardware behaviors, particularly the 32-thread warp size and specific register layouts (e.g., software fallbacks for ldmatrix with hardcoded 32-thread indexing). When running on architectures with a 64-thread warp/wavefront (such as Moore Threads MACA), these hardcoded memory mapping formulas cause severe data layout misalignment and precision issues.

Instead of adding complex, architecture-specific if/else fallbacks that pollute the PTX test suite, we are rolling these files back to cleanly align with upstream.

Modifications

Reverted the following files to the latest upstream/main state via git checkout:

• tests/python/tirx-base/test_tir_ptx_cp_async.py
• tests/python/tirx-base/test_tir_ptx_griddepcontrol.py
• tests/python/tirx-base/test_tir_ptx_ldmatrix.py
• tests/python/tirx-base/test_tir_ptx_mma.py
• tests/python/tirx-base/test_tir_ptx_mma_sp.py
• tests/python/tirx-base/test_tir_ptx_scalar_f32_math.py

Target Branch

dev