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Add Ailunce HD2 (HR_C7000 / CK803S) board port (miosix v3.01 — proposal)#1

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Add Ailunce HD2 (HR_C7000 / CK803S) board port (miosix v3.01 — proposal)#1
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fenfir:hd2-miosix-port

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@fenfir fenfir commented Jul 23, 2026

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⚠️ Version-base note (please read first). This port targets miosix v3.01
(current fedetft/miosix-kernel master). OpenRTX/miosix-kernel is on v2.81,
so this PR's diff includes the large v2.81→v3.01 delta and the port cannot merge
as-is
— it depends on v3-era interfaces (interfaces_private/os_timer.h,
IRQsetDefaultConsole, the v3 FastGlobalIrqLock/tickless model) that don't exist
in v2.81. Opened as a proposal / discussion starter for adopting the HD2 v3
port; the actual HD2 work is the 8 commits at the tip (everything under
arch/*/cskyv2, arch/*/hr_c7000, arch/board/hrc7000_hd2, plus small
build/kernel hooks).

Summary

Adds a Miosix port for the Ailunce HD2 handheld digital radio, built on the
HR_C7000 SoC with a C-SKY V2 CK803S CPU — a new CPU architecture for
Miosix. Standard three-layer structure on top of miosix v3.01:

  • cpu arch/cpu/cskyv2 — CK803S context switch, IRQ/fault entry, atomics, endianness
  • chip arch/chip/hr_c7000 — os-timer, GPIO, delays, cache (no-op), reboot
  • board arch/board/hrc7000_hd2 — boot/clock init, BSP, console, linker, settings

Validated on real HD2 hardware: boots, schedules, Thread::sleep, idle CPU sleep,
and console output all confirmed.

What works

Tickless scheduler, threads/sync/timers/delays; a CPU fault handler that decodes
PSR.VEC and dumps EPC/EPSR + registers; stdout/printf/bootlog over UART0; idle
CPU sleep via the C-SKY wait instruction; shutdown()/reboot().

Deliberate, hardware-dictated limitations (see the board README)

  • Unikernel only — no processes/userspace/MPU (the HR_C7000 has no MMU).
  • No hardware PendSV / software-triggerable IRQ on this SoC: the CK803S core VIC
    is not wired (verified on silicon — a Tspend probe never fired); the external PIC
    delivers all interrupts. A context switch requested under the global lock is
    therefore drained in kernel/lock.h + kernel/thread.cppguarded, and a no-op
    on architectures that have PendSV
    . A generic weak IRQtakeDeferredSwitch() hook
    would be a cleaner upstream mechanism if the maintainers prefer.
  • No deep sleep (no deep-sleep-surviving wake source) and no filesystem
    (optional, not wired).
  • Hand-rolled os-timer (the DW_apb_timers lack a match register + software-pend IRQ).

Full rationale in miosix/arch/board/hrc7000_hd2/README.md.

🤖 Generated with Claude Code

fedetft and others added 30 commits March 11, 2026 15:24
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
…an old compiler around

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
… boards (with new clock config)

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
…, does/did not compile.

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
fedetft and others added 30 commits April 23, 2026 10:47
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>
Add the GCC C-SKY toolchain file and wire the cskyv2 CPU / hr_c7000 chip / hrc7000_hd2 board into the arch CMake. The C-SKY multilib emits legacy .ctors rather than .init_array, so kernel_global_objects.pl renames the collected global-constructor section accordingly, and e20/unmember.cpp gains the __csky__ case for the Itanium-ABI pointer-to-member layout.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Context switch (cskyv2_context.S: full-frame save/restore + rte; the core does no HW register auto-stacking), the interrupt layer (VBR table, PIC autovector dispatch, dynamic IRQ registry, and a CPU fault handler that decodes PSR.VEC and reports EPC/EPSR + GPRs over a weak early-console hook), plus the interfaces-impl set: atomic ops, endianness, thread-context seeding, fast IRQ enable/disable, and no-op MPU/userspace (unikernel, no MMU on this core).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The CK803S port has no PendSV-equivalent wired yet, so a scheduler invocation made under the global lock is drained at lock release (lock.h) and on the wait path (thread.cpp). Both are guarded to stay a no-op on architectures that have a real deferred-switch exception. To be removed once the core VIC Tspend (vector 22) deferred switch is wired.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Tickless os_timer over the DW_apb_timers (two channels: free-running timebase + one-shot wakeup, 64-bit via the pending-bit trick, ns<->tick through Miosix TimeConversion fixed-point), busy-wait delays, GPIO, a no-op cache layer (no data cache), and chip-level reboot.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Board bring-up: early PLL/clock init (boot.cpp), IRQbspInit (LEDs, power self-latch, a polled-TX debug UART and the early-console shim the CPU fault reporter calls), shutdown/reboot, the unikernel linker script, and board_settings.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The idle thread previously busy-spun at the full 42 MHz CPU clock. Implement sleepCpu() with the C-SKY `wait` instruction (the WFI equivalent): it stops the CPU clock until an interrupt arrives, leaving peripherals (including the os-timer) running, and exits on a pending interrupt regardless of PSR.IE — satisfying the sleepCpu() contract of being callable with interrupts enabled or disabled. Validated on HD2 silicon; same bare-instruction idiom as the Cortex-M __WFI() and Linux arch/csky arch_cpu_idle().

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add HD2Console, a minimal polled Device wrapping the UART0 debug port (hd2_dbg_putc), registered as the default console in IRQbspInit via IRQsetDefaultConsole. stdout/printf/iprintf and the kernel bootlog now reach UART0 @57600 (previously stdout went nowhere and the bootlog was a no-op). IRQwrite gives an IRQ-safe boot/error path; readBlock polls the RX FIFO (non-blocking); ioctl(IOCTL_SYNC) is a no-op (polled TX is already synchronous). Validated on HD2 silicon — the boot banner now prints. The prior note that routing stdio through a Device 'hangs early boot' was a misdiagnosis.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Document the HD2/HR_C7000/CK803S port for upstream readers: the three-layer structure, hardware summary, build/unikernel/toolchain model, what works, and the deliberate hardware-dictated limitations (no MMU/processes, no hardware PendSV so the deferred switch is drained in the guarded kernel hooks, no deep sleep, hand-rolled os-timer). Records the core-VIC-not-wired finding so it isn't re-investigated. Facts cross-referenced to the CK803S/HR_C7000 manuals, C-SKY ABI, Linux arch/csky, and RT-Thread.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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4 participants