Compiler engineer at AMD, working on GPU compiler infrastructure and the kernel stack underlying modern AI workloads.
tensor program
β lower
βΌ
MLIR dialects βββΊ LLVM IR βββΊ AMDGPU ISA βββΊ the machine
β² β
βββββββββββββ read the disassembly βββββββββββ
My work sits at the boundary where a high-level tensor program is lowered into machine code that fully utilizes the hardware: IR design, code generation quality, and the domain-specific languages that allow kernel authors to express layout and scheduling without resorting to raw intrinsics. When a kernel misses peak, the answer is in the generated assembly β so that is where I start.
- LLVM and MLIR compiler infrastructure
- Code generation and performance analysis for AMD CDNA GPUs
- Kernel DSLs and layout abstractions for AI workloads
- Large language model inference and serving performance on ROCm
- AMD LLVM β AMDGPU backend and the ROCm compiler toolchain
- FlyDSL β Flexible LaYout DSL, a Python front end for authoring high-performance GPU kernels
- aiter β AI Tensor Engine for ROCm
LLVM Β· MLIR Β· ROCm / HIP Β· C++ Β· Python Β· Triton
Every abstraction leaks. The interesting work is deciding where.
