Name		Name	Last commit message	Last commit date
Core		Core
TCL		TCL
XDC		XDC
images		images
ALU.vhdl		ALU.vhdl
ALU_TESTBENCH.vhdl		ALU_TESTBENCH.vhdl
README.md		README.md
Register-File.vhdl		Register-File.vhdl
alu.tcl		alu.tcl
alu.xdc.txt		alu.xdc.txt
control_unit.vhdl		control_unit.vhdl
cpu.vhdl		cpu.vhdl
data_cache.vhdl		data_cache.vhdl
instruction_cache.vhdl		instruction_cache.vhdl
mux.vhdl		mux.vhdl
next_address.tcl		next_address.tcl
next_address.vhdl		next_address.vhdl
next_address.xdc.txt		next_address.xdc.txt
pc.vhdl		pc.vhdl
register-file.tcl		register-file.tcl
register-file.xdc.txt		register-file.xdc.txt
sign_extention.vhdl		sign_extention.vhdl
two_mux.vhdl		two_mux.vhdl
work-obj93.cf		work-obj93.cf

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MIPS-CPU

32 bit MIPS CPU

Implementation of a 32 bit CPU for the MIPS ISA. Based on VHDL. Tools Used Xilinx, modelsim

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32 bit MIPS CPU

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