Proposal: FPGA-Based NFC Student Attendance System Using Microwatt CPU and OpenPOWER ISA

Accurate and efficient attendance tracking is essential in academic institutions. Manual roll-calls and paper registers are slow, error-prone, and difficult to manage. This project proposes the design of an NFC-based student attendance system, implemented on FPGA hardware using the Microwatt CPU core and the OpenPOWER ISA. The design leverages open-source toolchains and cryptographic accelerators to ensure reliability, scalability, and security in real-world deployment.

Objectives

The objective of this project is to build a secure and reliable attendance system that runs entirely on FPGA hardware. The system will use the Microwatt CPU core to execute software routines, while custom hardware modules will handle cryptographic operations and communication tasks. The design will emphasize reproducibility, openness, and adaptability for institutional use.

Methodology

System Overview

Fig. 1: Overview of the attendance system

The proposed attendance system, as seen in Fig. 1, integrates both hardware and software elements to ensure efficient, accurate, and secure operation. At its core, the Microwatt CPU running the OpenPOWER ISA executes application-level software responsible for managing attendance data. The CPU communicates with external modules through the FPGA’s interconnect, which includes an NFC reader, cryptographic accelerators, and a communication interface.

Students will be issued NFC-enabled ID cards. When presented to the reader, the FPGA system captures the identifier and processes it through the Microwatt CPU. To ensure security, cryptographic accelerators based on AES and RSA are integrated into the CPU core. These modules provide fast, hardware-level support for authentication and encryption. Processed data is then transmitted via a UART-based communication module to a host computer, where a centralized attendance database is updated.

The design follows a modular approach. The NFC reader handles student identification, the CPU with RSA verifies authenticity, AES encrypts the attendance record, and the UART multiplexes between the NFC and host communication channels depending on the system’s operating mode. This division of responsibilities ensures clarity, maintainability, and extensibility of the design.

System Operations

The complete sequence of operations is as follows:

1. Student Identification – The NFC reader connected to the FPGA captures the ID card data when tapped by a student.
2. Authentication – The identifier is verified using the integrated RSA accelerator, which checks the cryptographic signature on the card. This hardware-level authentication prevents the use of unauthorized or counterfeit cards.
3. Data Protection – After successful authentication, the attendance record is encrypted with the AES accelerator. Hardware-accelerated encryption ensures confidentiality and prevents interception or tampering of records during transmission.
4. Communication – The encrypted data is sent to a host computer via a UART-based communication module. The UART multiplexes between the NFC reader input and the host output, switching dynamically based on whether the system is capturing card data or transmitting secure records.
5. Database Update – The host computer receives the encrypted data, decrypts it, and updates a centralized attendance database. This database supports long-term storage, reporting, and integration with academic management systems.

Implementation Steps

• Hardware Integration: Extend the Microwatt CPU with RSA and AES modules to enable hardware-accelerated cryptographic functions.
• Communication Design: Configure the UART interface to multiplex between the NFC reader and the host communication channel.
• FPGA Synthesis: Implement and test the design using open-source tools such as Yosys, GHDL, NextPNR, and Verilator.
• Software Development: Use GCC for POWER to build application code for attendance logging, cryptographic routines, and host communication. Debugging will be supported with GDB.
• Testing and Prototyping: Deploy on the ChipFoundry OpenFrame SoC platform or equivalent FPGA hardware, validating the workflow with NFC cards and live host integration.
• Verification with Assertions and Testbenches: Use SystemVerilog assertions and directed/random testbenches to ensure functional correctness, constant-time execution of the cryptographic accelerators, and secure data flow. Post-place-and-route timing simulations will be run to validate reproducibility and robustness.

Expected Outcomes

The project will deliver a fully functional prototype of a secure FPGA-based attendance system. The system will:

• Demonstrate the Microwatt CPU core as a viable processor for embedded applications.
• Highlight the use of the OpenPOWER ISA with open-source toolchains in practical designs.
• Authenticate student ID cards using RSA-based verification.
• Protect attendance records with AES-based encryption.
• Transmit encrypted data securely to a host system via a multiplexed UART communication channel.
• Provide a modular, extensible framework that institutions can adapt and scale without reliance on proprietary systems.
• Deliver verification evidence in the form of simulation waveforms, assertion logs, and testbench results that demonstrate correctness, reproducibility, and security properties of the design.

Conclusion

This project illustrates the potential of open hardware and software to address real-world challenges in education. By combining the Microwatt CPU, the OpenPOWER ISA, FPGA-based cryptographic accelerators, and open-source design flows, the proposed system delivers not only a practical attendance solution but also a compelling demonstration of transparency, security, and community-driven innovation. Its modular architecture ensures adaptability, while the integration of AES and RSA guarantees that institutional data remains protected throughout the process.

Outcomes

The following enhancements have been implemented as part of this challenge:

• AES Encryption Instruction: Added support for the vcipher instruction (AES encryption) to the Microwatt CPU core, following the OpenPOWER ISA specification.

• Design Files: The complete implementation can be found under the vhdl/ directory.

• Documentation: Detailed information about the AES instruction and its integration is available in docs/Documentation_microwatt_aes.md.