Harden OpenPocket Rev-A preproduction design and release gates

[Twotoz]

Summary

• add the authoritative generated KiCad 9 project, schematic, and 90 × 60 mm four-layer Revision-A board
• keep manufacturer/MPN/LCSC/DNP properties, BOMs, and both CPL variants aligned
• harden footprints, sourcing, fiducials, exposed-pad thermal vias, release gates, and manufacturing generation
• move the two GPIO expanders beside the long controls connector and repack the power block, reducing placement connectivity length by about 19%
• add deterministic short GND fanout for every outer-layer SMD ground pad: 221 track segments and 116 tented through vias
• persist the uninterrupted L2 GND fill from an isolated KiCad process and prevent signal copper from using L2
• document the autorouting experiments and the evidence-backed production-readiness decision

Validation

• KiCad 9 ERC: 0 errors, 0 warnings
• KiCad 9 geometric DRC: 0 errors, 1 location-less F.Cu copper-sliver warning
• KiCad connectivity: report cap of 499 unconnected items; 233 signal nets remain unrouted; 0 open GND items
• generated PCB: byte-stable repeat hash; all 337 routed copper objects belong to GND (221 segments + 116 vias)
• full PCB analysis: 370 findings — 234 errors, 18 warnings, 118 information; 233 errors are unrouted-net findings
• EMC pre-compliance: 79.0/100, 0 errors, 19 warnings; low trust while signal routing and datasheet coverage are incomplete
• BOM/CPL: 229 populated designators, exact set match in generic and JLCPCB CPLs
• LCSC snapshot: 85 exact stocked matches; AMT630A and modified RX5808 remain custom/consigned
• AMT630A firmware: 5/5 tests pass, including deterministic rebuild
• manufacturing generator and JLCPCB/PCBWay ZIP integrity: pass locally
• release gate: correctly remains blocked

Routing evidence

The improved floorplan reduced Freerouting's initial connection estimate from
752 to 531 after GND fanout. A pre-ground trial reached 272 remaining
connections, but it put signal tracks on the reserved L2 plane and was
rejected. The constrained full attempt exceeded the review host's memory
before producing a session. No partial or non-compliant autoroute was imported
into the reviewed PCB.

Release decision

This PR remains a draft engineering prototype and is not an order approval.
The ground architecture is implemented, but only GND is routed. Generated
fabrication files remain local ignored verification artifacts. See
hardware/rev-a/production-readiness.md for the full evidence and dispositions.

Blocking work

• route all 233 signal nets and reach zero unconnected items
• hand-review USB, RF, analog-video, switching, high-current, clock/RGB, and return paths
• remove the remaining copper-sliver warning and rerun DRC/analyzers on the exact final route
• complete panel pin-1/enclosure-stack and edge-connector mechanical audit
• complete independent schematic, layout, impedance, and Gerber reviews
• obtain assembler acceptance and inspected samples for AMT630A/RX5808
• complete independent AMT630A clean-room/license review
• add datasheet-backed thermal/electrical evidence and rerun pre-compliance
• validate first articles before changing release-status.json

[Twotoz]

Engineering audit update (2026-07-31)

I completed the firmware-side Revision-A work first: RivetTX PR #65 is merged at 777df90d078787c58951c321119cb1755d8a63a4, and its post-merge CI run 30638303608 passed all six jobs.

I did not mark or merge this hardware PR. The current PR tip is still a planning/release-gate change, not an orderable board:

• it contains no .kicad_pro, .kicad_sch, or .kicad_pcb source;
• its BOM still contains TBD, blocked, and preliminary component rows;
• it retains the obsolete AMT630A/AT050TN33 architecture;
• it has no verified TW8836-LB2-CE LQFP-128 pin map, reference circuit, power/decoupling network, or controller register source;
• the Renesas full TW8836 datasheet FN8645 is access-controlled; the public short-form sheet does not contain the pinout or register map needed to safely create the schematic or clean-room firmware;
• therefore there is no evidence-backed TW8836 firmware image, complete schematic, fully routed PCB, ERC/DRC result, or PCBWay package to review.

I also built a local trial generator to test whether the proposed 65 x 52 mm placement/routing envelope was geometrically plausible. That trial reached a four-layer autoroute with zero copper-clearance violations, but it intentionally failed engineering review because it had only the major IC connectivity and relied on unverified TW8836 pins/registers; it omitted the required passive networks and user connector circuits. Those unsafe trial artifacts were deleted and were never committed or pushed.

Merging this PR or generating Gerbers from that trial would mislabel an unverified netlist as manufacturing-ready. PR #3 should remain draft until an actual reviewed schematic and board replace the planning files.

[Twotoz]

MicroSD engineering update (aa692b2): added the audited TF-001A-P3 footprint/source review, SDMMC GPIO/expander allocation, switched-rail and SI calculations, pin audit, factory procedure, and exact first-article card matrix. RivetTX support is merged separately in PR #67-equivalent firmware work at 9a6e2e19c4bb5e2e6f2111bad74dab5a0809d160.\n\nThis hardware PR remains draft and must not be merged or ordered: the local generated whole-board draft still reports 325 ERC violations, 253 DRC violations, and 465 unconnected items. Those failures are outside the isolated microSD footprint/docs commit and mean the requested complete routed Revision-A motherboard/manufacturing ZIP does not yet exist.