cache-simulator

A configurable two-level (L1/L2) cache simulator written in C++.

Models an inclusive write-back cache hierarchy with LRU replacement and configurable write-allocate policy. Takes a memory access trace and computes L1/L2 miss rates and average memory access time (AMAT).

Cache hierarchy

CPU
 │
 ▼
L1 cache  ──── hit: done
 │ miss
 ▼
L2 cache  ──── hit: fill L1, done
 │ miss
 ▼
Main memory ── fill L2, fill L1

Inclusive: every block in L1 is also present in L2. When L2 evicts a block, L1 is checked and that block is invalidated if present.

Write-back: dirty lines are written to the next level only on eviction.

Write-allocate (configurable): on a write miss, the block is fetched and allocated in cache. With no-write-allocate, write misses go directly to memory.

Replacement: LRU per set, tracked via a monotonic access counter.

Build

make

Usage

./cacheSim <trace_file> \
  --mem-cyc <N>    \    # main memory latency (cycles)
  --bsize   <B>    \    # log2(block size in bytes)
  --wr-alloc <0|1> \    # 0 = no-write-allocate, 1 = write-allocate
  --l1-size  <S>   \    # log2(L1 total size in bytes)
  --l1-assoc <E>   \    # log2(L1 ways per set)
  --l1-cyc   <N>   \    # L1 hit latency (cycles)
  --l2-size  <S>   \    # log2(L2 total size in bytes)
  --l2-assoc <E>   \    # log2(L2 ways per set)
  --l2-cyc   <N>        # L2 hit latency (cycles)

All size and associativity values are log₂ — e.g., --bsize 5 = 32-byte blocks, --l1-assoc 2 = 4-way.

Trace format

r 0x1ff91ca8
w 0x00400120

Example

./cacheSim trace.in \
  --mem-cyc 100 --bsize 5 --wr-alloc 1 \
  --l1-size 15 --l1-assoc 1 --l1-cyc 4 \
  --l2-size 20 --l2-assoc 4 --l2-cyc 10

L1miss=0.042 L2miss=0.178 AccTimeAvg=7.231

Output

Field	Description
L1miss	L1 miss rate = L1 misses / total accesses
L2miss	L2 miss rate = L2 misses / L1 misses (conditional on reaching L2)
AccTimeAvg	AMAT = total cycles / total accesses

L2miss is the miss rate given a request reached L2. Dirty writebacks from L1 to L2 are not counted as L2 accesses for this metric.

License

MIT