- Sr. Engineer at 10xEngineers, working on RISC-V software enablement
- Official Committer at the Eclipse Foundation, maintaining the RV64 & RV32 ports of Eclipse ThreadX
- Official Maintainer at the seL4 Foundation, maintaining Banana Pi BPI-F3 (SpacemiT K1) board support in the seL4 Microkernel
- Contributor to the Linux Kernel, with the
spi: cadence-quadspipatch merged in v6.20 - Developer Eclipse Foundation backedup project ATESOR, an agentic AI system for autonomous RISC-V software porting
- Developer & maintainer of Cloud-V, a RISC-V CI platform (get a free RISC-V machine here)
- Wrote firmware for RISC-V real hardware: Banana Pi BPI-F3, Milk-V Jupiter, StarFive VisionFive 2
- Built a RISC-V hardware benchmark platform (see here)
- Write to teach, technical articles on Linux, Systems & AI
🏠
Working from home
Highlights
Pinned Loading
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eclipse-atesor/atesor
eclipse-atesor/atesor PublicMulti-stage Agent for Autonomous RISC-V SW Porting. You can download packages here ↓
Python 2
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riscV-processor
riscV-processor PublicThis is simple processor design, based on the RISC instruction set architecture. Used Xilinx Vivado to implement it.
VHDL 1
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HwVerification
HwVerification PublicThis repo contains the python scripts for MatMul's all modules testing.
Python
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