• 🎓 B.Tech in Electronics & Communication Engineering
• 🏫 SRM Institute of Science and Technology, Tiruchirappalli
• ⭐ CGPA: 9.67/10.00
• 💻 Passionate about RTL Design, FPGA Design, Digital Design, Computer Architecture, and VLSI
• 🌱 Currently learning SystemVerilog, Linux, and UVM
• 🎯 Seeking RTL Design, FPGA Design, Digital Design, and ASIC Verification internship opportunities

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Bachelor of Technology (B.Tech.)

• Major: Electronics and Communication Engineering
• University: SRM Institute of Science and Technology, Tiruchirappalli
• CGPA: 9.67 / 10.00
• Expected Graduation: 2028

• 📘 Learning SystemVerilog and UVM for RTL verification.
• 🐧 Building proficiency in Linux for semiconductor development workflows.
• ⚡ Strengthening RTL Design and FPGA implementation skills.
• 🧠 Exploring Computer Architecture and RISC-V Processor Design.
• 🎯 Preparing for RTL Design / FPGA Design / ASIC Verification internships.

• 🥇 Top 3 Winner — Currents 2026 Hackathon (NIT Tiruchirappalli)
• 🎤 ETCC 2026 Presenter — Presented research at the IEEE-associated International Conference on Emerging Technologies in Computing and Communication.
• 🇮🇳 Published Indian Patent — Optimized Pipelined Carry-Save Adder (PCSA).

Paper Presented: Optimized Pipelined Carry-Save Adder (PCSA) for 16-Bit Cryptographic Arithmetic Units

• 📍 Conference: ETCC 2026
• 🏛️ Host: PES University EC Campus, Bengaluru
• 🤝 Technical Association: IEEE Bangalore Section, IEEE Computer Society Bangalore Chapter, and IEEE Communications Society Bangalore Chapter
• 🎯 Presented research on the design, simulation, synthesis, and FPGA implementation of a 16-bit Optimized Pipelined Carry-Save Adder for cryptographic arithmetic applications.

Awarded Top 3 at Currents 2026, the annual technical festival of National Institute of Technology (NIT) Tiruchirappalli, for developing an innovative engineering solution in a competitive hackathon environment.

• 🏆 Achievement: Top 3 Winner
• 🏫 Institution: National Institute of Technology Tiruchirappalli
• 🎯 Event: Currents 2026 Hackathon
• 💡 Recognized for technical problem-solving, hardware-oriented innovation, and collaborative project development.

Technologies: SystemVerilog • RTL Design • RISC-V • FPGA • Xilinx Vivado

Designed an RL-adaptive RV32I System-on-Chip integrating processor, controller, and AI accelerator RTL modules. Performed behavioral simulation, synthesis, and timing analysis, resulting in a verified SoC architecture ready for FPGA implementation.

Technologies: Verilog • RTL Design • RISC-V • Xilinx Vivado

Designed an RV32I processor with an RVV-inspired vector extension featuring a Vector ALU, Vector Register File, and Vector Control Unit. Successfully verified scalar and vector execution through simulation.

Technologies: Verilog • FPGA • Artix-7 • Xilinx Vivado

Designed and implemented a 16-bit pipelined Carry-Save Adder optimized for cryptographic arithmetic. Verified through simulation and synthesized on the Artix-7 FPGA platform.

Technologies: Verilog • Neuromorphic Computing • Digital Design

Designed and simulated a Leaky Integrate-and-Fire (LIF) neuron architecture for efficient digital implementation of spiking neural networks.

💡 Passionate about designing efficient digital hardware and continuously learning modern VLSI design methodologies.