FPGA-Based Systolic Array Accelerator for GEMM Operations
This was a class project for EECS 570 Parallel Computing Architecture at the University of Michigan. The paper associated with this work is available under paper/570_FPGA_GEMM_Accel_Report.pdf.
This project was built for Vivado 2025.1 and uses a build script to avoid storing project information on the repo.
It targets a Digilent Arty-A7 dev board. Board files for installation into Vivado can be found at https://github.com/Digilent/vivado-boards. Vivado must have Artix-7 FPGA devices installed as well.
To open the Vivado project:
- Move to ws_fpga/scripts
- Run
vivado -mode tcl -source build_project.tcl - Type
exitto exit Vivado tcl mode - Move to ../project
- Run
vivado ws_fpga.xpr &
A bitfile is available for the Arty-A7 under ws_fpga/bitfiles.
The host interface can be controlled via JTAG in Vivado Lab Manager or UART in Python.
Information for sending JTAG reads and writes can be found in https://docs.amd.com/v/u/en-US/pg174-jtag-axi.
There is a UART driver class with methods for performing 32 bit reads and writes, 64 bit reads, asserting go, checking done, loading weights, loading input activations, reading psums, and performing a 3x3 matrix multiply that utilize all listed methods. This file is ws_fpga/scripts/ws_fpga_funcs.py. This module requires the pyserial package.
An example of the class being used can be found in ws_fpga/scripts/ws_simple_matrix_multiply_test.py which performs matrix multiplies on the FPGA and compares the results to a numpy dot product.
We were able to run an mnist model on this FPGA. Please see mnist/README.MD for more information.
There is an additional Vivado project built for a larger FPGA in the upto_16x16_pe_array branch with a 16x16 PE array.
The address map is:
Because the host interface uses AXI infrastructure, a different interface such as PCIe, ethernet, etc. could easily be connected.
For questions, please reach out to: cbarbr@umich.edu, drewkeil@umich.edu, tongsing@umich.edu, guanghao@umich.edu, maatla@umich.edu