[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] cxl/core: Fix caching dport GPF DVSEC issue#1855
Conversation
mainline inclusion from mainline-v6.15-rc4 category: bugfix Per Table 8-2 in CXL r3.2 section 8.1.1 and CXL r3.2 section 8.1.6, only CXL Downstream switch ports and CXL root ports have GPF DVSEC for CXL Port(DVSEC ID 04h). CXL subsystem has a gpf_dvsec in struct cxl_port which is used to cache the offset of a GPF DVSEC in PCIe configuration space. It will be updated during the first EP attaching to the cxl_port, so the gpf_dvsec can only cache the GPF DVSEC offset of the dport which the first EP is under. Will not have chance to update it during other EPs attaching. That means CXL subsystem will use the same GPF DVSEC offset for all dports under the port, it will be a problem if the GPF DVSEC offset cached in cxl_port is not the right offset for a dport. Moving gpf_dvsec from struct cxl_port to struct cxl_dport, make every cxl dport has their own GPF DVSEC offset caching, and each cxl dport uses its own GPF DVSEC offset for GPF DVSEC accessing. Fixes: a52b6a2 ("cxl/pci: Support Global Persistent Flush (GPF)") Signed-off-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Tested-by: Davidlohr Bueso <dave@stgolabs.net> Link: https://patch.msgid.link/20250323093110.233040-2-ming.li@zohomail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> (cherry picked from commit 87d2de0) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
Reviewer's guide (collapsed on small PRs)Reviewer's GuideMoves cached GPF DVSEC tracking from the shared cxl_port to individual cxl_dport instances so each downstream port maintains its own DVSEC offset, updating the GPF setup helper API and its callers accordingly. File-Level Changes
Tips and commandsInteracting with Sourcery
Customizing Your ExperienceAccess your dashboard to:
Getting Help
|
|
/approve |
|
[APPROVALNOTIFIER] This PR is APPROVED This pull-request has been approved by: Avenger-285714 The full list of commands accepted by this bot can be found here. The pull request process is described here DetailsNeeds approval from an approver in each of these files:
Approvers can indicate their approval by writing |
There was a problem hiding this comment.
Pull request overview
Fixes incorrect Global Persistent Flush (GPF) DVSEC offset caching in the CXL core by moving the cache from the shared cxl_port object to per-downstream-port (cxl_dport) storage, ensuring DVSEC accesses use the correct offset for each dport.
Changes:
- Move
gpf_dvseccaching fromstruct cxl_porttostruct cxl_dport. - Update
cxl_gpf_port_setup()to operate on astruct cxl_dport *and adjust its caller accordingly.
Reviewed changes
Copilot reviewed 4 out of 4 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| drivers/cxl/cxl.h | Relocates the cached gpf_dvsec field from cxl_port to cxl_dport and updates kerneldoc accordingly. |
| drivers/cxl/core/port.c | Updates the enumeration path to call cxl_gpf_port_setup() with the relevant cxl_dport. |
| drivers/cxl/core/pci.c | Changes cxl_gpf_port_setup() to cache/read the DVSEC per-dport and use dport->dport_dev for config access. |
| drivers/cxl/core/core.h | Updates the cxl_gpf_port_setup() prototype to accept struct cxl_dport *. |
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
mainline inclusion
from mainline-v6.15-rc4
category: bugfix
Per Table 8-2 in CXL r3.2 section 8.1.1 and CXL r3.2 section 8.1.6, only CXL Downstream switch ports and CXL root ports have GPF DVSEC for CXL Port(DVSEC ID 04h).
CXL subsystem has a gpf_dvsec in struct cxl_port which is used to cache the offset of a GPF DVSEC in PCIe configuration space. It will be updated during the first EP attaching to the cxl_port, so the gpf_dvsec can only cache the GPF DVSEC offset of the dport which the first EP is under. Will not have chance to update it during other EPs attaching. That means CXL subsystem will use the same GPF DVSEC offset for all dports under the port, it will be a problem if the GPF DVSEC offset cached in cxl_port is not the right offset for a dport.
Moving gpf_dvsec from struct cxl_port to struct cxl_dport, make every cxl dport has their own GPF DVSEC offset caching, and each cxl dport uses its own GPF DVSEC offset for GPF DVSEC accessing.
Fixes: a52b6a2 ("cxl/pci: Support Global Persistent Flush (GPF)")
Reviewed-by: Davidlohr Bueso dave@stgolabs.net
Reviewed-by: Jonathan Cameron Jonathan.Cameron@huawei.com
Reviewed-by: Dan Williams dan.j.williams@intel.com
Tested-by: Davidlohr Bueso dave@stgolabs.net
Link: https://patch.msgid.link/20250323093110.233040-2-ming.li@zohomail.com
(cherry picked from commit 87d2de0)
Summary by Sourcery
Move CXL Global Persistent Flush (GPF) DVSEC caching from the shared port structure to individual downstream port structures so each dport maintains its own GPF DVSEC offset.
Bug Fixes:
Enhancements: