Match and link ftdynamics (more are WIP) - #3030
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Recover the cached dynamics gate as an unsigned block-local web and keep the post-query decision in a separate signed web. Embedding the cached-bit assignment in its first condition makes MWCC lower the load directly into that web; adjacent declaration ordering then reproduces retail r4 for the cached flag and r3 for the decision, while the unsigned carrier selects cmplwi. Express the dynamic-tree traversal with an explicit cursor and seed its index through the decision web. This restores the retail induction web and pointer-update order without introducing compiler-owned homes: the frame remains 0x20, the r29-r31 save layout is unchanged, and no spill or inline-owned stack slots are added.
Restore ftCo_8009DB50 ahead of ftCo_8009DC54 so MWCC emits both functions at their retail object offsets, then expose the nine Kirby hat setup entry points that ftkirby resolves across the TU boundary. The candidate .data and .sdata payloads end before the target's zero-filled alignment tails, but the linker supplies the same padding and the resulting DOL is exact. The final ftCo_8009E7B4 allocation keeps the cached unsigned gate and signed query decision as adjacent block-local webs: the embedded assignment colors the cache to r4, declaration/lifetime ordering colors the decision to r3, and the unsigned carrier selects cmplwi. The explicit tree cursor restores the retail pointer/induction web without compiler-owned stack homes; the 0x20 frame and r29-r31 save band remain unchanged. Verified all 30 text symbols and material sections at 100%, ftCo_8009E7B4 at 100%, formatting, and the full GALE01 DOL checksum.
Report for GALE01 (013091a - ed6498d)📈 Matched code: 85.37% (+0.05%, +1924 bytes) ✅ 3 new matches
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Recreate the three inlined sqrt expansions with caller-owned volatile scratch in descending stack-slot order. This restores the retail 0x98 frame and exact temporary slots while avoiding the extra homes produced by an inline scalar helper. Split the first x/y subtraction webs while retaining the in-place z web, then permute the later scalar carriers to reproduce the retail instruction schedule and reduce the residual to seven FPR operands. The first distance block and every non-FPR operand are exact; the remaining later block is one greedy-color cycle (candidate f3/f2/f5 versus retail f4/f3/f2). Verified Ground_801C4FAC at 99.7794% with no insertion/deletion differences.
Give the inlined sqrt expansion and shadow-vector constants their retail .sdata2 owners, while keeping the definitions after the function so MWCC cannot fold the forward extern references back into anonymous literals. Reuse dist for the ortho positive extent to preserve the retail FPR load order. This reduces lbShadow_8000F38C from 16 differences at 99.6715% to two at 99.8418%, with the retail 0x148 frame and no insertion/deletion differences. One residual is the fallback pointer initialization (candidate li versus retail addi copy); the other is the 1.0f relocation. Keeping that value literal preserves the exact f0/f1 web, while naming it swaps the zero/one colors. Inline accessors add an eight-byte stack home and are deliberately avoided.
The chained assignment lightPos.z = upVec.y = lbShadow_804D7B88 resolves the 1.0F literal-ownership residual: the opaque outer carrier gives the named .sdata2 constant the same FPR web rank the anonymous pooled literal had, keeping the retail f1/f0 zero/one colors and store schedule while fixing the relocation. 99.8418% -> 99.8540%; the only remaining row is the r24/r28 pointer-copy web. Frame stays 0x148.
The second fog-distance block's seven-operand FPR color cycle is resolved by expressing the y-component squared difference inline as (sp2C.y - sp20.y) * (sp2C.y - sp20.y) instead of routing it through the early-declared named local dz. Allocator-replay (K=29 simplify + volatile-FPR color) showed the reused sp2C.y/dz carrier needed to live in the volatile-temp web stratum (number ~159, above the sp20.x load), not the low locals stratum: a CSE'd subexpression puts it there, so it claims f2 early and pushes the x-chain up to the target f3/f4. The x difference stays a named full expression and the z difference stays load-then-subtract; both are required for the exact schedule. 99.7794% -> 100%, frame unchanged at 0x98, zero regressions elsewhere in the TU.
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Looking into more close matches from #2933.
This PR is a follow up on #3025