This repository documents my ongoing work on CMOS standard cell design using the SKY130 (130nm) PDK.
The objective of this project is to understand and implement the complete standard cell design flow from schematic to layout-level verification.
- Transistor-level design of:
- CMOS Inverter (INV)
- 2-Input NAND Gate
- 2-Input NOR Gate
- SPICE simulation using NGSPICE
- Physical layout design using Magic
- Design Rule Check (DRC) verification
- Parasitic extraction from layout
- Switch-level functional verification using IRSIM
This work demonstrates understanding of:
- Pull-up and Pull-down network design
- CMOS logic implementation
- Layout design rules (130nm)
- Basic ASIC standard cell development flow