gateware: Fixed-point arithmetic fixes and other improvements - #1804
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convergent_round returns a value that is one bit longer than the non-fractional part of the passed value. it makes sense to pass a value that is exactly `discarded_bits` long IF it is unsigned. make convergent_round tolerate this edge case rather than fail, but make sure it still fails if `value` has less than `discarded_bits` non-sign bits. more practically, this fixes an error when assigning a fixed.Value of i_width=0 and f_width > 0 to another with f_width=0
when convergent_round is passed a signed value, not only does it return an unsigned value, the *contents* are wrong since the addition is done with the wrong signedness (since slicing drops signedness)
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This PR is the result of updating the fixed-point library with the code referenced in #1796 (comment). Adapting the gateware to the new semantics exposed several bugs and required additional optimizations to fit the designs within FPGA fabric.
Changes:
lib.fixedamaranth-lang/amaranth#1578. Minor API differences were resolved. The only modification is the addition of a rounding method based on ourconvergent_roundimplementation.convergent_roundfixes from fpga: Fixes to fixed-point arithmetic #1796 (thanks to @mildsunrise)convergent_roundto avoid extending the bit width by default. An optionalclipparameter can be set toFalseto disable clipping.fir_mac16: Replaced the skid buffer in DSP blocks with a proper clock enable signal, improving behavior inext_precision_txgateware.