RISC-V Assembler and Simulator

• The project is a RISC-V assembler and simulator.
• The framework implemented is for Linux or Windows only.

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Project Structure

Assembler Tests

Location: tests/assembly/

• simpleBin/, hardBin/, errorGen/: Input assembly code files.
• bin_s/, bin_h/: Expected machine code files corresponding to simpleBin and hardBin.
• user_bin_s/, user_bin_h/: Machine code generated by the assembler for simpleBin and hardBin, respectively.

Simulator Tests

Location: tests/bin/ and tests/traces/

• tests/traces/: Expected correct simulator traces.
• tests/bin/: Simulator traces generated by the simulator.

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How to Run

Prerequisite: Python3 must be installed on your device

Running the Assembler

The assembler takes an assembly file as input and produces a machine code file.

Navigate to /automatedTesting on your Terminal and run the following command to run the Assembler:

Linux:

python3 src/main.py --no-sim --linux

Windows:

python3 src\main.py --no-sim --windows

Running the Simulator

Simulator takes a machine code file as input and produces a trace file as output.

Navigate to /automatedTesting on your Terminal and run the following command to run the Simulator:

Linux:

python3 src/main.py --no-asm --linux

Windows:

python3 src\main.py --no-asm --windows

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Contributors

• Aryan Khare
• Jazl Anwar
• Arul Thirulvasagam
• Soumil Jain

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Last Update

10th May, 2025