Cache based side-channel attack in RISC-V.
Graduation project. The repository was tested on a RISC-V processor SiFive m74.
If you want to run Flush-Reload, you need to modify openSBI to implement Flush using CFLUSH.D.L1 opcode
mkdir build
cd build
cmake --no-warn-unused-cli -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=TRUE -DCMAKE_BUILD_TYPE:STRING=Debug -DCMAKE_C_COMPILER:FILEPATH=/usr/bin/riscv64-unknown-linux-gnu-gcc -DCMAKE_CXX_COMPILER:FILEPATH=/usr/bin/riscv64-unknown-linux-gnu-g++ ../ -G "Unix Makefiles"
make