GitHub - pranav33317/RISC-V-Processor · GitHub

Name		Name	Last commit message	Last commit date
N_point_fft.v		N_point_fft.v
README.md		README.md
adder.v		adder.v
alu_decoder.v		alu_decoder.v
controller.v		controller.v
data_mem.v		data_mem.v
data_path.v		data_path.v
flip_flop.v		flip_flop.v
instr_decoder.v		instr_decoder.v
instr_mem.v		instr_mem.v
main_fsm.v		main_fsm.v
mux_21.v		mux_21.v
mux_31.v		mux_31.v
n_point_fft_2.v		n_point_fft_2.v
processor.v		processor.v
sign_extender.v		sign_extender.v

Repository files navigation

Implementing a RISC-V Single and 5-stage stage processor with a modified FFT instruction which calculates N-point FFT.

About

No description, website, or topics provided.

0 stars

1 watching

Report repository

Releases

Packages

Contributors

Languages