fix: register DPLL pins on both EEC and PPS devices - #6
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The GNSS pin (and ext/port pins) were only registered on the PPS DPLL, resulting in pin.ParentDevice having a single entry. linuxptp-daemon's PhaseOffsetPin() requires len(ParentDevice) > PPS_PIN_INDEX (1) to read the phase offset — with only one parent the check fails, phaseOffset stays at FaultyPhaseOffset (99999999999), isOffsetInRange() returns false, and ptp4l remains at clock class 248 even when DPLL reports LOCKED_HO_ACQ. Register all pins on both EEC (index 0) and PPS (index 1) DPLLs, matching real E810 driver behavior. This gives each pin two parent device entries so the phase offset is read correctly and ptp4l can transition to clock class 6.
Use bnshr/ptp-operator@integrate-add-gnss so CI exercises the GNSS simulation work that this DPLL pin fix targets.
linuxptp-daemon enables periodic NAV-STATUS/NAV-CLOCK via CFG-MSGOUT-UBX_NAV_* CFG-VALSET keys, not classic CFG-MSG. netdevsim only started the 1 Hz emitter on CFG-MSG, so ubxtool never saw NAV frames, GNSS stayed s0, and ptp4l remained at clock class 248 despite DPLL/ts2phc being locked. Recognize CFG-MSGOUT STATUS/CLOCK keys (group 0x91) with a non-zero rate and start the NAV timer, matching real receiver behavior used by the daemon.
When gnss-sim reports NMEA fix quality 0, update gpsFix and transition kernel DPLL from locked to holdover (with netlink notify), matching the UBX INFIL path. Do not clobber sysfs freerun while GGA stays invalid.
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Summary
Root Cause
linuxptp-daemon's
PhaseOffsetPin()checkslen(pin.ParentDevice) > PPS_PIN_INDEX(wherePPS_PIN_INDEX = 1). With pins only registered on PPS DPLL,ParentDevicehas 1 entry, the check fails, phase offset stays atFaultyPhaseOffset(99999999999),isOffsetInRange()returns false, and ptp4l stays at clock class 248 even when DPLL reports LOCKED_HO_ACQ.Fix
Register all pins on both EEC (index 0) and PPS (index 1) DPLLs so each pin gets two parent device entries and the phase offset is read from
ParentDevice[1].PhaseOffsetcorrectly.Test plan
ptp-test (tgm)job passes with clock class reaching 6ptp-test (tgmbc)job passesscripts/test-dpll.shpasses on VM