asm! support for the Xtensa architecture#147302
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bjorn3
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Amanieu
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☔ The latest upstream changes (presumably #147645) made this pull request unmergeable. Please resolve the merge conflicts. |
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I've made most of the updates here (sorry for the delay!). It turns out we'll need a patch that landed just after rust branched LLVM: https://github.com/rust-lang/llvm-project/tree/rustc/21.1-2025-08-01/llvm/lib/Target/Xtensa , otherwise the asm tests fail :(. The good news is that we've since landed FP support in LLVM upstream too, so maybe the next time rust branches LLVM 21 (I guess 21.2?) we can rerun CI on this PR and it will be green. |
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Amanieu
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Deep-research synthesis from 5 parallel agents on inline-asm clobber
semantics, Zig std.lang.assembly location, and upstream Espressif
issue/PR freshness.
## docs/16 — new section "Cross-frontend inline-asm clobber matrix"
Documents the sharp difference between the 4 LLVM frontends on PIE
q-register clobbers (xtensa s3 EE.*):
- C / esp-clang 21.1.3: NO q-reg support — `~{q0}` rejected at parse
("unknown register name 'q0'"). Only `"memory"` reaches LLVM.
- Zig 0.17: First-class via `.{ .memory = true, .q0 = true, ... }` —
lowers to `~{q0},~{q1},~{q2}` in IR. Definition lives in
$ZIG/lib/std/lang/assembly.zig:852-938 (Xtensa branch); q0..q7 at
lines 930-937. (std.builtin → std.lang rename in 0.17; one-release
deprecation alias.)
- LDC `__asm`: Raw LLVM constraint string passes through verbatim;
no validation but full LLVM signal.
- rustc 1.95-nightly: `out("q0")` rejected — esp-rs/rust#265 OPEN, PR
#272 in draft (2026-06-05).
Plus the Zig RISC-V gap: Clobbers struct has v0..v31 (RVV) but NO q-regs
for Espressif ESPV vendor — only `.memory = true` is available for
esp32p4/s31 SIMD. Matches what experiments/simd/esp.zig already does.
Plus the new upstream milestone: rust-lang/rust#147302 ("asm! support
for Xtensa", MabezDev) MERGED 2026-06-05 — Xtensa asm! is no longer
fork-only.
## experiments/simd/ee.d — fix clobber list
The D source used `"r,r,r,~{memory}"` (matching the C version's ceiling)
but LDC can pass through `~{q0},~{q1},~{q2}`. Updated to
`"r,r,r,~{memory},~{q0},~{q1},~{q2}"` — codegen-affecting parity with
Zig. The 4 EE.* instructions still assemble identically; the register
allocator now knows to avoid reusing q0/q1/q2 across the block.
## docs/07 — outage notes + reframed #18916
- kassane/esp-idf-dlang now returns 404 (deleted entirely — confirmed
by 2 independent agents). No replacement mirror published. Existing
installs work from cached /home/user/dl/ldc-esp.tar.xz (sha256
c2cd9f5b...). scripts/setup.sh already handles the outage with a
$LDC2_UPSTREAM fallback.
- ziglang/zig#18916 reframed as resolved prior art (closed via
PR #19018), not "another open ABI bug".
https://claude.ai/code/session_01DuR5N3YJNe42ry8vcxVxBk
kassane
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Jun 6, 2026
Deep-research synthesis from 5 parallel agents on inline-asm clobber
semantics, Zig std.lang.assembly location, and upstream Espressif
issue/PR freshness.
## docs/16 — new section "Cross-frontend inline-asm clobber matrix"
Documents the sharp difference between the 4 LLVM frontends on PIE
q-register clobbers (xtensa s3 EE.*):
- C / esp-clang 21.1.3: NO q-reg support — `~{q0}` rejected at parse
("unknown register name 'q0'"). Only `"memory"` reaches LLVM.
- Zig 0.17: First-class via `.{ .memory = true, .q0 = true, ... }` —
lowers to `~{q0},~{q1},~{q2}` in IR. Definition lives in
$ZIG/lib/std/lang/assembly.zig:852-938 (Xtensa branch); q0..q7 at
lines 930-937. (std.builtin → std.lang rename in 0.17; one-release
deprecation alias.)
- LDC `__asm`: Raw LLVM constraint string passes through verbatim;
no validation but full LLVM signal.
- rustc 1.95-nightly: `out("q0")` rejected — esp-rs/rust#265 OPEN, PR
#272 in draft (2026-06-05).
Plus the Zig RISC-V gap: Clobbers struct has v0..v31 (RVV) but NO q-regs
for Espressif ESPV vendor — only `.memory = true` is available for
esp32p4/s31 SIMD. Matches what experiments/simd/esp.zig already does.
Plus the new upstream milestone: rust-lang/rust#147302 ("asm! support
for Xtensa", MabezDev) MERGED 2026-06-05 — Xtensa asm! is no longer
fork-only.
## experiments/simd/ee.d — fix clobber list
The D source used `"r,r,r,~{memory}"` (matching the C version's ceiling)
but LDC can pass through `~{q0},~{q1},~{q2}`. Updated to
`"r,r,r,~{memory},~{q0},~{q1},~{q2}"` — codegen-affecting parity with
Zig. The 4 EE.* instructions still assemble identically; the register
allocator now knows to avoid reusing q0/q1/q2 across the block.
## docs/07 — outage notes + reframed #18916
- kassane/esp-idf-dlang now returns 404 (deleted entirely — confirmed
by 2 independent agents). No replacement mirror published. Existing
installs work from cached /home/user/dl/ldc-esp.tar.xz (sha256
c2cd9f5b...). scripts/setup.sh already handles the outage with a
$LDC2_UPSTREAM fallback.
- ziglang/zig#18916 reframed as resolved prior art (closed via
PR #19018), not "another open ABI bug".
https://claude.ai/code/session_01DuR5N3YJNe42ry8vcxVxBk
kassane
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Jun 6, 2026
Ran /code-review across all 31 *.md files with 4 parallel finder angles (outdated bug-close framing / content redundancy / cross-ref + link rot / sweep). Applied 6 actionable findings: 1. docs/16:293 — "ESPV 2.2 spellings are not yet publicly documented" was stale. ESPV 2.2 .td files landed upstream in espressif/llvm-project commit 8108e99 (2026-04-23 on release/esp_22.x). Reframed: they ARE public upstream but not in bundled LLVM 22.1.4 — empirically the $ZIG/$LDC2 bundles still reject esp.vadd.s8 on -mcpu=esp32p4. 2. docs/16:95 — `#![feature(asm_experimental_arch)]` comment now notes rust-lang/rust#147302 ("asm! support for Xtensa", MabezDev) MERGED 2026-06-05. Xtensa asm! is no longer fork-only; the feature flag stays per Rust's stability policy. 3. docs/07:175 — "kassane/esp-idf-dlang — was at" tagged with "(repo deleted 2026-06)" for immediate clarity. 4. docs/05:232 — clang code-size claim was "223 B" — typo, should be "219 B" (matches docs/06 table, docs/00, HANDOFF). The number appeared in the Zig 0.16 legacy-lane comparison. 5. docs/16:128 — Xtensa branch line numbers stale post-patch. The scripts/setup.sh auto-patch shifts the file from 3199 → 3230 lines, moving .xtensa branch from line 852 → 883 and q0..q7 from 930-937 → 961-968. 6. docs/16:157 — "Will reach end-users once a fresh $ZIG tarball ships" was stale: scripts/setup.sh ALREADY auto-patches the bundled assembly.zig on every setup run (PR #42 + PR #43). Reframed: "the auto-patch will become a no-op once a fresh $ZIG tarball ships with the kassane HEAD assembly.zig". Plus a structural gap: CLAUDE.md repo map was missing 7 experiments subdirs (addrspace, baremetal-mixin, compiler-parity, esp-rs-issues, mangled-ffi, qemu-run, rust-zig) — all real experiments with their own docs (docs/08, /11, /12, /13, /14, /15, /17, /18). Added. Verified clean (no action needed per audit): - No present-tense Zig stack-spill slips post-PR #40 - All cross-arch numerical claims (171/201/204/219/375/516 + legacy 489/715) consistent across CLAUDE/HANDOFF/Research/docs/00/06/15 - Date consistency (2026-05-06 / 2026-05-29 / 2026-04-23 / 2026-05-30 used uniformly where referenced) - No TODO/FIXME/XXX/TBD markers in any .md - LLVM-21/22 cluster framing consistent across CLAUDE/docs/04/06/23 - All section anchors valid (no docs/27, no broken §xref) Larger-scope redundancy findings (esp32s31 narrative repeated in CLAUDE+docs/09+docs/16+HANDOFF, LDC byval/sret narrative repeated in docs/05+docs/19+docs/23) DEFERRED — they're load-bearing per-doc context, not pure duplication; PR #31 already trimmed the worst of it and further trimming risks losing per-doc reader paths. https://claude.ai/code/session_01DuR5N3YJNe42ry8vcxVxBk
Contributor
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the UI test still fails for me locally --- a/tests/ui/feature-gates/feature-gate-xtensa-target-feature.stderr
+++ b/tests/ui/feature-gates/feature-gate-xtensa-target-feature.stderr
@@ -1,5 +1,5 @@
error[E0658]: the target feature `bool` is currently unstable
- --> $DIR/feature-gate-xtensa-target-feature.rs:11:18
+ --> $DIR/feature-gate-xtensa-target-feature.rs:12:18
|
LL | #[target_feature(enable = "bool")]
| No idea why CI wouldn't catch that, let's try the job that failed earlier @bors try x86_64-gnu-llvm-22-3 |
Contributor
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Unknown argument "x86_64-gnu-llvm-22-3". Did you mean to use |
Contributor
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@bors try jobs=x86_64-gnu-llvm-22-3 |
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asm! support for the Xtensa architecture try-job: x86_64-gnu-llvm-22-3
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💔 Test for 9326e98 failed: CI. Failed job:
|
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Co-authored-by: Taiki Endo <te316e89@gmail.com> Co-authored-by: Kerry Jones <kerry@iodrive.co.za>
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@bors try jobs=x86_64-gnu-llvm-22-3 |
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asm! support for the Xtensa architecture try-job: x86_64-gnu-llvm-22-3
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I hope this should be good now. I've fixed the UI tests, and I've also simplified some of the fp asm tests to use explicit registers instead of the register class for now, as the |
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@bors r=Amanieu |
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asm! support for the Xtensa architecture This implements the asm! support for Xtensa. We've been using this code for a few years in [our fork](https://github.com/esp-rs/rust) and it's been working well. I finally found some time to clean it up a bit and start the upstreaming process. This should be one of the final PRs for Xtensa support on the Rust side (minus bug fixes of course). After this, we're mostly just waiting on the LLVM upstreaming which is going well. This PR doesn't cover all possible asm options for Xtensa, but the base ISA plus a few extras that are used in Espressif chips. r? Amanieu
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…uwer Rollup of 13 pull requests Successful merges: - #147302 (asm! support for the Xtensa architecture) - #148820 (Add very basic "comptime" fn implementation) - #157299 (Fix unstable diagnostics in tests) - #143511 (Improve TLS codegen by marking the panic/init path as cold) - #154608 (Add `_value` API for number literals in proc-macro) - #156762 (xfs support in `test_rename_directory_to_non_empty_directory`) - #157300 (Relax test requirements for consistency) - #157383 (tests: codegen-llvm: Ignore BPF targets in c-variadic-opt) - #157413 (fix: don't suggest .into_iter() for .cloned()/.copied() on non-reference Option) - #157578 (Fix diagnostics for non-exhaustive destructuring assignments (#157553)) - #157587 (explain that the size_of constant also serves to avoid optimizing away 'unused' size_of calls) - #157596 (test: remove ineffective link-extern-crate-with-drop-type test) - #157602 (rustdoc: Remove unnecessary fast path)
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Rollup merge of #147302 - esp-rs:xtensa-asm, r=Amanieu asm! support for the Xtensa architecture This implements the asm! support for Xtensa. We've been using this code for a few years in [our fork](https://github.com/esp-rs/rust) and it's been working well. I finally found some time to clean it up a bit and start the upstreaming process. This should be one of the final PRs for Xtensa support on the Rust side (minus bug fixes of course). After this, we're mostly just waiting on the LLVM upstreaming which is going well. This PR doesn't cover all possible asm options for Xtensa, but the base ISA plus a few extras that are used in Espressif chips. r? Amanieu
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This implements the asm! support for Xtensa. We've been using this code for a few years in our fork and it's been working well. I finally found some time to clean it up a bit and start the upstreaming process. This should be one of the final PRs for Xtensa support on the Rust side (minus bug fixes of course). After this, we're mostly just waiting on the LLVM upstreaming which is going well. This PR doesn't cover all possible asm options for Xtensa, but the base ISA plus a few extras that are used in Espressif chips.
r? Amanieu