Add inline asm support for amdgpu#149793
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Some changes occurred in compiler/rustc_codegen_gcc |
eholk
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This seems okay to me, but I'd rather someone more familiar with this part of the compiler give the final signoff. @bors r? |
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Error: Parsing assign command in comment failed: ...'' | error: specify user to assign to at >| ''... Please file an issue on GitHub at triagebot if there's a problem with this bot, or reach out on #triagebot on Zulip. |
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@bors r? compiler |
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@rustbot reroll |
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Removed return type from tests to fix conflict with #149991, which starts disallowing returns in |
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The change seems Ok, i'd like people with more background to take a look. |
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That's not me (sorry it took me a while because of holidays). But iirc that could be amanieu? r? @Amanieu |
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☔ The latest upstream changes (presumably #150866) made this pull request unmergeable. Please resolve the merge conflicts. |
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@bors delegate+ r=me once conflicts are resolved |
Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important.
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This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed. Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers. |
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@bors r=Amanieu |
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
JonathanBrouwer
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
JonathanBrouwer
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
JonathanBrouwer
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
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…uwer Rollup of 23 pull requests Successful merges: - #157716 (update Enzyme, June'26) - #149793 (Add inline asm support for amdgpu) - #152852 (Remove driver_lint_caps) - #155299 (make repr_transparent_non_zst_fields a hard error) - #155439 (Enable Cargo's new build-dir layout) - #157612 (Add a test where subtyping inhibits coercion.) - #157626 (Autogenerate unstable compiler flag stubs for unstable-book) - #157667 (Rename typing modes to better describe real usage) - #156212 (Additionally gate negative bounds behind new `-Zinternal-testing-features`) - #157342 (Reduce verbosity of cycle errors when possible) - #157366 (Add a regression test for an unconstrained TransmuteFrom ICE) - #157459 (rustc_target: callconv: powerpc64: Remove unreachable fallback code path) - #157658 (UnsafeCell: mention shared-ref-to-interior case, fix aliasing model inaccuracy) - #157698 (Remove an unnecessary cloning) - #157699 (Arg splat experiment - hir FnDecl impl) - #157713 (resolve: Remove exported imports from `maybe_unused_trait_imports`) - #157722 (Move create_scope_map to rustc_codegen_ssa.) - #157725 (Keep generic suggestion for macro-expanded missing-type items) - #157733 (Remove old FIXMEs about nocapture attribute) - #157737 (Reorganize `tests/ui/issues` [7/N]) - #157746 (supports_c_variadic_definitions: extend checklist for new targets) - #157763 (Move unused target expression error to appropriate place and rename it) - #157768 (codegen_ssa: peel trans. wrappers on scalable vecs)
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…uwer Rollup of 23 pull requests Successful merges: - #157716 (update Enzyme, June'26) - #149793 (Add inline asm support for amdgpu) - #152852 (Remove driver_lint_caps) - #155299 (make repr_transparent_non_zst_fields a hard error) - #155439 (Enable Cargo's new build-dir layout) - #157612 (Add a test where subtyping inhibits coercion.) - #157626 (Autogenerate unstable compiler flag stubs for unstable-book) - #157667 (Rename typing modes to better describe real usage) - #156212 (Additionally gate negative bounds behind new `-Zinternal-testing-features`) - #157342 (Reduce verbosity of cycle errors when possible) - #157366 (Add a regression test for an unconstrained TransmuteFrom ICE) - #157459 (rustc_target: callconv: powerpc64: Remove unreachable fallback code path) - #157658 (UnsafeCell: mention shared-ref-to-interior case, fix aliasing model inaccuracy) - #157698 (Remove an unnecessary cloning) - #157699 (Arg splat experiment - hir FnDecl impl) - #157713 (resolve: Remove exported imports from `maybe_unused_trait_imports`) - #157722 (Move create_scope_map to rustc_codegen_ssa.) - #157725 (Keep generic suggestion for macro-expanded missing-type items) - #157733 (Remove old FIXMEs about nocapture attribute) - #157737 (Reorganize `tests/ui/issues` [7/N]) - #157746 (supports_c_variadic_definitions: extend checklist for new targets) - #157763 (Move unused target expression error to appropriate place and rename it) - #157768 (codegen_ssa: peel trans. wrappers on scalable vecs)
JonathanBrouwer
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Add inline asm support for amdgpu Add support for inline assembly for the amdgpu backend (the amdgcn-amd-amdhsa target). Add register classes for `vgpr` (vector general purpose register) and `sgpr` (scalar general purpose register). The LLVM backend supports two more classes, `reg`, which is either VGPR or SGPR, up to the compiler to decide. As instructions often rely on a register being either a VGPR or SGPR for the assembly to be valid, reg doesn’t seem that useful (I struggled to write correct tests for it), so I didn’t end up adding it. The fourth register class is AGPRs, which only exist on some hardware versions (not the consumer ones) and they have restricted ways to write and read from them, which makes it hard to write a Rust variable into them. They could be used inside assembly blocks, but I didn’t add them as Rust register class. There are a few change affecting general inline assembly code, that is `InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`. Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4 VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu reg stores the register number(s) and a non-static String is generated at runtime for the register name. Similar for register classes and supported_types. Vectors of 64-bit types are supported by the LLVM backend, but omitted here to make the code simpler. There is currently no systematic support in LLVM of which vectors of 64-bit types are supported. Also, they are likely seldomly unused, vectors of 16- and 32-bit types are important. Tracking issue: rust-lang#135024
rust-bors Bot
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…uwer Rollup of 23 pull requests Successful merges: - #157716 (update Enzyme, June'26) - #149793 (Add inline asm support for amdgpu) - #155299 (make repr_transparent_non_zst_fields a hard error) - #155439 (Enable Cargo's new build-dir layout) - #157612 (Add a test where subtyping inhibits coercion.) - #157626 (Autogenerate unstable compiler flag stubs for unstable-book) - #157667 (Rename typing modes to better describe real usage) - #149749 (Make `BorrowedBuf` and `BorrowedCursor` generic over the data) - #156212 (Additionally gate negative bounds behind new `-Zinternal-testing-features`) - #157342 (Reduce verbosity of cycle errors when possible) - #157366 (Add a regression test for an unconstrained TransmuteFrom ICE) - #157459 (rustc_target: callconv: powerpc64: Remove unreachable fallback code path) - #157658 (UnsafeCell: mention shared-ref-to-interior case, fix aliasing model inaccuracy) - #157698 (Remove an unnecessary cloning) - #157699 (Arg splat experiment - hir FnDecl impl) - #157713 (resolve: Remove exported imports from `maybe_unused_trait_imports`) - #157722 (Move create_scope_map to rustc_codegen_ssa.) - #157725 (Keep generic suggestion for macro-expanded missing-type items) - #157733 (Remove old FIXMEs about nocapture attribute) - #157737 (Reorganize `tests/ui/issues` [7/N]) - #157746 (supports_c_variadic_definitions: extend checklist for new targets) - #157763 (Move unused target expression error to appropriate place and rename it) - #157768 (codegen_ssa: peel trans. wrappers on scalable vecs)
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Add support for inline assembly for the amdgpu backend (the
amdgcn-amd-amdhsa target).
Add register classes for
vgpr(vector general purpose register) andsgpr(scalar general purpose register).The LLVM backend supports two more classes,
reg, which is either VGPRor SGPR, up to the compiler to decide. As instructions often rely on a
register being either a VGPR or SGPR for the assembly to be valid, reg
doesn’t seem that useful (I struggled to write correct tests for it), so
I didn’t end up adding it.
The fourth register class is AGPRs, which only exist on some hardware
versions (not the consumer ones) and they have restricted ways to write
and read from them, which makes it hard to write a Rust variable into
them. They could be used inside assembly blocks, but I didn’t add them
as Rust register class.
There are a few change affecting general inline assembly code, that is
InlineAsmReg::name()now returns aCowinstead of a&'static str.Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4
VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu
reg stores the register number(s) and a non-static String is generated
at runtime for the register name.
Similar for register classes and supported_types.
Vectors of 64-bit types are supported by the LLVM backend, but omitted
here to make the code simpler. There is currently no systematic support
in LLVM of which vectors of 64-bit types are supported. Also, they are
likely seldomly unused, vectors of 16- and 32-bit types are important.
Tracking issue: #135024