MSc Microelectronics · Newcastle University UK (2025–2026)
Analog/IC Layout · Physical Design
Cadence Virtuoso · OpenLane/SKY130
I'm a Microelectronics postgraduate bridging 2.5 years of industry verification experience with formal VLSI training across the full design-to-silicon stack. My background is in functional verification and test automation at Checkpoint Systems — skills I'm applying directly to RTL testbench design, UVM environments, and analog IC layout.
Two peer-reviewed publications (IEEE Xplore + IJRASET). Currently targeting Design Verification Engineer and Analog/IC Layout Engineer roles in the UK and India.
| # | Project | Key Results | Status |
|---|---|---|---|
| P01 | Two-Stage Miller-Compensated OTA | Gain 75.6 dB · GBW 57.5 MHz · PM 60.9° · CMRR 76.4 dB · PSRR 164.4 dB · 9-corner sweep · DRC/LVS/PEX | ✅ Complete |
| P02 | OTA_LDO Error Amplifier | Gain 79.1 dB · GBW 46.87 MHz · PM 77.5° · DRC/LVS clean · M6/M7 parallel strapping fix · PEX complete | ✅ Complete |
| P03 | 1.2V LDO Voltage Regulator | Schematic PM 46.57°–74.99° · Post-layout 43.1°–73.8° · 9 PVT corners · DRC/LVS · C-only PEX | ✅ Complete |
| P04 | 6T SRAM Bit-Cell & 8×8 Array | CR=2.5 · Read SNM 140.0mV/138.6mV (pre/post) · MC yield 98.5% (200 runs) · 8×8 array · full read-path (precharge + sense amp, schematic + PEX) · DRC/LVS | ✅ Complete |
Part A — Standard Cell Design & Verification
| Cell | Pre-layout → Post-layout | Key Result |
|---|---|---|
| Inverter (inv1) | tpHL: 32.05 → 35.99 ps (+12.3%) · Energy: 1.748 → 2.493 fJ (+42.6%) | Logical Effort sizing 2:1 → 1.6:1 (DRC-driven correction) · Full DRC/LVS/PEX signoff |
| Tri-State Inverter | tpHL: 46.74 → 50.65 ps (+8.4%) · Energy: 4.326 → 5.078 fJ (+17.4%) | Layout · DRC/LVS/PEX |
| D Flip-Flop | Energy: 89.49 → 174.6 fJ (+95.1%) | Master-slave hierarchical build · dual-spike structure linked to clock gating motivation |
Part B — Experimental Characterisation
| Experiment | Key Finding |
|---|---|
| Fanout Analysis (FO0–FO4) | Cin(schematic) = 0.703 fF · Cin(extracted) = 1.078 fF (+53%) · Cpar/Cin ≈ 3.9× · LE overestimates delay by 60% at FO4 |
| Wire Delay (1µm vs 100µm M1) | Wire-added delay = 61.62 ps · C_wire = 0.113 fF/µm · Crossover length ~55µm (wire delay = one gate delay) |
| Energy–VDD Sweep (48-stage chain) | MEP at 0.8V (E = 0.719 fJ, 25.5% below nominal) · EDP minimum at 1.2–1.4V · Circuit fails below 0.4V |
| Project | Key Results |
|---|---|
| CMOS Inverter | Schematic · Layout · DRC/LVS · DC/transient · VM parametric sweep · W/L ratio sweep · LTSpice cross-validation |
| Ring Oscillator | f = 1.45 GHz (tp = 115 ps/stage) · W-L sweep · freq/power CSV + plots |
| Project | What It Shows | Tools |
|---|---|---|
| 4-Bit ALU | ADD/SUB/AND/OR/XOR · carry + zero flags · synthesis utilization report | Vivado · Verilog |
| UART Transmitter FSM | Baud generator + 4-state FSM (IDLE/START/DATA/STOP) · simulation waveform | Vivado · Verilog |
| Traffic Light Controller | Moore FSM · tick divider · FPGA constraints (.xdc) · synthesis report | Vivado · Verilog |
| 4-Bit Counter | Synchronous counter · testbench · Vivado simulation | Vivado · Verilog |
| Sequence Detector FSM (Moore) | 101-pattern detector · two-process FSM style · iVerilog + VCD | iVerilog · GTKWave |
| Full Adder, Comparator, MUX 4×1, 8-bit Register | RTL building blocks with testbenches + waveform captures | iVerilog |
| Module | Type |
|---|---|
| D Latch, SR Latch (NOR), D Flip-Flop, JK Flip-Flop | Logic simulation (.circ) |
| 4-Bit Ripple Counter, 4-Bit Synchronous Counter | |
| PIPO, PISO, SIPO, SISO Shift Registers |
RTOS in Motorola 68000 Assembly — Newcastle University EEE8087
Built from scratch on EASy68K simulator. Features:
- Round-robin scheduler with circular TCB ready list
- Context switching — full 16-register save/restore via FLIH + RTE dispatch
- Mutex (wait/signal) with blocked task queue
- 6 system calls via
trap #0: create, delete, wait_time, wait_mutex, signal_mutex, init_mutex - Two application programs: stopwatch (concurrent task + polling) and radiation monitor (shared counter with mutex protection)
Demonstrates: interrupt handling, context switching, critical sections, deadlock prevention — directly analogous to DV lab infrastructure design.
UART RTL-to-GDSII — SKY130 130nm
Complete physical design flow from RTL to manufacturing-ready GDSII using OpenLane 2, Yosys, OpenROAD, Magic, KLayout, and Netgen on SkyWater SKY130A.
- Synthesis: 267 cells, 60 flip-flops, 3034.16 µm² — 0 CHECK problems
- Floorplan: 40.1% core utilisation (target 40%)
- Placement: HPWL optimised 4127.8 → 3925.2 µm, 0.0 µm displacement
- CTS: H-tree, real measured clock skew ~1.6 ps
- Routing: 0 congestion overflow, 0 antenna violations, 0 DRC violations
- STA: 0 setup/hold violations across all 9 PVT corners — worst setup 10.55 ns, worst hold 0.144 ns
- Sign-off: DRC clean (Magic + KLayout independent cross-check), LVS matched uniquely (Netgen)
- Output: 3 GDSII files generated, ready for foundry submission
Full debugging log included — toolchain setup on WSL2, Yosys/Pyosys version conflicts, KLayout display issues, and 10+ other real environment fixes documented.
| # | Project | Tools | Status |
|---|---|---|---|
| 1 | SPI Master — RTL & Directed Verification (Week 1 ✅) | SystemVerilog · QuestaSim | 🟡 Week 2 In Progress |
| 2 | AXI4-Lite Verification IP (VIP) | SystemVerilog · UVM · Sequences | 🟡 In Progress |
| 4 | STA Timing Closure — Custom Constraints & ECO | OpenSTA · SDC · TCL Scripting | 🟡 In Progress |
| 5 | RISC-V ALU — Full Stack Integration | RTL → Synthesis → P&R → GDSII | 🟡 In Progress |
| # | Project | Key Technique | Status |
|---|---|---|---|
| P05 | StrongARM Latch — High-Speed Comparator | Metastability · Common-centroid layout · PEX timing | 🔜 Planned |
| P06 | Switched-Capacitor Integrator | Charge injection · Capacitor matching · MOM layout | 🔜 Planned |
Details to follow on completion — September 2026.
Cadence Virtuoso · Mentor Calibre (DRC/LVS/PEX) · Cadence Spectre · Xilinx Vivado · ModelSim / QuestaSim · LTSpice · Electric VLSI · OpenLane · OpenSTA · iVerilog
SystemVerilog · UVM · Verilog · VHDL · Python · TCL Scripting · C/C++ (embedded) · M68K Assembly
CMOS Layout · DRC / LVS / PEX · Parasitic Extraction · Static Timing Analysis (STA) · Logical Effort Sizing · Coverage-Driven Verification · Constrained-Random Testing · RTL Design · Logic Synthesis · Power Optimisation · RTOS Design
SPI · AXI4-Lite · I2C · RS232 · UART · AMBA
FPGA (Xilinx ISE / Vivado) · Arduino · ESP8266 · RISC-V
IEEE Xplore — ICMNWC 2021
Wearable assistive device for deafblind communication. ESP8266 (Bolt IoT) + 3 vibrating modules (200Hz, 10mm×2.8mm). SqueezeNet CNN (TensorFlow/Keras) trained on 1,000 images across 8 gesture categories — 75–78% recognition accuracy. Google SpeechRecognition API — ~95% speech-to-text accuracy.
IJRASET
Soil NPK sensor (TTL-485 Modbus) + pH sensor (analogue) → NodeMCU/ESP8266 → ThingSpeak cloud. Random Forest classifier + Decision Tree regression. Flask web app with 6/12-month crop price forecasting.
Chip-based VLSI Design for Industrial Applications — L&T EduTech / Coursera · June 2025
Electric VLSI · LTSpice · VHDL on Xilinx ISE/Vivado · SPI, I2C, RS232 sensor interfacing
VLSI CAD Part I: Logic & Part II: Layout — University of Illinois / Coursera · March 2025
BDD · SAT-based verification · Logic synthesis · ASIC placement · Maze routing · STA (AT/RAT/slack · Elmore delay)
MSc Microelectronics: Systems and Devices — Newcastle University, UK · 2025–2026
Low-Power VLSI Design · Microelectronics Design Tools · Advanced Device Fabrication · Advanced Electronic Devices · Real-Time Embedded Systems
BE Electronics and Communication Engineering — BNM Institute of Technology (VTU), India · 2022 · CGPA 8.2/10
Software Engineer II — Checkpoint Systems, Bengaluru · Sept 2022 – Nov 2024
Functional verification and test automation across 3 concurrent RFID-based retail product lines. 900+ test cases, 500+ verified defects, 200+ API validations. Regression suites, root-cause documentation, defect triage — directly transferable to RTL testbench workflows.
📧 sachinathani05@gmail.com
🔗 linkedin.com/in/sachin-athani
📍 Newcastle, UK · Graduate Route Visa (open to UK work)
Active build — updated progressively through September 2026.