SoC Hub FI

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1. Marian Marian Public

   Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions

   SystemVerilog 17 4

2. ReImA ReImA Public

   A Reconfigurable Image Acqusition and Prosessing Subsystem in SystemVerilog.

   SystemVerilog 5 4

3. Atalanta Atalanta Public

   Tcl 4 2

4. AnTiQ AnTiQ Public

   A hardware priority queue with constant response time written in SystemVerilog.

   SystemVerilog 3 3

5. rt-ibex rt-ibex Public

   Real-time optimized version of Ibex

   SystemVerilog 3 3

6. soc-hub-hal soc-hub-hal Public

   (Placeholder) Experimental Rust Hardware Abstraction Layers (HALs) for Ballast RISC-V MPSoC

   1