GitHub - tabell/prng: School project, basic hardware PRNG in verilog · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
gebali/UA_TX		gebali/UA_TX
Makefile		Makefile
div.v		div.v
div.wcfg		div.wcfg
div_tb.v		div_tb.v
model.c		model.c
mult.v		mult.v
mult_tb.v		mult_tb.v
prng.v		prng.v
sim.do		sim.do
tb_prng.v		tb_prng.v
test1.v		test1.v
test1.wcfg		test1.wcfg
top_block.ucf		top_block.ucf
top_block.v		top_block.v

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School project, basic hardware PRNG in verilog

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