#
aes-sbox
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SystemVerilog (RTL) AES-based Hash core with FSMD architecture. Features a C golden model for verification and optimization for Intel Cyclone V FPGAs.
cryptography fpga digital-logic systemverilog hash-algorithm cyclone-v hardware-security aes-sbox rtl-design intel-quartus-prime
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Updated
May 28, 2026 - SystemVerilog
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