Production-grade MCP server for KiCad EDA: PCB design, DRC/ERC, BOM, DFM, simulation, manufacturing.

Neural Network models for automating design parameters of CS amplifier. Includes automated SPICE data generation and model validation in Python and MATLAB.

Engineering traceability framework for Cadence Virtuoso ADE XL using SKILL and Python.

An automated RTL-to-Synthesis EDA tool wrapper written in Tcl. Automates multi-module hierarchy checks, SDC constraint generation, Yosys synthesis mapping, and OpenTimer static timing analysis (STA) for the openMSP430 core.