riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way
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Jun 13, 2026 - C
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fpga-projects
Here are 12 public repositories matching this topic...
Simple Ping Pong game on Xilinx Spartan 3E
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Apr 29, 2022 - HTML
A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.
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Dec 29, 2024 - Verilog
A A collection of Verilog/SystemVerilog projects developed for the DE10-Lite FPGA board using Intel Quartus.
fpga verilog systemverilog state-machines electrical-engineering hardware-testing hardware-description-language clock-divider de10-lite digital-logic-design intel-fpga seven-segment-display rtl-design fpga-projects synchronous-design
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Jul 12, 2025 - Verilog
Verilog Code to Implementation on FPGA of 8 Bit Signed Multiplier
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Oct 17, 2024 - Verilog
Undergraduate level RISC-V microcontroller
microcontroller cpu fpga amd riscv xilinx xilinx-fpga utfsm riscv32 nexys4ddr entry-level riscv-cpu fpga-projects
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Oct 12, 2022 - SystemVerilog
T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.
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Dec 23, 2023 - Verilog
Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.
verilog systemverilog digital-design asic-verification hardware-verification fpga-projects rtl-design-and-verification
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Oct 30, 2025 - Jupyter Notebook
COE758 - This course covers advanced computing systems with emphasis on system architecture, memory hierarchy (Cache, Virtual memory), processor-peripheral interfacing, and bus organization. Laboratory projects include Cache Controller and VGA display design using FPGA. This course is taken at TMU, formally known as Ryerson.
vhdl virtual-memory dma memory-hierarchy vga-controller cache-memory cache-design video-output subsystems cache-controller digital-systems-design fpga-projects
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Dec 19, 2025 - C
Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.
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Oct 17, 2024 - Verilog
Este projeto contém uma implementação lógica que simula o funcionamento de uma Memória de Acesso Aleatório (RAM) em uma placa FPGA.
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May 26, 2026 - VHDL
RTL Design and Verification of a 4-bit Synchronous Up/Down Counter using Verilog HDL, featuring parallel load, enable control, ripple carry output, simulation, synthesis, and FPGA implementation in Xilinx Vivado.
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May 25, 2026 - Verilog
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