🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Apr 30, 2026 - Python
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vyges
Here are 24 public repositories matching this topic...
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
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Oct 8, 2025 - SystemVerilog
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges vyges-ip vybox vybox-lite
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Feb 20, 2026 - JavaScript
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2
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Jun 9, 2026 - SystemVerilog
STA-driven buffer insertion: split high-fanout / over-transition nets to fix slew and timing.
rust digital optimization eda semiconductor silicon eda-tools vyges open-silicon vyges-loom buffer-insertion
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Jun 23, 2026 - Rust
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
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Oct 8, 2025 - SystemVerilog
Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.
docker magic asic container eda vlsi yosys semiconductor klayout netgen ngspice gdsii physical-design openroad sky130 chip-design gf180mcu open-source-silicon rtl-to-gdsii vyges
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Jun 22, 2026 - Dockerfile
Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.
rust digital eda semiconductor silicon static-timing-analysis signal-integrity eda-tools vyges sign-off open-silicon vyges-loom
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Jun 23, 2026 - Rust
A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz
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Oct 8, 2025 - Python
Public release home for the Vyges CLI — prebuilt binaries + curl/PowerShell installers (catalog, PDK, and Loom-engine installs). Homebrew tap: vyges/homebrew-tap.
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Jun 23, 2026
Vyges open-PDK catalog: index.json + full PDK descriptors
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Jun 6, 2026 - Python
RC parasitic extraction — routed layout to SPEF; a calibrated sky130 deck tracks OpenRCX.
rust digital analog eda semiconductor mixed-signal silicon spef eda-tools rc-extraction vyges open-silicon vyges-loom parasitic-extraction
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Jun 23, 2026 - Rust
STA-driven Vt swapping: trade threshold-voltage flavors (iso-footprint) to cut leakage while holding timing, or to close setup.
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Jun 23, 2026 - Rust
Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration.
rust digital eda spice characterization liberty semiconductor silicon eda-tools vyges open-silicon vyges-loom
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Jun 23, 2026 - Rust
Power-integrity sign-off — power-distribution-network IR-drop + electromigration against a budget.
rust digital analog eda semiconductor mixed-signal silicon power-integrity electromigration ir-drop eda-tools vyges open-silicon vyges-loom
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Jun 23, 2026 - Rust
Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.
rust digital analog eda semiconductor mixed-signal silicon lvs eda-tools vyges open-silicon vyges-loom layout-vs-schematic
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Jun 23, 2026 - Rust
Gate sizing — STA-driven drive-strength resize to close setup or recover area.
rust digital optimization eda semiconductor silicon gate-sizing eda-tools vyges open-silicon vyges-loom
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Jun 23, 2026 - Rust
The shared design-data foundation for the Vyges Loom EDA suite — parse-once/query-many readers (Verilog, Liberty, SDC, SPEF) + an in-memory design database.
rust parser digital eda semiconductor silicon design-database eda-tools vyges open-silicon vyges-loom
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Jun 23, 2026 - Rust
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