feat: implement vertical schematic layout bias for power and ground nets

[sagarmaurya64-ai]

This PR implements vertical net bias for power (VCC/VDD) and ground (GND/VSS) nets to resolve layout ordering issues (#12).

Implementation Details:

1. Net Bias Detection Utility: Implemented netBiasUtils.ts to identify positive voltage nets and ground nets by direct flag checks or naming conventions (e.g. vcc, vdd, vsys, gnd, vss, digit patterns).
2. Always Preserve Power/Ground Nets: Updated createFilteredNetworkMapping in networkFiltering.ts to skip filtering of power/ground nets when strong connections are present, enabling the layout engine to align them.
3. Injected Attractors: Modified both SingleInnerPartitionPackingSolver and PartitionPackingSolver to inject static attractor components at Y coordinate extremes ((0, -100) for VCC/VDD nets to pull them upward, and (0, 100) for GND/VSS nets to pull them downward).
4. Layout Cleanup: Filtered out these virtual attractor_ components when extracting layout results to prevent downstream visualization/calculation issues.

Verification:

• Added a new integration test tests/LayoutPipelineSolver/LayoutPipelineSolverPowerBias.test.ts verifying that decoupling capacitors are correctly oriented vertically (Pin 1/VCC above Pin 2/GND).
• Ran the entire test suite (bun test) successfully with all 23 tests passing.

Closes #12

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[sagarmaurya64-ai]

/claim #12