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fix(dts): align XiangShan profiles with NEMU OpenSBI #49

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Merged
poemonsense merged 1 commit into from
Aug 17, 2026
Merged

fix(dts): align XiangShan profiles with NEMU OpenSBI #49

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36 changes: 28 additions & 8 deletions dts/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -75,8 +75,15 @@ standard templates retain these profiles:
| Template | DRAM |
|----------|------|
| `xiangshan-fpga-noAIA-2hart-mem8g` | 8 GiB |
| `xiangshan-fpga-noAIA-2hart-mem16g` | 16 GiB |
| `xiangshan-fpga-noAIA-32hart-mem64g` | 64 GiB |

`xiangshan-fpga-noAIA-mem16g-novec` is the single-hart Host profile for
`virt/linux/*`. It disables AIA and vector advertisement, retains the H
extension required by RISC-V KVM, and describes exactly 16 GiB of DRAM. The
virtual build validates all three properties that affect nesting: one CPU, at
least 16 GiB, and structured ISA extension `h`.

Select the complete template basename explicitly when building, for example:

```sh
Expand All @@ -97,16 +104,29 @@ python3 scripts/generate-xiangshan-multihart-dts.py \
--output dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in
```

`--harts` must be in the range 2 through 128. The generator copies the CPU node for each hart,
extends the CLINT, PLIC, and debug interrupt contexts, and applies the NEMU
UARTLITE and PLIC settings. Generated multi-hart templates reserve the fixed
131 MiB checkpoint window `[0x80300000, 0x88600000)`.
Use `--memory-gib` to override the copied DRAM capacity. The checked-in 16 GiB
two-hart profile is generated with:

```shell
python3 scripts/generate-xiangshan-multihart-dts.py \
--base dts/xiangshan-fpga-noAIA-mem8g.dts.in \
--harts 2 \
--memory-gib 16 \
--output dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in
```

`--harts` must be in the range 2 through 128, and `--memory-gib` must be a
positive integer when specified. The generator copies the CPU node for each
hart, extends the CLINT, PLIC, and debug interrupt contexts, and applies the
NEMU UARTLITE and PLIC settings. Generated multi-hart templates reserve the
fixed 131 MiB checkpoint window `[0x80300000, 0x88600000)`.

The full capability block describes XiangShan hardware and is not fully
emulated by the current QEMU `nemu` machine. In particular, DT-advertised
`smrnmi` requires an OpenSBI platform `smrnmi_handlers_init` callback, while
the `nemu` timer path cannot execute the DT-advertised `sstc` CSR sequence.
The current multi-core DTB must omit `smrnmi` and `sstc` and run with
emulated by the current generic OpenSBI/QEMU `nemu` path. In particular,
DT-advertised `smrnmi` requires an OpenSBI platform
`smrnmi_handlers_init` callback, so all generic-platform DTS templates omit
it. The `nemu` timer path likewise cannot execute the DT-advertised `sstc` CSR
sequence; multi-core diagnostic runs may need to omit `sstc` and use
`sstc=false`.

The build does not invoke this generator automatically. Run it and review the
Expand Down
2 changes: 1 addition & 1 deletion dts/xiangshan-fpga-AIA-mem16g.dts.in
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Expand Up @@ -48,7 +48,7 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smaia", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
Expand Down
14 changes: 6 additions & 8 deletions dts/xiangshan-fpga-noAIA-2hart-mem16g.dts.in → ...shan-fpga-noAIA-2hart-mem16g-novec.dts.in
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Expand Up @@ -43,10 +43,10 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
"i", "m", "a", "f", "d", "c", "h",
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
Expand All @@ -64,8 +64,7 @@
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
"zkn", "zknd", "zkne", "zknh", "zksed",
"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
"zvkt", "zvl128b", "zvl32b", "zvl64b";
"zksh", "zkt";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;

Expand Down Expand Up @@ -104,10 +103,10 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
"i", "m", "a", "f", "d", "c", "h",
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
Expand All @@ -125,8 +124,7 @@
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
"zkn", "zknd", "zkne", "zknh", "zksed",
"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
"zvkt", "zvl128b", "zvl32b", "zvl64b";
"zksh", "zkt";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;

Expand Down
14 changes: 6 additions & 8 deletions dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in → ...gshan-fpga-noAIA-2hart-mem8g-novec.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,10 +43,10 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
"i", "m", "a", "f", "d", "c", "h",
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
Expand All @@ -64,8 +64,7 @@
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
"zkn", "zknd", "zkne", "zknh", "zksed",
"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
"zvkt", "zvl128b", "zvl32b", "zvl64b";
"zksh", "zkt";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;

Expand Down Expand Up @@ -104,10 +103,10 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
"i", "m", "a", "f", "d", "c", "h",
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
Expand All @@ -125,8 +124,7 @@
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
"zkn", "zknd", "zkne", "zknh", "zksed",
"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
"zvkt", "zvl128b", "zvl32b", "zvl64b";
"zksh", "zkt";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;

Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
115 changes: 115 additions & 0 deletions dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in
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@@ -0,0 +1,115 @@
/*
* Single-hart Host DTS for a virtualized workload.
*
* AIA is disabled and the H extension is advertised so Host Linux can use
* KVM. The 16 GiB profile matches the default 8 GiB Guest configuration.
*/

/dts-v1/;

/ {
compatible = "freechips,rocketchip-unknown-dev";
model = "xiangshan,Kunminghu-dev";
#address-cells = <2>;
#size-cells = <2>;

cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;

cpu0: cpu@0 {
compatible = "ICT,xiangshan", "riscv";
device_type = "cpu";
reg = <0>;
status = "okay";
mmu-type = "riscv,sv48";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
"smstateen", "sscofpmf", "sstc", "zicntr", "zihpm",
"svpbmt", "sdtrig", "smcsrind", "sscsrind", "svade";

intc_cpu0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};

l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-block-size = <64>;
cache-size = <1048576>;
};

memory: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x4 0x00000000>;
};

reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

reserved0: buffer@0 {
no-map;
reg = <0x0 0x80000000 0x0 0x100000>;
};
};

soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;

clint: clint@38000000 {
compatible = "riscv,clint0";
reg = <0x0 0x38000000 0x0 0x10000>;
reg-names = "control";
interrupts-extended = <&intc_cpu0 3 &intc_cpu0 7>;
};

PLIC: interrupt-controller@3c000000 {
compatible = "riscv,plic0";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x0 0x3c000000 0x0 0x4000000>;
reg-names = "control";
interrupts-extended = <&intc_cpu0 11 &intc_cpu0 9>;
riscv,max-priority = <7>;
riscv,ndev = <66>;
};

uart0: serial@310b0000 {
compatible = "ns16550a";
reg = <0x0 0x310b0000 0x0 0x10000>;
reg-shift = <0x2>;
reg-io-width = <0x4>;
clock-frequency = <50000000>;
current-speed = <115200>;
status = "okay";
};
};

aliases {
serial0 = &uart0;
};

chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
stdout-path = "serial0:115200n8";
linux,initrd-start = <INITRAMFS_BEGIN_HI INITRAMFS_BEGIN_LO>;
linux,initrd-end = <INITRAMFS_END_HI INITRAMFS_END_LO>;

opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem24g.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem64g.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
4 changes: 2 additions & 2 deletions dts/xiangshan-fpga-noAIA-mem8g.dts.in
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Expand Up @@ -50,15 +50,15 @@
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smrnmi", "smstateen",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
Expand Down
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